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INTEGRATED CIRCUITS
74F821/822/823/824/825/826 Bus interface registers
Product specification IC15 Data Handbook 1996 Jan 05
Philips Semiconductors
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
74F821 74F822 74F823 74F824 74F825 74F826
10-bit bus interface register, non-inverting (3-State) 10-bit bus interface register, inverting (3-State) 9-bit bus interface register, non-inverting (3-State) 9-bit bus interface register, inverting (3-State) 8-bit bus interface register, non-inverting (3-State) 8-bit bus interface register, inverting (3-State)
DESCRIPTION
The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions. The 74F822 is the inverted output version of 74F821. The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The 74F824 is the inverted version of 74F823. The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) to allow multiuser control of the interface, e.g., CS, DMA, and RD/WR. They are ideal for uses as an output port requiring high IOL/IOH. The 74F826 is the inverted version of 74F825. TYPICAL fmax 180MHz 180MHz 180MHz TYPICAL SUPPLY CURRENT (TOTAL) 75mA 70mA 65mA
FEATURES
flip-flops
* High speed parallel registers with positive edge-triggered D-type * High performance bus interface buffering for wide data/address
paths or busses carrying parity
* High impedance PNP base inputs for reduced loading (20A in
high and low states)
* IIL is 20A vs 1000A for AM29821 series * Buffered control inputs to reduce AC effects * Ideal where high speed, light loading, or increased fan-in as
required with MOS microprocessor
* Positive and negative over-shoots are clamped to ground * 3-State outputs glitch free during power-up and power-down * Slim Dip 300 mil package * Broadside pinout compatible with AMD AM 29821-29826 series * Outputs sink 64mA and source 24mA * Industrial temperature range available (-40C to +85C) for
74F823
TYPE 74F821, 74F822 74F823, 74F824 74F825, 74F826
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F821N, N74F822N, N74F823N, N74F824N, N74F825N, N74F826N N74F821D, N74F822D, N74F823D, N74F824D, N74F825D, N74F826D INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C I74F823N I74F823D PKG. DWG. #
24-pin plastic slim DIP (300mil) 24-pin plastic SOL
SOT222-1 SOT137-1
1996 Jan 05
2
853-1304 16195
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS Dn 74F821 74F822 CP OE Qn, Qn Dn CP 74F823 74F824 CE MR OE Qn, Qn Dn CP 74F825 74F826 CE MR OE Qn, Qn Data inputs Clock input Output enable input (active low) Data outputs Data inputs Clock input Clock enable input (active low) Master reset input (active low) Output enable input (active low) Data outputs Data inputs Clock input Clock enable input (active low) Master reset input (active low) Output enable input (active low) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/3.0 1200/106.7 1.0/1.0 1.0/1.0 1.0/3.0 1.0/3.0 1.0/3.0 1200/106.7 1.0/1.0 1.0/1.0 1.0/3.0 1.0/3.0 1.0/3.0 1200/106.7 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/1.8mA 24mA/64mA 20A/0.6mA 20A/0.6mA 20A/1.8mA 20A/1.8mA 20A/1.8mA 24mA/64mA 20A/0.6mA 20A/0.6mA 20A/1.8mA 20A/1.8mA 20A/1.8mA 24mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state.
PIN CONFIGURATION - 74F821
OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11 GND 12 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 13 CP
LOGIC SYMBOL - 74F821
2 3 4 5 6 7 8 9 10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13 1
CP OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
VCC = Pin 24 GND = Pin 12
23
22
21
20
19
18
17
16
15
14
SF00483
SF00482
1996 Jan 05
3
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
IEC/IEEE SYMBOL - 74F821
1 EN1 13 G2 2 3 4 5 6 7 8 9 10 11 23 22 21 20 19 18 17 16 15 14
IEC/IEEE SYMBOL - 74F822
1 EN1 13 G2 2 3 4 5 6 7 8 9 10 11 23 22 21 20 19 18 17 16 15 14
2D
1
2D
1
SF00484
SF00487
PIN CONFIGURATION - 74F822
OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11 GND 12 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 13 CP
PIN CONFIGURATION - 74F823
OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 MR 11 GND 12 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 CE 13 CP
SF00485
SF00488
LOGIC SYMBOL - 74F822
2 3 4 5 6 7 8 9 10 11
LOGIC SYMBOL - 74F823
2 3 4 5 6 7 8 9 10
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 13 13 1 CP OE 14 11 1 CP CE MR OE
D0 D1 D2 D3 D4 D5 D6 D7 D8
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
23 VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
14 VCC = Pin 24 GND = Pin 12
23
22
21
20
19
18
17
16
15
SF00486
SF00489
1996 Jan 05
4
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
IEC/IEEE SYMBOL - 74F823
1 11 14 13 EN1
IEC/IEEE SYMBOL - 74F824
1 11 EN1 R G1 1G2 23 22 21 20 19 18 17 16 15
R 14 G1 1G2 23 22 21 20 19 18 17 16 15 13
2 3 4 5 6 7 8 9 10
2 3 4 5 6 7 8 9 10
2D
1
2D
1
SF00490
SF00493
PIN CONFIGURATION - 74F824
OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 MR 11 GND 12 24 V CC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 CE 13 CP
PIN CONFIGURATION - 74F825
OE0 1 OEI 2 DO 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 MR 11 GND 12 24 VCC 23 OE2 22 QO 21 Q1 20 Q2 19 Q3 18 Q4 17 Q5 16 Q6 15 Q7 14 CE 13 CP
SF00491
SF00494
LOGIC SYMBOL - 74F824
2 3 4 5 6 7 8 9 10
LOGIC SYMBOL - 74F825
3 4 5 6 7 8 9 10
D0 D1 D2 D3 D4 D5 D6 D7 D8 13 13 14 11 1 CP CE MR OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 14 11 1 2 23 CP CE MR OE0 OE1 OE2
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
23 VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15 VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
SF00492
SF00495
1996 Jan 05
5
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
IEC/IEEE SYMBOL - 74F825
1 2 23 11 14 13 R G1 1G2 22 21 20 19 18 17 16 15 & EN
LOGIC SYMBOL - 74F826
3 4 5 6 7 8 9 10
D0 D1 D2 D3 D4 D5 D6 D7 13 14 11 1 2 1 23 CP CE MR OE0 OE1 OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
3 4 5 6 7 8 9 10
2D
22 VCC = Pin 24 GND = Pin 12
21
20
19
18
17
16
15
SF00498
IEC/IEEE SYMBOL - 74F826
1 & EN 2 23
SF00496
PIN CONFIGURATION - 74F826
OE0 1 OEI 2 DO 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 MR 11 GND 12 24 VCC 23 OE2 22 QO 21 Q1 20 Q2 19 Q3 18 Q4
11 14 13
R G1 1G2 22 21 20 19 18 17 16 15
3 4 5 6 7 8
2D
1
17 Q5 16 Q6 15 Q7 14 CE 13 CP
9 10
SF00499
SF00497
LOGIC DIAGRAM FOR 74F821
D0 2 D CP Q CP 13 D1 3 D CP Q D2 4 D CP Q D3 5 D CP Q D4 6 D CP Q D5 7 D CP Q D6 8 D CP Q D7 9 D CP Q D8 10 D CP Q D9 11 D CP Q
OE
1 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9
VCC = Pin 24 GND = Pin 12
SF00500
1996 Jan 05
6
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
LOGIC DIAGRAM FOR 74F822
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11
D CP Q CP 13
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
OE
1 23 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9
VCC = Pin 24 GND = Pin 12
Q0
SF00501
FUNCTION TABLE FOR 74F821 AND 74F822
OUTPUTS INPUTS OE L L L H H= h= L= l= NC= X= Z= = = CP X Dn l h X X 74F821 Q L H NC Z 74F822 Q H L NC Z Load and read data Hold High impedance OPERATING MODE
High-voltage level High state must be present one setup time before the low-to-high clock transition Low-voltage level Low state must be present one setup time before the low-to-high clock transition No change Don't care High impedance "off" state Low-to-high clock transition Not low-to-high clock transition
LOGIC DIAGRAM FOR 74F823
CE 14 D0 13 2 D CP RQ MR 11 D1 3 D CP RQ D2 4 D CP RQ D3 5 D CP RQ D4 6 D CP RQ D5 7 D CP RQ D6 8 D CP RQ D7 9 D CP RQ D8 10 D CP RQ
CP
OE
1 23 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8
VCC = Pin 24 GND = Pin 12
Q0
SF00502A
1996 Jan 05
7
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
LOGIC DIAGRAM FOR 74F824
CE 14 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10
CP
13 D CP RQ MR 11 D CP RQ D CP RQ D CP RQ D CP RQ D CP RQ D CP RQ D CP RQ D CP RQ
OE
1 23 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8
VCC = Pin 24 GND = Pin 12
Q0
SF00503A
FUNCTION TABLE for 74F823 and 74F824
OUTPUTS INPUTS OE L L L L H H= h= L= l= NC= X= Z= *= MR L H H H X CE* X L L H X CP X X X Dn X h l X X 74F823 Q L H L NC Z 74F824 Q L L H NC Z Load and read data Hold High impedance Clear OPERATING MODE
High-voltage level High state must be present one setup time before the low-to-high clock transition Low-voltage level Low state must be present one setup time before the low-to-high clock transition No change Don't care High impedance "off" state Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders or other potentially glitch prone device on the CE input. = Low-to-high clock transition
LOGIC DIAGRAM FOR 74F825
CE 14 D0 13 3 D CP RQ MR 11 D1 4 D CP RQ D2 5 D CP RQ D3 6 D CP RQ D4 7 D CP RQ D5 8 D CP RQ D6 9 D CP RQ D7 10 D CP RQ
CP
1 OE0 2 OE1 23 OE2 VCC = Pin 24 GND = Pin 12
22 Q0
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
15 Q7
SF00504A
1996 Jan 05
8
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
LOGIC DIAGRAM FOR 74F826
CE 14 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10
13 CP D CP RQ MR 11 D CP RQ D CP RQ D CP RQ D CP RQ D CP RQ D CP RQ D CP RQ
1 OE0 2 OE1 23 OE2 VCC = Pin 24 GND = Pin 12
22 Q0
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
15 Q7
SF00505A
FUNCTION TABLE FOR 74F825 AND 74F826
OUTPUTS INPUTS OEn L L L L H H= h= L= l= NC= X= Z= *= MR L H H H X CE* X L L H X CP X X X Dn X h l X X 74F825 Q L H L NC Z 74F826 Q L L H NC Z Load and read data Hold High impedance Clear OPERATING MODE
High-voltage level High state must be present one setup time before the low-to-high clock transition Low-voltage level Low state must be present one setup time before the low-to-high clock transition No change Don't care High impedance "off" state Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders or other potentially glitch prone device on the CE input. = Low-to-high clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Commercial range Operating free-air temperature range free air Storage temperature range Industrial range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 128 0 to +70 -40 to +85 -65 to +150 UNIT V V mA V mA C C C
1996 Jan 05
9
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIk IOH IOL Tamb b Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current O erating Operating free-air tem erature range temperature Commercial range Industrial range 0 -40 PARAMETER MIN 4.5 2.0 0.8 -18 -24 64 +70 +85 LIMITS NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC 0.42 -0.73 LIMITS MIN 2.4 2.4 2.0 2.0 0.55 0.55 -1.2 100 20 -20 50 -50 -100 75 VCC = MAX 75 75 65 VCC = MAX 70 75 60 VCC = MAX 60 65 -225 105 105 115 100 105 110 85 90 95 TYP2 MAX UNIT V V V V V V V A A A A A mA mA mA mA mA mA mA mA mA mA
VO OH
High level output voltage High-level
VCC = MIN, VIL = MAX MAX, VIH = MIN VCC = MIN, VIL = MAX MAX, VIH = MIN
IO = -15mA 15mA OH
IO = -24mA 24mA OH
VO OL VIK II IIH IIL IOZH IOZL IOS
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, high-level voltage applied Off-state output current, low-level voltage applied Short-circuit output current3 ICCH 74F821, 74F822 ICCL ICCZ ICCH
IO = MAX OL
VCC = MIN, II = IIK VCC = 0.0V, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX
ICC
Supply current (total)
74F823, 74F824
ICCL ICCZ ICCH
74F825, 74F826
ICCL ICCZ
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1996 Jan 05
10
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
AC ELECTRICAL CHARACTERISTICS FOR 74F821/74F822/74F824/74F825/74F826
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to Qn or Qn Propagation delay CP to Qn Propagation delay MR to Qn or Qn Output enable time OEn to Qn or Qn Output disable time OEn to Qn or Qn 74F821, 74F825, 74F826 74F822, 74F824 74F824 74F825, 74F826 Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 150 4.0 4.0 4.5 4.5 3.0 2.0 3.0 1.5 1.5 TYP 180 6.5 6.0 6.5 6.5 5.0 4.5 5.0 3.5 3.5 8.5 8.5 9.0 9.0 8.0 8.0 8.0 6.5 6.5 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 140 4.0 3.5 4.5 4.5 3.0 2.0 2.5 1.5 1.5 9.5 9.0 10.0 9.0 8.0 9.0 9.0 7.5 7.5 MAX ns ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS FOR 74F821/74F822/74F824/74F825/74F826
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) tsu (H) tsu (L) th (H) th (L) tw (L) trec Setup time, high or low Dn to CP Hold time, high or low Dn to CP CP Pulse width, high or low Setup time, high or low, CE to CP Hold time, high or low CE to CP MR Pulse width, low Recovery time, MR to CP 74F824, 74F825, 74F826 Waveform 3 Waveform 3 Waveform 1 Waveform 3 Waveform 3 Waveform 2 Waveform 2 1.0 1.0 2.0 2.0 3.5 3.5 0.0 2.0 0.0 3.0 4.5 2.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 1.0 1.0 2.0 2.0 4.0 4.0 0.0 2.0 0.0 3.5 4.5 2.5 MAX ns ns ns ns ns ns ns UNIT
1996 Jan 05
11
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
AC ELECTRICAL CHARACTERISTICS FOR 74F823
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF RL = 500 MIN fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to Qn or Qn Propagation delay MR to Qn or Qn Output enable time OEn to Qn or Qn Output disable time OEn to Qn or Qn Waveform 1 Waveform 1 Waveform 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 150 4.0 4.0 3.0 2.0 3.0 1.5 1.5 TYP 180 6.5 6.0 5.0 4.5 5.0 3.5 3.5 8.5 8.5 8.0 8.0 8.0 6.5 6.5 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF RL = 500 MIN 140 4.0 3.5 3.0 2.0 2.5 1.5 1.5 9.5 9.0 8.0 9.0 9.0 7.5 7.5 MAX Tamb = -40C to +85C VCC = +5.0V 10% CL = 50pF RL = 500 MIN 130 4.0 3.5 3.0 2.0 2.5 1.5 1.5 10.0 9.0 8.5 11.0 9.0 8.5 8.5 MAX ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS FOR 74F823
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) tsu (H) tsu (L) th (H) th (L) tw (L) trec Setup time, high or low Dn to CP Hold time, high or low Dn to CP CP Pulse width, high or low Setup time, high or low, CE to CP Hold time, high or low CE to CP MR Pulse width, low Recovery time, MR to CP Waveform 3 Waveform 3 Waveform 1 Waveform 3 Waveform 3 Waveform 2 Waveform 2 1.0 1.0 2.0 2.0 3.5 3.5 0.0 2.0 0.0 3.0 4.5 2.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF RL = 500 MIN 1.0 1.0 2.0 2.0 4.0 4.0 0.0 2.0 0.0 3.5 4.5 2.5 MAX Tamb = -40C to +85C VCC = +5.0V 10% CL = 50pF RL = 500 MIN 2.0 1.5 2.5 2.0 4.0 4.0 0.0 2.0 1.5 4.0 4.5 2.5 MAX ns ns ns ns ns ns ns UNIT
1996 Jan 05
12
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax CP VM tw(H) tPLH Qn tPHL Qn VM VM tw(L) VM VM tPHL MR VM tw(L) CP tPHL Qn, Qn VM VM trec VM
VM tPLH VM
SF00507 SF00506
Waveform 2. Master reset pulse width, master reset to output delay and master reset to clock recovery time
Waveform 1. Propagation delay for clock input to output, clock pulse width, and maximum clock frequency
Dn, CE
VM tsu(H)
VM th(H)
VM tsu(L)
VM th(L)
OEn
VM tPZH
VM tPHZ VM 0V VOH -0.3V
CP
VM
Qn, Qn VM
SF00508 SF00509
Waveform 3.
Data setup time and hold times
Waveform 4. 3-State output enable time to high level and output disable time from high level
OEn
VM tPZL
VM tPLZ VM VOL +0.3V
3.5V
Qn, Qn
SF00510
Waveform 5. 3-State output enable time to low level and output disable time from low level
1996 Jan 05
13
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for Open Collector Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00128
1996 Jan 05
14
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
1996 Jan 05
15
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1996 Jan 05
16
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
NOTES
1996 Jan 05
17
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05185

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