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INTEGRATED CIRCUITS
DATA SHEET
SAA7199B Digital Video Encoder (DENC) GENLOCK-capable
Product specification Supersedes data of April 1993 File under Integrated Circuits, IC22 1996 Sep 27
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
FEATURES * Monolithic integrated CMOS video encoder circuit * Standard MPU (12 lines) and I2C-bus interfaces for controls * Three 8-bit signal inputs PD7 to PD0 for RGB respectively YUV or indexed colour signals (Tables 19 to 26) * Square pixel and CCIR input data rates * Band limited composite sync pulses * Three 256 x 8 colour look-up tables (CLUTs) for example for gamma correction * External subcarrier from a digital decoder (SAA7151B or SAA7191B) * Multi-purpose key for real time format switching * Autonomous internal blanking * Optional GENLOCK operation with adjustable horizontal sync timing and adjustable subcarrier phase * Stable GENLOCK operation in VCR standard playback mode * Optional still video capture extension * Three suitable video 9-bit digital-to-analog converters * Composite analog output signals CVBS, Y and C for PAL/NTSC * Line 21 data insertion possible. QUICK REFERENCE DATA SYMBOL VDDD VDDA IP(tot) VI Vo RL ILE DLE Tamb PARAMETER digital supply voltage (pins 2, 21 and 41) analog supply voltage (pins 64, 66, 70 and 72) total supply current input signal levels analog output voltage Y, C and CVBS without load (peak-to-peak value) output load resistance LF integral linearity error in output signal (9-bit DAC) LF differential linearity error in output signal (9-bit DAC) operating ambient temperature - 90 - - 0 MIN. 4.5 4.75 -
SAA7199B
GENERAL DESCRIPTION The SAA7199B encodes digital baseband colour/video data into analog Y, C and CVBS signals (S-video included). Pixel clock and data are line-locked to the horizontal scanning frequency of the video signal. The circuit can be used in a square pixel or in a consumer TV application. Flexibility is provided by programming facilities via MPU-bus (parallel) or I2C-bus (serial).
TYP. 5.0 5.0 - 2 - - - -
MAX. 5.5 5.25 200 - - 1 0.5 70
UNIT V V mA V LSB LSB C
TTL-compatible
ORDERING INFORMATION TYPE NUMBER SAA7199BWP PACKAGE NAME PLCC84 DESCRIPTION plastic leaded chip carrier; 84 leads VERSION SOT189-2
1996 Sep 27
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1996 Sep 27
+5 V MPK VSSD1 to VSSD3 TP CUR 63 71 66, 70, 72, 64 1, 22, 42 53 73 VrefH VDDA4 32 KEY VDDA1 to 65 C CLUTS 3 256 8 MATRIX ENCODER RTCI 69 67 Y outputs to monitor/TV CVBS TRIPLE DACs OUTPUT BUFFERS
BLOCK DIAGRAM
+5 V
Philips Semiconductors
VDDD1 to VDDD3
3 x 8-bit input data
2, 21, 41
PD1(7 to 0)(1) (digital red)
11 to 4
PD2(7 to 0)(1) (digital green)
19 to 12
INPUT INTERFACE
Digital Video Encoder (DENC) GENLOCK-capable
PD3(7 to 0)(1) (digital blue)
31 to 24
internal control bus
68 VSSA
83 to 76 62 VrefL
CVBS(7 to 0)
LDV
20
3
CONTROL INTERFACE SYNC PROCESSING 57 33 A1 CS R/W D(7 to 0) HSY A0 to/from microcontroller HCL LFCO HSN 34 35 36 75 74 61 84 RTCI/ GPSW 46 to 43, 40 to 37 58 SLT VSN/CSYN 3 56 55 23 51 CREF CB
STATUS REGISTER
SAA7199B
47 CLOCK INTERFACE
60 59
XTALO XTALI 50 49 52 CLKSEL CLKO LLC PIXCLK CLKIN
MEH416
SDA I2C-bus SCL
48
I2C-BUS CONTROL
54
RESET
(1) RGB respectively input formats YUV and indexed colour (Tables 19 to 26).
Product specification
SAA7199B
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
PINNING SYMBOL VSSD1 VDDD1 VSN/CSYN PD1(0) PD1(1) PD1(2) PD1(3) PD1(4) PD1(5) PD1(6) PD1(7) PD2(0) PD2(1) PD2(2) PD2(3) PD2(4) PD2(5) PD2(6) PD2(7) LDV VDDD2 VSSD2 CB PD3(0) PD3(1) PD3(2) PD3(3) PD3(4) PD3(5) PD3(6) PD3(7) MPK A0 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 digital ground 1 (0 V) digital supply 1 (5 V) DESCRIPTION
SAA7199B
vertical sync output (3-state), conditionally composite sync output; active LOW or active HIGH data 1 input: digital signal R (red) respectively V signal; bit 0 (formats in Tables 19 to 25) data 1 input: digital signal R (red) respectively V signal; bit 1 (formats in Tables 19 to 25) data 1 input: digital signal R (red) respectively V signal; bit 2 (formats in Tables 19 to 25) data 1 input: digital signal R (red) respectively V signal; bit 3 (formats in Tables 19 to 25) data 1 input: digital signal R (red) respectively V signal; bit 4 (formats in Tables 19 to 25) data 1 input: digital signal R (red) respectively V signal; bit 5 (formats in Tables 19 to 25) data 1 input: digital signal R (red) respectively V signal; bit 6 (formats in Tables 19 to 25) data 1 input: digital signal R (red) respectively V signal; bit 7 (formats in Tables 19 to 25) data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 0 (formats in Tables 19 to 25) data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 1 (formats in Tables 19 to 25) data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 2 (formats in Tables 19 to 25) data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 3 (formats in Tables 19 to 25) data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 4 (formats in Tables 19 to 25) data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 5 (formats in Tables 19 to 25) data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 6 (formats in Tables 19 to 25) data 2 input: digital signal G (green) respectively Y signal or indexed colour data; bit 7 (formats in Tables 19 to 25) load data clock input signal to input interface (samples PDn(7 to 0), CB, MPK, KEY and RTCI) digital supply 2 (5 V) digital ground 2 (0 V) composite blanking input; active LOW data 3 input: digital signal B (blue) respectively U signal; bit 0 (formats in Tables 19 to 25) data 3 input: digital signal B (blue) respectively U signal; bit 1 (formats in Tables 19 to 25) data 3 input: digital signal B (blue) respectively U signal; bit 2 (formats in Tables 19 to 25) data 3 input: digital signal B (blue) respectively U signal; bit 3 (formats in Tables 19 to 25) data 3 input: digital signal B (blue) respectively U signal; bit 4 (formats in Tables 19 to 25) data 3 input: digital signal B (blue) respectively U signal; bit 5 (formats in Tables 19 to 25) data 3 input: digital signal B (blue) respectively U signal; bit 6 (formats in Tables 19 to 25) data 3 input: digital signal B (blue) respectively U signal; bit 7 (formats in Tables 19 to 25) multi-purpose key input; active HIGH subaddress bit A0 input for microcontroller access (Table 3)
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SYMBOL A1 R/W CS D0 D1 D2 D3 VDDD3 VSSD3 D4 D5 D6 D7 SDA SCL CLKIN CLKSEL PIXCLK CLKO TP RESET LLC CREF GPSW/RTCI SLT XTALI XTALO LFCO VrefL VrefH VDDA4 C VDDA1 Y VSSA CVBS VDDA2 CUR VDDA3 KEY 1996 Sep 27 PIN 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 DESCRIPTION subaddress bit A1 input for microcontroller access (Table 3) read/write not input signal from microcontroller chip select input for parallel interface; active LOW bidirectional port from/to microcontroller; bit D0 bidirectional port from/to microcontroller; bit D1 bidirectional port from/to microcontroller; bit D2 bidirectional port from/to microcontroller; bit D3 digital supply 3 (5 V) digital ground 3 bidirectional port from/to microcontroller; bit D4 bidirectional port from/to microcontroller; bit D5 bidirectional port from/to microcontroller; bit D6 bidirectional port from/to microcontroller; bit D7 I2C-bus data input/output I2C-bus clock input external clock signal input (maximum frequency 60 MHz) clock source select input CLKO/2 or conditionally CLKO output signal selected clock output signal (LLC or CLKIN) test pin; connected to ground reset input; active LOW line-locked clock input signal from external clock generation circuit (CGC) clock qualifier input of external CGC
SAA7199B
general purpose switch output (set via I2C-bus or MPU-bus); real time control input, defined by I2C or MPU programming GENLOCK output flag (3-state): HIGH = sync lost in GENLOCK mode; LOW = otherwise crystal oscillator input (26.8 or 24.576 MHz) crystal oscillator output line frequency control output signal for external CGC reference voltage LOW of DACs (resistor chains) reference voltage HIGH of DACs (resistor chains) analog supply 4 for resistor chains of the DACs (5 V) chrominance analog output signal analog supply 1 for output buffer amplifier of DAC1 (5 V) luminance analog output signal analog ground (0 V) CVBS analog output signal analog supply 2 for output buffer amplifier of DAC2 (5 V) current input for analog output buffers analog supply 3 for output buffer amplifier of DAC3 (5 V) key input signal to insert CVBS input signal into encoded CVBS output signal; active HIGH 5
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SYMBOL HSY HCL CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 HSN PIN 74 75 76 77 78 79 80 81 82 83 84 DESCRIPTION
SAA7199B
horizontal sync indicator output signal; active HIGH (3-state output to ADC) horizontal clamping output; active HIGH (3-state output) digital CVBS input signal; bit 0 digital CVBS input signal; bit 1 digital CVBS input signal; bit 2 digital CVBS input signal; bit 3 digital CVBS input signal; bit 4 digital CVBS input signal; bit 5 digital CVBS input signal; bit 6 digital CVBS input signal; bit 7 horizontal sync output; active LOW or active HIGH for 60/66/72 x PIXCLK at 12.27/13.5/14.75 MHz (3-state output)
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SAA7199B
VSN/CSYN
VDDD1
VSSD1
83 CVBS7
82 CVBS6
81 CVBS5
80 CVBS4
79 CVBS3
78 CVBS2
77 CVBS1
handbook, full pagewidth
76 CVBS0
11 PD1(7)
10 PD1(6)
PD1(5)
PD1(4)
PD1(3)
PD1(2)
PD1(1)
PD1(0)
84 HSN
75 HCL 74 HSY 73 KEY 72 VDDA3 71 CUR 70 VDDA2 69 CVBS 68 VSSA 67 Y 66 VDDA1 65 C 64 VDDA4 63 VrefH 62 VrefL 61 LFCO 60 XTALO 59 XTALI 58 SLT 57 RTCI/ GPSW 56 CREF 55 LLC 54 RESET TP 53
9
8
7
6
5
4
3
2 VSSD3 42
PD2(0) 12 PD2(1) 13 PD2(2) 14 PD2(3) 15 PD2(4) 16 PD2(5) 17 PD2(6) 18 PD2(7) 19 LDV 20 VDDD2 21 VSSD2 22 CB 23 PD3(0) 24 PD3(1) 25 PD3(2) 26 PD3(3) 27 PD3(4) 28 PD3(5) 29 PD3(6) 30 PD3(7) 31 MKP 32 A0 33 A1 34 R/W 35 CS 36 D0 37 D1 38 D2 39 D3 40 VDDD3 41 D4 43 D5 44 D6 45 D7 46 SDA 47 SCL 48 CLKIN 49 CLKSEL 50 PIXCLK 51 CLKO 52
SAA7199B
1
MEH417
Fig.2 Pin configuration.
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
FUNCTIONAL DESCRIPTION The SAA7199B is a digital video encoder that translates digital RGB, YUV or 8-bit indexed colour signals into the analog PAL/NTSC output signals Y (luminance), C (4.43/3.58 MHz chrominance) and CVBS (composite signal including sync). Four different modes are selectable (Table 18): Stand-alone mode (horizontal and vertical timings are generated) Slave mode (stand-alone unit that accepts external horizontal and vertical timing), and optional real time information for subcarrier/clock from a digital colour decoder GENLOCK mode (GENLOCK capabilities are achieved in conjunction with determined ICs) Test mode (only clock signal is required). The input data rate (pixel sequence) has an integer relationship to the number of horizontal clock cycles (Table 1). A sufficient stable external clock signal ensures correct encoding. The generated clock frequency in the GENLOCK mode may deviate by 7% depending on the reference signal which is corresponding to its input sync signal. The clock will be nominal in the GENLOCK mode when the reference signal is absent (nominal with crystal oscillator accuracy for TV time constants, and nominal 1.4% for VCR time constants). The on-chip colour conversion matrix provides "CCIR 601" code-compatible transcoding of RGB to YUV data. RGB data out of bounds, with respect to "CCIR 601" specification, can be clipped to prevent over-loading of the colour modulator. RGB data input can be either in linear colour space or in gamma-corrected colour space. YUV data must be gamma-corrected in accordance with "CCIR 601". This circuit operates primarily in a 24-bit colour space (3 x 8-bit) but can also accommodate different data formats (4 : 1 : 1, 4 : 2 : 2 and 4 : 4 : 4) plus 8-bit indexed pseudo-colour space operations (FMT-bits in Table 8). RGB CLUTs on-chip provide gamma-correction and/or other CLUT functions. They consist of programmable tables to be loaded independently, and they generate 24-bit gamma-corrected output signals from 24-bit data of one of the input formats or from 8-bit indexed pseudo-colour data.
SAA7199B
Required modulation is performed. The digital YUV data is encoded in accordance with standards "RS-170A" (composite NTSC) and "CCIR 624-4" (composite PAL-B/G). S-video output signal is available (Y/C) also some sub-standard output signals (STD-bits in Table 12). A 7.5 IRE set-up level is automatically selected in the 60 Hz mode, but not selected in the 50 Hz mode. The analog signal outputs can drive directly into terminated 75 coaxial lines, a passive external filter is recommended (Figs 3, 13 and 14). Analog post-filtering is required (LP in Fig.3). GENLOCK to an external reference signal is achieved by addition of a video ADC and a clock generator combination. Thus, the system is enabled to lock on a stable video source or to a stable VCR source (normal playback). The SAA7199B, the ADC and the clock generator combination (Fig.3) form a control loop achieving a highly stable line-locked clock. The clock has to be generated by a crystal oscillator without this availability. The GENLOCK mode is not available in a single device set-up. Control interface The SAA7199B supports a standard parallel MPU interface and the serial I2C-bus interface. The MPU has direct access to internal control registers and colour tables. Update is possible at any time, excluding coincident internal reading and external writing of the same cell (the current pixel value could be destroyed). The two interfaces of Table 2 are selected automatically. However, the I2C-bus control is inactive when the MPU interface is selected by CS = LOW. No simultaneous access may occur. I2C-bus and MPU control complement each other and have access to common registers controlled via a common internal bus. The programmer can use virtually identical programs. The internal memory space is devided into the look-up table and the control table, each with its own 8-bit address register used as a pointer for specific location. This address register is provided with auto-incrementation and can be written by only one addressing. The look-up table contains three banks of 256 bytes. Therefore, each read or write cycle must access all three banks in a pre-determined order. The support logic is part of the control interface.
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Timing (see Fig.3) The reference to generate internal clocks from LLC in GENLOCK operation with SAA7197 is CREF LLC CREF = ----------- . 2 In this event input CLKSEL is HIGH and the SRC-bit = 1. In non-GENLOCK operation the signal from CLKIN is used and LDV is clock reference (input CLKSEL = 0; SCR-bit = CPR-bit = 0). Pins LLC and CLKIN are tied together when no switching between LLC and CLKIN is applied. In Fig.3 it is assumed that LLC and CLKIN are double the pixel clock frequency of CREF and LDV respectively. CREF must be at the same frequency (or constant HIGH or LOW) when LLC is at pixel clock frequency. CPR-bit = 1 if CLKIN is at pixel clock frequency. The buffered CLKO signal is always delayed. LLC or CLKIN signals are in accordance with CLKSEL. Mapping The method of mapping external control signals on to the internal bus is simple. The MPU-bus contains the signals as shown in Table 4 (names in chip-internal nomenclature). Table 1 Pixel relationships FIELD RATE (Hz) 60 60 50 50 Access to the control interface DESCRIPTION I2C-bus serial data line (bidirectional) I2C-bus clock line MPU-bus address inputs read/write control input chip select input; I2C-bus disabled when LOW general purpose switch output (bit of control register) reset input signal; active-LOW MULTIPLES OF LINE FREQUENCY 780 858 944 864 Bit allocation
SAA7199B
The Bit Allocation Map (BAM) shows the individual control signals, used to control the different operational modes of the circuit. The I2C-bus is normally used for control. The SAA7199B also has an MPU-bus interface for direct microcontroller connection. The BAM shown in Table 6 resembles the I2C-bus type but can be also used for the parallel bus; the control registers are indexed from 00H to 0FH. Auto-incrementation is applied. Digital-to-analog converters The converters use a combination of resistor chains with low-impedance output buffers. The bottom output voltage is 200 mV to reduce integral non-linearity errors. The analog signal, without load on output pin, is between 0.2 and 2.2 V. Figure 16 shows the application for 1.23 V/75 outputs, using the serial 25 + 22 resistors. Each digital-to-analog converter has its own supply pin for the purpose of decoupling. VDDA4 is the supply voltage for the resistor chains of the three DACs. The accuracy of this supply voltage directly influences the output amplitudes. The current CUR into pin 71 is 0.3 mA (VDDA4 = 5 V; R64-71 = 20 k); a larger current improves the bandwidth but increases the integral non-linearity.
ACTIVE PIXELS PER LINE 640 (square) 720 768 720 Table 2
PIXCLK OUTPUT SIGNAL (MHz) 12.27 13.5 14.75 13.5
CRYSTAL (MHz) 26.8 24.576 26.8 24.576
SYMBOL SDA SCL A1, A0 R/W CS GPSW RESET
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Table 3 Address assignment I2C-BUS SUBADDRESS 00 01 02 03 SELECTION
SAA7199B
ADDRESS INPUTS A1 0 0 1 1 Table 4 A0 0 1 0 1
ADR-CLUT (address register of look-up tables) DATA-CLUT ADR-CTRL (index register of control table) DATA-CTRL
Signals on the internal bus SYMBOL DESCRIPTION select read/write (read = 1; write = 0) control table/look-up table (control table = 1; look-up table = 0) select data/address (data = 1; address = 0) data bus on port inputs/outputs D7 to D0 enable from control interface to synchronize data transfer Signals on the internal bus I2C-BUS INTERFACE LSB of slave address byte (read = HIGH; write = LOW) X 4 subaddresses after decoding X 4 subaddresses after decoding data bits D7 to D0 for each subaddress enable by every 9th clock of sample of SCL (control of serial-to-parallel conversion)
R/W C/T D/A DI/DO (0 to 7) EN Table 5
INTERNAL PARALLEL BUS PARALLEL INTERFACE R/W C/T A/T DI/DO (0 to 7) EN R/W (pin 35) A1 (pin 34) A0 (pin 33) D7 to D0 CS and R/W
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(1)
RTCO (from SAA7151B or SAA7191B)
CVBS1 VIN0 TDA8708A (ADC) VIN1 D(7 to 0) RESET CREF LLCA LFCO 8 SAA7197 (CGC)
CLK
GPSW LLC2A
(1)
Philips Semiconductors
CVBS2
I2C-bus controls
SDA SCL CVBS(7 to 0) HCL HSY GPSW RESET CREF RTCI (2) C LP LLC LFCO
analog outputs (passive filters optional)
Digital Video Encoder (DENC) GENLOCK-capable
data PD1(7 to 0) PD2(7 to 0) input data PD3(7 to 0)
PIXCLK HSN VSN
C
8
8
RAM INTERFACE
8
SAA7199B
Y
LP
Y
controls LDV CB
11
KEY MPK D(7 to 0) CS A1 A0 R/W SLT CLKSEL TP XTALO XTALI
CVBS
LP
CVBS
CLKO CLKIN
MHA 418
8 pixel frequency in non-GENLOCK mode (fpix or 2fpix)
controls
MPU INTERFACE
(1) Not necessary in GENLOCK mode. (2) RTCI optional (GPSW not possible).
Product specification
SAA7199B
Fig.3 System configuration.
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Table 6 Bit allocation map (I2C-bus access in Table 17) INDEX BINARY HEX D7 D6 D5 DATA BYTE D4 D3 D2 D1
SAA7199B
DF(1) D0
Input processing 0000 0000 0000 0001 0000 0010 0000 0011 00 01 02 03 VTBY TRER7 TREG7 TREB7 FMT2 TRER6 TREG6 TREB6 FMT1 TRER5 TREG5 TREB5 FMT0 TRER4 TREG4 TREB4 SCBW TRER3 TREG3 TREB3 CCIR TRER2 TREG2 TREB2 MOD1 TRER1 TREG1 TREB1 HLCK(2) GDC1 IDEL1 PSO1 MOD0 TRER0 TREG0 TREB0 OEF(2) GDC0 IDEL0 PSO0 5C XX XX XX
Sync processing 0000 0100 0000 0101 0000 0110 0000 0111 04 05 06 07 SYSEL1 SYSEL0 SCEN 0 IDEL7 0 0 IDEL6 0 GDC5 IDEL5 PSO5 VTRC GDC4 IDEL4 PSO4 NINT GDC3 IDEL3 PSO3 HPLL GDC2 IDEL2 PSO2 10 21 52 32
Control, clock and output formatter 0000 1000 0000 1001 0000 0000 1010(3) 1011(3) 08 09 0A(3) 0B(3) DD 0 0 0 KEYE BAME 0 0 SRC MPKC1 0 0 CPR MPKC0 0 0 COKI IEPI 0 0 IM RTSC 0 0 GPSW RTIN 0 0 SRSN RTCE 0 0 64 02 00 00 XX(4) 00 0C
Encoder control 0000 1100 0000 1101 0000 1110 0000 Notes 1. DF is the default value for a typical programming example: GENLOCK mode for a VCR; non-gamma-corrected RGB data (real time keying is possible). SLT will be set if there is no horizontal lock.NTSC-M standard with normal colour bandwidth and 12.2727 MHz pixel rate. CSYN signal will be provided, arriving 8 pixel clocks earlier, to compensate pipeline delay in the previous RAM interface. The encoded CVBS is 12 clocks earlier than the CVBS reference on the input of the previous ADC. The CLUTs are bypassed at MPK = HIGH in real time. 2. Read only bits. 3. Reserved. 4. Adjust as required. 1111(3) 0C 0D 0E 0F(3) CHPS7 FSCO7 0 0 CHPS6 FSCO6 0 0 CHPS5 FSCO5 0 0 CHPS4 FSCO4 CLCK(2) 0 CHPS3 FSCO3 STD3 0 CHPS2 FSCO2 STD2 0 CHPS1 FSCO1 STD1 0 CHPS0 FSCO0 STD0 0
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Table 7 Function of registers bits of Table 6 BIT Index 00 VTBY FMT2 to FMT0 SCBW CCIR MOD1 to MOD0 Index 01 TRER7 to TRER0 Index 02 TREG7 to TREG0 Index 03 TREB7 to TREB0 input formats see Table 8 chrominance bandwidth: 0 = enhanced; 1 = standard select level: 0 = DMSD2 levels; 1 = CCIR levels select mode see Table 9 test register red (read/write via MPU-bus; write only via I2C-bus) test register green (read/write via MPU-bus; write only via I2C-bus) test register blue (read/write via MPU-bus; write only via I2C-bus) FUNCTION
SAA7199B
video look-up table by-pass: 0 = not bypassed; 1 = bypassed (logically OR-ed with MPK)
Index 04 sync select see Table 10 SYSEL1 to SYSEL0 SCEN VTRC NINT HPLL OEF HLCK Index 05 GDC5 to GDC0 sync/clamping (HSY/HCL) enable: 0 = disabled (set to HIGH); 1 = enabled select TV/VTR mode: 0 = TV mode (slow); 1 = VTR mode (fast) select interlace of encoded signal: 0 = interlaced (262.5/262.5 or 312.5/312.5); 1 = non-interlaced (262/262 or 312/312 in modes 1 and 3 only) select horizontal lock: 0 = lock enabled; 1 = lock disabled (crystal reference) status bit field organization (to be read): 0 = even field; 1 = odd field status bit sync indication (to be read): 0 = locked to external sync; 1 = external sync lost GENLOCK delay compensation; note 1: data 00 to 3F equals timing of CVBS output signal which is (46 - GDC) pixel clocks = tofs earlier with respect to reference point tREF1. (tREF1 corresponds to the falling edge of the horizontal sync pulse of CVBS input signal; tofs is designated for propagation delay of external GENLOCK source, Fig.10). increment delay: update of line-locked clock frequency (Table 6, data `43' hex recommended) Phase sync in output signal, note 1: data 00 to 3F equals to active slope of HSN, VSN/CSYN is (58 - PSO) pixel clocks = tRint earlier with respect to reference point tREF2 (tREF2 corresponds to PSO = 58; tRint is designated for pipeline delay of the feeding RAM interface, Fig.10). digital video encoder disable: 0 = enabled; 1 = disabled keying enable: 0 = disabled; 1 = enabled (logically AND-connected with KEY) clock source: 0 = external system clock; 1 = DTV2 system clock clock phase reference: 0 = LDV is input (pin 20); 1 = LDV is not colour-killer: 0 = colour on; 1 = colour off (subcarrier is switched off) interrupt mask: 1 = interrupt not masked at sync lost (pin 58) 0 = interrupt masked at sync lost (pin 58) general purpose switch at bit RTIN = 1: 0 = pin 57 LOW; 1 = pin 57 HIGH software reset: 0 = no reset; 1 = reset (see "Reset" procedure) Burst amplitude indication: 0 = burst amplitude measurement is overridden; colour lock always assumed; 1 = burst amplitude is used to control the CLCK status bit, recommended for reference signal without subcarrier burst (pure black and white) in order to avoid PLL hunting. multipurpose key control: with MKP = LOW (pin 32) all functions are as given by software programming; MKP = HIGH sets in real time with respect to PDn (7 to 0); functions see Table 11 13
Index 06 IDEL7 to IDEL0 Index 07 PSO7 to PSO0 Index 08 DD KEYE SRCC CPR COKI IM GPSW SRSN Index 09 BAME
MPKC1 to MPKC0
1996 Sep 27
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
BIT IEPI RTSC FUNCTION
SAA7199B
polarity of external PAL-ID signal (H/2 signal) from RTCI input (pin 57): 0 = not inverted; 1 = inverted Real time select control: 0 = real time control HPLL increment is selected, which means, information concerning actual clock frequency from the digital colour decoder is received (SAA7151B or SAA7191B); the corresponding subcarrier frequency is calculated; 1 = real time control FSC increment with PAL-ID is selected, which means, information concerning actual subcarrier frequency and PAL-ID from the digital colour decoder is received (SAA7151B or SAA7191B). select real time control input: 0 = pin 57 is input for RTCI signal; 1 = pin 57 is port output GPSW real time control enabled: 0 = disabled; 1 = enabled (RTIN = 0) phase adjustment between chrominance output signal and reference: 00 to FF equals 0 to 358.59375 degrees in steps of 1.40625 degrees fine adjustment of subcarrier frequency in non-GENLOCK modes: 00 to 7F increasing and FF to 80 decreasing equal approximately to 450 x 10-6 of the subcarrier frequency in 256 steps lock to external chrominance (to be read): 0 = possible; 1 = not possible colour encoding standards; see Table 12 status bits to be read via I2C-bus: see Table 15 status bits to be read by microcontroller: all registers from 00 up to 0F can be read via MPU-bus, read only bits are OEF, HCLK (index 04) and CLCK (index 0E)
RTIN RTCE Index 0C CHPS7 to CHPS0 Index 0D FSC7 to FSC0 Index 0E CLCK STD3 to STD0 - - Note
1. Field blanking (Figs 11 and 12): normally, video to be encoded should not become active after the active edge of VSN or CSYN before line 22.5 at 50 Hz (line 18 at 60 Hz). Total internal field blanking is 11 lines at 50 Hz (13 lines at 60 Hz). Table 8 FMT2 0 0 0 0 1 1 1 1 Table 9 MOD1 0 0 1 1 Input formats FMT1 0 0 1 1 0 0 1 1 Select mode MOD0 0 1 0 1 GENLOCK mode stand alone mode slave mode test mode MODE FMT0 0 1 0 1 0 1 0 1 YUV 4 : 1 : 1 format; customized YUV 4 : 2 : 2 format; DMSD2 compatible YUV 4 : 2 : 2 format; customized YUV 4 : 4 : 4 format RGB 4 : 4 : 4 format reserved 8-bit indexed colour FORMAT YUV 4 : 1 : 1 format; DMSD2 compatible
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Table 10 Sync select SYSEL1 SYSEL0 0 0 1 1 0 1 0 1 CSYN (active LOW; pin 3) HSN and VSN (active LOW; pins 84 and 3) CSYN (active HIGH; pin 3) HSN and VSN (active HIGH; pins 84 and 3) SYNCHRONIZED FROM
SAA7199B
Table 11 Multi-purpose key control SET BY BITS MPKC1 0 0 1 MPKC0 0 1 X IN FUNCTION BLOCKS INPUT FORMATTER CLUTs MATRIX LEVEL MATCHING
control via CCIR bit and FMT bits bypass format 5 (RGB) CCIR level format 7 (indexed colour) CCIR level
control via FMT bits control via CCIR bit CCIR level CCIR level
active, active no indexed colour active, active no indexed colour
Table 12 Colour encoding standards STD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 STD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 STD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 STD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 STANDARD NTSC 4.43; 60 Hz; SQP (12.27 MHz) NTSC 4.43; 50 Hz; SQP (14.75 MHz) PAL-B/G 4.43; 50 Hz; SQP (14.75 MHz) NTSC 4.43; 60 Hz; CCIR (13.5 MHz) NTSC 4.43; 50 Hz; CCIR (13.5 MHz) PAL-B/G 4.43; 50 Hz; CCIR (13.5 MHz) reserved reserved PAL-M; 60 Hz; SQP (12.27 MHz) PAL-M; 60 Hz; CCIR (13.5 MHz) PAL-N; 50 Hz; CCIR (13.5 MHz) PAL-N; 50 Hz; SQP (14.75 MHz) NTSC-M; 60 Hz; SQP (12.27 MHz) NTSC-M; 60 Hz; CCIR (13.5 MHz) reserved reserved
Colour look-up tables (CLUTs) The CLUTs consist of RAM tables. The RAM tables can be loaded with X = 0 to 255 in accordance with equation 1 for the signals R, G and B. Gamma-correction (pre-distortion) by the following equation: 219 Y = NINT (b + a x X11/g); Y(X 16) = 16; Y(X 235) = 235 (equation 1) with g = 2.2: a = --------------------------------------- ; - 2.2 - 2.2 235 - 16 b = 16 - a x 16-2.2 The RAM tables are loaded via MPU-bus or via I2C-bus (Table 17).
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
I2C-bus format Table 13 I2C-bus address; see Table 14 S SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK --------
SAA7199B
DATA n
ACK
P
Table 14 Explanation of Table 13 PART S Slave address ACK Subaddress (note 2) DATA -------P Notes 1. X is the read/write control bit; X = 0 is order to write (the circuit is slave receiver); X = 1 is order to read (the circuit is slave transmitter). 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. Table 15 I2C-bus status byte (address byte B1) STATUS BYTE FUNCTION D7 Read status 0 D6 0 D5 0 D4 0 D3 FFOS D2 OEF D1 CLCK D0 HLCK START condition 1 0 1 1 0 0 0 X (note 1) acknowledge, generated by the slave subaddress byte (Table 17) data byte (Table 6) continued data bytes and ACKs STOP condition DESCRIPTION
Table 16 Function of the bits in Table 15 BIT FFOS OEF CLCK HLCK FUNCTION first field of sequence: 0 = false; 1 = first of 4 fields for NTSC (first of 8 fields for PAL). FFOS is not valid for non-interlaced signals. field organization: 0 = even field; 1 = odd field lock to external chrominance: 0 = possible; 1 = not possible sync indication: 0 = locked to external sync; 1 = external sync lost
Table 17 I2C-bus write bytes (address byte B0) ACCESS DESCRIPTION OF BYTE data bytes (auto-increment) 3 data bytes for one RGB sequence (auto-increment)
Control registers address byte B0 subaddress byte 02 index byte (00 to 0F); Table 6 CLUTs registers address byte B0 subaddress byte 00 CLUT address bytes (00 to FF)
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Modes of the SAA7199B Table 18 The four different modes of the SAA7199B MODE Stand alone Slave DESCRIPTION
SAA7199B
The SAA7199B receives a line-locked clock CLKIN and generates CSYN or HSN/VSN output signals, which trigger the RGB or the YUV source signal to provide data and composite blanking CB. The SAA7199B receives the line-locked clock CLKIN, CSYN or HSN/VSN, CB and data from an RGB or YUV source. The sync inputs are edge-sensitive; their minimum active length is 1 PIXCLK. A real time control signal RTCI is received from a digital colour decoder as an option. Horizontal and vertical sync plus colour are locked on a received CVBS reference signal. The CVBS reference signal also generates a line-locked clock by the SAA7197 clock generator. Auxiliary signals HCL and HSY plus CSYN or HSN/VSN are generated to trigger the RGB or the YUV source providing data and composite blanking CB. Similar to stand alone mode, but the contents of the test registers TRER, TREG and TREB consists of data to be encoded. VSN/CSYN and HSN outputs are in 3-state condition.
GENLOCK
Test
RELATIONSHIP BETWEEN HORIZONTAL FREQUENCY AND COLOUR SUBCARRIER FREQUENCY IN NON-GENLOCK MODE 1. Internal subcarrier frequency with n = integer PAL: fSC = fH (n/4 + 1/625) respectively fH (n/4 + 1/525) NTSC: fSC = fH (n/2) Necessary conditions: non-GENLOCK mode; RTCE = 0, FSCO = 00H; phase coupling of the two frequencies is given by a definite phase reset every 8th field at PAL (4th field at NTSC). FSCO 00H adjusts the subcarrier frequency, phase reset is disabled and phase between fSC and fH is not constant. 2. External subcarrier frequency fSC is given by RTCI real time input from a digital colour decoder Necessary conditions: Slave mode; RTCE = 1, RTSC = 1. The 8th respectively 4th field reset is enabled at FSCO = 00H (disabled at FSCO 00H). The subcarrier frequency is not influenced by FSCO bits, but is given by real time increment. 3. External HPLL increment fSC is calculated by RTCI real time input signal from a digital colour decoder. The frequency of fSC depends on the absolute crystal frequency value used by the digital colour decoder. Necessary conditions: Slave mode; RTCE = 1, RTSC = 0. The 8th respectively 4th field reset is enabled at FSCO = 00H (disabled at FSCO 00H). The subcarrier frequency is influenced by FSCO bits. The absolute phase relationship between sync and subcarrier (colour burst output) can be influenced in all three events by CHPS7 to CHPS0 register byte (index 0C).
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Data input formats
SAA7199B
One clock cycle equals 12.27 MHz, 13.5 MHz or 14.75 MHz; Cb = (B - Y) equals U; Cr = (R - Y) equals V; (n) = number of pixels. Table 19 Format 0; DMSD2 compatible YUV 4 : 1 : 1 format (FMT-bits in index 00 = 000) INPUT SIGNAL PD2(7 to 0) PD3(7) PD3(6) PD3(5) PD3(4) PD3(3 to 0) PD1(7 to 0) Y(0) Cb7(0) Cb6(0) Cr7(0) Cr6(0) CLOCK CYCLE (PIXEL SEQUENCE) 0 Y(1) Cb5(0) Cb4(0) Cr5(0) Cr4(0) 1 Y(2) Cb3(0) Cb2(0) Cr3(0) Cr2(0) 2 Y(3) Cb1(0) Cb0(0) Cr1(0) Cr0(0) 3 Y(4) Cb7(4) Cb6(4) Cr7(4) Cr6(4) not used not used 4 Y(5) Cb5(4) Cb4(4) Cr5(4) Cr4(4) 5 Y(6) Cb3(4) Cb2(4) Cr3(4) Cr2(4) 6 Y(7) Cb1(4) Cb0(4) Cr1(4) Cr0(4) 7
Table 20 Format 1; customized YUV 4 : 1 : 1 format (FMT-bits in index 00 = 001) INPUT SIGNAL PD2(7 to 0) PD3(7) PD3(6) PD3(5) PD3(4) PD3(3) PD3(2) PD3(1) PD3(0) PD1(7 to 0) Y(0) Cb7(0) Cb6(0) Cb5(0) Cb4(0) Cb3(0) Cb2(0) Cb1(0) Cb0(0) CLOCK CYCLE (PIXEL SEQUENCE) 0 Y(1) - - - - - - - - 1 Y(2) Cr7(0) Cr6(0) Cr5(0) Cr4(0) Cr3(0) Cr2(0) Cr1(0) Cr0(0) 2 Y(3) - - - - - - - - 3 Y(4) Cb7(4) Cb6(4) Cb5(4) Cb4(4) Cb3(4) Cb2(4) Cb1(4) Cb0(4) not used 4 Y(5) - - - - - - - - 5 Y(6) Cr7(4) Cr6(4) Cr5(4) Cr4(4) Cr3(4) Cr2(4) Cr1(4) Cr0(4) 6 Y(7) - - - - - - - - 7
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Table 21 Format 2; DMSD2 compatible YUV 4 : 2 : 2 format (FMT-bits in index 00 = 010) INPUT SIGNAL PD2(7 to 0) PD3(7) PD3(6) PD3(5) PD3(4) PD3(3) PD3(2) PD3(1) PD3(0) PD1(7 to 0) Y(0) Cb7(0) Cb6(0) Cb5(0) Cb4(0) Cb3(0) Cb2(0) Cb1(0) Cb0(0) CLOCK CYCLE (PIXEL SEQUENCE) 0 Y(1) Cr7(0) Cr6(0) Cr5(0) Cr4(0) Cr3(0) Cr2(0) Cr1(0) Cr0(0) 1 Y(2) Cb7(2) Cb6(2) Cb5(2) Cb4(2) Cb3(2) Cb2(2) Cb1(2) Cb0(2) 2 Y(3) Cr7(2) Cr6(2) Cr5(2) Cr4(2) Cr3(2) Cr2(2) Cr1(2) Cr0(2) 3 Y(4) Cb7(4) Cb6(4) Cb5(4) Cb4(4) Cb3(4) Cb2(4) Cb1(4) Cb0(4) not used 4 Y(5) Cr7(4) Cr6(4) Cr5(4) Cr4(4) Cr3(4) Cr2(4) Cr1(4) Cr0(4) 5 Y(6)
SAA7199B
6 Y(7) Cb7(6) Cb6(6) Cb5(6) Cb4(6) Cb3(6) Cb2(6) Cb1(6) Cb0(6)
7 Cr7(6) Cr6(6) Cr5(6) Cr4(6) Cr3(6) Cr2(6) Cr1(6) Cr0(6)
Table 22 Format 3; customized YUV 4 : 2 : 2 format (FMT-bits in index 00 = 011) INPUT SIGNAL PD2(7 to 0) PD3(7 to 0) PD1(7 to 0) Y(0) Cb(0) Cr(0) CLOCK CYCLE (PIXEL SEQUENCE) 0 Y(1) - - 1 Y(2) Cb(2) Cr(2) 2 Y(3) - - 3 Y(4) Cb(4) Cr(4) 4 Y(5) - - 5 Y(6) Cb(6) Cr(6) 6 Y(7) - - 7
Table 23 Format 4; YUV 4 : 4 : 4 format (FMT-bits in index 00 = 100) INPUT SIGNAL PD2(7 to 0) PD3(7 to 0) PD1(7 to 0) Y(0) Cb(0) Cr(0) CLOCK CYCLE (PIXEL SEQUENCE) 0 Y(1) Cb(1) Cr(1) 1 Y(2) Cb(2) Cr(2) 2 Y(3) Cb(3) Cr(3) 3 Y(4) Cb(4) Cr(4) 4 Y(5) Cb(5) Cr(5) 5 Y(6) Cb(6) Cr(6) 6 Y(7) Cb(7) Cr(7) 7
Table 24 Format 5; RGB 4 : 4 : 4 format (FMT-bits in index 00 = 101) INPUT SIGNAL PD2(7 to 0) PD3(7 to 0) PD1(7 to 0) R(0) G(0) B(0) CLOCK CYCLE (PIXEL SEQUENCE) 0 R(1) G(1) B(1) 1 R(2) G(2) B(2) 2 R(3) G(3) B(3) 3 R(4) G(4) B(4) 4 R(5) G(5) B(5) 5 R(6) G(6) B(6) 6 R(7) G(7) B(7) 7
Table 25 Format 7; indexed colour format (FMT-bits in index 00 = 111), input codes 0 to 255 are allowed, output code of CLUTs should preferably be the same as given in format 5 INPUT SIGNAL PD2(7 to 0) CLOCK CYCLE (PIXEL SEQUENCE) 0 INC(0) 1 INC(1) 2 INC(2) 3 INC(3) 4 INC(4) 5 INC(5) 6 INC(6) 7 INC(7)
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SAA7199B
Table 26 Input data levels for formats 0 to 4 and 5; EBU colour bar; 100% white equals 100 IRE intensity, 5% colour saturation for formats 1 to 4, 100% for format 5 INPUT CHANNEL Y Cb LEVEL 0 IRE 100 IRE bottom peak colourless top peak Cr bottom peak colourless top peak Y Cb 0 IRE 100 IRE bottom peak colourless top peak Cr bottom peak colourless top peak R, G and B 0 IRE 100 IRE GENLOCK INPUT DATA Table 27 Format 7; CVBS GENLOCK input data format has an 8-bit word length, the input data comes from an analog-to-digital converter (TDA8708) with gain controlled and clamped CVBS or VBS signals INPUT SIGNAL CVBS(7-0) CLOCK CYCLE (PIXEL SEQUENCE) 0 CVBS(0) 1 CVBS(1) 2 CVBS(2) 3 CVBS(3) 4 CVBS(4) 5 CVBS(5) 6 CVBS(6) 7 CVBS(7) DIGITAL LEVEL 12 230 -101 0 100 -106 0 105 16 235 44 128 212 44 128 212 16 235 offset binary 1 5 offset binary 1 0 to 4 offset binary 1 0 to 4 offset binary 1 0 to 4 two's complement 0 0 to 4 two's complement 0 0 to 4 CODE offset binary 0 CCRIR-BIT FORMAT 0 to 4
Conditions of CVBS input signal Sync bottom 0 IRE (black) 100 IRE (white) Top peak of 75% colour Bottom peak of 75% colour Note
two's complement representation corresponding to binary code -128 corresponding to binary code -64(1) corresponding to binary code 95 corresponding to binary code 95 corresponding to binary code -100
1. If exactly matched levels are required in the internal multiplexer, the value 0 IRE should correspond to -68 and 100 IRE to 82.
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
ENCODING DATA LEVELS Input data levels are transformed in three stages: In the matrix when RGB or indexed colour is applied (formats 5 and 7) In the normalizing amplifier depending on 50/60 Hz mode and CCIR-bit (index 00) In the modulator. Table 28 Y and C output levels for RGB input levels (100/100 colour bar) INPUT DATA SIGNAL R G B (R - Y) Y (B - Y) MATRIX OUTPUT DATA NORMALIZER OUTPUT DATA V(1) Y U
SAA7199B
MODULATOR OUTPUT DATA Y C(2)
Y and C output levels in 50 Hz mode (PAL) White Yellow Cyan Green Magenta Red Blue Black Blanking Burst Top sync 235 235 16 16 235 235 16 16 X(3) X(3) X(3) 235 235 235 235 16 16 16 16 X(3) X(3) X(3) 235 16 235 16 235 16 235 16 X(3) X(3) X(3) 128 146 16 34 221 240 110 128 X(3) X(3) X(3) 235 210 170 145 107 82 41 16 X(3) X(3) X(3) 128 16 166 54 202 90 240 128 X(3) X(3) X(3) 0 29 -184 -155 152 183 -30 0 X(3) 45 X(3) 421 387 332 297 245 211 154 120 X(3) X(3) X(3) 0 -132 44 -87 86 -45 131 0 X(3) -45 X(3) 421 387 332 297 245 211 154 120 120 X(3) 0 0 135 189 178 175 188 134 0 0 63 X(3)
Y and C output levels in 60 Hz mode (NTSC) White Yellow Cyan Green Magenta Red Blue Black Blanking Burst Top sync Notes 1. The V component is inverted in the PAL line. 2. The are peak values of the subcarrier signal. 3. X = not defined. 235 235 16 16 235 235 16 16 X(3) X(3) X(3) 235 235 235 235 16 16 16 16 X(3) X(3) X(3) 235 16 235 16 235 16 235 16 X(3) X(3) X(3) 128 146 16 34 221 240 110 128 X(3) X(3) X(3) 235 210 170 145 107 82 41 16 X(3) X(3) X(3) 128 16 166 54 202 90 240 128 X(3) X(3) X(3) 0 29 -184 -155 152 183 -30 0 X(3) 0 X(3) 416 385 335 303 256 225 173 142 X(3) X(3) X(3) 0 -132 44 -87 86 -45 131 0 X(3) -64 X(3) 416 385 335 303 256 225 173 142 120 X(3) 0 0 135 189 178 175 188 134 0 0 64 X(3)
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
CHROMINANCE FILTERING IN THE ENCODER 1. Decimation for 4 : 4 : 4 format input data (formats 4, 5 and 7; Fig.4).
SAA7199B
2. Interpolation for 4 : 1 : 1 input data into 4 : 2 : 2 data, also suitable to reduce the bandwidth of 4 : 2 : 2 data. This filter is controlled by the SCBW-bit (SCWB = 1 means active). 3. Interpolation at 13.5 MHz for 4 : 2 : 2 input data into 4 : 4 : 4 data before modulating baseband signals onto the colour subcarrier. Figures 5, 6 and 7 show the overall transfer characteristics of chrominance in "standard bandwidth condition" (SCBW = 1). Figures 8 and 9 show the overall transfer characteristics of chrominance in enhanced bandwidth condition (SCBW = 0), which is not possible for 4 : 1 : 1 input data. The transfer curves are slightly different at 12.27 and 14.75 MHz.
handbook, halfpage
10
MEH346
handbook, halfpage
10
MEH347
(dB) 0
(dB) 0
-10 -20 -30 -40 -50 0 0.2 0.4 0.6 f / fCLK 0.8
-10 -20 -30 -40 -50 0 2 4 6 f (MHz) 8
Fig.4
Transfer characteristics of 4 : 4 : 4 to 4 : 2 : 2 decimator.
Fig.5
Overall transfer characteristics 4 : 1 : 1 input data.
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SAA7199B
handbook, halfpage
10
MEH348
handbook, halfpage
10
MEH349
(dB) 0
(dB) 0
-10 -20 -30 -40 -50 0 2 4 6 f (MHz) 8
-10 -20 -30 -40 -50 0 2 4 6 f (MHz) 8
Fig.6
Overall transfer characteristics 4 : 2 : 2 input data (SCBW-bit = 1).
Fig.7
Overall transfer characteristics 4 : 4 : 4 input data (SCBW-bit = 1).
handbook, halfpage
10
MEH350
handbook, halfpage
10
MEH351
(dB) 0
(dB) 0
-10 -20 -30 -40 -50 0 2 4 6 f (MHz) 8
-10 -20 -30 -40 -50 0 2 4 6 f (MHz) 8
Fig.8
Overall transfer characteristics 4 : 2 : 2 input data (SCBW-bit = 0).
Fig.9
Overall transfer characteristics 4 : 4 : 4 input data (SCBW-bit = 0).
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Accuracy of matrix Evaluation of quantization errors. The RGB to YUV matrix is achieved in accordance with the following algorithm: Y = INT [(NINT(R x 2 x 0.299) + NINT(G x 2 x 0.587) + NINT(B x 2 x 0.114) / 2] U = NINT [(B - Y) x 0.57722] V = NINT [(R - Y) x 0.72955]. Errors can occur in the calculation of Y, which as a result influence the U and V outputs. The greatest positive error occurs, if in all of the three for Y calculation used ROMs the values are rounded up to 0.5 LSB, and no truncation error of 0.5 LSB is generated after summation: 0.5 LSB 3 x -------------------- = +0.75 LSB; 2 with truncation "error": 0.5 LSB 3 x -------------------- -0.5 LSB = +0.25 LSB. 2 The greatest negative error occurs at rounding off in all the three ROMs and by consecutive truncation: - 0.5 LSB 3 x ----------------------- - 0.5 LSB = -1.25 LSB. 2 As a result, the matrix error can be 1 digit, which corresponds to approximately 0.5% differential non-linearity. Estimation of noise by quantization The sum of all sqared quantization errors is SS normalized to 2203 input combinations (3-dimensional colour scale). SS = 0.187545 LSB2. Compared with noise energy for ideal quantization, SSI = 112LSB2 results in a deterioration by the conversion matrix of: D = 10 log (0.187545 x 12) = 3.5 dB (equals 0.5 bit). If SS is the sum of all squared quantization errors, normalized to 220 input combinations of a grey-scale (R = G = B), then: SS = 0.12273 LSB2. Compared with noise energy for ideal quantization, SSI = 112LSB2 results in a deterioration by the conversion matrix of: D = 10 log (0.12273 x 12) = 1.7 dB (equals 0.25 bit).
SAA7199B
Normalizing amplifiers in the luminance channel The absolute amplification error for 50 Hz non-set-up signals is 0.375%; differential non-linearity is -0.333% (equals -1 LSB). The absolute amplification error for 60 Hz set-up signals is -1.5%; differential non-linearity is -0.365% (equals -1 LSB). Normalizing amplifiers in the chrominance channel The absolute amplification error is approximately 0.5% with a truncation error of -0.5 LSB. The subcarrier amplitude for standards with luminance set-up is the same as for the standards without luminance set-up. Modulator The absolute amplification error is -0.39%; there is no truncation error. Functional timing (see Fig.10) GENLOCK MODE The encoded signal can be generated earlier with respect to CVBS7 to CVBS0 bits (offset tofs set by GDC-bits; index 05). The HSN output signal can be generated early by PSO-bits (index 07) with respect to CB to compensate for pipelining delay tRint of the RAM interface (valid also in stand alone mode). The horizontal timing is independent of active video at data inputs PDn(7 to 0). The line blanking period on the outputs is set to approximately 12 s in 50 Hz standards (11 s in 60 Hz standards). SLAVE MODE HSN pin is used as an input. The active edge of the input signal is assumed to fit to the incoming CB signal. Deviations can be compensated in the range of the GCD-bits (index 05). The tenc time is the total delay from data input to analog CVBS output; it is 55 pixel clock periods long (PIXCLK) plus the propagation delay of the LDV input register regardless of mode and colour standard. The key input signal is delay compensated with respect to PDn(7 to 0) data input. The generated vertical field and burst blanking sequences are shown in Fig.11 (50 Hz PAL) and Fig.12 (60 Hz NTSC).
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
Reset Prior to a reset all outputs are undefined. RESET = LOW sets the circuit into the slave mode. MOD1 bit = 1, MOD0-bit = 0. All other control register bits are set to zero. The outputs CSYN/VSN, HSN, SLT, HSY and HCL are automatically set to a high impedance state.The I2C-bus interface is set to a slave receiver. The D7 to D0 pins of the MPU interface are inputs during RESET = LOW. As the circuit requires an external clock signal on pin CLKIN in slave mode, the clock select signal CLKSEL (pin 50) must be LOW during RESET = LOW (pin 54). The LOW time of RESET is at least 50 pixel clock periods long. Disable chip
SAA7199B
All analog outputs are set to zero by DD-bit = 1 (index 08); while the outputs CSYN/VSN, HSN, HCL, HSY and SLT are set to a high impedance state. The internal clock is divided-by-4 at DD-bit = 1. The circuit can be disabled for any reason and it must be disabled when CLKIN exceeds 32 MHz. After setting DD-bit = 1, the CLKIN input signal can be set to a frequency of <60 MHz (modification of control registers and RAM tables is not certain). To re-enable the circuit, CLKIN must be set to a frequency <32 MHz, a hardware reset is then required to set DD-bit to zero.
handbook, full pagewidth
CVBS input signal; GENLOCK only
tREF2 HSN output signal tRint(1) t(2) CB input signal active video 0 to 640/720/780 PIXCLK PDn(7 to 0) digital input data tenc CVBS output signal tofs(3)
tREF1
MEH345-1
(1) tRint is the pipeline delay of the RAM interface adjustable from -5 to +58 pixel clocks (PIXCLK). (2) t = 125 x PIXCLK at 12.27 MHz t = 163 x PIXCLK at 14.75 MHz t = 134 x PIXCLK at 13.50 MHz in 50 Hz mode t = 122 x PIXCLK at 13.50 MHz in 60 Hz mode. (3) tofs is the propagation delay of external GENLOCK line adjustable from -17 to +46 pixel clocks.
Fig.10 Horizontal timing.
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SAA7199B
(a) full field CVBS output signal handbook, 1stpagewidth 621 622 623 624 625 1 2 3 4 5 6 7 23 24 25
(a) 3rd field CVBS output signal
VSN
CB (b) 2nd field CVBS output signal 309 310 311 312 313 314 315 316 317 318 319 320 335 336
(b) 4th field CVBS output signal
VSN CB
MEH352-1
Fig.11 Vertical field and burst blanking sequence for PAL 50 Hz mode.
1996 Sep 27
26
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SAA7199B
(a) full field CVBS output signal handbook,1st pagewidth 521 522 523 524 525 1 2 3 4 5 6 7 19 20 21
VSN
CB (b) 2nd field CVBS output signal 259 260 261 262 263 264 265 266 267 268 269 270 281 282
VSN CB
MEH353-1
Fig.12 Vertical field and burst blanking sequence for NTSC 60 Hz mode.
1996 Sep 27
27
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA1 VDDA2 VDDA3 VDDA4 VDDD1 VDDD2 VDDD3 Vdiff(GND) Vn Ptot Tstg Tamb Vesd Note 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. PARAMETER analog supply voltage 1 (pin 66) analog supply voltage 2 (pin 70) analog supply voltage 3 (pin 72) analog supply voltage 4 (pin 64) digital supply voltage 1 (pin 2) digital supply voltage 2 (pin 21) digital supply voltage 3 (pin 41) voltage difference between analog and digital ground pins (VSSA - VSSDn) voltage on all pins except grounds total power dissipation storage temperature operating ambient temperature electrostatic handling for all pins note 1 CONDITIONS MIN. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 - 0 - -65 0 -2000
SAA7199B
MAX. +7 +7 +7 +7 +7 +7 +7 100 VP 1.1 +150 70 +2000 V V V V V V V
UNIT
mV V W C C V
1996 Sep 27
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Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
CHARACTERISTICS VDDA = 4.75 to 5.25 V; VDDD = 4.5 to 5.5 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL VDDA VDDD IDDA IDDD VIL VIH ILI Ci PARAMETER analog supply voltage (pins 64, 66, 70 and 72) digital supply voltage (pins 2, 21 and 41) analog supply current IDDA1 to IDDA4 digital supply current IDDD1 to IDDD3 40 pF output load 40 pF output load CONDITIONS MIN. 4.75 4.5 - - TYP. 5.0 5.0 - - - - - - - - - - - -
SAA7199B
MAX. 5.25 5.5 60 140
UNIT V V mA mA
Data and control inputs (pins 3 to 20, 23 to 40, 43 to 46, 49, 50, 54 to 56, 59, 73 and 76 to 84) LOW level input voltage HIGH level input voltage input leakage current input capacitance data inputs CLKIN, LLC and LDV 3-state I/O LFCO output (pin 61) Vo(p-p) V61 VOL VOH Vo(p-p) Vo(min) Vo(max) Ro(int) RL B ILE DLE ICUR output voltage (peak-to-peak value) output voltage range 1.4 0 2.6 VDDD V V - - - 8 10 10 pF pF pF note 1 note 1 0 2.0 -1 0.8 +1 V A VDDD + 0.5 V
Data and other control outputs (pins 3, 51, 52, 57, 58, 60, 74 and 75) LOW level output voltage HIGH level output voltage note 2 note 2 0 2.4 - 0.6 VDDD - - - 35 - - 1.0 0.5 - V V
C, Y and CVBS analog outputs (pins 65, 67 and 69) output voltage (peak-to-peak value) minimum output voltage maximum output voltage internal serial output resistance output load resistance output signal bandwidth LF integral linearity error LF differential linearity error input current (pin 71) without load; VDDA = 5 V 2 0.2 2.2 25 - - - - 300 - - - - - V V V MHz LSB LSB A without load; VDDA = 5 V - without load; VDDA = 5 V - not tested recommendation -3 dB 9-bit data 9-bit data Fig.1; R70-71 = 20 k 18 90 10 - - - -0.5 3.0 VI = LOW or HIGH IOL = 3 mA during acknowledge -10 - 3
I2C-bus SDA and SCL (pins 47 and 48) VIL VIH II VOL IO LOW level input voltage HIGH level input voltage input current SDA LOW level output voltage SDA output current +1.5 +10 0.4 - V A V mA VDDD + 0.5 V
1996 Sep 27
29
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SYMBOL PARAMETER CONDITIONS MIN. - - - TYP.
SAA7199B
MAX.
UNIT
Crystal oscillator (see Fig.15) fn f/fn nominal frequency permissible deviation of fn 3rd harmonic; Table 1 3rd harmonic; Table 1 X1 crystal specification Tamb CL Rs Cmot Cpar Tcy(LLC) tW(CH) tr tf tcy(LDV) tsu(LDV) th(LDV) ambient temperature range load capacitance series resonance resistance motional capacitance parallel capacitance 0 8 - - - 40 70 - 80 +20% +20% C pF fF pF 24.576 - 26.8 50 - - MHz MHz 10-6
-20% 1.5 -20% 3.5 - 50 - - - - - - - - - - - -
LDV and LLC timing (pins 20 and 55) see Fig.17 LLC cycle time pulse width rise time fall time LDV cycle time LDV set-up time LDV hold time note 3 31.5 40 - - 63 4 10 - 44.5 60 5 6 89 - - ns % ns ns ns ns ns
PIXCLK and CLKO timing (pins 51 and 52) see Fig.17 td(CLK) PIXCLK and CLKO delay time 25 - - - - - - ns
PD1 to 3(7 to 0), CB, MPK, KEY and RTCI input timing (pins 4 to 19, 23 to 32, 57 and 73) see Fig.17 tSU; DAT tHD; DAT input data set-up time input data hold time 4 6 ns ns
CVBS(7 to 0), VSN/CSYN and HSN timing (pins 76 to 83, 3 and 84) see Fig.18 tSU; DAT tHD; DAT input data set-up time input data hold time 10 5 ns ns
CREF timing (pin 56) see Fig.18 tSU(CREF) th(CREF) input set-up time input hold time 10 2 ns ns
1996 Sep 27
30
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - - - TYP.
SAA7199B
MAX. - - - - - - - - - - 275 25
UNIT
MPU timing A1, A0, R/W, CS, D(7 to 0) (pins 33 to 36, 37 to 40 and 43 to 46) see Fig.19 tsu(ADD) th(ADD) tsu(R) th(R) tW(CL) tW(CH) tsu;DAT th;DAT td(Q) tZR td(ZR) td(RZ) A1 and A0 address set-up time (pins 33 and 34) A1 and A0 address hold time R/W set-up time (pin 35) R/W hold time CS pulse width LOW CS pulse width HIGH data set-up time (D7 to D0) data hold time (D7 to D0) data output hold time (D7 to D0) delay to driven ports (D7 to D0) delay to ports valid (D7 to D0) port outputs disable time (D7 to D0) note 4 note 4 write mode write mode read mode read mode read mode; note 5 read mode 4 25 4 25 95 95 80 5 5 5 - - - ns ns ns ns ns ns ns ns ns ns ns ns
Output timing (pins 3, 74, 75 and 84); see Fig.18 td Notes 1. XTALO, XTALI and TP are not characterized with respect to levels; CLKO is characterized up to 32 MHz and PIXCLK up to 16 MHz. 2. Levels are measured with load circuit. LFCO output with 10 k in parallel with 15 pF and other outputs with 1.2 k in parallel with 40 pF at 3 V (TTL load). 3. TLLC must be 63 to 89 ns at CREF = HIGH (pin 56); TLLC = 16.5 ns is only allowed if the multiplexer clock is active. 4. tPIXCLK(min) + 5 ns. 5. 3 x [t PIXCLK(min) + 5 ns]. 6. 40 ns at low supply voltage (4 V) and high temperature (70 C). output delay time minimum clock period; note 6 20 45 ns
1996 Sep 27
31
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SAA7199B
handbook, halfpage
10
MEH357
handbook, halfpage
10
MEH358
(dB) 0
(dB) 0
-10 -20 -30 -40 -50 0 2 4 6 8 f (MHz) 10
-10 -20 -30 -40 -50 0 2 4 6 8 f (MHz) 10
Fig.13 Characteristics of low-pass post-filters; without compensation of DC hold.
Fig.14 Characteristics of low-pass post-filters.; with compensation of DC hold.
handbook, full pagewidth
XTALO X1
(2)
60 SAA7199B
XTALO
60 SAA7199B
10 pF
(1)
XTALI 1 nF 10 H 20 % 10 pF
(1)
59
XTALI
59
MHA417
(a)
(b)
(1) Value depends on crystal parameters. (2) 24.576 MHz (3rd harmonic), Philips: 4322 143 05291; 26.8 MHz (3rd harmonic), Philips: 9922 520 30004.
Fig.15 Oscillator application (a) and optional external clock sync (b).
1996 Sep 27
32
agewidth
+5 V 20 k 0.1 F 0.1 F 0.1 F VrefH 63 66 71 70 72 CUR VDDA1 VDDA2 VDDA3 0.1 F 0.1 F VDDA4 64 VDDD3 41 0.1 F
1996 Sep 27
+5 V 25 65 DAC3 load 2.7 H 120 pF 75 (3) 560 pF DAC2 load analog output 1.23 V (p-p) 2.7 H 120 pF 75 (3) 560 pF DAC1 25 69 22 (3) 1.23 V (p-p) CVBS 75 (3) 1.8 H 25 67 22 (3) 1.23 V (p-p) Y 75 (3) 1.23 V (p-p) 2.7 H analog output 75 (3) 22 (3) 1.23 V (p-p) C
0.1 F
0.1 F
0.1 F
VDDD1
VDDD2
Philips Semiconductors
2
21
external output filters
Digital Video Encoder (DENC) GENLOCK-capable
25
22 (3)
(1)
digital input and output signals of Fig.1
390 pF
33
SAA7199B
1 22 VSSD2 VrefL VSSD3 VSSD1 42 62
25
22 (3)
(2)
390 pF
68 VSSA
MEH420
(1) Without compensation of the DAC hold characteristic (see Fig.13).
sin ( x ) (2) With compensation of the DAC hold characteristic ----------------- correction (see Fig.14). x
(3) Output amplitude determined by load resistors RL > 90 .
Product specification
SAA7199B
Fig.16 Application details of Fig.1 showing proposals of analog low-pass post-filtering of output signals.
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SAA7199B
handbook, full pagewidth
tf 2.0 V input clocks LLC and CLKIN 1.5 V 0.8 V tw(CH) Tcy(LLC); Tcy(CLKIN) th(LDV) tsu(LDV)
tr
2.0 V input data clock LDV 1.5 V 0.8 V
tSU; DAT tHD; DAT
inputdata PDn(7 to 0) CB, MPK, KEY and RTCI (pin 57)
2.0 V data valid 0.8 V
td(CLK) PIXCLK
CLKO and PIXCLK CLKO
MEH421
Fig.17 LDV input data timing.
1996 Sep 27
34
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SAA7199B
handbook, full pagewidth
tf
tr 2.0 V
input clock LLC
1.5 V 0.8 V tw(CH) Tcy(LLC) th(CREF) tsu(CREF) 2.0 V
input CREF
1.5 V 0.8 V
td
outputs HCL, HSY, HSN, VSN and CSYN
2.4 V data valid 0.6 V data valid
tSU; DAT tHD; DAT
2.0 V input data CVBS(7 to 0) data valid 0.8 V
MEH355
Fig.18 Clock and data timing.
1996 Sep 27
35
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SAA7199B
handbook, full pagewidth
tW(CL) 2.0 V
input CS
1.5 V 0.8 V tW(CH) tsu(ADD) th(ADD)
inputs A1 and A0
1.5 V
data valid
tsu(R)
th(R)
input R/W
1.5 V
tsu;DAT
th;DAT
write D (7 to 0)
1.5 V
data valid
td(DR) td(ZR)
td(RZ) td(Q)
read D (7 to 0)
1.5 V
data valid
MEH356
Fig.19 MPU-bus timing.
1996 Sep 27
36
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
PACKAGE OUTLINE PLCC84: plastic leaded chip carrier; 84 leads
SAA7199B
SOT189-2
eD y 74 75 X 54 53 Z E A
eE
bp b1 wM 84 HE A A4 A1 (A 3) k1 Lp detail X 12 e D HD 0 5 scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
1
pin 1 index e
E
k
11 32 ZD
33
vM A B vMB 10 mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
29.41 29.41 28.70 28.70 30.35 30.35 1.22 1.27 29.21 29.21 27.69 27.69 30.10 30.10 1.07
45 o
0.180 inches 0.020 0.01 0.165
1.130 1.130 1.195 1.195 0.048 0.057 0.021 0.032 1.158 1.158 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 1.090 1.090 1.185 1.185 0.042 0.040 0.013 0.026 1.150 1.150
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT189-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1996 Sep 27
37
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA7199B
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Sep 27
38
Philips Semiconductors
Product specification
Digital Video Encoder (DENC) GENLOCK-capable
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7199B
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Sep 27
39
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 615 800, Fax. +358 615 80920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. +30 1 4894 339/911, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657021/1200/02/pp40
Date of release: 1996 Sep 27
Document order number:
9397 750 01285

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