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Advance Information
This document contains information on a product under development. The parametric information contains target parameters that are subject to change.
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
The CX28333 is a three-channel, E3/DS3/STS-1 fully-integrated Line Interface Unit (LIU). It is configured via external pins and does not need a microprocessor interface. Each channel has an independent equalizer on the receive side requiring no user configuration. Also, each channel has a programmable transmit pulse shaper that can be set to ensure that the cross-connect pulse mask requirement is met for transmit cable length up to 450 feet. The CX28332 is a dual-channel, and the CX28331 is a single-channel LIU with performance identical to the CX28333. The CX28333 gives the user new economies of scale in concentrator applications where three DS3 or STS-1 channels are concentrated into a single STS-3 channel. By including three independent transceivers on a chip, significant external components are eliminated, with the exception of 1:1 coupling transformers, termination resistors, and supply bypass capacitors.
NOTE:
Distinguishing Features
* Can be used as a data transceiver over a maximum of 900 feet of Type 734/728 coaxial cable or equivalent in an on-premise environment Programmable pulse filtering to meet cross-connect pulse masks (ANSI T1.102-1993) Meets jitter specifications of Bellcore GR499, GR253, and TBR24 (with external JAT). Large input dynamic range Alarms for coding violation and loss of signal Full diagnostic loopback capability Uses a minimum of external components Compatible with ITU-T G.703, G.823 Independent power down mode per channel Easily interfaced to the DS3/E3 Framer IC (CX28342/3/4/6/8 and CN8330) Selectable B3ZS/HDB3 encoding/decoding Superior input receiver sensitivity (< 25 mV) Transmit monitor inputs (CX2833i-3x series only)
*
*
* * * * * * *
In this document, "i" is used to represent the number of channels: i = 1 (CX28331), i = 2 (CX28332), and i = 3 (CX28333).
Functional Block Diagram
XOE LBO E3MODE PDB
* * *
TPOS TNEG TCLK TAIS
PDATA/ NDATA ENCODER TCLK
Pulse Shaper
LINE DRIVER
TLINEP TLINEM/N
Physical Characteristics
* * * * * * 80- and 100-pin ETQFP package Single 3.3 V power supply 1 W maximum power dissipation (CX28333) -40 C to +85 C temperature range 5 V-tolerant pins TTL digital pins
ENDECDIS
TX Monitor
TMONP TMONM TXMON TMONTST REFCLK
RLOOP LLOOP
DATA MUX
Applications
RPOS RNEG RCLK RLOS DECODER PDATA Clock/ NDATA Data DATCLK Recovery P N Receiver RLINEP RLINEM/N
ALOS
REQH LIU #1 LIU #2 LIU #3
* * * * * * *
Digital Cross-Connect Systems Routers ATM Switches Channelized Line Aggregation Units Test Equipment Channel Service Units Multiplexers
NOTE(S): The TX Monitor is only used with the 100-pin CX2833i-3X.
Data Sheet
100985A June 2, 2000
CX28333EVM
TX B3ZS/HDB3 analog out NRZTX DATA and CLK in CH1 NRZRX DATA and CLK out F R A M E R S I D E CH1 RX B3ZS/HDB3 analog in TX B3ZS/HDB3 analog out NRZTX DATA and CLK in CH2 NRZRX DATA and CLK out L I N E S I D E
CX28333
CH2 RX B3ZS/HDB3 analog in TX B3ZS/HDB3 analog out
NRZTX DATA and CLK in CH3 NRZRX DATA and CLK out Loss of Signal Code Violation CH3 RX B3ZS/HDB3 analog in Clock Input Control
100985_002
(c) 2000, Conexant Systems, Inc.
All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Conexant's Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: ConexantTM, the Conexant C symbol, and "What's Next in Communications Technologies"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Conexant's Legal Information posted at www.conexant.com, which is incorporated by reference. Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer.
100985A
Conexant
Ordering Information
Model Number CX28331-1x CX28332-1x CX28333-1x CX28331-3x CX28332-3x CX28333-3x Package 80-Pin ETQFP 80-Pin ETQFP 80-Pin ETQFP 100-Pin ETQFP 100-Pin ETQFP 100-Pin ETQFP Description Single-channel LIU Dual-channel LIU Triple-channel LIU Single channel with Transmit Monitoring Dual channel with Transmit Monitoring Triple channel with Transmit Monitoring Operating Temperature
-40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C
Revision History
Revision A Level -- Date May 5, 2000 Initial Release Description
100985A
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100985A
Conexant
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 2.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.4 2.5 2.4.1 2.5.1 2.5.2 2.5.3 2.6 2.7 AMI B3ZS/HDB3 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3.1 Transmit Pulse Mask Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Alarm Indication Signal (AIS) Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Transmit Monitor Block (CX2833i-3x Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Jitter Generation (Intrinsic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Receive Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC/VGA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The PLL Clock Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss Of Signal (LOS) Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B3ZS/HDB3 Decoder With Bipolar Violation Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Squelching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-10 2-10 2-10 2-11 2-11 2-11 2-12
Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Jitter Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Loopback Multiplexers (MUXes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Additional CX28331/CX28332/CX28333 Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
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Table of Contents
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.7.1 2.7.2 2.8 2.9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
3.0
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 PCB Design Considerations for CX28331/CX28332/CX28333 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 Power Supply and Ground Plane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Other Passive Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Recommended Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1 Evaluation Module Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
vi
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100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
List of Figures
List of Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 3-1. Figure B-1. Figure B-2. Figure B-3. CX28331-1x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 CX28332-1x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 CX28333-1x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 CX28331-3x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 CX28332-3x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 CX28333-3x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Typical Application Of Single CX2833i Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Pulse Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Transmit Pulse Mask for DS3 Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Transmit Pulse Mask for STS-1 Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Transmit Pulse Mask for E3 Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 AIS Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Minimum Jitter Tolerance Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Maximum Jitter Transfer Curve Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 CX2833i-1x Mechanical Drawing (80-Pin)--Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 CX2833i-3x Mechanical Drawing (100-Pin)--Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Typical CX28333 Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Recommended Schematic for the CX2833i-1x Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Recommended Schematic for the CX2833i-3x Device (1 of 2) . . . . . . . . . . . . . . . . . . . . . . B-3 Recommended Schematic for the CX2833i-3x Device (2 of 2) . . . . . . . . . . . . . . . . . . . . . . B-4
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List of Figures
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
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CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
List of Tables
List of Tables
Table 1-1. Table 1-2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. CX28331/CX28332/CX28333 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 CX2833i-3x Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 DS3 Transmit Template Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 STS-1 Transmit Template Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 AC Characteristics (Logic Timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
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List of Tables
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
x
Conexant
100985A
1
1.0 Pin Description
1.1 Pin Assignments
Figures 1-1 (CX28331-1x), 1-2 (CX28332-1x), and 1-3 (CX28333-1x) illustrate pin assignments for the 80-pin Exposed Thin Quad Flat Package (ETQFP). See Table 1-1 for the CX2833i-1x pin descriptions. Figures 1-4 (CX28331-3x), 1-5 (CX28332-3x), and 1-6 (CX28333-3x) illustrate pin assignments for the 100-pin ETQFP. The 100-pin package adds more functionality, supporting new features such as Transmit Monitoring and Transmit Monitoring Status testing. See Table 1-2 for the CX2833i-3x pin descriptions. The input/output (I/O) column is coded as follows: I = Input O = Output I/O = Bidirectional P = Power
NOTE:
All digital inputs and outputs contain 75 k pull-down resistors.
When a channel is disabled (i.e., the PDx pin is tied low or not connected), all receive and transmit analog circuitry powers down. Analog inputs (RLINE) are ignored and analog outputs (TLINE) are high impedance. Digital inputs of a powered-down channel are still active, but ignored. Overall noise on the device can be lowered by not driving the digital inputs of a powered-down channel.
NOTE:
When power is disconnected from the device, TLINE pins are low impedance to ground if driven by more than one forward-bias diode voltage (0.7 V) below ground. Additionally, driving TLINE, a forward-bias diode voltage above the VGG pin, creates a low impedance path from the TLINE pin to the VGG pin. Otherwise, the TLINE pins are high impedance.
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1-1
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 1-1. CX28331-1x Pin Diagram
DVDDIO
RESET
RBIAS
VGG
GPD
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
VSS NC NC VDD VDD NC NC VSS TVSS TLINEP TLINEN TVDD RVDD RLINEP RLINEN RVSS VSS NC NC VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
61 60 59 58 57 56 55 54 53 52 51
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DVDDC ENDECDIS PD RLOOP LLOOP RNEG/RLCV RPOS/RNRZ RCLK RLOS TAIS TCLK TPOS/TNRZ TNEG/NC REFCLK REQH XOE LBO E3MODE NC DVSSC
CX28331-1x
50 49 48 47 46 45 44 43 42 41
NC
VDD
DVSSIO
NC
NC
NC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 1-2. CX28332-1x Pin Diagram
1.0 Pin Description
1.1 Pin Assignments
RPOS1/RNRZ1
RNEG1/RLCV1
TPOS1/TNRZ1
TNEG1/NC1
REFCLK1
RLOOP1
LLOOP1
DVDDIO
REQH1
RESET
RLOS1
RCLK1
TCLK1 62
RBIAS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
TVSS1 TLINE1P TLINE1N TVDD1 RVDD1 RLINE1P RLINE1N RVSS1 VSS NC NC VDD VDD NC NC VSS TVSS2 TLINE2P TLINE2N TVDD2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
61 60 59 58 57 56 55 54 53 52 51
TAIS1
XOE1
LBO1
VGG
GPD
PD1
DVDDC ENDECDIS NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC E3MODE NC DVSSC
CX28332-1x
50 49 48 47 46 45 44 43 42 41
RVDD2
RLINE2P
PD2
DVSSIO
XOE2
RNEG2/RLCV2
RPOS2/RNRZ2
RLINE2N
RVSS2
REQH2
REFCLK2
RLOOP2
RCLK2
RLOS2
TNEG2/NC2
LLOOP2
TPOS2/TNRZ2
TCLK2
TAIS2
LBO2
100985_004
100985A
Conexant
1-3
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 1-3. CX28333-1x Pin Diagram
RPOS1/RNRZ1
RNEG1/RLCV1
TPOS1/TNRZ1
TNEG1/NC1
REFCLK1
RLOOP1
LLOOP1
DVDDIO
REQH1
RESET
RLOS1
RCLK1
TCLK1 62
RBIAS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
61
TAIS1
XOE1
LBO1
VGG
GPD
PD1
TVSS1 TLINE1P TLINE1N TVDD1 RVDD1 RLINE1P RLINE1N RVSS1 TVSS2 TLINE2P TLINE2N TVDD2 RVDD2 RLINE2P RLINE2N RVSS2 TVSS3 TLINE3P TLINE3N TVDD3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 59 58 57 56 55 54 53 52
DVDDC ENDECDIS PD2 RLOOP2 LLOOP2 RNEG2/RLCV2 RPOS2/RNRZ2 RCLK2 RLOS2 TAIS2 TCLK2 TPOS2/TNRZ2 TNEG2/NC2 REFCLK2 REQH2 XOE2 LBO2 E3MODE NC DVSSC
CX28333-1x
51 50 49 48 47 46 45 44 43 42 41
RVDD3
RLINE3P
PD3
DVSSIO
XOE3
RNEG3/RLCV3
RPOS3/RNRZ3
RLINE3N
RVSS3
REQH3
REFCLK3
RLOOP3
RCLK3
RLOS3
TNEG3/NC3
LLOOP3
TPOS3/TNRZ3
TCLK3
TAIS3
LBO3
100985_005
1-4
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CX2833i-1x Pin Definitions (1 of 6) Pin # Signal Name CX28331-1x CX28332-1x CX28333-1x Coaxial Line Pins
14 -- 15 -- -- -- -- -- 10 -- 11 -- -- -- -- -- -- 6 -- 7 22 23 -- -- -- 2 -- 3 18 19 -- -- -- 6 -- 7 14 15 22 23 -- 2 -- 3 10 11 18 19 RLINEP RLINE1P RLINEN RLINE1N RLINE2P RLINE2N RLINE3P RLINE3N TLINEP TLINE1P TLINEN TLINE1N TLINE2P TLINE2N TLINE3P TLINE3N Ch1 positive receive data Ch1 negative receive data Ch2 positive receive data Ch2 negative receive data Ch3 positive receive data Ch3 negative receive data Ch1 positive transmit data Ch1 negative transmit data Ch2 positive transmit data Ch2 negative transmit data Ch3 positive transmit data Ch3 negative transmit data I
1.0 Pin Description
1.1 Pin Assignments
Description
I/O/P
Notes
I
I I I I O
Differential inputs for each channel from its respective receive coax line. The RX expects balanced differential inputs, usually achieved using a 1:1 transformer. The inputs are internally DC biased to 1.9 V.
O
Differential, coax-driver balanced outputs for pulse-shaped AMI B3ZS/HDB3 encoded waveforms for each channel. These pins should be connected to the primary side of the 1:1 transformer through two backmatch resistors (see Appendix B).
O O O O
100985A
Conexant
1-5
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CX2833i-1x Pin Definitions (2 of 6) Pin # Signal Name CX28331-1x CX28332-1x CX28333-1x Digital Data Pins
54 -- 55 -- -- -- -- -- 53 -- -- -- 49 -- 48 -- -- -- -- -- -- 68 -- 69 33 32 -- -- -- 67 34 -- -- 63 -- 64 38 37 -- -- -- 68 -- 69 54 55 33 32 -- 67 53 34 -- 63 -- 64 49 48 38 37 RPOS/ RNRZ RPOS1/ RNRZ1 RNEG/ RLCV RNEG1/ RLCV1 RPOS2/ RNRZ2 RNEG2/ RLCV2 RPOS3/ RNRZ3 RNEG3/ RLCV3 RCLK RCLK1 RCLK2 RCLK3 TPOS/ TNRZ TPOS1/ TNRZ1 TNEG/ NC TNEG1/ NC1 TPOS2/ TNRZ2 TNEG2/ NC2 TPOS3/ TNRZ3 TNEG3/ NC3 Ch2 transmit Positive or NRZ data Ch2 transmit Negative rail or no connect data Ch3 transmit Positive or NRZ data Ch3 transmit Negative rail or no connect data I I I I Ch1 transmit Negative rail or no connect data I Receive clock Ch2 Receive clock Ch3 Ch1 transmit Positive rail or NRZ data O O I Synchronized transmit data intended to be strobed in by the corresponding TCLK. Ch2 receive Positive rail or NRZ data Ch2 receive Negative rail or line code violation Ch3 receive Positive rail or NRZ data Ch3 receive Negative rail or line code violation Receive clock Ch1 O O O O O Recovered clock for each channel receiver, intended for strobing the corresponding RDAT into the following framer or logic. Ch1 receive Negative rail or line code violation O Ch1 receive Positive rail or NRZ data O Resynchronized receive data intended to be strobed out by the corresponding RCLK. When ENDECDIS = 1, these outputs are positive and negative AMI data (RPOS and RNEG). When ENDECDIS = 0, these outputs are decoded NRZ data (RNRZ) and line code violation (RLCV). A line code violation is indicated when RLCV = 1.
Description
I/O/P
Notes
See notes on the ENDECDIS pin in the Control Signals section.
When ENDECDIS = 1, these inputs are expected to be positive and negative AMI data (TPOS and TNEG). When ENDECDIS = 0, these inputs are expected to be uncoded NRZ data (TNRZ) and no connects (NC). See notes on the ENDECDIS pin in the Control Signals section.
1-6
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CX2833i-1x Pin Definitions (3 of 6) Pin # Signal Name CX28331-1x CX28332-1x CX28333-1x
50 -- -- -- 52 -- -- -- -- 62 39 -- -- 66 35 -- -- 62 50 39 -- 66 52 35 TCLK TCLK1 TCLK2 TCLK3 RLOS RLOS1 RLOS2 RLOS3 Loss of signal Ch2 Loss of signal Ch3 O O Transmit clock Ch2 Transmit clock Ch3 Loss of signal Ch1 I I O Transmit clock Ch1 I
1.0 Pin Description
1.1 Pin Assignments
Description
I/O/P
Notes
Transmit bit clock input for strobing with transmit data into the CX2833i.
Loss Of Signal (LOS) indication for each channel, as determined by insufficient pulse density. Signal loss detected when RLOS = 1. An LOS will be asserted when 175 75 0s occur in a row and deasserted when the pulse density is between 28% and 33% (DS3/STS-1) (i.e., a 1s density).
Control Signals
59 59 59 ENDECDIS Encoder/decoder disable (for all channels) I 1 = Dual rail pulse coded data format. Input transmit data pins TPOS, TNRZ, TNEG and NC are interpreted as TPOS and TNEG (encoded positive and negative rail data). Output receive data pins RPOS and RNRZ, and RNEG and RLCV are interpreted as RPOS and RNEG, with RPOS having a positive pulse in place of every positive AMI pulse and RNEG having a negative pulse in place of every negative AMI pulse. 0 = NRZ format. Transmit data pins TPOS and TNEG are interpreted as TNRZ and NC (not connected). Receive data pins RPOS and RNEG are interpreted as RNRZ and RLCV. In this mode, all line code violations are reported as active high on RLCV. Transmission of Alarm Indication Signal (AIS) for a given channel. Replace transmit data with AIS signal. The AMI form of AIS supported is alternating 1s. (+1, -1, +1, -1, +1, ...) Looping takes precedence over AIS. 1 = AIS mode enabled 0 = AIS mode disabled
51 -- -- --
-- 61 40 --
-- 61 51 40
TAIS TAIS1 TAIS2 TAIS3
Transmit Ch1 AIS mode enable Transmit Ch2 AIS mode enable Transmit Ch3 AIS mode enable
I
I I
100985A
Conexant
1-7
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CX2833i-1x Pin Definitions (4 of 6) Pin # Signal Name CX28331-1x CX28332-1x CX28333-1x
43 43 43 E3MODE E3MODE I When the pin is set to high, it enables the E3 mode on all channels, instead of the DS3/STS-1 mode. This also changes the pulse shaper to E3 mode and overrides all LBO pins. It also changes the encoder/decoder from B3ZS mode to HDB3 mode. 1 = E3 mode 0 = DS3/STS-1 mode Line build-out mode per channel, based on the length of cable on the transmit side of the cross-connect block. This bit is overridden and the pulse shaper is disabled (no pulse shaping) if E3MODE = 1. 1 = Inserts line build-out into the transmit channel. Usually used when the transmit cable is less than 350 feet in length. 0 = Line build-out bypassed (not inserted). Usually used when the transmit cable is greater than 350 feet in length. Local loopback enable per channel. The transmit data is looped back immediately from the encoder to the decoder in place of the received data. 1 = local loopback enabled 0 = local loopback disabled Remote loopback enable per channel. The receive data, retimed after clock recovery, is looped back into the AMI generator in place of the transmit data. 1 = remote loopback enabled 0 = remote loopback disabled Transmit output enable per channel. 1 = transmit line output driver enabled 0 = transmit output driver set to high impedance state
Description
I/O/P
Notes
44 -- -- --
-- 72 29 --
-- 72 44 29
LBO LBO1 LBO2 LBO3
Transmit line Ch1 build-out mode Transmit line Ch2 build-out mode Transmit line Ch3 build-out mode
I
I I
56 -- -- -- 57 -- -- -- 45 -- -- --
-- 74 27 -- -- 75 26 -- -- 71 30 --
-- 74 56 27 -- 75 57 26 -- 71 45 30
LLOOP LLOOP1 LLOOP2 LLOOP3 RLOOP RLOOP1 RLOOP2 RLOOP3 XOE XOE1 XOE2 XOE3
Local loopback enable Ch1 Local loopback enable Ch2 Local loopback enable Ch3 Remote loopback enable Ch1 Remote loopback enable Ch2 Remote loopback enable Ch3 Transmit output enable Ch1 Transmit output enable Ch2 Transmit output enable Ch3
I
I I I
I I I
I I
1-8
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CX2833i-1x Pin Definitions (5 of 6) Pin # Signal Name CX28331-1x CX28332-1x CX28333-1x
46 -- -- -- -- 70 31 -- -- 70 46 31 REQH REQH1 REQH2 REQH3 Ch1 Receive High EQ Gain Enable Ch2 Receive High EQ Gain Enable Ch3 Receive High EQ Gain Enable I I
1.0 Pin Description
1.1 Pin Assignments
Description
I/O/P
Notes
The equalizer in the CX2833i has two gain settings. The higher gain setting is designed to optimally equalize a nominally-shaped (meets the pulse template), pulse-driven DS3 or STS-1 waveform that is driven through 0-900 feet of cable. Square-shaped pulses such as E3 or DS3-HIGH require less high-frequency gain and should use the low EQ gain setting. REQH = 1 high EQ gain (DS3/STS-1 modes) REQH = 0 low EQ gain (E3/DS3 Square Modes)
Power/Ground
12 -- -- -- 9 -- -- -- 13 -- -- -- 16 -- -- -- 60 41 79 -- 4 20 -- -- 1 17 -- -- 5 21 -- -- 8 24 -- 60 41 79 -- 4 12 20 -- 1 9 17 -- 5 13 21 -- 8 16 24 60 41 79 TVDD TVDD1 TVDD2 TVDD3 TVSS TVSS1 TVSS2 TVSS3 RVDD RVDD1 RVDD2 RVDD3 RVSS RVSS1 RVSS2 RVSS3 DVDDC DVSSC VGG RX ground Ch2 RX ground Ch3 Digital core power Digital core ground 5 V/3.3 V ESD pin (1) P P P P P Connect to ground. Digital core power for all channels (3.3 V). Digital core ground for all channels. 5 V supply for 5 V-tolerant, digital pad ESD diodes. No static power is drawn from pin. Connect to 3.3 V digital power. Digital ground. RX power Ch2 RX power Ch3 RX ground Ch1 P P P Connect to 3.3 V power. Ground pins for receive circuitry per channel. TX ground Ch2 TX ground Ch3 RX power Ch1 P P P Power pins for receive circuitry per channel (3.3 V). TX power Ch2 TX power Ch3 TX ground Ch1 P P P Ground pins for transmit circuitry per channel. TX power Ch1 P Power pins for transmit circuitry per channel (3.3 V).
73 28
73 28
73 28
DVDDIO DVSSIO
Digital I/O power Digital ground
P P
100985A
Conexant
1-9
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-1. CX2833i-1x Pin Definitions (6 of 6) Pin # Signal Name CX28331-1x CX28332-1x CX28333-1x
4, 5, 20, 21 1, 8, 17, 24 12, 13 9, 16 -- -- VDD VSS Power Ground P P Connect to 3.3 V power. Connect to ground.
Description
I/O/P
Notes
Miscellaneous
58 -- -- -- -- 76 25 -- -- 76 58 25 PD PD1 PD2 PD3 Power down for Ch2 Power down for Ch3 I I Power down for Ch1 I Power down transceiver channel 0 = Power down channel (off) 1 = Channel active (on) Note: A special power-down mode exists when all three PDBs are set low. This special mode shuts off the entire chip (including biasing). This is useful for static Idd testing. Reference clock from off-chip. This clock should be set to one of the following: * E3 rate (34.368 MHz) * DS3 rate (44.736 MHz) * STS-1 rate (51.84 MHz) The clock rate should correspond to the mode of operation that has been chosen for the channel. A 12.1 k 1% resistor tied from this pin to ground provides the current reference to the entire chip.(2) Asynchronous reset (reset entire device). Power down (Static Idd testing). 0 = Power down disable 1 = Power down active Not connected.
47 -- -- --
-- 65 36 --
-- 65 47 36
REFCLK REFCLK1 REFCLK2 REFCLK3
Reference clock for Ch1
I
Reference clock for Ch2 Reference clock for Ch3
I I
80
80
80
RBIAS
Bias resistor
O
78 77
78 77
78 77
Reset GPD
Reset Global Power down
I/O I/O
2, 3, 6, 7, 18, 19, 22, 23, 25, 26, 27, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 42, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76
NOTE(S):
(1) (2)
10, 11, 14, 15, 42, 44-58
42
NC
No connect
--
This pin should be connected to 3.3 V in an all-3.3 V design. Placing a capacitor from this pin to ground may result in instabilities. 3. All digital input pins contain a 75 k pull-down resistor from input to DVSS.
1-10
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1.0 Pin Description
1.1 Pin Assignments
Figure 1-4. CX28331-3x Pin Diagram
NC NC NC NC VDD VDD NC NC VSS TVSS TMONP TLINEP TLINEM TMONM TVDD RVDD RLINEP RLINEM RVSS VSS NC NC NC NC VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VSS RBIAS VGG RESET GPD NC NC NC DVDDIO NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
CX28331-3x
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DVDDC ENDECDIS PD RLOOP LLOOP RNEG/RLCV RPOS/RNRZ RCLK RLOS NC NC NC TAIS TCLK TPOS/TNRZ TNEG/NC TLOS REFCLK REQH XOE LBO TMONTST E3MODE NC DVSSC
VDD NC NC VSS NC NC NC DVSSIO NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100985_015
100985A
Conexant
1-11
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 1-5. CX28332-3x Pin Diagram
TMON1P TLINE1P TLINE1M TMON1M TVDD1 RVDD1 RLINE1P RLINE1M RVSS1 VSS NC NC NC NC VDD VDD NC NC VSS TVSS2 TMON2P TLINE2P TLINE2M TMON2M TVDD2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TVSS1 RBIAS VGG RESET GPD PD1 RLOOP1 LLOOP1 DVDDIO LBO1 XOE1 REQH1 NC NC NC RNEG1/RLCV1 RPOS1/RNRZ1 RCLK1 RLOS1 REFCLK1 TLOS1 TNEG1/NC1 TPOS1/TNRZ1 TCLK1 TAIS1
CX28332-3x
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DVDDC ENDECDIS NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC TMONTST E3MODE NC DVSSC
RVDD2 RLINE2P RLINE2M RVSS2 PD2 RLOOP2 LLOOP2 DVSSIO LBO2 XOE2 REQH2 NC NC NC RNEG2/RLCV2 RPOS2/RNRZ2 RCLK2 RLOS2 REFCLK2 TLOS2 TNEG2/NC2 TPOS2/TNRZ2 TCLK2 TAIS2 NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100985_016
1-12
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 1-6. CX28333-3x Pin Diagram
1.0 Pin Description
1.1 Pin Assignments
TMON1P TLINE1P TLINE1M TMON1M TVDD1 RVDD1 RLINE1P RLINE1M RVSS1 TVSS2 TMON2P TLINE2P TLINE2M TMON2M TVDD2 RVDD2 RLINE2P RLINE2M RVSS2 TVSS3 TMON3P TLINE3P TLINE3M TMON3M TVDD3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TVSS1 RBIAS VGG RESET GPD PD1 RLOOP1 LLOOP1 DVDDIO LBO1 XOE1 REQH1 NC NC NC RNEG1/RLCV1 RPOS1/RNRZ1 RCLK1 RLOS1 REFCLK1 TLOS1 TNEG1/NC1 TPOS1/TNRZ1 TCLK1 TAIS1
CX28333-3x
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DVDDC ENDECDIS PD2 RLOOP2 LLOOP2 RNEG2 / RLCV2 RPOS2 / RNRZ2 RCLK2 RLOS2 NC NC NC TAIS2 TCLK2 TPOS2/TNRZ2 TNEG2/NC2 TLOS2 REFCLK2 REQH2 XOE2 LBO2 TMONTST E3MODE NC DVSSC
RVDD3 RLINE3P RLINE3M RVSS3 PD3 RLOOP3 LLOOP3 DVSSIO LBO3 XOE3 REQH3 NC NC NC RNEG3/RLCV3 RPOS3/RNRZ3 RCLK3 RLOS3 REFCLK3 TLOS3 TNEG3/NC3 TPOS3/TNRZ3 TCLK3 TAIS3 NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100985_006
100985A
Conexant
1-13
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-2. CX2833i-3x Pin Definitions (1 of 8) Pin # Signal Name CX28331-3x CX28332-3x CX28333-3x Coaxial Line Pins
17 -- 18 -- -- -- -- -- 12 -- 13 -- -- -- -- -- -- 7 -- 8 27 28 -- -- -- 2 -- 3 22 23 -- -- -- 7 -- 8 17 18 27 28 -- 2 -- 3 12 13 22 23 RLINEP RLINE1P RLINEM RLINE1M RLINE2P RLINE2M RLINE3P RLINE3M TLINEP TLINE1P TLINEM TLINE1M TLINE2P TLINE2M TLINE3P TLINE3M Ch1 positive receive data Ch1 negative receive data Ch2 positive receive data Ch2 negative receive data Ch3 positive receive data Ch3 negative receive data Ch1 positive transmit data Ch1 negative transmit data Ch2 positive transmit data Ch2 negative transmit data Ch3 positive transmit data Ch3 negative transmit data I Differential inputs for each channel from its respective receive coax line. The RX expects balanced differential inputs, usually achieved using a 1:1 transformer. The inputs are internally DC biased to 1.9 V.
Description
I/O/P
Notes
I
I I I I O Differential, coax-driver balanced outputs for pulse-shaped AMI B3ZS/HDB3 encoded waveforms for each channel. These pins should be connected to the primary side of the 1:1 transformer through two backmatch resistors (see Appendix B).
O
O O O O
1-14
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-2. CX2833i-3x Pin Definitions (2 of 8) Pin # Signal Name CX28331-3x CX28332-3x CX28333-3x Digital Data Pins
69 -- 70 -- -- -- 84 -- 85 41 -- 84 -- 85 69 RPOS/ RNRZ RPOS1/ RNRZ1 RNEG/ RLCV RNEG1/ RLCV1 RPOS2/ RNRZ2 RNEG2/ RLCV2 Ch1 receive Positive rail or NRZ data O
1.0 Pin Description
1.1 Pin Assignments
Description
I/O/P
Notes
Resynchronized receive data intended to be strobed out by the corresponding RCLK. When ENDECDIS = 1, these outputs are positive and negative AMI data (RPOS and RNEG). When ENDECDIS = 0, these outputs are decoded NRZ data (RNRZ) and line code violation (RLCV). A line code violation is indicated when RLCV = 1.
Ch1 receive Negative rail or line code violation Ch2 receive Positive rail or NRZ data Ch2 receive Negative rail or line code violation Ch3 receive Positive rail or NRZ data Ch3 receive Negative rail or line code violation Receive clock Ch1 Receive clock Ch2 Receive clock Ch3
O
O
--
40
70
O
See notes on the ENDECDIS pin in the Control Signals section.
--
--
41
RPOS3/ RNRZ3 RNEG3/ RLCV3
O
--
--
40
O
68 -- -- --
-- 83 42 --
-- 83 68 42
RCLK RCLK1 RCLK2 RCLK3
O
Recovered clock for each channel receiver, intended for strobing the corresponding RDAT into the following framer or logic.
O O
100985A
Conexant
1-15
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-2. CX2833i-3x Pin Definitions (3 of 8) Pin # Signal Name CX28331-3x CX28332-3x CX28333-3x
61 -- 60 -- -- -- 78 -- 79 47 -- 78 -- 79 61 TPOS/ TNRZ TPOS1/ TNRZ1 TNEG/ NC TNEG1/ NC1 TPOS2/ TNRZ2 TNEG2/ NC2 TPOS3/ TNRZ3 TNEG3/NC3 Ch1 transmit Positive rail or NRZ data I Synchronized transmit data intended to be strobed in by the corresponding TCLK.
Description
I/O/P
Notes
Ch1 transmit Negative rail or no connect data
I
When ENDECDIS = 1, these inputs are expected to be positive and negative AMI data (TPOS and TNEG). When ENDECDIS = 0, these inputs are expected to be uncoded NRZ data (TNRZ) and no connects (NC). See notes on the ENDECDIS pin in the Control Signal section.
Ch2 transmit Positive or NRZ data Ch2 transmit Negative data or no connect data Ch3 transmit Positive or NRZ data Ch3 transmit Negative data or no connect data Transmit clock Ch1 Transmit clock Ch2 Transmit clock Ch3 Loss of signal Ch1 Loss of signal Ch2 Loss of signal Ch3
I
--
46
60
I
--
--
47
I
--
--
46
I
62 -- -- -- 67 -- -- --
-- 77 48 -- -- 82 43 --
-- 77 62 48 -- 82 67 43
TCLK TCLK1 TCLK2 TCLK3 RLOS RLOS1 RLOS2 RLOS3
I
Transmit bit clock input for strobing with transmit data into the CX2833i.
I I O Loss Of Signal (LOS) indication for each channel, as determined by insufficient pulse density. Signal loss detected when RLOS = 1. An LOS will be asserted when 175 75 0s occur in a row and deasserted when the pulse density is between 28% and 33% (DS3/STS-1) (i.e., a 1s density).
O O
1-16
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-2. CX2833i-3x Pin Definitions (4 of 8) Pin # Signal Name CX28331-3x CX28332-3x CX28333-3x Control Signals
74 74 74 ENDECDIS Encoder/decoder disable (for all channels) I
1.0 Pin Description
1.1 Pin Assignments
Description
I/O/P
Notes
1 = Dual rail pulse coded data format. Input transmit data pins TPOS, TNRZ, TNEG and NC are interpreted as TPOS and TNEG (encoded positive and negative rail data). Output receive data pins RPOS and RNRZ, and RNEG and RLCV are interpreted as RPOS and RNEG, with RPOS having a positive pulse in place of every positive AMI pulse and RNEG having a negative pulse in place of every negative AMI pulse. 0 = NRZ format. Transmit data pins TPOS and TNEG are interpreted as TNRZ and NC (not connected). Receive data pins RPOS and RNEG are interpreted as RNRZ and RLCV. In this mode, all line code violations are reported as active high on RLCV.
63 -- -- --
-- 76 49 --
-- 76 63 49
TAIS TAIS1 TAIS2 TAIS3
Transmit Ch1 AIS mode enable Transmit Ch2 AIS mode enable Transmit Ch3 AIS mode enable E3MODE
I
I --
Transmission of Alarm Indication Signal (AIS) for a given channel. Replace transmit data with AIS signal. The AMI form of AIS supported is alternating 1s. (+1, -1, +1, -1, +1, ...) Looping takes precedence over AIS. 1 = AIS mode enabled 0 = AIS mode disabled When the pin is set to high, it enables the E3 mode on all channels, instead of the DS3/STS-1 mode. This also changes the pulse shaper to E3 mode and overrides all LBO pins. It also changes the encoder/decoder from B3ZS mode to HDB3 mode. 1 = E3 mode 0 = DS3/STS-1 mode Line build-out mode per channel, based on the length of cable on the transmit side of the cross-connect block. This bit is overridden and the pulse shaper is disabled (no pulse shaping) if E3MODE = 1. 1 = Inserts line build-out into the transmit channel. Usually used when the transmit cable is less than 350 feet in length. 0 = Line build-out bypassed (not inserted). Usually used when the transmit cable is greater than 350 feet in length.
53
53
53
E3MODE
I
55 -- --
-- 91 34
-- 91 55
LBO LBO1 LBO2
Transmit line Ch1 build-out mode Transmit line Ch2 build-out mode Transmit line Ch3 build-out mode
I
I
--
--
34
LBO3
I
100985A
Conexant
1-17
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-2. CX2833i-3x Pin Definitions (5 of 8) Pin # Signal Name CX28331-3x CX28332-3x CX28333-3x
71 -- -- -- 72 -- -- -- 93 32 -- -- 94 31 -- 93 71 32 -- 94 72 LLOOP LLOOP1 LLOOP2 LLOOP3 RLOOP RLOOP1 RLOOP2 Local loopback enable Ch1 Local loopback enable Ch2 Local loopback enable Ch3 Remote loopback enable Ch1 Remote loopback enable Ch2 Remote loopback enable Ch3 Transmit output enable Ch1 Transmit output enable Ch2 Transmit output enable Ch3 Ch1 Receive High EQ Gain Enable Ch2 Receive High EQ Gain Enable Ch3 Receive High EQ Gain Enable I Local loopback enable per channel. The transmit data is looped back immediately from the encoder to the decoder in place of the received data. 1 = local loopback enabled 0 = local loopback disabled Remote loopback enable per channel. The receive data, retimed after clock recovery, is looped back into the AMI generator in place of the transmit data. 1 = remote loopback enabled 0 = remote loopback disabled I
Description
I/O/P
Notes
I I I
I
--
--
31
RLOOP3
56 -- -- -- 57 -- --
-- 90 35 -- -- 89 36
-- 90 56 35 -- 89 57
XOE XOE1 XOE2 XOE3 REQH REQH1 REQH2
I
Transmit output enable per channel. 1 = transmit line output driver enabled 0 = transmit output driver set to high impedance state
I I I
I
--
--
36
REQH3
I
The equalizer in the CX2833i has two gain settings. The higher gain setting is designed to optimally equalize a nominally-shaped (meets the pulse template), pulse-driven DS3 or STS-1 waveform that is driven through 0-900 feet of cable. Square-shaped pulses such as E3 or DS3-HIGH require less high-frequency gain and should use the low EQ gain setting. REQH = 1 high EQ gain (DS3/STS-1 modes) REQH = 0 low EQ gain (E3/DS3 Square Modes)
Power/Ground
15 -- 5 -- -- 25 -- -- 5 15 25 TVDD TVDD1 TVDD2 TVDD3 TX power Ch2 TX power Ch3 P P TX power Ch1 P Power pins for transmit circuitry per channel (3.3 V).
1-18
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-2. CX2833i-3x Pin Definitions (6 of 8) Pin # Signal Name CX28331-3x CX28332-3x CX28333-3x
10 -- -- -- 16 -- -- -- 19 -- -- -- 75 51 98 92 33 5, 6, 25, 26 9, 20, 29, 100 -- 100 20 -- -- 6 26 -- -- 9 29 -- 75 51 98 92 33 15, 16 10, 19 -- 100 10 20 -- 6 16 26 -- 9 19 29 75 51 98 92 33 -- -- TVSS TVSS1 TVSS2 TVSS3 RVDD RVDD1 RVDD2 RVDD3 RVSS RVSS1 RVSS2 RVSS3 DVDDC DVSSC VGG DVDDIO DVSSIO VDD VSS RX ground Ch2 RX ground Ch3 Digital core power Digital core ground 5 V/3.3 V ESD pin (1) Digital I/O power Digital ground Power Ground P P P P P P P P P Connect to ground. RX power Ch2 RX power Ch3 RX ground Ch1 P P P TX ground Ch2 TX ground Ch3 RX power Ch1 P P P TX ground Ch1 P
1.0 Pin Description
1.1 Pin Assignments
Description
I/O/P
Notes
Ground pins for transmit circuitry per channel.
Power pins for receive circuitry per channel (3.3 V).
Connect to 3.3 V power. Ground pins for receive circuitry per channel.
Digital core power for all channels (3.3 V). Digital core ground for all channels. 5 V supply for 5 V-tolerant, digital pad ESD diodes. No static power is drawn from pin. Connect to 3.3 V digital power. Digital ground. Connect to 3.3 V power. Connect to ground.
Miscellaneous
73 -- -- -- -- 95 30 -- -- 95 73 30 PD PD1 PD2 PD3 Power down for Ch1 Power down for Ch2 Power down for Ch3 I Power down transceiver channel 0 = Power down channel (off) 1 = Channel active (on) Note: A special power-down mode exists when all three PDBs are set low. This special mode shuts off the entire chip (including biasing). This is useful for static Idd testing.
I I
100985A
Conexant
1-19
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-2. CX2833i-3x Pin Definitions (7 of 8) Pin # Signal Name CX28331-3x CX28332-3x CX28333-3x
58 -- -- -- -- 81 44 -- -- 81 58 44 REFCLK REFCLK1 REFCLK2 REFCLK3 Reference clock for Ch1 Reference clock for Ch2 Reference clock for Ch3 I Reference clock from off-chip. This clock should be set to one of the following: * E3 rate (34.368 MHz) * DS3 rate (44.736 MHz) * STS-1 rate (51.84 MHz) The clock rate should correspond to the mode of operation that has been chosen for the channel. A 12.1 k 1% resistor tied from this pin to ground provides the current reference to the entire chip.(2) Asynchronous reset (reset entire device). Power down (Static Idd testing). 0 = Power down disable 1 = Power down active Transmit monitor input pins are normally tied to their respective transmit line outputs, i.e., (TMON1P TLINE1P and
Description
I/O/P
Notes
I I
99
80
99
RBIAS
Bias resistor
O
97 96
97 96
97 96
Reset GPD
Reset Global Power down Ch1 positive input Ch1 negative input Ch2 positive input Ch2 negative input Ch3 positive input Ch3 negative input TX loss of signal Ch1 Output TX loss of signal Ch2 Output TX loss of signal Ch3 Output TX monitor test pin
I/O I/O
11 -- 14 -- -- -- -- -- 59 -- -- -- 54
-- 1 -- 4 21 24 -- -- -- 80 45 -- 54
-- 1 -- 4 11 14 21 24 -- 80 59 45 54
TMONP TMON1P TMONM TMON1M TMON2P TMON2M TMON3P TMON3M TLOS TLOS1 TLOS2 TLOS3 TMONTST
I
I
I I I I O
TMON1M TLINE1M). Loss of signal outputs are active high when the monitor inputs detect no signal. The TX monitor test pin will assert all TLOS outputs when TMONTST is high. This is used to test board level functionality downstream from the TLOS outputs.
O O I
1-20
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-2. CX2833i-3x Pin Definitions (8 of 8) Pin # Signal Name CX28331-3x CX28332-3x CX28333-3x
1-4, 7, 8, 21-24, 27, 28, 30-32, 34-50, 52, 64-66, 76-91, 93-95
NOTE(S):
(1) (2)
1.0 Pin Description
1.1 Pin Assignments
Description
No connect
I/O/P
-- Not connected.
Notes
11-14, 17-18, 37-39, 50, 52, 55-73, 86-88
37, 38, 39, 50, 64, 65, 66, 86, 87, 88
52
This pin should be connected to 3.3 V in an all-3.3 V design. Placing a capacitor from this pin to ground may result in instabilities. 3. All digital input pins contain a 75 k pull-down resistor from input to DVSS.
100985A
Conexant
1-21
1.0 Pin Description
1.1 Pin Assignments
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
1-22
Conexant
100985A
2
2.0 Functional Description
2.1 Overview
CX28333 is a triple E3/DS3/STS-1 Line Interface Unit (LIU). It is the physical layer interface between the data framer (or other terminal-side equipment) and the electrical cable used for data transmission. The CX28333 LIU consists of three independent data transceivers that can operate over type 734/728 coaxial cable at the rates of 34.368 Mbps (E3), 44.736 Mbps (DS3), and 51.84 Mbps (STS-1). The transmit side takes an NRZ or already-encoded dual rail input and encodes it into AMI B3ZS (for DS3/STS-1) or HDB3 (for E3) analog waveforms to be transmitted over the coaxial cable. The receiver side takes in the attenuated and distorted analog receive signal and equalizes, slices, and resynchronizes the signal before decoding it to the NRZ output or sending out a non-decoded dual rail. CX28331 and CX28332 are single- and dual-E3/DS3/STS-1 LIUs, respectively. In all respects, their performance and features are identical to the CX28333. The architecture of the CX2833i includes the following internal functions for each channel: Transmitter: * * * * * AMI B3ZS/HDB3 encoder pulse shaper line driver Alarm Indication Signal (AIS) insertion transmit monitor
Receiver: * * * * * * * receive sensitivity Automatic Gain Control (AGC) receive equalizer Clock Recovery circuit Loss Of Signal (LOS) detector B3ZS/HDB3 decoder with bipolar violation detector data squelching
100985A
Conexant
2-1
2.0 Functional Description
2.1 Overview
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Additional Functions: * * * bias generator power-on reset loopback MUXes
In addition, each channel has the ability to perform remote and local loopbacks. Figure 2-1 illustrates a typical application using the CX2833i in a channel. External pins are provided to configure the various line rates and formats for each channel. The CX2833i is used as a data transceiver over a coaxial cable that is up to 900 feet long (or up to 450 feet from the DSX) in an on-premise environment within any public or private networks which use these data rates.
Figure 2-1. Typical Application Of Single CX2833i Channel
TX
0-450 ft COAX (type 734/728)
DSX
0-450 ft COAX (type 734/728)
RX
RX
0-450 ft COAX (type 734/728)
DSX
0-450 ft COAX (type 734/728)
TX
100604_012
2-2
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.2 Transmitter
2.2 Transmitter
This section describes the detailed operation of the various blocks in the CX2833i transmitter.
2.2.1 AMI B3ZS/HDB3 Encoder
ENDECDIS and the E3MODE pins configure the encoder mode. When ENDECDIS = 0, the encoder is receiving non-encoded Nonreturn to Zero (NRZ) data on the TNRZ (TPOS) pin alone, and the NC (no connect) (TNEG) pin is ignored. Data is encoded into a representation of a three-level B3ZS (E3MODE = 0) or HDB3 (E3MODE = 1) signal (conforming to the coding rules as specified in Appendix A) before going on to the pulse shaper in the form of two binary signals representing the positive and negative three-level pulses. When ENDECDIS = 1, the encoder is disabled. The encoder passes already-encoded data over TPOS (TNRZ) and TNEG (NC) to the pulse shaper. The transmit digital data is clocked into the chip via a rising TCLK edge, which must be equal to the symbol rate (line rate). A small delay added to the data provides a certain amount of negative data hold time.
2.2.2 Pulse Shaper
The pulse shaper converts the two digital (clocked) positive and negative pulses into a single analog three-level Alternate Mark Inversion (AMI) pulse. The pulses are in Return to Zero (RZ) format, meaning that all positive and negative pulses have a duration of the first half of the symbol period. For the E3 rate (E3MODE = 1), the AMI pulse is a full-amplitude, square-shaped pulse with very little slope.
Figure 2-2. Pulse Shaper
E3 Mode + Pulse LBO LBO = 0 Pulse Shaper - Pulse
Line Driver LBO = 1
100604_008
100985A
Conexant
2-3
2.0 Functional Description
2.2 Transmitter
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
For DS3/STS-1 rates, a pulse-shaper block is used to shape the transmit waveform and reduce its high-frequency energy content. This ensures that the transmit pulse template is met at the cross-connect block, which follows 0-450 feet of transmit-side coaxial cable.
2.2.3 Line Driver
The differential line driver takes the filtered transmit waveform, increases it to the proper level, and drives it into the transmit magnetics. The two external discrete back-matching resistors (36 ) aid in line matching. The driver is presented with an approximately 150 differential load. Driver gain accounts for the 6 dB gain loss in the back-matching resistors. Figure 2-3 illustrates the Pulse/Power template measurement points for the various data rates.
Figure 2-3. Pulse Measurement Points
Pulse/Power Template for DS3/STS-1
TX
0-450 ft COAX (type 734/728)
DSX
0-450 ft COAX (type 734/728)
RX
Pulse/Power Template for E3
RX
0-450 ft COAX (type 734/728)
DSX
0-450 ft COAX (type 734/728)
TX
100604_013
2-4
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.2 Transmitter
2.2.3.1 Transmit Pulse Mask Templates
Figure 2-4. Transmit Pulse Mask for DS3 Rates
Transmit Pulse Mask for STS-1 Rates 1.2
1
0.8
Normalized Pulse Amplitude
0.6
0.4
0.2
0
0.2
1
0.5
0 0.5 Normalized Symbol Time
1
1.5
100985_014
Table 2-1. DS3 Transmit Template Specifications Time Axis Range (UI)
Upper Curve -0.85 T -0.68 -0.68 T 0.36 0.36 T 1.4 Lower Curve -0.85 T -0.36 -0.36 T 0.36 0.36 T 1.4 -0.03 -0.03 + 0.5{1 + sin[(pi / 2)(1 + T / 0.18)]} 0.03 0.03 0.03 + 0.5 {1 + sin [(pi / 2)(1 + T / 0.34)]} 0.08 + 0.407 e -1.84(T - 0.36)
Normalized Amplitude Equation
100985A
Conexant
2-5
2.0 Functional Description
2.2 Transmitter
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 2-5. Transmit Pulse Mask for STS-1 Rates
Transmit Pulse Mask for STS-1 Rates 1.2
1
0.8 Normalized Pulse Amplitude
0.6
0.4
0.2
0
0.2
1
0.5
0 0.5 Normalized Symbol Time
1
1.5
100985_014
Table 2-2. STS-1 Transmit Template Specifications Time Axis Range (T)
Upper Curve -0.85 T -0.68 -0.68 T 0.26 0.26 T 1.4 Lower Curve -0.85 T -0.38 -0.38 T 0.36 0.36 T 1.4 -0.03 -0.03 + 0.5{1 + sin[(pi / 2)(1 + T / 0.18)]} 0.03 0.03 0.03 + 0.5{1 + sin[(pi / 2)(1 + T / 0.34)]} 0.1 + 0.61 e -2.4(T - 0.26)
Normalized Amplitude Equation
2-6
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.2 Transmitter
Figure 2-6. Transmit Pulse Mask for E3 Rate
17 ns 0.2 0.1 0.1 Volts Normalized 0.1 0.2 8.65 ns 12.1 ns 14.55 ns
24.5 ns 0.1 0.1 29.1 ns Time
100985_007
100985A
Conexant
2-7
2.0 Functional Description
2.2 Transmitter
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.2.4 Alarm Indication Signal (AIS) Generator
When TAIS is asserted, an AIS replaces the transmit data at TPOS and TNEG. The E3 type of AIS signal (all 1s) is supported. In three-level signal form, this is a continuously alternating positive and negative pulse stream, as if the transmit data were a continuous string of logical 1s. Figure 2-7 illustrates the AIS signal. The TAIS pin has the same data latency as the TX data pins and can be used to replace single symbols within a data stream. When the encoder is disabled (ENDECDIS = 1), the TAIS mode maintains the proper phase, based upon the polarity of the last 1 received. The AIS signal follows the same path as the TX data during remote or local loopback.
Figure 2-7. AIS Signal
POSITIVE PULSE
NEGATIVE PULSE
TLINEP (output voltage)
TLINEN (output voltage)
8333_009
2.2.5 Transmit Monitor Block (CX2833i-3x Only)
The transmit monitor inputs (TMONP and TMONM) are designed to monitor the line driver outputs (TLINEP and TLINEM/N) for pulses and to assert a Loss Of Signal (TLOS) indicator when no output pulse has been detected for 32 TCLK periods. After TLOS is asserted, it will not deassert until a pulse is again detected. The transmit monitor is an independent function in which TMONP and TMONM must be externally connected to TLINEP and TLINEM/N, respectively. A special pin (TMONTST) is available for testing board-level functionality downstream from the TLOS outputs. When TMONST is high it will assert all TLOS channel outputs. TLOS outputs are active high when the monitor inputs do not detect a signal.
2-8
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.2 Transmitter
2.2.6 Jitter Generation (Intrinsic)
The CX2833i device meets the jitter generation requirements for various rates with large margins, with the condition that the input transmit clock (TCLK) is jitter-free. Data rates and jitter generation requirements are defined in the following documents: * * * E3 rate--ETSI TBR24, ITU-T 9.823 DS3 rate--Bellcore Telecardia GR499, AT&T Accunet TR54014, ITU-T 9.824 STS-1 rate--Bellcore Telecardia GR253
100985A
Conexant
2-9
2.0 Functional Description
2.3 Receiver
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.3 Receiver
This section describes the detailed operation of the various blocks in the CX2833i receiver.
2.3.1 Receive Sensitivity
The receiver recovers data from the coaxial cable that is attenuated due to the frequency-dependent characteristics of the cable. In addition, the receiver compensates for the flat loss (across all frequencies) in the various electrical components and the variation in transmitted signal power. The CX2833i device is able to recover data that has been attenuated by a maximum of 900 feet of coax having characteristics and attenuation consistent with ANSI T1.102-1993, Annex C, Figure C.2. This approximates the characteristics of AT&T type 734/728 cable; almost the same attenuation characteristic is achieved by one-half the length of AT&T type 735 cable.
2.3.2 AGC/VGA Block
The Variable Gain Amplifier (VGA) receives the AMI input signal from the coaxial cable. The VGA supplies flat gain (independent of frequency) to make up for various flat losses in the transmission channel and for loss at one-half the symbol rate that cannot be made up by the equalizer. The VGA gain is controlled by a feedback loop which senses the amplitude of the equalizer output, acting to servo this amplitude for optimal slicing.
2.3.3 Receive Equalizer
The receive equalizer receives the differential signal from a VGA and acts to boost the high frequency content of the signal to reduce inter-symbol interference (ISI) to the point that correct decisions can be made by the slicer with a minimum of jitter in the recovered data. The REQH pin is provided to allow lower amounts of equalization (shorter equivalent cable lengths) for cases where a square-shaped pulse (that does not meet the DS3/STS-1 standards) is transmitted to the receiver. A square-shaped input has a much larger high-frequency content and could have overshoots at the EQ output high enough to cause bit errors. Setting REQH = 0 will lower the gain and reduce the amount of overshoot.
2-10
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.3 Receiver
2.3.4 The PLL Clock Recovery Circuit
The clock recovery circuit (RX PLL) extracts the embedded clock from the sliced data and provides this clock and the retimed data to the decoder (data mode). Upon startup (after the internal reset is deasserted), the RX PLL uses a reference clock (REFCLK, running at the symbol rate) and a phase-frequency detector to lock to the correct data rate (reference mode). During reference mode, the data outputs are squelched (set to 0). The RX PLL is kept in reference mode until a valid input is detected.
2.3.5 Loss Of Signal (LOS) Detector
The Receive Loss Of Signal (RLOS) is a digital function which monitors the retimed data from the clock recovery block. The AMI data is checked for a continuous run of zeroes. When a continuous run of 128 1 consecutive zeroes occurs, the RLOS signal is asserted. After the RLOS signal is asserted, a 1s count is made on every block of 128 AMI symbols. The RLOS signal is deasserted when the 1s count within a block of 128 symbols is at least: B3ZS: Minimum 1s density = 39 1 count out of 128 (~30.5%) HDB3: Minimum 1s density = 29 1 count out of 128 (~22.7%) The RLOS detector will always monitor the cable-side RX inputs. The detector is not affected by the state of remote or local looping.
2.3.6 B3ZS/HDB3 Decoder With Bipolar Violation Detector
In the CX2833i device, when ENDECDIS = 0 (encoder/decoder enabled), the decoder takes the output from the clock recovery circuit and decodes the data (HDB3 or B3ZS) into a single retimed NRZ data signal. The data signal is then sent out of the CX2833i over the RNRZ (RPOS) pin. Any detected Line Code Violations (LCV) are sent out over the corresponding RLCV (RNEG) pin. The RLCV pin is asserted for one symbol period at the time the violation appears on the RX output pin (RNRZ). The following shows data sequence criteria for LCV; violations are indicated in bold text. A valid bipolar pulse is indicated by a B. A bipolar violation (non-alternating positive or negative) pulse is indicated by a V . * * Excessive zeros: 0, 0, 0, 0 (HDB3) or 0, 0, 0 (B3ZS). These violations are passed on as 0 data on the RNRZ pin. Bipolar violation: B, 0, V (i.e., +1, 0, +1 or -1, 0, -1 for HDB3) B, V (B3ZS and HDB3). These violations are passed on as 1 data on the RNRZ pin. Coding violation: 0, 0, V (HDB3) or 0, V (B3ZS) with an even number of Bs since the last valid 0 substitution V (follows coding rule). These violations are passed on as 0 data on the RNRZ pin.
*
The even/odd counter (used to count the number of Bs between Vs) will count a bipolar violation as a B. A coding violation or a valid 0 substitution resets the counter.
100985A
Conexant
2-11
2.0 Functional Description
2.3 Receiver
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
When ENDECDIS = 1, the decoder is disabled, and the retimed slicer outputs are sent out over RPOS (RNRZ) and RNEG (RLCV) pins. These outputs are then decoded by the Framer or other downstream device. Line code violations are not detected in this mode of operation. The decoder is configurable for either: * * E3 mode using HDB3 coding (E3MODE = 1) DS3/STS-1 mode using B3ZS coding (E3MODE = 0)
The receiver digital data outputs are centered on the rising edge of RCLK (see Section 2.9).
2.3.7 Data Squelching
A counter in the receiver keeps track of the number of consecutive symbol periods without a valid data pulse. When 128 or more 0s in a row are counted, the receiver assumes that it has lost the signal and resets itself to try and regain the signal. While the receiver is reacquiring the signal, the clock recovery block locks to the reference clock and the data squelching is achieved by forcing the data bits to zero. The data squelching is true in both NRZ and dual rail mode. When the input signal has been properly amplified and equalized, the clock recovery PLL will then switch to the incoming data.
2-12
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.4 Jitter Tolerance
2.4 Jitter Tolerance
The CX2833i receiver is able to tolerate a specified amount of high-frequency jitter in the received signal while providing error-free operation (generally defined as a bit error rate of less than 10-9). The specifications (illustrated in Figure 2-9) for jitter tolerance are discussed in the following documents: *
NOTE:
E3 rate - ITU-T G.823 and ETSI TBR24 contain frequency masks for input jitter tolerance. To meet jitter transfer requirements for loop-timed operation, an external jitter attenuator is required. The jitter attenuator lessens jitter from the receive clock. DS3 rate - ITU-T G.823 and Bellcore GR499 specify jitter tolerance frequency masks for Category I and Category II interfaces. STS-1 rate - Bellcore GR253 specifies a jitter tolerance. It is noted that the STS-1 jitter tolerance differs from DS3 requirements only for Category II interfaces.
* *
100985A
Conexant
2-13
2.0 Functional Description
2.4 Jitter Tolerance
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 2-8. Minimum Jitter Tolerance Requirement
E3 Rate
1.0 UI Input Jitter Amplitude 0.1 UI
100 Hz
1 kHz
10 kHz Jitter Frequency
100 kHz
1 MHz
DS3 / STS-1 Rates
10 UI STS-1 DS3 Category I DS3 Category II
Input Jitter Amplitude
1.0 UI
0.1 UI
10 Hz
100 Hz
1 kHz Jitter Frequency
10 kHz
100 kHz
100604_014
2-14
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.4 Jitter Tolerance
2.4.1 Jitter Transfer
The receiver must meet certain jitter transfer specifications between the input and output jitter as a function of frequency. These specifications are only intended to be met with the use of a jitter attenuator. Because the CX2833i does not contain a jitter attenuator, one will have to be supplied externally. For reference purposes, the specifications are discussed in the following documents and shown in Figure 2-9. E3 rate--Assume the same as DS3. DS3 rate--Bellcore GR499, section 7.3.2 and figures 7-3, 7-4, and 7-5, defines and describes DS3 jitter transfer. STS-1 rate--Bellcore GR253, section 5.6.2.1, defines and describes jitter transfer for the STS-1 rate.
Figure 2-9. Maximum Jitter Transfer Curve Requirement
0.1 dB
Jitter Gain
-19.9 dB
STS-1 Category II DS3 Category I DS3 Category II (Note: All slopes are 20 dB/decade)
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Jitter Frequency
100985_012
100985A
Conexant
2-15
2.0 Functional Description
2.5 Additional CX2833i Functions
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.5 Additional CX2833i Functions
2.5.1 Bias Generator
To achieve good isolation between the channels, each channel utilizes an independent power and ground to both transmit and receive. Additionally, each channel has its own band gap voltage reference. Because only one external resistor for current generation exists, only one band gap voltage can be used. The band gap from Ch1 has been chosen for this task. The 12.1 k external resistor from pin RBIAS to ground, is specified to have a tolerance of 1%. This helps to keep tighter control on power dissipation and circuit performance.
NOTE:
Capacitance should be kept to a minimum on the RBIAS pin.
2.5.2 Power-On Reset (POR)
A POR function is provided in the CX2833i device to ensure all of the resettable digital logic and analog control lines are starting from a known state. This circuit uses a fixed RC timer (~1s); additionally, 128 clocks from REFCLK are counted (after the RC timer has timed-out) before reset is deasserted, which begins timing after a minimum supply voltage is reached (see Table 2-4).
2.5.3 Loopback Multiplexers (MUXes)
Two loopback MUXes per channel in the CX2833i allow for local loopback (terminal or framer side), remote loopback (cable side), or both (the AIS signal follows the same path as the transmit data during loopback). The RLOS signal monitors the RX cable inputs irrespective of any loopback. In remote loopback, set by asserting pin RLOOP high, the receive data (retimed after clock recovery but not decoded) loops back into the pulse shaper in place of the transmit data. Additionally, this data sent out the RPOS, RNEG, and RCLK pins. In local loopback, set by asserting pin LLOOP, the transmit data loops back immediately from the encoder output to the decoder input in place of the received data. Additionally, this data is sent out the TLINEP and TLINEM/N pins.
2-16
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.6 Mechanical Specifications
2.6 Mechanical Specifications
Figure 2-10. CX2833i-1x Mechanical Drawing (80-Pin)--Dimensions
D D1 Pin #1 Ref. Mark D2 D 3
D D1 D2
D1
D3
e
b
TOP
BOTTOM
Millimeters Dim. See DETAIL B A A1 A2 D D1 D2 D3 L L1 b c e Coplanarity Min. Max. Min. Inches Max.
1.20 MAX. 0.05 0.15 0.95 1.05 15.75 16.25 13.90 14.10 12.35 REF. 6.50 REF. 0.45 0.75 1.00 REF. 0.32 REF. 0.09 0.20 0.65 REF. 0.10 MAX.
0.047 MAX. 0.002 0.006 0.040 0.041 0.620 0.547 0.640 0.555
A A A1
2
c
0.486 REF. 0.256 REF. 0.018 0.030 0.039 REF. 0.013 REF. 0.004 0.008 0.026 REF. 0.004 MAX.
L
DETAIL B
L
1
Ref. 80-Pin ETQFP (GP00-D537)
100985_008
100985A
Conexant
2-17
2.0 Functional Description
2.6 Mechanical Specifications
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 2-11. CX2833i-3x Mechanical Drawing (100-Pin)--Dimensions
D D1 Pin #1 Ref. Mark D 2 D3
D D1 D2
D1
D3
e
b
TOP
BOTTOM
Millimeters Dim. See DETAIL B A A1 A2 D D1 D2 D3 L L1 b e c Coplanarity Min. Max. Min. Inches Max.
1.20 MAX. 0.05 0.15 0.95 1.05 15.75 16.25 13.90 14.10 12.00 REF. 8.00 REF. 0.45 0.75 1.00 REF. 0.22 REF. 0.50 REF. 0.09 0.20 0.08 MAX.
0.047 MAX. 0.002 0.006 0.004 0.041 0.620 0.640 0.547 0.555 0.472 REF. 0.315 REF. 0.018 0.006 0.039 REF. 0.009 REF. 0.020 REF. 0.004 0.008 0.004 MAX.
A
A
A2 1
c
L
DETAIL B
L1
Ref. 100-Pin ETQFP (GP00-D543)mm
100985_008a
2-18
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.7 Electrical Characteristics
2.7 Electrical Characteristics
2.7.1 Absolute Maximum Ratings
Table 2-3. Absolute Maximum Ratings Symbol
DVDDC/ RVDD/ TVDD/ VDD VI TST TVSOL
Parameter
Power Supply Voltage
Min
-0.3
Max
6
Unit
V
Voltage on Any Signal Pin Storage Temperature Vapor Phase Soldering Temperature (1 min.) Thermal Resistance (Still air, socketed) Thermal Resistance (Still air, soldered) -- Failures in time @ 89,000 device hours, temperature of 55 C, 0 failures.
-1.0 -40 -- -- -- -- --
VGG + 0.3 V 125 220 40 24 7.40 313
V C C C/W C/W C/W fits
JA JA Jc
FIT
NOTE(S):
1. Stresses above those listed as absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
100985A
Conexant
2-19
2.0 Functional Description
2.7 Electrical Characteristics
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.7.2 Recommended Operating Conditions
Table 2-4 specifies various operating conditions, power supplies, and the bias resistor.
Table 2-4. Recommended Operating Conditions Parameter
Power supply voltage ESD voltage(1) Power dissipation (CX28333) Power dissipation (CX28332) Power dissipation (CX28331) External bias resistor
NOTE(S):
(1)
Conditions
DVDDC, RVDD, TVDD, VDD VGG Total chip Total chip Total chip Pin RBIAS to GND; 1%
Min
3.135 3.135 -- -- -- 11.98
Nom
3.3 5 0.83 -- -- 12.1
Max
3.465 5.5 1.0 0.8 .450 12.22
Unit
V V W W W k
With 5 V logic input, VGG should be tied to 5 V. With 3.3 V logic input, VGG should be tied to 3.3 V.
2-20
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.0 Functional Description
2.8 DC Characteristics
2.8 DC Characteristics
Table 2-5. DC Characteristics Parameter
Vih high threshold Vil low threshold Voh high threshold Vol low threshold ILEAK Input capacitance Load capacitance
NOTE(S):
Conditions
Digital inputs Digital inputs Digital outputs, Ioh = -4 mA Digital outputs, Iol = 4 mA 0 V digital Vin VGG -- Digital outputs
Min
2.0 -0.3 2.4 -- -10 -- --
Nom
-- -- -- -- -- -- --
Max
VGG + 0.3 0.8 -- 0.4 200 10 15
Unit
V V V V A pF pF
1. The digital inputs of CX2833i are TTL 5 V compliant. These inputs are diode protected to DVDDIO and DVSSIO pins. Additionally, all of the CX2833i digital inputs contain 75 k pull-down resistors. 2. The digital outputs of CX2833i are also TTL 5 V compliant. However, these outputs will not drive to 5 V, nor will they accept 5 V external pull-ups. The output is DVDDC (3.3 V).
100985A
Conexant
2-21
2.0 Functional Description
2.9 AC Characteristics
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.9 AC Characteristics
Table 2-6. AC Characteristics (Logic Timing) Parameter
Tosym, Tisym RCLK and TCLK Clock Duty Cycle
Conditions
E3 DS-3 STS-1 Towidth/Tosym, RCLK Tiwidth/Tisym, TCLK Tiwidth/Tisym, REFCLK -- TPOS/TNRZ, TNEG, TAIS TPOS/TNRZ, TNEG, TAIS
Min
--
Nom
29.10 22.35 19.29 --
Max
--
Unit
ns ns ns % % % ns ns ns
45 40 40 -- 4 0
55 60 60 3 -- --
Todelay Tisetup Tihold
NOTE(S):
-- -- --
1. The description applies to the DS3, E3, and STS-1 clock rates and other parameters such as pulse width, set-up time, hold time, and duty cycle. 2. The timing diagram, illustrated in Figure 2-12, describes the logical relationship between various clock and data signals, and parameter values.
2-22
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Figure 2-12. Timing Diagram
Tosym
2.0 Functional Description
2.9 AC Characteristics
DATA OUTPUTS
RCLK Towidth Todelay
RPOS/RNRZ, RNEG/RLCV
Tisym
DATA INPUTS
TCLK Tiwidth
Tisetup
Tihold
TPOS/TNRZ, TNEG, TAIS,
Don't Care
Valid Data
Don't Care
100604_016
100985A
Conexant
2-23
2.0 Functional Description
2.9 AC Characteristics
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2-24
Conexant
100985A
3
3.0 Applications
The CX28331/CX28332/CX28333 can be used in a variety of applications. Figure 3-1 illustrates an example of three DS3 lines being terminated by the CX28333. The data and clock are extracted and passed on to the framer chip for further data manipulation and user interface. It is important to employ high-frequency design techniques for the printed board layout.
3.1 PCB Design Considerations for CX2833i
The CX28333 device is a triple LIU operating at frequencies up to 52.84 MHz. The high-speed nature of the device calls for a careful design of the PCB using this device. Some design considerations are outlined below.
3.1.1 Power Supply and Ground Plane
A unified power plane with properly placed capacitors of the correct size will mitigate most power rail-related voltage transients. A properly placed bulk capacitor, where the power enters the board, with noise-bypassing capacitors at the power pins on the integrated circuits should be adequate. The noise-bypassing capacitors must be able to supply all the switching current. Ferrite beads are used with power rails to filter the high-frequency noise. For every design, noise frequencies and levels are different. Therefore, whether beads are necessary, and the effective frequency where they should operate, is difficult to determine. It is a good idea to provision for ferrite beads on the boards. The board trace from the CX28333 power supply pin to the noise-bypassing capacitor should be minimized. Additionally, ground connections from the ground plane to the CX28333 ground pins and the noise-bypassing capacitor ground pins should be minimized. A unified ground plane is the best way to minimize ground impedance. Most of the ground noise is produced by the return currents and power supply transients during switching. This effect is minimized by reducing the ground plane impedance.
100985A
Conexant
3-1
3.0 Applications
3.1 PCB Design Considerations for CX2833i
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
3.1.2 Impedance Matching
It is critical that traces around the transformers and matching resistors be kept to a minimum length and, in the following cases, the trace impedance be matched to 75 with a 10% tolerance: * * The impedance from the BNC connector to the transformer The impedance from the transformer to the matching resistors
3.1.3 Other Passive Parts
The reference design uses the Pulse T3001 extended temperature range 1:1 transformer for the coupling of the BNC connector to the device. The ferrite beads used to decouple the receive- and transmit-VDD pins on all analog input VDD pins are type 2508056017Y0 from Fair-Rite Products Corporation. The bulk capacitor used for where the power enters the board should be a tantulum-type capacitor, the recommended value and type is a 220 f tantulum capacitor.
3.1.4 IBIS Models
IBIS (Input/Output Buffer Interface Specification) models for the CX28331/CX28332/CX28333-1x and -3x are available from Conexant's web site (www.conexant.com).
3.1.5 Recommended Vendors
Product: Transformers America Address: Pulse Corporate Office 12220 World Trade Drive San Diego, CA 92128 858-674-8100 858-674-8262 Pulse 3F-4, No. 81, Sec. 1 Hsin Tai Wu Road Hsi-Chih Tapei Hsien, Taiwan R.O.C. 886-2-26980228 886-2-26980948 Pulse 1S2 Huxley Road The Surrey Research Park Guildford, Surrey GU2 5RE United Kingdom 44-1483-401700 44-1483-401701
Product: Ferrite Beads Fair-Rite Products Corp. P.O. Box J One Commercial Row Wallkill, NY 12589 914-895-2055 www.Fair-Rite.com
Telo: Fax: Northern Asia
Telo: Web site:
Telo: Northern Europe
Product: Crystals Crystek Corp. 12730 Commonwealth Drive Fort Myers, FL 33913 800-237-3061 941-561-1025 sales@crystek.com www.crystek.com
Telo: Fax:
Telo: Fax: E-mail: Web site:
3-2
Conexant
100985A
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
3.0 Applications
3.1 PCB Design Considerations for CX2833i
Figure 3-1.
CX28333
TMONP TPOS TNEG TCLK TLINEP TX TLINEN TMONM 31.6 9 37.4 9 0.01F 1:1 Type 728, 734, 735 75 9 31.6 9 1:1 Type 728, 734, 735 75 9
Framer
Channel 1
RPOS RNEG RCLK MODE RLINEP RX RLINEN
37.4 9 BIAS RESET
TMONP TPOS TNEG TCLK TLINEP TX TLINEN TMONM
31.6 9 1:1
Type 728, 734, 735 75 9
Framer
Channel 2
RPOS RNEG RCLK MODE RLINEP RX RLINEN
31.6 9 37.4 9 0.01F 1:1
Type 728, 734, 735 75 9
37.4 9 BIAS RESET
TPOS TNEG TCLK
TMONP TLINEP TX TLINEN TMONM
31.6 9 1:1
Type 728, 734, 735 75 9
Framer
Channel 2
RPOS RNEG RCLK MODE RLINEP RX RLINEN
31.6 9 37.4 9 0.01F 1:1
Type 728, 734, 735 75 9
37.4 9 BIAS RESET
MODE
BIAS
RESET RBIAS
12.1K 9
Mode/Status Pins
100985_009
NOTE(S):
1. All transformers are part number T3001 from Pulse Technology. See Recommended Vendors, Section 3.1.5. 2. TMONP and TMONM are only available on the CX2833i-3x device and are denoted by dotted lines.
100985A
Conexant
3-3
3.0 Applications
3.1 PCB Design Considerations for CX2833i
CX28331/CX28332/CX28333 Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
3-4
Conexant
100985A
A
Appendix A
A.1 Applicable Standards
The applicable standards documents are as follows: * ANSI T1.102-1993 (DS3 and STS-1 standard) * ANSI T1.404a-1996 (DS3 metallic interface) * ITU Recommendation G.703 (DS3 and E3 standard) * ITU Recommendation G.823 and G.824 (jitter and wander) * Bellcore GR499, Issue 1, 12/89 (formerly TR-TSY-000499) (DS3 and STS-1 requirements) * Bellcore GR253, Issue 2, 12/91 (formerly TA-NWT-000253) (STS-1 requirements and jitter) * Bellcore TR-TSY-000191, Issue 1, 5/86 (AIS and LOS) * ETSI TBR24 and TBR25 (E3 terminal equipment interface) * ETSI ETS 300 686 and ETS 300 687 (E3 standard) * AT&T Technical Reference TR54014, May 1992 (Accunet Interface Specification for DS-3 jitter only)
100985A
Conexant
A-1
Appendix A
A.1 Applicable Standards
CX28331/CX28332/CX28333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
A-2
Conexant
100985A
B
Appendix B
B.1 Evaluation Module Schematic
100985A
Conexant
B-1
1
2
3
4
5
6
1
2
3
4
5
6
CC +3_3V C11 14 13 12 11 CC RPOS1/RNRZ1 RCLK1 RLOS1 REFCLK TNEG1/NC1 0.1 R13 CC R6 CC RBIAS L12 1 TVSS1 TLINE1P TLINE1M TVDD1 RVDD1 RLINE1P SOCKET RPOS2/RNRZ2 54 53 RNEG2/RLCV2 RCLK2 RLOS2 52 51 TAIS2/TMUXA3 TCLK2 U1 TPOS2/TNRZ2 TNEG2/NC2 REFCLK2 REQH2/TMUXA0 XOE2 45 LBO2 44 E3MODE 43 TMUXLAT 42 DVSS 41 E3MODE TMUXLAT 47 46 48 49 50 RLINE1M RVSS1 TVSS2 TLINE2P TLINE2M TVDD2 RVDD2 RLINE2P RLINE2M RVSS2 TVSS3 TLINE3P TLINE3M TVDD3 55 RLOOP2 57 LLOOP2 56 PDB2 RLOOP2 LLOOP2 RNEG2/RLCV2 RPOS2/RNRZ2 RCLK2 RLOS2 TAIS2/TMUXA3 TCLK2 TPOS2/TNRZ2 TNEG2/NC2 REFCLK REQH2/TMUXA0 XOE2 LBO2 +3_3V 0.1 CC 3 N1 5 6 7 8 C7 0.1 11 L13 12 13 14 15 L4 6 37.4 5 CC +3_3V L14 PDB3 LBO3 XOE3 CC CC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 C8 L15 6 31.6 CC C9 ANALOG GND 0.1 4 31.6 R10 CC 5 R9 CC +3_3V 0.1 SW5 TAIS3/TMUXA4 TCLK3 TPOS3/TNRZ3 TNEG3/NC3 REFCLK RLOS3 RCLK3 RPOS3/RNRZ3 RNEG3/RLCV3 REQH3/TMUXA1 XOE3 L6 6 37.4 5 CC 4 37.4 R12 CC C3 0.01 R11 CC LBO3 LLOOP3 RLOOP3 PDB3 REQH2/TMUXA0 REQH3/TMUXA1 TAIS1/TMUXA2 TAIS2/TMUXA3 TAIS3/TMUXA4 REQH1/TMUXDAT RVDD3 RLINE3P RVSS3 RLOOP3 LLOOP3 DVSS2 RCLK3 RLOS3 RLINE3M REFCLK3 TCLK3 4 37.4 R8 C2 20 0.01 19 18 R7 CC 17 16 +3_3V CC 10 9 4 C6 0.1 2 80 73 DVDD2 LBO1 72 31.6 +3_3V 12.1K TAIS1/TMUXA2 TCLK1 TAIS1/TMUXA2 REQH1/TMUXDAT 0.1 TPOS1/TNRZ1 XOE1 LBO1 LLOOP1 RLOOP1 PDB1 0.1 C12 C5 CC 0.1 6 CC 31.6 5 R5 C4 CC RNEG1/RLCV1 10 SW1 4 CC REQH1/TMUXDAT 37.4 R4 1 CC XOE1 L17
L7 2 7
LBO1
SW2
B.1 Evaluation Module Schematic
3
9
9
8
14
13
12
11
PULSE T3001
PDB2 RLOOP2 LLOOP2 LBO2 XOE2 TAIS2/TMUXA3 REQH2/TMUXA0
BNC L3
CHANNEL 2 TRANSMIT
J3
1
2
3
4
+3_3V
PDB1 76 RLOOP1 75 LLOOP1 74
VGG 79 78 TMUXIO1 TMUXIO2 77
REFCLK1 65
PULSE T3001
1
2
3
4
5
TNEG1/NC1 64 TPOS1/TNRZ1 63
RNEG1/RLCV1 69 RPOS1/RNRZ1 68 67 RCLK1 RLOS1 66
TCLK1 62 TAIS1/TMUXA2 61
+3_3V SW3 ENDECDIS CC C10 PDB3 RLOOP3 LLOOP3 LBO3 XOE3 TAIS3/TMUXA4 REQH3/TMUXA1
XOE1 71 REQH1/TMUXDAT 70
DVDD 60 59 ENDECDIS PDB2 58
9
6
14
13
12
11
CX28333 80 ETQFP
BNC
CHANNEL 2 RECEIVE
J4
1
SW4 E3MODE 1 2 ENDECDIS 4 3 +3_3V
10
8
7
Figure B-1. Recommended Schematic for the CX2833i-1x Device
L16
REQH3/TMUXA1
RNEG3/RLCV3
RPOS3/RNRZ3
TNEG3/NC3
TPOS3/TNRZ3
TAIS3/TMUXA4
1
2
3
4
5
38
39
PULSE T3001 L5
BNC
CHANNEL 3 TRANSMIT
40
6
9
8
12
11
10
J5
7
Conexant
+3_3V 1 J8 R14 RLOS1 J9 R15 RLOS2 J10 R16 RLOS3 402 CR3 CC 1 2 CH3_LOS 402 CR2 CC 1 2 CH2_LOS 402 CR1 CC CH1_LOS SOCKET NC VCC Y1 7 GND OUT 8 R17 42.2 CC C13 0.1 1/4 CC REFCLK 14 +3_3V SW9 TMUXLAT
2
3
DIGITAL GND
1
2 Pin DIP Switch Setting
Pin 1 ENDECDIS 1=Dual rail pulse coded data format Pin 2 E3MODE 1=E3 mode is enabled 0=Disabled DECODER AND E3 SELECTION
2
3
PULSE T3001
Seven Position DIP Switch Settings for all Channels Position 1 PDB POWERDOWN (0=Powerdown 1=Active) Position 2 RLOOP (1=Remote LPBK Enabled 0=Disabled) Position 3 LLOOP (1=Local Loop Enabled 0=Disabled) Position 4 LBO (1=TX CABLE less than 250ft 0=greater than 250ft) Position 5 XOE (1=Transmitter Enabled 0=Disabled) Position 6 TAIS (1=Enable AIS operation 0=disable) Position 7 REQH(1=Enable Equalization 0=Disable)
BNC
CHANNEL 3 RECEIVE
J6
1
2
3
PULSE T3001
10
8
7
B-2
L1 6 31.6 5 R1 CC 4 31.6 +3_3V TMUXIO1 +5V CC PDB1 L11 C1 +3_3V 0.01 3 LLOOP1 L10 J7 RLOOP1 +3_3V TMUXIO2 +3_3V +3_3V R2 CC L2 6 37.4 5 R3
Appendix B
BNC
CHANNEL 1 TRANSMIT
J1
1
2
3
PULSE T3001
BNC
CHANNEL 1 RECEIVE
J2
1
2
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
CX28331/CX28332/CX28333
100985_017
100985A
J1
Channel 1 Transmit
2
2
bead
2
bead
bead
J4 L11 bead C7 0.1 C5 R52 0 R53 0 C4 0.1 C10 0.1 C6 bead L10
Channel 2 Receive
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
2
2,3,4
0.1 0.1
Pulse
T3001
37.4
TVSS1 RBAIS VGG RESET GPD PD1 RLOOP1 LLOOP1 DVDDIO LBO1 XOE1 REQH1 N/C10 N/C9 N/C8 RNEG1/RLCV1 RPOS1/RNRZ1 RCLK1 RLOS1 REFCLK1 TLOS1 TNEG1/NC1 TPOS1/TNRZ1 TCLK1 TAIS1
2
C9 0.1 L15 +3.3V bead
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RVDD3 RLINE3P RLINE3M RVSS3 PD3 RLOOP3 LLOOP3 DVSSIO LBO3 XOE3 REQH3 N/C1 N/C2 N/C3 RNEG3/RLCV3 RPOS3/RNRZ3 RCLK3 RLOS3 REFCLK3 TLOS3 TNEG3/NC3 TPOS3/TNRZ3 TCLK3 TAIS3 N/C4
2
100985A
+3.3V Chn 1 R23 +3.3V L17 1k 1 2 3 4 5 6 7 SW1 14 13 12 11 10 9 8 TMUXIO1 TMUXIO2 PD1 PD1 RLOOP1 RLOOP1 LLOOP1 LLOOP1 LBO1 LBO1 XOE1 XOE1 TAIS1/TMUXA2 TAIS1/TMUXA2 REQH1/TMUXDAT REQH1/TMUXDAT +5V J7 1 TMUXIO1 TMUXIO2 PD1 RLOOP1 LLOOP1 C12 0.1 +3.3V +3.3V L13 L12 +3.3V L16 bead +3.3V +3.3V 12.1K R13 TNEG1/NC1 TPOS1/TNRZ1 TCLK1 +3.3V C11 0.1 LBO1 XOE1 REQH1/TMUXDAT RNEG1/RLCV1 RPOS1/RNRZ1 RCLK1 RLOS1 REFCLK TLOS1 TNEG1/NC1 TPOS1/TNRZ1 TCLK1 TAIS1/TMUXA2 RNEG1/RLCV1 RPOS1/RNRZ1 RCLK1 +3.3V Chn 2 R22 1k ENDECDIS PD2 RLOOP2 LLOOP2 RNEG2/RLCV2 RNEG2/RLCV2 RPOS2/RNRZ2 RPOS2/RNRZ2 RCLK2 RCLK2 RLOS2 R18 0 R19 0 U1
1
1
L1
6
R1
2
5
31.6
3
2,3,4
Pulse
4
R2
T3001
31.6
J2
Channel 1 Receive
1
1
L2
6
R3
2
5
37.4
C1
2,3,4
3
Pulse
4
R4
0.01
T3001
37.4
J3
Channel 2 Transmit
1
1
L3
6
R5
2
5
31.6
3
CX28331/CX28332/CX28333
2,3,4
Pulse
4
R6
T3001
31.6
1
1
L4
6
R7
2
5
37.4
C2
3
4
R8
0.01
J5
Channel 3 Transmit
1
1
L5
6
R9
2
5
31.6
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
3
2,3,4
Pulse
4
R10
T3001
31.6
CX28333 DS3/E3/STS-1 LIU
1 2 3 4 5 6 7 SW2
R20 R21 L14 +3.3V bead C8 0.1 0
0
TAIS2/TMUXA3 TCLK2 TCLK2 TPOS2/TNRZ2 TPOS2/TNRZ2 TNEG2/NC2 TNEG2/NC2 TLOS2 REFCLK +3.3V REQH2/TMUXA0 XOE2 1 LBO2 E3MODE TMUXLAT
14 13 12 11 10 9 8
PD2 RLOOP2 LLOOP2 LBO2 XOE2 TAIS2/TMUXA3 REQH2/TMUXA0
PD2 RLOOP2 LLOOP2 LBO2 XOE2 TAIS2/TMUXA3 REQH2/TMUXA0
J21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TMON1P TLINE1P TLINE1M TMON1M TVDD1 RVDD1 RLINE1P RLINE1M RVSS1 TVSS2 TMON2P TLINE2P TLINE2M TMON2M TVDD2 RVDD2 RLINE2P RLINE2M RVSS2 TVSS3 TMON3P TLINE3P TLINE3M TMON3M TVDD3 DVDDC ENDECDIS PD2 RLOOP2 LLOOP2 RNEG2/RLCV2 RPOS2/RNRZ2 RCLK2 RLOS2 N/C7 N/C6 N/C5 TAIS2 TCLK2 TPOS2/TNRZ2 TNEG2/NC2 TLOS2 REFCLK2 REQH2 XOE2 LBO2 TMONTST E3MODE NC11 DVSSC TMUXLAT
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Figure B-2. Recommended Schematic for the CX2833i-3x Device (1 of 2)
Conexant
TAIS3/TMUXA4 TCLK3 TPOS3/TNRZ3 TNEG3/NC3 TLOS3 REFCLK RLOS3 RCLK3 RPOS3/RNRZ3 RNEG3/RLCV3 REQH3/TMUXA1 XOE3 LBO3 LLOOP3 RLOOP3 PD3 +3.3V Chn 3 R25 1k 1 2 3 4 5 6 7 SW3 2 402 2 402 2 402 Red Led 402 R16 TLOS3 1 2 Red Led +3.3V CR3 JP11 R62 402 CR62 R15 TLOS2 1 2 CR2 JP10 R61 CR61 402 R14 CR1 JP9 TLOS1 1 2 R60 CR60 14 13 12 11 10 9 8
+3.3V R24 TCLK3 TPOS3/TNRZ3 TNEG3/NC3 E3MODE 1k E3MODE 1 ENDECDIS2 SW4 RCLK3 RPOS3/RNRZ3 RNEG3/RLCV3 4 3
J6
Channel 3 Receive
1
1
L6
6
R11
2
5
37.4
C3
3
2,3,4
Pulse
4
R12
0.01
T3001
37.4
+3.3V PD3 RLOOP3 LLOOP3 LBO3 XOE3 TAIS3/TMUXA4 REQH3/TMUXA1 R36 1k PD3 RLOOP3 LLOOP3 LBO3 XOE3 TAIS3/TMUXA4 REQH3/TMUXA1 1 2 3 4 5 6 SW7 12 11 10 9 8 7 REQH1/TMUXDAT REQH2/TMUXA0 REQH3/TMUXA1 TAIS1/TMUXA2 TAIS2/TMUXA3 TAIS3/TMUXA4
JP6
RLOS1
1
CH1_RLOS CH2_RLOS CH3_RLOS
CH1_TLOS CH2_TLOS CH3_TLOS
JP7
RLOS2
1
JP8
RLOS3
1
Note: All capacitors are in Microfarads NC
Socket
Y1 1 7
Vcc
14 8
C13 .1
SW10 TMUXIO1 1 R17
SW9 TMUXLAT1 4
4 +3.3V +3.3V REFCLK REFCLK 42.2 44.736/34.368/51.256Mhz +/- 20ppm 2 3 Title
Conexant Systems 9868 Scranton Road San Diego,Ca 92121
Gnd
Out
2
3
CX 28333 (LIU) w/Jitter Attenuator Circuit
Reset Device
Size C Date:
Document Number BT01-D630Sheet 1 of 2
Notes: Seven Position Dip switch for all Channels (SW1,2,3) Position 1 PDB# ( 0 = Powerdown 1 = Active) Position 2 RLOOP# ( 0 = RLPBK Disable 1 = RLPBK Enable) Position 3 LLOOP# ( 0 = LPBK Disable 1 = LPBK Enable) Position 4 LBO# ( 0 = Tx Cable > 250ft 1 = Tx Cable < 250ft) Position 5 XOE# ( 0 = Tx Disable 1 = Tx Enable) Position 6 TAIS# ( 0 =Tx AIS Disable 1 = Tx AIS Enable) Position 7 REQH# ( 0 =EQ Disable 1 = EQ Enable)
Rev A
Appendix B
B.1 Evaluation Module Schematic
100985_010
B-3
R26 1Meg
RNEG1/RLCV1
RNEG2/RLCV2
DJATCLK3 RCLK2
DJATCLK1 RCLK1 RNEG3/RLCV3 DJATCLK2
RCLK3
VCO2
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
VCCIO_7 RNEG1 NC/89 RNEG2 NC/88 NC/87 NC/86 DJATCK3 RCLK2 GND_15 DJATCK1 RCLK1 RNEG3 DJATCK2 VCCI_4 GND_14 GND_13 RSTN GND_12 RCLK3 GND_11 VCCI_3 NC/85 NC/84 NC/83 NC/82 NC/81 NC/80 NC/79 VCCIO_6 VCO2 NC/78 NC/77 NC/76 NC/75 NC/74
NC/19 NC/20 NC/21 NC/22 NC/23 NC/24 NC/25 NC/26 NC/27 NC/28 NC/29 NC/30 NC/31 VCCIO_2 VCCI_1 GND_5 NC/32 VCO3 NC/33 NC/34 GND_6 VCCI_2 GND_7 NC/35 NC/36 NC/37 NC/38 GND_8 NC/39 NC/40 NC/41 NC/42 NC/43 NC/44 NC/45 NC/46
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VCO3
1Meg 7 VCO DIJITCK1 +3.3V 8 DJATCLK1
VCO1_CNTRL
0.1 2 CR13 R40 330 Green Led Y3 14 8 DJATCLK2 7 VCO DIJITCK2 +3.3V C28 .1 C20 0.1 C21 220
1Meg
JP5
R33
C17
1
B-4
JP1 DJATCLK1 DJATPOS1 DJATNEG1 DJATCLK2 DJATPOS2 DJATNEG2 DJATCLK3 DJATPOS3 DJATNEG3 REFCLK TCLK2 RCLK2 TPOS2/TNRZ2 RPOS2/RNRZ2 TNEG2/NC2 RNEG2/RLCV2 TCLK2 RCLK2 TPOS2/TNRZ2 RPOS2/RNRZ2 TNEG2/NC2 RNEG2/RLCV2 TCLK1 RCLK1 TPOS1/TNRZ1 RPOS1/RNRZ1 TNEG1/NC1 RNEG1/RLCV1 TCLK1 RCLK1 TPOS1/TNRZ1 RPOS1/RNRZ1 TNEG1/NC1 RNEG1/RLCV1 JP2 JP3 +3.3V +3.3V D14 J20 DIODE C26 10 TDI Header Header Header TCK TDO TMS 12 34 56 78 9 10 TCLK3 RCLK3 TPOS3/TNRZ3 RPOS3/RNRZ3 TNEG3/NC3 RNEG3/RLCV3 TCLK3 RCLK3 TPOS3/TNRZ3 RPOS3/RNRZ3 TNEG3/NC3 RNEG3/RLCV3 REFCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 +3.3V R27 330 1 TMUXIO1 C14 0.1 J14 TMUXIO1 J12 TMUXLAT REQH2/TMUXA0 REQH3/TMUXA1 TAIS1/TMUXA2 TAIS2/TMUXA3 TAIS3/TMUXA4 REQH1/TMUXDAT +3.3V R28 330 C15 0.1 1 TMUXIO2 J15 TMUXIO2 TMUXLAT REQH2/TMUXA0 REQH3/TMUXA1 TAIS1/TMUXA2 TAIS2/TMUXA3 TAIS3/TMUXA4 REQH1/TMUXDAT TDO 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 J13 RLOOP1 E3MODE XOE1 RLOOP2 XOE2 RLOOP3 XOE3 REQH2/TMUXA0 TMUXLAT U3 RLOOP1 E3MODE XOE1 RLOOP2 XOE2 RLOOP3 XOE3 REQH2/TMUXA0 TMUXLAT 144 Pin - TQFP CHANNEL1_STATUS VCO1 TCK
Appendix B
B.1 Evaluation Module Schematic
RPOS3/RNRZ3 RPOS2/RNRZ2
TDI
RPOS1/RNRZ1
DJATNEG2
DJATNEG3 DJATPOS2
CHANNEL3_STATUS DJATPOS3 TMS
Figure B-3. Recommended Schematic for the CX2833i-3x Device (2 of 2)
Conexant
Conexant Jitter Attenuator
CHANNEL1_STATUS CHANNEL2_STATUS CHANNEL3_STATUS J22 Red - Banana - Jack +3.3V Y2 14 C27 .1 +5VSRC J24 Blue Banana - Jack +5V U2 JP4 2 VIN VOUT GND LT1086-3.3 1 2 C22 10 3 1
DJATNEG1 DJATPOS1 CHANNEL2_STATUS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC/73 NC/72 NC/71 GND_10 TDO NC/70 NC/69 NC/68 NC/67 NC/66 NC/65 NC/64 NC/63 VCCIO_5 NC/62 NC/61 STATUS1 VCO1 NC/60 TCK NC/59 NC/58 NC/57 GND_9 NC/56 NC/55 NC/54 NC/53 NC/52 NC/51 NC/50 NC/49 VCCIO_4 NC/48 NC/47 VCCIO_3 PD1 LLOOP1 LBO1 TAIS1/TMUXA2 PD2 LLOOP2 LBO2 TAIS2/TMUXA3 PD3 LLOOP3 LBO3 TAIS3/TMUXA4 REQH1/TMUXDAT REQH3/TMUXA1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 PD1 LLOOP1 LBO1 TAIS1/TMUXA2 PD2 LLOOP2 LBO2 TAIS2/TMUXA3 PD3 LLOOP3 LBO3 TAIS3/TMUXA4 REQH1/TMUXDAT REQH3/TMUXA1
RPOS3 RPOS2 GND_1 TDI NC/1 NC/2 NC/3 NC/4 NC/5 RPOS1 NC/6 DJATNEG2 GND_2 NC/7 DJATNEG3 DJATPOS2 GND_3 STATUS3 DJATPOS3 TMS NC/8 NC/9 NC/10 VCCIO_1 DJATNEG1 DJATPOS1 STATUS2 NC/11 NC/12 NC/13 NC/14 NC/15 GND_4 NC/16 NC/17 NC/18
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
R32
VCO1
C16 0.1
VCO1_CNTRL 1
Optional external 3.3V Supply Please remove JP3 when in use
+3.3V
R34
VCO2
C18 0.1
1Meg
VCO2_CNTRL 1
+
C23 0.1
R35
C19
25V 1 square inch copper plane used for heat sink
VCO2_CNTRL
0.1
1Meg
R37 Y4 1 7 VCO DIJITCK3 8 DJATCLK3 14 C29 .1
VCO3
C24 0.1 Black- Banana - Jack J23
1Meg
R38
C25
VCO3_CNTRL
VCO3_CNTRL
0.1
1Meg
Conexant Systems 9868 Scranton Road San Diego,Ca 92121
Title Size C Date: CX 28333 (LIU) w/Jitter Attenuator Evualation Module Document Number BT01-D630Sheet 2 of 2 Rev A
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
CX28331/CX28332/CX28333
100985_011
100985A
0.0 Sales Offices
Further Information: literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com World Headquarters Conexant Systems, Inc. 4311 Jamboree Road, P.O. Box C Newport Beach, CA 92658-8902 Phone: (949) 483-4600 Fax: (949) 483-6375 U.S. Florida/South America Phone: (727) 799-8406 Fax: (727) 799-8306 U.S. Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Mid-Atlantic Phone: (215) 244-6784 Fax: (215) 244-9292 U.S. North Central Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. Northeast Phone: (978) 692-7660 Fax: (978) 692-8185 U.S. Northwest/Pacific West Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. South Central Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Southeast Phone: (919) 858-9110 Fax: (919) 858-8669 U.S. Southwest Phone: (949) 483-9119 Fax: (949) 483-9090 APAC Headquarters Conexant Systems Singapore, Pte. Ltd. 1 Kim Seng Promenade Great World City #09-01 East Tower Singapore 237994 Phone: (65) 737 7355 Fax: (65) 737 9077 Australia Phone: (61 2) 9869 4088 Fax: (61 2) 9869 4077 China Phone: (86 2) 6361 2515 Fax: (86 2) 6361 2516
Hong Kong Phone: (852) 2 827 0181 Fax: (852) 2 827 6488 India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 Korea Phone: (82 2) 565 2880 Fax: (82 2) 565 1440 Europe Headquarters Conexant Systems France Les Taissounieres B1 1681 Route des Dolines BP 283 06905 Sophia Antipolis Cedex France Phone: (33 4) 93 00 33 35 Fax: (33 4) 93 00 33 03 Europe Central Phone: (49 89) 829 1320 Fax: (49 89) 834 2734 Europe Mediterranean Phone: (39 02) 9317 9911 Fax: (39 02) 9317 9913 Europe North Phone: (44 1344) 486 444 Fax: (44 1344) 486 555 Europe South Phone: (33 1) 41 44 36 50 Fax: (33 1) 41 44 36 90 Middle East Headquarters Conexant Systems Commercial (Israel) Ltd. P.O. Box 12660 Herzlia 46733, Israel Phone: (972 9) 952 4064 Fax: (972 9) 951 3924 Japan Headquarters Conexant Systems Japan Co., Ltd. Shimomoto Building 1-46-3 Hatsudai, Shibuya-ku, Tokyo 151-0061 Japan Phone: (81 3) 5371 1567 Fax: (81 3) 5371 1501 Taiwan Headquarters Conexant Systems, Taiwan Co., Ltd. Room 2808 International Trade Building 333 Keelung Road, Section 1 Taipei 110, Taiwan, ROC Phone: (886 2) 2720 0282 Fax: (886 2) 2757 6760

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