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CXA1372BQ/BS
RF Signal Processing Servo Amplifier for CD Player
Description The CXA1372BQ/BS is a bipolar IC developed for RF signal processing (focus OK, mirror, defect detection, EFM comparator) and various servo control. Features * Dual 5V and single 5V power supplies * Low power consumption * Fewer external parts * Disc defect countermeasure circuit * Fully compatible with the CXA1182 for microcomputer software Functions * Auto asymmetry control * Focus OK detection circuit * Mirror detection circuit * Defect detection, countermeasure circuit * EFM comparator * Focus servo control * Tracking servo control * Sled servo control Structure Bipolar silicon monolithic IC CXA1372BQ 48 pin QFP (Plastic) CXA1372BS 48 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta = 25C) 12 V * Supply voltage VCC - VEE * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 457 (CXA1372BQ) mW 833 (CXA1372BS) mW Recommended Operating Conditions VCC - VEE 3.6 to 11 VCC - DGND 3.6 to 5.5
V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E95927A67-PS
CXA1372BQ/BS
Block Diagram
C. OUT DGND DFCT SENS XRST
24 DATA CB 37 CP 38 RFI 39 * TTL * IIL 23 XLT 22 CLK 21 LOCK * IIL DATA REGISTER DVEE 41 * TTL * IIL * INPUT SHIFT REGISTER * ADDRESS DECODER 20 DIRC 19 AVEE TG1 TM1 * I SET ATSC 45 * BPF * WINDOW COMPARATOR * FOCUS PHASE COMPENSATION DFCT FS1 TM7 TM4 TM3 FS4 FS3 FS2 TG2 TM2 14 SLO 13 SL+ TM6 TM5 * F SET 17 ISET 16 FSET 15 SL- * TRACKING PHASE COMPENSATION 18 SSTOP 12
DVcc
EFM
FOK
ASY
MIRR
CC2
CC1
36
35
34
33
32 31 30
29
28
27
26 25
* IIL * TTL
RFO 40
* OUTPUT DECODER TZC 42 * FS1 to 4 TE 43 TDFCT 44 DFCT * TG1 to 2 * TM1 to 7 * PS1 to 3
FZC 46 FE 47 FDFCT 48
1
2
3
4
5
6
7
8
9
10
11
FGD
FEO
TG2
SRCH
AVCC
TGU
TAO
FLB
FE-
VC
FS3
-2-
TA-
CXA1372BQ/BS
Pin Configuration CXA1372BQ
DGND C. OUT
26
SENS
DFCT
EFM
36 CB 37 CP 38 RFI 39 RFO 40 DVEE 41 TZC 42 TE 43 TDFCT 44 ATSC 45 FZC 46 FE 47 FDFCT 48 1
35
CC1
34
33
32
31
30
29
28
27
25 24 DATA 23 XLT 22 CLK 21 LOCK 20 DIRC 19 AVEE
CXA1372BQ 18 SSTOP 17 ISET 16 FSET 15 SL- 14 SLO 13 SL+ 2 3 4 5 6 7 8 9 10 11 12
FEO
AVcc
FS3
SRCH
FGD
TGU
CXA1372BS
C. OUT
DGND
TAO
FLB
FE-
TG2
TA-
VC
XRST
DVcc
CC2
MIRR
FOK
ASY
SENS
DFCT
MIRR
XRST
LOCK
DVEE
DATA
DIRC
26 23
DVcc
RFO
EFM
CC2
CC1
TZC
ASY
CB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CLK
RFI
CP
30
29
28
27
25
CXA1372BS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
FGD
FLB
FS3
FE-
TE
SRCH
-3-
SSTOP
FE
TDFCT
TGU
TG2
ATSC
FSET
TZC
AVcc
SLO
VC
SL+
FDFCT
ISET
TAO
FEO
TA-
SL-
AVEE
FOK
XLT
CXA1372BQ/BS
Pin Description Pin No. Q S Symbol I/O Equivalent circuit Description Center voltage input. For dual power supplies: GND For single power supply: (VCC + GND)/2
1
7
VC
I
Vcc 147 48k 130k VEE
2
8
FGD
I
2 20A
Connects a capacitor between this pin and Pin 3 to cut high-frequency gain.
46k
580k
3
9
FS3
I
3
The high-frequency gain of the focus servo is switched through FS3 ON and OFF.
4
10
FLB
I
40k 4
External time constant to boost the low frequency of the focus servo.
5
11
FEO
O
5
Focus drive output.
11
17
TAO
O
11 14 250A 2.5A
Tracking drive output.
14
20
SLO
O
Sled drive output.
90k
6
12
FE-
147
I
6 40k 2.5A
Inverted input for focus amplifier.
-4-
CXA1372BQ/BS
Pin No. Q S
Symbol
I/O
Equivalent circuit
Description
147
7
13
SRCH
I
7 50k 3.5A 11A
External time constant for forming the focus search waveforms.
110k
8
14
20k
TGU
I
8 82k
External time constant for selecting the tracking high-frequency gain.
147
9
15
TG2
I
9 470k
External time constant for selecting the tracking high-frequency gain.
90k
12
18
TA-
147
I
12 3A 11A
Inverted input for tracking amplifier.
10k
13
19
SL+
I
13
Non-inverted input for sled amplifier.
15
21
SL-
I
147 15 3A 22A
Inverted input for sled amplifier.
-5-
CXA1372BQ/BS
Pin No. Q S
Symbol
I/O
Equivalent circuit
Description
147
16
22
FSET
I
16 15k 15k
Sets the peak frequency of focus tracking phase compensation.
147
17
23 ISET
I
17
Current is input to determine focus search, track jump, and sled kick level.
7A 147 18
18
24
SSTOP
I
Limit SW ON/OFF signal detection for disc innermost track detection.
20
26
DIRC
I
Used for 1-track jump. Contains a 47k pull-up resistor. At "Low" sled overrun prevention circuit operates. Contains a 47k pull-up resistor.
47k 147 15A
21
27
LOCK
I
20 21
22
28
CLK
I
22 23 24
Serial data transfer clock input from CPU. (no pull-up resistor) Latch input from CPU. (no pull-up resistor) Serial data input from CPU. (no pull-up resistor) Reset input, reset at "Low". (no pull-up resistor)
23 24 25
29 30 31
XLT DATA XRST
I I I
25
26
32
C. OUT
O
20k 147 26 27
Track number count signal output.
27
33
SENS
O
100k
Outputs FZC, AS, TZC and SSTOP through command from CPU.
-6-
CXA1372BQ/BS
Pin No. Q S
Symbol
I/O
Equivalent circuit
Description
29
35
MIRR
O
38
147
MIRR comparator output. (DC voltage: 10k load connected)
147 29
38
44
CP
I
20k
Connects MIRR hold capacitor. Non-inverted input for MIRR comparator.
34
40
CC1
O
147 147 37 35
DEFECT bottom hold output.
35
41
CC2
I
Input for DEFECT bottom hold output with capacitance coupled.
30
36
DFCT
O
30
147
147 34
DEFECT comparator output. (DC voltage: 10k load connected)
37
43
CB
I
Connects DEFECT bottom hold capacitor.
31
37
ASY
I
147 31
Auto asymmetry control input.
32
4.8k
32
38
EFM
O
Current source depending on power supply (VCC to DGND)
EFM comparator output. (DC voltage: 10k load connected)
20k 147 33
33
39
FOK
O
FOK comparator output. (DC voltage: 10k load connected)
-7-
CXA1372BQ/BS
Pin No. Q S
Symbol
I/O
Equivalent circuit
Description
39
45
RFI
I
40k 147 39
Input for RF summing amplifier output with capacitance coupled.
40
46
RFO
O
40
147
RF summing amplifier output. Check point of eye pattern.
7A 147 42 75k
42
48
TZC
I
Tracking zero-cross comparator input.
43
1
TE
I
147 43
470k
Tracking error input.
147
44
2
TDFCT
I
44
Connects a capacitor for time constant during defect.
Vcc
470k
45
3
ATSC
I
45 330k VEE 47P
Window comparator input for ATSC detection.
46
4
FZC
I
46
60k 147 1.2k
Focus zero-cross comparator input.
47
5
FE
I
147 47
470k
Focus error input.
147
48
6
FDFCT
I
48
Connects a capacitor for time constant during defect.
-8-
Electrical Characteristics SW condition S1 S2 S3 S4 S5 S6 S7 S8 S9 E1 E2 E3 E4 point method 00 10, 36 8 -24 V1 = 10Hz, 100mVp-p GFEO = 20 log (Vout/Vin) 18.0 SG = 10kHz, 40mVp-p Difference in gain when SD = 00 and SD = 08 V1 = 0.5VDC V1 = -0.5VDC V1 = 0.5VDC V1 = -0.5VDC -640 360 (VCC + DGND)/2 = SENS value when E4 is varied. 27 11 V2 = 10Hz, -500mVp-p GTEO = 20 log (Vout/Vin) 11 11 11 25 25 2C 28 11 11 11 11 V2 = 10kHz, 40mVp-p Difference in gain when SD = 00 and SD = 25 V2 = -0.5VDC V2 = 0.5VDC V2 = -0.5VDC V2 = 0.5VDC -640 360 1.2 -1.2 -360 640 2.0 -2.0 39 11.6 50 13.3 1.2 -1.2 -360 640 61 17.6 2.0 -2.0 21.0 -17 -8 24.0 19 27 19, 41 5 SD
ment waveform and measurement Min.
(Ta = 25C, VCC = 2.5V, VEE = -2.5V, D. GND = -2.5V) Bias condition Measure- Description of output Typ. Max. Unit mA mA dB
No.
Item
Symbol
1 00 08
Current consumption
ICC
2
Current consumption
IEE
3
DC voltage gain
GFEO
4 O O OO OO 02 5 5 03 00 25 08 5 08 5 08 5 08 5
Feedthrough
VFEOF
00 5
-35
dB V V V V mV mV mV dB
5
Max. output voltage
VFE01
6
Max. output voltage
VFE02
7
Max. output voltage
VFE03
FOCUS SERVO
8
Max. output voltage
VFE04
TRACKING SERVO
-9- 00 O 25 25 O OO OO
9
Search output voltage
VSRCH1
10
Search output voltage
VSRCH2
11
FZC threshold value VFZC
12
DC voltage gain
GTEO
13
Feedthrough
VTEOF
-39
dB V V V V mV mV
14
Max. output voltage
VTE01
15
Max. output voltage
VTE02
16
Max. output voltage
VTE03
17
Max. output voltage
VTE04
18
Jump output voltage VJUMP1
CXA1372BQ/BS
19
Jump output voltage VJUMP2
No. S1 S2 S3 S4 S5 S6 S7 S8 S9 E1 E2 E3 E4 point 10 27 27 7 26 0 20 45 -20 50 27 14 V5 = 10Hz, 20mVp-p Open loop gain V5 = 10kHz, 100mVp-p Difference in gain when SD = 00 and SD = 25 V5 = 1.0VDC V5 = -1.0VDC V5 = 1.0VDC V5 = -1.0VDC -750 450 (VCC + DGND)/2 = SENS value when E1 is varied. 27 27 26 33 33 33 33 V4 = 1Vp-p - 375mVDC 45 (VCC + DGND)/2 = value between Pins 39 and 40 when V4 is varied. -400 -356 2.2 -1.8 -40 -25 2.0 -2.0 -450 750 -10 -2.0 -2.0 -330 2.0 -2.0 (VCC + DGND)/2 = SENS value when E2 is varied. (VCC + DGND)/2 = SENS value when E3 is varied. -45 -26 -7 mV mV mV dB SD
ment waveform and measurement Min. method
Item
Symbol Typ. Max. Unit
SW condition
Bias condition Measure- Description of output
20 10 20 25
ATSC threshold value VATSC1
TRACKING SERVO
21
ATSC threshold value VATSC2
22
TZC threshold value
VTZC
23
DC voltage gain
GSLO
24 25 14 14 14 14 14 14 25 O O 23 22 30 25 25
Feedthrough
VSLOF 00 14
-34
dB V V V V mV mV mV V V mV V V
CXA1372BQ/BS
25
Max. output voltage
VSL01
26
Max. output voltage
VSL02
SLED SERVO
27
Max. output voltage
VSL03
FOK
- 10 -
28
Max. output voltage
VSL04
29
Kick output voltage
VKICK1
30
Kick output voltage
VKICK2
31
SSTOP threshold value
VSSTOP
32
SENS Low level
VSENS
33
COUT Low level
VCOUT
34
FOK threshold value
VFOKT
35
High level voltage
VFOKH
36
Low level voltage
VFOKL
37
Max. operating frequency
FFOK
kHz
No. S1 S2 S3 S4 S5 S6 S7 S8 S9 E1 E2 E3 E4 point 29 29 -2.0 30 0.3 V4 = 10kHz - 0.4VDC 29 30 30 30 V4 = 0.8Vp-p + 375mVDC 30 30 30 O O OO OO O O 31 31 32 V4 = 750kHz, 0.7Vp-p 32 A V4 = 750kHz A 1.8 Vp-p -1.2 0.12 V 2.5 0.5 V4 = 50Hz + 375mVDC (square wave) V4 = 750kHz, 0.7Vp-p V4 = 750kHz, 0.7Vp-p + 0.25VDC 1.8 -50 0 1.2 0 50 50 100 kHz Vp-p Vp-p mV mV V 1.8 1.8 -2.0 1 Vp-p V V kHz 29 29 V4 = 800mVp-p - 0.4VDC V4 = 10kHz 1.0Vp-p - 0.4VDC V V kHz Vp-p 1.8 SD
ment waveform and measurement Min. method
Item
Symbol
SW condition Typ. Max. Unit
Bias condition Measure- Description of output
38
High level voltage
VMIRH
39
Low level voltage
VMIRL
MIRROR
40
Max. operating frequency
FMIR
41
Min. input operating voltage
VMIR1
42
Max. input operating voltage
VMIR2
43
High level output voltage
VDFCTH
44
Low level output voltage
VDFCTL
45
Min. operating frequency
FDFCT1
DEFECT
EFM
- 11 -
46
Max. operating frequency
FDFCT2
47
Min. input operating voltage
VDFCT1
48
Max. input operating voltage
VDFCT2
49
Duty 1
DEFM1
50
Duty 2
DEFM2
51
High level output voltage
VEFMH
52
Low level output voltage
VEFML
CXA1372BQ/BS
53
Min. input operating voltage
VEFM1
Vp-p
54
Max. input operating voltage
VEFM2
CXA1372BQ/BS
Electric Characteristics Measurement Circuit
A Vcc DGND DGND
1k
DVcc 3300P
DGND DGND DGND Vcc Vcc Vcc
S9 S8 10k 10k 10k
28 27 26
DGND
10k
10k
1M
0.01
A
36 35 34 33 32 31 30
10k
25
29
CC2
MIRR
SENS
EFM
CC1
ASY
C. OUT
DVcc
DFCT
37 CB DGND DGND
+
DGND
XRST
FOK
1000P 38 CP 3300P V4 AC V3 39 RFI 40 RFO
DATA 24 XLT CLK LOCK DIRC 23 22 21 20
DATA XLT CLK
DVEE
GND GND
AC 41 DVEE 42 TZC
SSTOP 18 ISET 17 240k FSET 16 510k 5.1k SL- 15
GND
+
E2
V2 AC
43 TE 44 TDFCT
GND GND
0.1
60k
45 ATSC GND
46 FZC
SLO 14 S7 SL+ 13
+
E4
GND
+
V1 AC
47 FE
13k
V5 AC
SRCH
48 FDFCT
AVcc
FGD
TGU
FEO
TG2
FS3
FE-
TAO
0.1
FLB
TA-
VC
GND
GND
1
2
3
4
5 100k
6
7 0.033
8
9
10
1000P
0.1
GND
11 100k
12
A
S2 200k S4 200k S5
S1
S3
130
13k
GND
GND
GND
GND
- 12 -
130 S6
AVcc
13k
GND
E3
130
E1
A
AVEE 19
A
Vcc GND GND AVEE Vcc Vcc
CXA1372BQ/BS
Description of Functions Focus Servo
1.2k 56k FZC FE 10k 22k 2200p 47 FE 470k 48 0.1 2 0.1 3 FS3 580k FS3 46k 40k 10k 17 50k FS1 FLB 4 0.1 FSET 16 510k 0.01 SRCH 7 4.7 DGND 11 22 FDFCT FGD FS2 40k 6 120k ISET 120k FE- FS4 DFCT 20k 48k Focus Phase Compensation 100k 5 FEO FOCUS COIL 46 FZC
The above figure shows a block diagram of the focus servo. Ordinarily the FE signal is input to the focus phase compensation circuit through a 20k and 48k resistance; however, when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal 470k resistance and the capacitance connected to Pin 48. When this DFCT countermeasure circuit is not used, leave Pin 48 open. When FS3 is ON, the high-frequency gain can be cut by forming a low-frequency time constant through a capacitor connected between Pins 2 and 3 and the internal resistor. The capacitor connected between Pin 4 and GND is a time constant to boost the low frequency in the normal playback state. The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510k is connected to Pin 16. The focus search level is approximately 1.1Vp-p when using the constants indicated in the above figure. This level is inversely proportional to the resistance connected between Pin 17 and GND. However, changing this resistance also changes the level of the track jump and sled kick as well. The FZC comparator inverted input is set to 2% of VCC and VC (Pin 1); (VCC - VC) x 2%. 510k resistance is recommended for Pin 16.
- 13 -
CXA1372BQ/BS
Tracking Sled Servo
100k 0.022 42 TZC 100k 18 SSTOP 100k 1k SLO 14 0.047 ATSC 45 BPF TE 43 TE 22k 44 0.1 TDFCT 470k 1k 1k TM6 10k 100k DFCT 680k TG1 TM1 TGU 8 0.033 9 470k FSET 16 510k 0.01 20k TG2 TG2 TG1 10k 680K 66P 10k TM5 22A 11A TM4 12 TM3 11A 90k TAO 11 13 TM2 TA- 100k TRACKING COIL 82k 15k ATSC 22A 15 SL+ 3.3 22 SLED MOTOR
TZC
SSTOP
M
0.015 SL- 120k 8.2k
Tracking Phase Compensation
TM7
The above figure shows a block diagram of the tracking and sled servo. The capacitor connected between Pins 8 and 9 is a time constant to cut the high-frequency gain when TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510k resistance connected to Pin 16. To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be more specific, Track jump peak voltage = TM3 (or TM4) current x feedback resistance The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15; Sled kick peak voltage = TM5 ( or TM6) current x feedback resistance The values of the current for each switch are determined by the resistance connected between Pin 17 and GND. When this resistance is 120k: TM3 ( or TM4) = 11A, and TM5 (or TM6) = 22A. This current value is almost inversely proportional to the resistance and the variable range is approximately 5 to 40A at TM3. SSTOP is the ON/OFF detection signal for the limit SW of the linear motor's innermost track. As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the internal resistance (470k) and the capacitor connected to Pin 44. TM-1 was ON at DFCT in the CXA1082 and CXA1182, but it does not operate in the CXA1372. - 14 -
CXA1372BQ/BS
Focus OK circuit
VCC
RFO RF signal C5 0.01 RFI 40 39 15k x1 VG 54k
20k 33 FOK 92k 0.625V
FOCUS OK AMP
FOCUS OK COMPARATOR
The focus OK circuit creates the timing window okaying the focus servo from the focus search state. The HPF output is obtained at Pin 39 from Pin 40 (RF signal), and the LPF output (opposite phase) of the focus OK amplifier output is also obtained. The focus OK output reverses when VRFI - VRFO -0.37V. Note that, C5 determines the time constants of the HPF for the EFM comparator and mirror circuit and the LPF of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01F selected, the fc is equal to 1kHz, and block error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented.
EFM comparator EFM comparator changes RF signal to a binary value. The asymmetry generated due to variations in disc manufacturing cannot be eliminated by the AC coupling alone. Therefore, the reference voltage of EFM comparator is controlled through 1 and 0 that are in approximately equal numbers in the binary EFM signals.
VC AUTO ASYMMETRY CONTROL AMP 100k x6 ASY 20k 31 C8 C9 CMOS BUFFER R8 R9
Vcc 40k 40k
AUTO ASYMMETRY BUFFER
DGND = 0V
RFI
39 EFM COMPARATOR
32 EFM
CXD2500
As this comparator is a current SW type, each of the High and Low levels is not equal to the power supply voltage. A feedback has to be applied through the CMOS buffer. R8, R9, C8, and C9 form a LPF to obtain (VCC + DGND)/2V. When fc (cut-off frequency) exceeds 500Hz, the EFM low-frequency components leak badly, and the block error rate worsens.
- 15 -
CXA1372BQ/BS
DEFECT circuit After inversion, RFI signal is bottom held by means of the long and short time constants. The long timeconstant bottom hold keeps the mirror level prior to the defect. The short time-constant bottom hold responds to a disc mirror defect in excess of 0.1ms, and this is differentiated and level-shifted through the AC coupling circuit. The long and short time-constant signals are compared to generate at mirror defect detection signal.
0.033 CC1 34 CC2 35
RFO 40
a x2
b
c d
e 30 DFCT
DEFECT AMP 37 CB 0.01
DEFECT BOTTOM HOLD
DEFECT COMPARATOR
a
RFO
b
DEFECT AMP
c
BOTTOM HOLD (1); Solid line CC1 H DEFECT L
d
BOTTOM HOLD (2); Dotted line CC2
e
- 16 -
CXA1372BQ/BS
Mirror Circuit The mirror circuit performs peak and bottom hold after the RFI signal has been amplified. For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation.
RFO
MIRROR HOLD AMP 0.033 38 39 PEAK & BOTTOM HOLD H
x1
CP J K 29 20k MIRROR COMPARATOR DGND MIRR
RFI
x 2.2
G MIRROR AMP
I
RFO 0V G (RFI)
0V
H (PEAK HOLD)
0V
I (BOTTOM HOLD) J K (MIRROR HOLD)
0V
MIRR
H L
Through differential amplification of the peak and bottom hold signals H and I, mirror output can be obtained by comparing an envelope signal J (demodulated to DC) to signal K for Which peak holding at a level 2/3 that of the maximum was performed with a large time constant. In other words, mirror output is low for tracks on the disc and high for the area between tracks (the MIRR areas). In addition, a high signal is output when a defect is detected. The mirror hold time constant must be sufficiently large in comparison with the traverse signal.
- 17 -
CXA1372BQ/BS
Commands The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F. Commands for the CXA1372 can be broadly divided into four groups ranging in value from $0X to $3X. 1. $0X ("FZC" at SENS (Pin 27)) These commands are related to focus servo control. The bit configuration is as shown below. D7 0 D6 0 D5 0 D4 0 D3 FS4 D2 FS3 D1 FS2 D0 FS1
Four focus-servo related switches exist: FS1 to FS4 corresponding to D0 to D3, respectively. $00 $02 When FS1 = 0, Pin 7 is charged to (22A - 11A) x 50k = 0.55V. If FS2 = 0, this voltage is no longer transferred, and the output at Pin 5 becomes 0V. From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output to Pin 5. This voltage level is obtained by equation 1 below. (22A - 11A) x 50k x $03 resistance between Pins 5 and 6 50k .... Equation 1
From the state described above, FS1 becomes 1, and a current source of +22A is split off. Then, a CR charge/discharge circuit is formed, and the voltage at Pin 7 decreases with the time as shown in Fig. 1 below.
0V
Fig. 1. Voltage at Pin 7 when FS1 gose from 0 1
This time constant is obtained with the 50k resistance and an external capacitor. By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
0V
$
00 02
03
02
03
02
00
Fig. 2. Constructing the search voltage by alternating between $02 and $03 (Voltage at Pin 5)
- 18 -
CXA1372BQ/BS
1-1. FS4 This switch is provided between the focus error input (Pin 47) and the focus phase compensation, and is in charge of turning the focus servo ON and OFF. $00 $08 Focus OFF Focus ON 1-2. Procedure of focus activation For description, suppose that the polarity is as described below. a) The lens is searching the disc from far to near; b) The output voltage (Pin 5) is changing from negative to positive; and c) The focus S-curve is varying as shown below.
A t
Fig. 3. S-curve The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and turning the focus servo switch ON are performed when the focus S-curve transits the point A indicated in Fig. 3. To prevent misoperation, this signal is ANDed with the focus OK signal. In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 27) as the point A transit signal. Focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case). Following the line of the above description, focusing can be well obtained by observing the following timing chart.
(20ms) (200ms) $02 ($00) $03 $08
Drive voltage
The broken lines in the figure
Focus error
indicate the voltage assuming the signal is not in focus.
SENS pin (FZC) The instant the signal is brought into focus.
Focus OK
Fig. 4. Focus ON timing chart - 19 -
CXA1372BQ/BS
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ? YES
Transfer $08 NO
F. OK ? YES Transfer $08
F. OK ? NO YES FZC ? YES NO
NO
Latch
Latch
(A)
(B)
Fig. 5. Poor and good software command sequences 1-3. SENS (Pin 27) The output of the SENS pin differs depending on the input data as shown below. $0X: FZC $1X: AS $2X: TZC $3X: SSTOP $4X to 7X: HIGH-Z
2. $1X ("AS" at SENS (Pin 27)) These commands deal with switching TG1 and TG2 ON/OFF. The bit configuration is as follows D7 D6 D5 D4 D3 D2 D1 0 0 0 1 ANTI Break TG2 SHOCK circuit ON/OFF ON/OFF
D0 TG1
TG1, TG2 The purpose of these switches is to switch the tracking servo gain Up/Normal. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely 10-track jump has been performed actually though a 100-track jump was intended to be done due to the extremely degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump. When the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the tracking error is 180out-of-phase to cut the unneeded portion of the tracking error and apply braking. - 20 -
CXA1372BQ/BS
[A] RFI 39 Tracking error (TZC) 42 [D] Waveform Shaping Envelope Detection
[B] Waveform Shaping [E] Edge Detection (Latch) (MIRR) [C] [F] DQ CK
D2 [G] BRK TM7 Low: open High: make [H]
Fig. 6. TM7 operation (brake circuit)
From inner to outer track [A] [B] [C] [D] [E] [F] [G] [H]
From outer to inner track
("MIRR")
("TZC")
0V
Braking is applied from here.
Fig. 7. Internal waveform
3. $2X ("TZC" at SENS (Pin 27)) These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse and fast forward pulse during access operations. D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 Tracking control 00: OFF 01: Servo ON 10: F-JUMP 11: R-JUMP TM1, TM3, TM4 Sled control 00: OFF 01: Servo ON 10: F-FAST FORWARD 11: R-FAST FORWARD TM2, TM5, TM6
- 21 -
CXA1372BQ/BS
DIRC (Pin 20) and 1 Track Jump Normally, an acceleration pulse is applied for a 1-track jump. Then a deceleration pulse is given for a specified time observing the tracking error from the moment it passes point 0, and tracking servo is turned ON again. For the 100-track jump to be explained in the next item, as long as the number of tracks is about 100 there is no problem. However a 1-track jump must be performed here, which requires the above complicated procedure. For the 1-track jump in CD players, both the acceleration and deceleration take about 300 to 400s. When software is used to execute this operation, it turns out as shown in the flow chart of Fig. 9. Actually, it takes some time to transfer data.
Deceleration Pulse waveform Acceleration
Tracking error
Fig. 8. Pulse waveform and tracking error of 1-track jump
$2C transfer latch
TR: REV SL: OFF
Execute
$2C transfer latch
TR: REV SL: OFF
Execute
$28 transfer only
TR: FWD SL: OFF
TZC ? YES
NO
TZC ? YES Execute
NO
TR: FWD DIRC = L SL: OFF
Latch
Timer (0.3ms)
Timer (0.3ms)
$25 transfer latch
TR: ON SL: ON
Execute
DIRC = H
TR: ON SL: ON
Fig. 9. 1-track jump not using DIRC (Pin 20)
Fig. 10. 1-track jump with DIRC (Pin 20)
The DIRC (Direct Control) pin was provided in this IC to facilitate the 1-track jump operation. Conduct the following process to perform 1-track jump using DIRC (normal High). (a) Acceleration pulse is output. ($2C for REV or $28 for FWD). (b) With TZC (or TZC ), set DIRC to Low. (SENS Pin 27 outputs "TZC"). As the jump pulse polarity is inverted, deceleration is applied. (c) Set DIRC to High after a specific time. Both the tracking servo and sled servo are switched ON automatically. As a result, the track jump turns out as shown in the flow chart of Fig. 10 and the two serial data transfers can be omitted. - 22 -
CXA1372BQ/BS
4. $3X This command selects the focus search and sled kick levels. D0, D1 ..... Sled, NORMAL feed, high-speed feed D2, D3 ..... Focus search level selection Focus search level D7 D6 D5 D4 D3 (PS4) 0 0 0 0 1 1 1 1 D2 (PS3) 0 1 0 1 Sled kick level D1 (PS2) 0 0 1 1 D0 (PS1) 0 1 0 1 Relative value 1 2 3 4
- 23 -
CXA1372BQ/BS
Parallel Direct Interface 1. DIRC
$28 latch $2C latch
XLT DIRC ON FWD JUMP REV JUMP TRACK SERVO SLED SERVO OFF ON OFF ON ON
OFF OFF
2. LOCK (Sled overrun prevention circuit)
LOCK SLED SERVO TG1, TG2 TRACKING GAIN ON OFF ON OFF UP DOWN
- 24 -
CXA1372BQ/BS
CPU Serial Interface Timing Chart
DATA D0 tWCK CLK 1/fck tD tWL D1 D2 tWCK D3 tSU D4 th D5 D6 D7
XLT
(DVCC - DGND = 4.5 to 5.5V) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width Symbol fck fwck 500 500 500 1000 1000 Min. Typ. Max. 1 Unit MHz ns ns ns ns ns
tsu th tD tWL
System Control Address Item D7 D6 D5 D4 0 0 0 FS4 0 Focus ON 1 Anti-shock 0 D3 FS3 Gain Down D2 Data D1 FS2 Search ON TG2 Gain set 1 Sled mode 3 PS2 Sled kick + 2 PS1 Sled kick + 1 D0 FS1 Search Up TG1 SENS output
Focus control Tracking control
FZC A. S TZC SSTOP
0
0 0 0
0 1 1
Tracking mode 0 Select 0
Brake ON 2 Tracking mode PS3 Focus search + 1
PS4 1 Focus search + 2
1 Gain set TG1 and TG2 can be set independently. When the anti-shock is at 1 (00011xxx), both TG1 and TG2 are inverted when the internal anti-shock is at High. 2 Tracking mode D3 OFF ON FWD JUMP REV JUMP 0 0 1 1 D2 0 1 0 1 OFF ON FWD MOVE REV MOVE 3 Sled mode D1 0 0 1 1 D0 0 1 0 1
- 25 -
CXA1372BQ/BS
Serial Data Truth Table Serial data FOCUS CONTROL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F Hex. Function FS = 4 3 2 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AS = 0 TG = 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AS = 1 TG = 2 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 0 1
TRACKING CONTROL
TRACKING MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F
DIRC = 1 DIRC = 0 TM = 654321 654321 000000 000010 010000 100000 000001 000011 010001 100001 000100 000110 010100 100100 001000 001010 011000 101000 - 26 - 001000 001010 011000 101000 000100 000110 010100 100100 001000 001010 011000 101000 000100 000110 010100 100100
DIRC = 1 654321 000011 000011 100001 100001 000011 000011 100001 100001 000011 000011 100001 100001 000011 000011 100001 100001
Application Circuit
FE
TE
RF
LDON
VCC
VO
VCC
MUTE
SCOR SQCK
SUBQ GFS CLK XLT
DATA
XRST
SENS FOK GND
GND
GND
GND
RV1 FE RV2 TE RF GND GND GND CNIN SEIN VDD MIRR XLTO XLAT MIRR DATA XRST SENS CLKO DATO CLOK MUTE SQCK SQSO C15 C16 C17 1 2 3 4 5 DVCC CC2 CC1 FOK EFM CXA1372BQ DFCT MIRR GND DGND SENS C.OUT XRST 25 26 16 17 18 19 20 GND 21 22 23 24 GND BIAS ASYI ASYO ASYE NC PSSL 27 15 NC VPCO VCKI FILO FILI PCO AVSS CLTV AVDD DATA (48) BCLK (48) DATA (64) BCLK (64) LRCK (64) RF 28 14 NC 29 13 NC 30 DFCT 12 VSS ASY 31 11 PDO CXD2500AQ 32 PCM 10 TEST 33 9 VCOI 34 8 VCOO 35 7 NC 36 6 LOCK MDS MDP MON FSW FOK C12 C11 C13 C14 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
GND
EXCK
GND
VDD
LDON
SBSO SCOR WFCK EMPH DOUT MD2 C16M C4M FSTT XTSL XTAO XTAI VSS APTL APTR MNT0 MNT1 MNT2 MNT3 XRAOF C2PO RFCK GFS XPLCK GTOP LRCK (48) VDD XUGF WDCK (48)
64 63 62 61 60 59 58 57 56 GND 55 54 53 GND 52 51 50 49 48 47 46 GND 45 44 43 42 41 RFCK GFS XPLCK XRAOF MNT0 MNT1 MNT2 MNT3 GND GND DOUT WFCK
TD
FD
SLD
SPD
48 47 46 45 44 43 42 41 40 39 38 37 FE TE CP FZC TZC FDFCT ATSC TDFCT DVEE RFO RFI CB
GND
TRACK-D
1
VC
GND
R1
C9
2
FGD
FOCUS-D
3
FS3
GND
GND
4
FLB
C10
SLED-D
5
FEO
GND
C23
6
FE-
GND
GND GND GND
GND
C26
8
TGU
DIRC
LOCK
CLK
XLT
SL+
SL0
SL-
FSET
ISET
SSTOP
C28 R4 R3
13 14 15 16 17 18 19 20 21 22 23 24
R6
C27
GND
GND
R1 1M AVDD
AVEE
DATA
R10 R12
GND
GND
R14
R13
VSS
GND
VCC
BCLK
DATA
C2PO
MUTE
LRCK
CXA1372BQ/BS
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
WDCK
DEMP
GND
GND
- 27 -
200p
SSTOP
9
TG2
GND
10
AVCC
R1
11
TA0
12
TA-
GND
R7
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 UGFS GND GTOP
GND
GND GND
SPIND-D
7
SRCH
CXA1372BQ/BS
Notes on Operation 1. Connection of the power supply pin Vcc dual 5V power supplies single 5V power supplies +5V +5V VEE -5V 0V VC 0V VC
2. FSET pin The FSET pin determines the cut-off frequency fc for the focus and tracking high-frequency phase compensation. 3. ISET pin ISET current = 1.27V/R = Focus search current = Tracking jump current = 1/2 sled kick current 4. The tracking amplifier input is clamped at 1VBE to prevent overinput. 5. FE (focus error) and TE (tracking error) gain changing method (1) High gain: Resistance between FE pins (Pins 5 and 6) 100k Large Resistance between TA pins (Pins 11 and 12) 100k Large (2) Low gain: A signal, whose resistance is divided, is input to FE and TE.
FE TE
6. Input voltage of microcomputer interface Pins 20 to 25, should be set as follows. VIH VCC x 90% or more VIL VCC x 10% or less 7. Focus OK circuit (1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the mirror amplifier HPF. (2) The equivalent circuit of FOK output pin is as follows.
VCC 20k FOK 50k 100k VCC 33 RL
FOK comparator output is: Output voltage High: VFOKH near Vcc Output voltage Low: VFOKL Vsat (NPN) + DGND
DGND
DGND
- 28 -
CXA1372BQ/BS
8. Mirror Circuit (1) The equivalent circuit of MIRR output pin is as follows.
Vcc
MIRR 29 20k RL
VEE
DGND
DGND
MIRR comparator output is: Output voltage High: VMIRH VCC - Vsat (LPNP) Output voltage Low: VMIRL near DGND 9. EFM Comparator (1) Note that EFM duty varies when the CXA1372 Vcc differs from that of DSP IC (such as the CXD2500). (2) The equivalent circuit of the EFM output pin is as follows.
4.8k
50 EFM 32 RL
700A
2mA DGND
When the power supply current between Vcc and DGND is 5V. EFM comparator output is: Output voltage High: VEFMH VCC - VBE (NPN) Output voltage Low: VEFML VCC - 4.8 (k) x 700 (A) - VBE (NPN)
- 29 -
Standard Circuit Design Data for Focus/Tracking Internal Phase Compensation SW condition SD
ment waveform and measurement Min. method
Mode Typ. Max. dB deg dB deg 13 -125 26.5 -130 dB deg dB deg Unit 21.5 63 16 63 E1 E2 E3 E4 point 08 5 When CFLB = 0.1F 5 5 5 11 11 11 11
Item
Symbol
Bias condition Measure- Description of output
S1 S2 S3 S4 S5 S6 S7 S8 S9
1.2kHz gain 08 0C 0C O O O O 25 13 25 13 25 25
O
1.2kHz phase
O
FOCUS
1.2kHz gain
O
1.2kHz phase
O
1.2kHz gain
1.2kHz phase
TRACKING
2.7kHz gain
2.7kHz phase
- 30 -
CXA1372BQ/BS
CXA1372BQ/BS
Example of Representative Characteristics
FOCUS frequency characteristics
40 35 30 CFLB = 0.1 CFGD = 0.1 180 135 90 45 0 15 10 5 0 NORMAL GAIN DOWN -45 -90 -135 -180 101 102 103 f - Frequency [Hz] 104 105
G
G - Gain [dB]
25 20
Tracking frequency characteristics
40 180
30 G CTGU = 0.033 20
120
60
10 0 NORMAL GAIN UP
0
-60
-10
-120
-20 101
-180 102 103 f - Frequency [Hz] 104 105
- 31 -
- Phase [degree]
G - Gain [dB]
- Phase [degree]
CXA1372BQ/BS
Package Outline CXA1372BQ
Unit: mm
48PIN QFP (PLASTIC)
15.3 0.4 + 0.4 12.0 - 0.1 + 0.1 0.15 - 0.05
36
25
0.15
37
24
48
13
+ 0.2 0.1 - 0.1
1 + 0.15 0.3 - 0.1
12
0.8
0.12 M
+ 0.35 2.2 - 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g
CXA1372BS
48PIN SDIP (PLASTIC) 600mil
+ 0.1 0.05 0.25 -
+ 0.4 43.2 - 0.1 48 25
15.24 + 0.3 13.0 - 0.1
1 1.778
24
0.5 0.1 0.9 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-48P-02 SDIP048-P-0600-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 5.1g
- 32 -
3.0 MIN
+ 0.4 4.6 - 0.1
0.5 MIN
0.9 0.2
0 to 15
13.5

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