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CXD2409R
Timing Controller for ICX076/077AL
Description The CXD2409R is a timing controller for CCD camera systems which use the ICX076/077AL black-and-white CCD image sensors. Features * Supports EIA/CCIR standards * Electronic iris (electronic shutter) function * Sync signal generation function * Backlight compensation function * AGC flickerless circuit * Electronic iris power on reset function * Oscillator frequency: 13.5 MHz Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD VSS - 0.5 to +7.0 V * Input voltage VI VSS - 0.5 to VDD + 0.5 V * Output voltage VO VSS - 0.5 to VDD + 0.5 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDD 5.0 0.25 * Operating temperature Topr -20 to +75 CCD Image Sensors Used ICX076/077AL 64 pin LQFP (Plastic)
Applications * Doorphones * Small sized surveillance cameras Structure Silicon gate CMOS IC
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94847A52-PP
OSCO
H1
HD
SHP
SHD
RG
XV2
H2
CL
AVSS
XV3
CLP2
VD
XSG1
XSG2
CLP1
WSEL1
WSEL2
OSCI
AVDD
XV1
2 3 33 42 WND 34 AGCO2 32 DETC3 FL 31 DETC2 30 DETC1 TG 29 AGCI2 28 AGCO1 WND 26 AGCI1 51 PS SSG DECODE IRIS /SHUTTER CLK GEN. WND 18 DETC4 20 IRIN/ED1 7 11 59
1 4 39 14 10 15 27 44
48 5 12
50
49 38 43
6
13 60
CKI
13.5MHz
64
X'tal
1/2
VDD 56
VDD
9
1/429 1/432
VSS 55
VSS
8
1/525 1/625
SYNC 45
CBLK 46
FLD 47 21 Vreg COMP 24 GATE COUNT LIMIT SELECT UP/DOWN ADDER COMP 23 SPDNV/ED2 SPUPV/ED0
TEST1 35
TEST2 36
TEST
TEST3 41
XV4
SVDD1
17 19
58 54
57
16
53
62
63
61
52
40
37
22
25
FL
EIA
VSS
ENB
LLIM
VSS
XSUB
CVDD
CVSS
HLIM1
HLIM2
IRENB
SVDD2
SVSS2
SVSS1
Block Diagram
POWER
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CXD2409R
CXD2409R
Pin Configuration (Top View)
TEST3 TEST2 AGCO2 TEST1 CLP1 FLD VSS SVSS1
32 DETC3 31 DETC2 30 DETC1 29 AGCI2 28 AGCO1 27 SVDD1 26 AGCI1 25 CVSS 24 SPUPV/ED0 23 SPDNV/ED2 22 CVDD 21 Vreg 20 IRIN/ED1 19 SVSS2 18 DETC4 17 SVDD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SYNC
CBLK
CLP2
WND
SHD
SHP
CL
VSS
48 47 VD 49 HD 50 PS 51 IRENB 52 ENB 53 POWER 54 VSS 55 VDD 56 FL 57 EIA 58 WSEL1 59 WSEL2 60 LLIM 61 HLIM1 62 HLIM2 63 CKI 64
46 45 44
43 42
41 40 39
38 37 36
35
34 33
H2
VDD
OSCI
XV1
XSG2
AVDD
AVSS
XV2
RG
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Symbol OSCO OSCI AVDD H1 H2 AVSS RG VSS VDD XV2 XV1 XSG1 I/O O I -- O O -- O -- -- O O O Oscillation inverter output Oscillation inverter input Power supply (for H1, H2) Clock output for CCD horizontal register drive Clock output for CCD horizontal register drive GND (for H1, H2) Reset gate pulse output GND Power supply Clock output for CCD vertical register drive Clock output for CCD vertical register drive CCD sensor charge readout pulse output Description
OSCO
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XSUB
XSG1
XV3
XV4
H1
VSS
CXD2409R
Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Symbol XV3 XSG2 XV4 XSUB SVDD2 DETC4 SVSS2 IRIN/ED1 Vreg CVDD SPDNV/ED2 SPUPV/ED0 CVSS AGCI1 SVDD1 AGCO1 AGCI2 DETC1 DETC2 DETC3 SVSS1 AGCO2 TEST1 TEST2 VSS SHP SHD VSS TEST3 WND CLP2 CLP1 SYNC CBLK FLD
I/O O O O O -- O -- I I -- I I -- I -- O I O O O -- O I I -- O O -- I O O O O O O
Description Clock output for CCD vertical register drive CCD sensor charge readout pulse output Clock output for CCD vertical register drive CCD discharge pulse output Power supply (for the iris window switch) Capacitor for iris detection GND (for the iris window switch) Iris signal input/shutter speed setting; clock input in serial mode Bias current supply for the comparator Power supply (for the comparator) Shutter speed down reference voltage/ shutter speed setting; data input in serial mode Shutter speed up reference voltage/ shutter speed setting; strobe input in serial mode GND (for the comparator) AGC detection signal input Power supply (for the AGC window switch) AGC detection signal output AGC flickerless circuit input AGC detection capacitor 1 AGC detection capacitor 2 AGC detection capacitor 3 GND (for the AGC window switch) AGC flickerless circuit output Test input (with the pull-down resistor) Test input (with the pull-down resistor) GND Precharge level sample-and-hold pulse Data sample-and-hold pulse GND Test input (with the pull-down resistor) Window pulse output Pulse output for clamp Pulse output for clamp Composite sync output Composite blanking output Field pulse output
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CXD2409R
Pin No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol CL VD HD PS IRENB ENB POWER VSS VDD FL EIA WSEL1 WSEL2 LLIM HLIM1 HLIM2 CKI
I/O O O O I I I I -- -- I I I I I I I I Master clock output Vertical sync signal output Horizontal sync signal output
Description
Electronic shutter speed input switchover Low: serial input; high: parallel input (with the pull-up resistor) Low: electronic shutter mode; high: electronic iris mode (with the pull-up resistor) Low: XSUB pulse stop; high: XSUB pulse output (with the pull-up resistor) Electronic iris power on reset GND Power supply Low: normal mode; high:AGC flickerless mode (with the pull-down resistor) Low: EIA; high: CCIR (with the pull-down resistor) Window pulse output switchover (with the pull-down resistor) Window pulse output switchover (with the pull-down resistor) Electronic iris low speed limiter switchover Low: limiter OFF; high: limiter ON (with the pull-down resistor) Electronic iris high speed limiter switchover (with the pull-down resistor) Electronic iris high speed limiter switchover (with the pull-down resistor) 2 fck clock input
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CXD2409R
Electrical Characteristics DC Characteristics Item Supply voltage Pins 3, 9, 17, 22, 27, and 56 Input voltage 1 All input pins except Pins 20, 21, 23, 24, 26, and 29 Input voltage 2 Pins 20, 21, 23, 24, 26, and 29 Output voltage 1 Pins 4, 5, and 7 Output voltage 2 Pins 38 and 39 Output voltage 3 Pins 18, 28, 30, 31, 32, and 34 Output voltage 4 Pin 48 Symbol VDD VIH VIL VIN VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 IOH = -4mA IOL = 8mA IOH = -2mA IOL = 4mA VIN = VSS or VDD 250k 20k 20k VIN = 2.5V 1V 20k 50k 1M 50k 50k VDD - 0.8 0.4 2.5M 125k 125k 200 125k VDD - 0.8 0.4 IOH = -7mA IOL = 20mA IOH = -4mA IOL = 8mA VDD - 0.8 0.4 1.9 VDD - 0.8 0.4 Conditions (VDD = 4.75 to 5.25V, Topr = -20 to +75C) Min. 4.75 0.7VDD 0.3VDD 5.0 Typ. 5.0 Max. 5.25 Unit V V V V V V V V V V V V V V mA
Output voltage 5 VOH5 Pins 10, 11, 12, 13, 14, 15, 16, 42, 43, VOL5 44, 45, 46, 47, 49, and 50 Feedback resistance Pull-up resistance Pull-down resistance Analog switch ON resistance Current consumption RFB RPU RPD RON IDD
Input/Output Capacitance Item Input pin capacitance Output pin capacitance
(VDD = VSS = 0V, VI or VO = 0V, fM = 1MHz) Symbol CIN COUT Min. Typ. Max. 9 11 Unit pF pF
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CXD2409R
Mode Control Pin No. 52 53 58 59 60 61 62 63 57 51 Symbol IRENB ENB EIA WSEL1 WSEL2 LLIM HLIM1 HLIM2 FL PS I/O I I I I I I I I I I Low Electronic shutter XSUB stop EIA High Electronic iris XSUB output CCIR Remarks Valid when ENB is high.
Four types of window settings can be selected by combining WSEL1 and WSEL2. The minimum shutter speed can be selected during electronic iris mode. The maximum shutter speed can be selected during electronic iris mode by combining HLIM1 and HLIM2. AGC flickerless OFF Serial input AGC flickerless ON Parallel input Valid when ENB is high and IRENB is high. Valid when ENB is high and IRENB is high. Valid when AGC is used. Valid when ENB is high and IRENB is low.
* The functions of the pins (Pins 20, 23, and 24) listed below change according to the IRENB (Pin 52) mode setting. (Valid when ENB is high.) Pin No. 20 23 24 Symbol IRIN /ED1 SPDNV /ED2 SPUPV /ED0 I/O I I I IRENB Low Electronic shutter speed setting; clock input in serial mode Electronic shutter speed setting; data input in serial mode Electronic shutter speed setting; strobe input in serial mode IRIS signal input Comparator reference voltage input (shutter speed down side) Comparator reference voltage input (shutter speed up side) High
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CXD2409R
Description of Operation Electronic Shutter/Electronic Iris By setting the ENB pin (Pin 53) high, the XSUB pulse is output for a specific period to activate the electronic shutter and electronic iris.
Electronic Shutter Parallel input (IRENB = low, PS = high) Mode OFF EIA CCIR EIA L H L L L EIA L L L L Electronic shutter L H H H CCIR H H H H H ENB L L H H H H H H H H H H H H H H H H IRENB x x L L L L L L L L L L L L L L L L SPUPV x x H L H L H L H L H L H L H L H L IRIN x x H H L L H H L L H H L L H H L L SPDNV x x H H H H L L L L H H H H L L L L Shutter speed 1/60 (s) 1/50 (s) 1/100 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/5000 (s) 1/10000 (s) 1/100000 (s) 1/120 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/5000 (s) 1/10000 (s) 1/70000 (s)
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CXD2409R
Serial input (IRENB = low, PS = low) By inputting 8-bit data to the ED2 pin (Pin 23), the electronic shutter speed can be controlled. Serial input data format
SPDNV/ED2
D7
D6
D5
D4
D3
D2
D1
D0
IRIN/ED1
SPUPV/ED0
The ED2 (Pin 23) data is latched in the register at the ED1 (Pin 20) rise, and retrieved internally at the ED0 (Pin 24) rise. Typical shutter speeds EIA Shutter speed (s) 1/60 1/100 1/250 1/500 1/1000 1/2000 1/5000 1/10000 1/30000 1/100000 DATA (ED0: 8bit) 11111111 (0 step) 11110110 (9 step) 11100101 (26 step) 11010010 (45 step) 11000010 (61 step) 10111000 (71 step) 10101000 (87 step) 10011011 (100 step) 10000010 (125 step) 01101010 (149 step) Shutter speed (s) 1/50 1/120 1/250 1/500 1/1000 1/2000 1/5000 1/10000 1/30000 1/100000 CCIR DATA (ED0: 8bit) 11111111 (0 step) 11110001 (14 step) 11100011 (28 step) 11010000 (47 step) 11000000 (63 step) 10110111 (72 step) 10100110 (89 step) 10011000 (103 step) 01111101 (130 step) 01100011 (156 step)
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CXD2409R
AC Characteristics
SPDNV/ED2 ts2 IRIN/ED1 ts1 SPUPV/ED0 tw0 ts0 th2
Symbol
Min. SPDNV (ED2) setup time for IRIN (ED1) rise SPDNV (ED2) hold time for IRIN (ED1) rise IRIN (ED1) setup time for SPUPV (ED0) rise SPUPV (ED0) pulse width SPUPV (ED0) setup time for IRIN (ED1) rise 20ns 20ns 20ns 20ns 20ns
Max. -- -- -- 50s --
ts2 th2 ts1 tw0
ws0
Electronic Iris Pin No. 20 23 24 Symbol IRIN/ED1 SPDNV/ED2 SPUPV/ED0 Iris signal input Function
(ENB = high, IRENB = high)
Comparator reference voltage input for shutter speed down Comparator reference voltage input for shutter speed up
(a) Electronic iris characteristics Shutter speed : 1/60 to 1/100000 (s) (EIA) 1/50 to 1/70000 (s) (CCIR) Iris steps : 149 steps (EIA) 151 steps (CCIR) Contraction ratio for one iris step : average 6% Note) When LLIM = low, HLIM1 = low, and HLIM2 = low (b) LLIM (low speed shutter limiter) By setting the LLIM pin (Pin 61) high, the minimum shutter speed can be changed. (ENB = high, IRENB = high) LLIM L H Minimum shutter speed EIA 1/60 1/100 CCIR 1/50 1/120
- 10 -
CXD2409R
(c) HLIM (high speed shutter limiter) By combining the HLIM1 pin (Pin 62) and the HLIM2 pin (Pin 63), the maximum shutter speed can be changed. (ENB = high, IRENB = high) HLIM1 L H H L HLIM2 L L H H Maximum shutter speed EIA 1/100000 (s) 1/30000 (s) 1/10000 (s) 1/5000 (s) CCIR 1/70000 (s) 1/30000 (s) 1/10000 (s) 1/5000 (s)
(d) Power on reset During electronic iris mode (IRENB = high), the initial settings for the iris are made in the instant the POWER pin (Pin 54) switches from low to high. The initial setting shutter speed is 1/1000 (s). By applying the circuit shown below, the shutter speed can be initialized when the power is turned on.
+5 V power supply
100k 54 POWER 0.68 55 VSS
56 VDD
- 11 -
CXD2409R
(e) Backlight compensation By applying the window pulse to the electronic iris detection signal (IRIS) input to IRIN (Pin 20) and the AGC detection signal (DET OUT) input to AGCI1 (Pin 26), backlight compensation can be performed. Compensation is achieved by detecting a limited area with the built-in analog switch for the window and the external sample-and-hold capacitor. In addition, four types of backlight compensation areas can be selected by combining the WSEL1 pin (Pin 59) and WSEL2 pin (Pin 60) as shown in the table below. The basic circuit to perform the window operations is shown in the figure below, and window pulse timing charts are shown on the following pages. Window types WSEL1 L H L H WSEL2 L L H H Minimum shutter speed Full measurement1 Lower measurement Center measurement Lower center measurement
1 The signal is masked during blanking.
Basic Circuit Configuration
Comparator for iris DETC4 18 Iris window switch 20 IRIN Window pulse (WND) CXD2409R AGCO1 28 AGC window switch 26 AGCI1 100k GND 10k 1k 10k GND 19 OP+ 13 DET OUT 2SC2785 10k CXA1310Q 10k +5V 2SC2785 39k 1 10k 10k 27 IRIS
- 12 -
Window Pulse Response Chart
EIA V direction timing XV1 XSG1
1. Full measurement
WSEL1 = L / WSEL2 = L WND 11 XV1 249 XV1 XV1 H direction timing CL 6.75MHz WND 40 CL 394 CL CCIR V direction timing XV1 XSG1
- 13 -
WND 10 XV1 294 XV1 XV1 H direction timing CL 6.75MHz WND 45 CL 395 CL
CXD2409R
2. Lower measurement
EIA V direction timing XV1 XSG1
WSEL1 = H / WSEL2 = L
WND 189 XV1 249 XV1 XV1 H direction timing CL 6.75MHz
WND 40 CL 394 CL CCIR V direction timing XV1 XSG1
- 14 -
WND 223 XV1 294 XV1 XV1 H direction timing CL 6.75MHz WND 45 CL 395 CL
CXD2409R
3. Center measurement
EIA V direction timing XV1 XSG1
WSEL1 = L / WSEL2 = H
WND 70 XV1 189 V1 XV1
H direction timing
CL 6.75MHz
WND 158 CL 276 CL CCIR V direction timing XV1 XSG1
- 15 -
WND 152 XV1 223 XV1 XV1 H direction timing CL 6.75MHz WND 170 CL 288 CL
CXD2409R
4. Lower center measurement
EIA V direction timing XV1 XSG1
WSEL1 = H / WSEL2 = H
WND 189 XV1 249 XV1 XV1 H direction timing CL 6.75MHz WND 158 CL 276 CL CCIR V direction timing XV1 XSG1
- 16 -
WND 223 XV1 294 XV1 XV1 H direction timing CL 6.75MHz WND 170 CL 288 CL
CXD2409R
CXD2409R
AGC Flickerless By setting the FL pin (Pin 57) of the CXD2409R high when using the CXA1310Q AGC, the fluorescent light flicker component generated by differences between the fluorescent light emission cycle and the EIA field cycle can be controlled. Basic Circuit Configuration
AGCO2 34 DETC1 30 Flickerless circuit DETC2 31 DETC3 32 AGCI2 29 CXD2409R AGCO1 28 AGC window switch 26 AGCI1 100k GND 10k 1k 50k +5V 1M 10k 18 OP- CXA1310Q 19 13 OP+ DET OUT 17 OP OUT 16 AGC CONT
2.7k 1k 2k
- 17 -
Timing Chart (1)
EIA Vertical Direction
EVEN FIELD ODD FIELD
ODD FIELD EVEN FIELD
FLD 20H 20H
BLK 9H
VD
9H
HD
SYNC 10.5H
11H
XSG1
- 18 -
2 1 3 5 7 4 6 482 484 486 488 490 492 483 485 487 489 491
XSG2
XV1
XV2
XV3
XV4
CCD OUT
483 485 487 489 491
1 2
3 4
5 6
7 8
9 10
484 486 488 490 492
CLP1
CLP2
CXD2409R
Timing Chart (2)
CCIR Vertical Direction
EVEN FIELD
ODD FIELD ODD FIELD
EVEN FIELD
FLD 25H 25H
BLK 7.5H
7.5H
VD
HD
SYNC 15H
15.5H
XSG1
- 19 -
2 1 3 4 5 6 7 574 576 578 580 582 575 577 579 581 583
XSG2
XV1
XV2
XV3
XV4
CCD OUT
574 576 578 580 582
2 1
4 3
6 5
8 7
10 9
573 575 577 579 581 583
CLP1
CLP2
CXD2409R
Timing Chart (3)
CL = 6.75MHz : 148.148ns 20 30 40 50 60 70 80 90
EIA Horizontal Direction
0
10
HD 42 74
BLK
MCK
(CL) 17 51
H1
H2
RG
SHP
SHD 21 29 17 37 25 45 36 49 41 33
- 20 -
55 42 26
XV1
XV2
XV3
XV4
XSUB
CLP1
5
16 65
CLP2
HSYNC
10
EQ
VSYNC
FLD
VD
CXD2409R
Timing Chart (4)
CL = 6.75MHz : 148.148ns 20 30 40 50 60 70 80 90
CCIR Horizontal Direction
0
10
HD 42
BLK
81
MCK
(CL) 20 58
H1
H2
RG
SHP
SHD 24 32 44 40 28 39 48 52 20 36
- 21 -
42 26
XV1
XV2
XV3
XV4
XSUB
CLP1
5
16 63 73
CLP2
HSYNC
10
EQ
VSYNC
FLD
VD
CXD2409R
Timing Chart (5)
CL = 6.75MHz : 148.148ns 429CK 2CK (0.296s) 17CK (2.52s) 17CK (2.52s) 14CK (2.07s) 9CK (1.33s) 11CK (1.63s)
EIA Charge Readout Timing
0
HD
42
XSG1
268
285
XSG2
296
313
ODD
XV1
21
33
- 22 -
41 257 68CK (10.1s) 327 37 259 45 41 257 37 259 45 327
XV2
29
XV3
17
208CK (30.8s)
XV4
25
EVEN
XV1
21
33
XV2
29
XV3
17
208CK (30.8s)
CXD2409R
XV4
25
Timing Chart (6)
CL = 6.75MHz : 148.148ns 432CK 2CK (0.296s) 17CK (2.52s) 17CK (2.52s) 14CK (2.07s) 11CK (1.63s) 9CK (1.33s)
CCIR Charge Readout Timing
0
HD
42
XSG1 270 287
XSG2 298
ODD
XV1
24
36
- 23 -
44 68CK (10.1s) 259 40 261 48 44 259 40 261 48
XV2
32
329
XV3
20
212CK (31.4s)
XV4
28
EVEN
XV1
24
36
XV2
32
XV3
20
212CK (31.4s)
CXD2409R
XV4
28
329
Timing Chart (7)
H Effective Period
10CK (1.484s) 10CK 10CK
1/2H
CL = 6.75MHz : 148.148ns
EIA
42CK (6.222s)
HDO
74CK (10.963s)
BLKO
HSYNC
32CK (4.74s)
EQ
16CK (2.370s)
32CK (4.74s)
VSYNC
VD
- 24 -
FLD
CCIR
42CK (6.222s)
HDO
81CK (12.000s)
BLKO
HSYNC
32CK (4.74s)
EQ
16CK (2.370s)
32CK (4.74s)
VSYNC
VD
CXD2409R
FLD
CXD2409R
Timing Chart (8)
TS + SG High Speed Phase Timing Chart
74.074ns for both EIA and CCIR
CK
148.148ns for both EIA and CCIR
H1
H2
RG
CCD OUT
SHP
SHD
- 25 -
Application Circuit -EIA-
100 100
* Electronic iris mode * High speed shutter limit: 1/30000s * Full measurement * AGC flickerless mode
2.2k
+5V
2.2k 2.2k 2.2k
GND
47P 47P 47P 47P 44 41 34 32 20 31 21 16 17 0.68 28 50k 1k 2k 10k 19 4.7/10V 0.1 13 27 26 2.7k 18 27 IRIS OP+ DET OUT +5V 1M 30 10 10 10 24 25 30 29 4 33 43 42 36 40 39 38 37 35
48
47
46
45
49
50
51
CXA1310AQ
52 29
53
100k
54
0.1
55
4.7/10V
56
CXD2409R
25 SPUPV 24 10k 23 2SC2785 2SC2785 22 21 20 3.9k 19 18 15 17 5 7 11 8 10 12 14 15 16 6 9 13 4.7/10V 0.1 10k 10k SPDNV 50k 39k 50k 10k
57
10k
- 26 -
4.7/10V 0.1 36k 10k 4.7/10V 180K-pixel B/W CCD
58
10k
1k
59
60
100k
61
10k
VIDEO OUT
62
63
64
1
2
3
4
0.1
1000P
4.7/10V
12P
20P
VSUB ADJ CXD1267N
CXD2409R
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CCD out
CXD2409R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 0.2 48 49 10.0 0.1 33 32
A 64 1 0.5 0.08 16 + 0.2 1.5 - 0.1 17 (0.22) + 0.08 0.18 - 0.03
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g
- 27 -
0.5 0.2
(11.0)

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