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| CXG1006N High-Frequency SPDT Antenna Switch For the availability of this product, please contact the sales office. Description The CXG1006N is a high power antenna switch MMIC. This IC is designed using the Sony's GaAs JFET process and operates at a single positive power supply. Features * Single positive power supply operation * Low insertion loss 0.5dB (Typ.) at 2.0GHz * High isolation 27dB (Typ.) at 2.0GHz * High power switching P1dB (Typ.) 32dBm at 2.0GHz VCTL (H) = 2.0V 34dBm at 2.0GHz VCTL (H) = 4.0V Application Antenna switch for digital cellular telephones Structure GaAs J-FET MMIC 8 pin SSOP (Plastic) Absolute Maximum Ratings (Ta = 25C) * Control voltage Vctl 7 * Operating temperature Topr -35 to +85 * Storage temperature Tstg -65 to +150 Operating Condition Control voltage V C C 0/4 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E95Z31A66-ST CXG1006N Electrical Characteristics VCTL (L) = 0V, VCTL (H) = 4V, PIN = 30dBm, RRF = 75k Item Insertion Loss Isolation Insertion Loss Isolation Insertion Loss Isolation VSWR Switching Time Symbol IL1 ISO1 IL1.5 ISO1.5 IL2 ISO2 VSWR TSW f = 2.0GHz 24 Test Condition f = 1.0GHz Min. Typ. 0.3 35 40 0.4 29 32 0.5 27 1.5 100 ns 0.8 0.7 (Ta = 25C) Max. 0.6 Unit dB dB dB dB dB dB f = 1.5GHz VCTL (L) = 0V, f = 2GHz Item 1dB Compression Point 1dB Compression Point Symbol P1dB (3) P1dB (4) Test Condition VCTL (H) = 3V VCTL (H) = 4V Min. 30 32 Typ. 32 34 (Ta = 25C) Max. Unit dBm dBm VCTL (L) = 0V, RRF = 75k Item Control Current Control Current Control Current Symbol ICTL (1) ICTL (2) ICTL (3) Test Condition VCTL (H) = 3V VCTL (H) = 4V VCTL (H) = 5V Min. Typ. 100 150 200 (Ta = 25C) Max. 170 220 270 Unit A A A Block Diagram Package Outline/Pin Configulation Port3 Port1 Port2 CTLB 1 Port1 2 GND 3 CTLA 4 8 pin SSOP (PLASTIC) 8 Port3 7 GND 6 GND 5 Port2 VCTLA High Low VCTLB Low High Port1-Port2 ON Port1-Port3 OFF Port1-Port2 OFF Port1-Port3 ON -2- CXG1006N Recommended Circuit 100pF CTLB 100pF Port1 100pF 3 6 100pF CTLA 100pF 4 5 RRF 75k Port2 2 1 8 RRF 75k 7 Port3 RRF is used to stabilize the electrical characteristics at high power signal input Example of Representive Characteristics (Ta = 25C) Insertion Loss and Isolation vs. Input Power Insertion Loss [dB] 0 Insertion Loss -2 -4 -6 VCTL (H) = 3V VCTL (H) = 4V VCTL (H) = 5V Isolation -30 @2.0GHz 24 28 32 36 40 44 -20 VCTL (H) = 5V VCTL(H)=4V VCTL (H) = 4V VCTL(H)=3V VCTL (H) = 3V -10 0 Input Power [dBm] Insertion Loss and Isolation vs. Frequency 0 Insertion Loss -1 -10 0 Insertion Loss [dB] -2 -20 -3 Isolation -30 -4 -40 -5 0 1 2 Frequency [GHz] 3 -50 -3- Isolation [dB] Isolation [dB] CXG1006N Package Outline Unit: mm 8PIN SSOP (PLASTIC) 3.0 0.1 + 0.2 1.25 - 0.1 0.1 8 5 A 4.4 0.1 1 4 0.65 + 0.08 0.24 - 0.07 B 0.25 0.13 M 0.1 0.05 6.4 0.2 (0.22) (0.15) + 0.025 0.17 - 0.015 + 0.08 0.24 - 0.07 0 to 10 DETAIL A DETAIL B NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-8P-L01 SSOP008-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER ALLOY 0.04g -4- (0.5) 0.6 0.15 |
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