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7c198: 10/25/89 Revision: February 29, 1996
Features
D D D D D D D
High speed 15 ns CMOS for optimum speed/power Low active power 990 mW Low standby power 195 mW Easy memory expansion with CE and OE features TTL compatible inputs and outputs Automatic power down when deselected
The CY7C198 is a high performance CMOS static RAM organized as 32,768 words by8bits.Easymemoryexpansionis provided by an active LOW chip enable (CE)andactiveLOWoutputenable(OE) and three state drivers. This device has an automatic power down feature, reducing the power consumption by 80% when de selected. The CY7C198 is available in a 600 mil wide cerDIP and LCC package and a 32 lead TSOP package. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs arebothLOW,dataontheeightdatainput/
Functional Description
output pins (I/O0 through I/O7) is written intothememorylocationaddressedbythe address present on the address pins (A0 through A14). Reading the device is ac complishedbyselectingthedeviceanden abling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the con tents of the location addressed by the in formationonaddresspinsispresentonthe eight data input/output pins. Theinput/outputpinsremaininahigh im pedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to ensure alpha immunity.
32K x 8 Static RAM
CY7C198
Logic Block Diagram
Pin Configurations
CerDIP Top View
A5 A6 A7 A8 A9 A10 I/O0 A11 A12 I/O1 A13 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 A6 A5 A4 A3 A2 A1 A0 NC I/O0 4 5 6 7 8 9 10 11 12 13 A7 A 12 A 14 V CC
LCC Top View
3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE I/O7 I/O6 WE NC A 13 C198 1
INPUT BUFFER
A0
ROW DECODER
A1 A2 A3 A4 A5 A6 A7 A8 A9
I/O0 I/O2 SENSE AMPS I/O1 I/O2 I/O3 GND
14 15 16 17 1819 20 GND I/O 1 I/O 2 NC I/O 3 I/O 4 I/O 5
1024 x 32 x 8 ARRAY
C198 3 I/O4
I/O5
CE WE COLUMN DECODER OE POWER DOWN
I/O6
I/O7
A 10
A 11
A 12
A 13
A 14
C198 2
Selection Guide
Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Military Maximum Standby Current (mA)
7C198-15 7C198-20 7C198-25 7C198-35 7C198-45
15
Shaded area contains preliminary information.
Cypress Semiconductor Corporation
180 30
20 150 170 30
25
35
45
150 30
150 25
150 25
D
3901 North First Street 1
D
San Jose
D CA 95134 D 408-943-2600 February 1988 - Revised February 1996
7c198: 10/25/89 Revision: February 29, 1996
CY7C198
Pin Configurations (continued)
OE A1 A2 A3 A4 WE VCC NC NC A5 A6 A7 A8 A9 A10 A11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TSOP Top View
32 21 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC GND I/O2 I/O1 I/O0 A14 A13 A12
C198 4
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature . . . . . . . . . . . . . . . . . . . -65_C to +150_C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . -55_C to +125_C Supply Voltage to Ground Potential (Pin 28 to Pin 14) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[15] . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V DC Input Voltage[15] . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V Output Current into Outputs (LOW) . . . . . . . . . . . . . . . 20 mA
Notes:
15. VIL (min.) = -2.0V for pulse durations less than 20 ns. 16. TA is the instant on" case temperature.
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . >2001V (per MIL STD 883, Method 3015) Latch Up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Operating Range
Range
Commercial Military[16]
Ambient Temperature
0_C to +70_C -55_C to +125_C
VCC
5V 10% 5V 10%
2
7c198: 10/25/89 Revision: February 29, 1996
CY7C198
Electrical Characteristics Over the Operating Range
[17]
7C198-15 Parameter VOH Description Output HIGH V oltage VOL Output LOW V oltage VIH Input HIGH V oltage Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 VCC +0.3V -0.5 0.8 0.4 Min. 2.4 Max.
7C198-20 Min. 2.4 Max.
7C198-25 Min. 2.4 Max.
7C198-35, 45 Min. 2.4 Max. Unit V
0.4
0.4
0.4
V
2.2
VCC +0.3V
2.2
VCC
2.2
VCC
V
VIL
Input LOW V oltage
[15]
-0.5
0.8
-0.5
0.8
-0.5
0.8
V
IIX IOZ
Input Load Current Output Leakage Current
GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max.,
-5 -5
+5 +5
-5 -5
+5 +5
-5 -5
+5 +5
-5 -5
+5 +5
mA mA
mA
IOS
Output Short Circuit Current
[18]
-300
-300
-300
-300
VOUT = GND VCC = Max., IOUT = 0 mA mA, Mil 180 170 150 150 Com'l 150 mA
ICC
VCC Operating Supply Current
f = fMAX = 1/tRC ISB1 Automatic CE Power Down Current Inputs ISB2 Automatic CE Power Down Current Inputs CMOS Max. VCC, TTL
Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX
30
30
30
25
mA
15
15
15
15
mA
CE > VCC - 0.3V VIN > VCC - 0.3V or , VIN < 0.3V f = 0
Shaded area contains preliminary information
Capacitance
[19]
Parameter CIN COUT
Notes: 17.
Description Input Capacitance Output Capacitance
Test Conditions TA = 25_C, f = 1 MHz, VCC = 5.0V 5 0V
Max. 10 10
Unit pF pF
See the last page of this specification for Group A subgroup testing in formation.
19.
T ested initially and after any design or process changes that may affect these parameters.
18.
Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
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7c198: 10/25/89 Revision: February 29, 1996
CY7C198
AC Test Loads and Waveforms[20]
5V OUTPUT
R1 481W
5V OUTPUT
R1 481W 3.0V GND 10% < fr
R2 R2 5 pF 30 pF 255W 255W INCLUDING INCLUDING JIG AND JIG AND C198 5 SCOPE (b) SCOPE (a) Equivalent to: THEVENIN EQUIVALENT 167W OUTPUT 1.73V Switching Characteristics Over the Operating Range[17, 21]
7C198-15 Parameter READ CYCLE Description Min. Max. 7C198-20 Min. Max.
ALL INPUT PULSES 90% 90% 10% < tr
C198 6
7C198-25 Min. Max.
7C198-35 Min. Max.
7C198-45 Min. Max. Unit
tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD
WRITE CYCLE[24, 25]
Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[22] OE HIGH to High Z[22, 23] CE LOW to Low Z[22] CE HIGH to High Z[22, 23] CE LOW to Power Up CE HIGH to Power Down Write Cycle Time CE LOW to Write End Address Set Up to Write End Address Hold from Write End Address Set Up to Write Start WE Pulse Width Data Set Up to Write End Data Hold from Write End WE LOW to High Z[23] WE HIGH to Low Z[22]
15 3 0 3 0 15 10 10 0 0 9 9 0 3
15 15 7 7 7 15
20 3 0 3 0 20 15 15 0 0 15 10 0 3
20 20 9 9 9 20
25 3 3 3 0 25 20 20 0 0 20 15 0 3
25 25 10 11 11 20
35 3 3 3 0 35 22 30 0 0 22 15 0 3
35 35 16 15 15 20
45 3 3 3 0 45 22 40 0 0 22 15 0 3
45 45 16 15 15 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Shaded area contains preliminary information.
Notes:
tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
7
10
11
15
15
20 tr 3 ns for the 15 ns and 20 ns speeds, tr 5 ns for the 20 ns and slower speeds. 21. Test conditions assume signal transition time of 3 ns or less for the 12 ns and15 ns speeds and 5 ns for the 20 ns andslowerspeeds,timing referencelevelsof1.5V,inputpulselevelsof0to3.0V,andoutputload ing of the specified IOL/IOH and 30 pF load capacitance. 22. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
23. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage. 24. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set upandholdtimingshouldbereferencedtotherisingedgeofthesignal that terminates the write. 25. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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7c198: 10/25/89 Revision: February 29, 1996
CY7C198
Switching Waveforms
Read Cycle No. 1[26, 27]
tRC ADDRESS DATA OUT
Read Cycle No. 2[27, 28]
tOHA PREVIOUS DATA VALID
tAA DATA VALID
C198 7
CE OE tACE tLZOE HIGH IMPEDANCE tLZCE tPU 50% tDOE
tRC
tHZOE tHZCE DATA VALID tPD 50%
DATA OUT VCC SUPPLY CURRENT
HIGH IMPEDANCE ICC ISB
C198 8
Write Cycle No. 1 (WE Controlled)[24, 29, 30]
tWC
ADDRESS CE WE OE DATA I/O tHZOE
Notes:
26. 27. 28. Device is continuously selected. OE, CE = VIL. WE is HIGH for read cycle. . Address valid prior to or coincident with CE transition LOW 29. 30. Data I/O is high impedance if OE = VIH. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
tSA
tAW
tPWE
tHA
tSD DATAIN VALID
tHD
C198 9
5
7c198: 10/25/89 Revision: February 29, 1996
CY7C198
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[24, 29, 30]
tWC
ADDRESS
CE tSA tAW
tSCE
tHA
WE tSD DATA I/O DATAIN VALID
C198 10
tHD
Write Cycle No. 3 (WE Controlled, OE LOW)[25, 30]
tWC
ADDRESS
CE
tAW tSA WE
tHA
tSD DATA I/O
tHD
DATAIN VALID tHZWE tLZWE
C198 11
6
7c198: 10/25/89 Revision: February 29, 1996
CY7C198
T ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT (mA)
vs. AMBIENT TEMPERATURE
vs. OUTPUT VOLTAGE
1.4
SB
1.4
SB
120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25_C
NORMALIZED I CC, I
1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5
ICC
NORMALIZED I CC, I
1.2
ICC
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 VCC = 5.0V VIN = 5.0V ISB 25 125
VIN = 5.0V TA = 25_C
ISB 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (_C)
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
1.4 1.3 1.2 1.1 TA = 25_C 1.0
OUTPUT SINK CURRENT (mA)
1.6
140 120 100 80 60 40 20 0
NORMALIZED tAA
NORMALIZED tAA
1.4
1.2
1.0 VCC = 5.0V 0.8
VCC = 5.0V TA = 25_C
0.9 0.8 4.0
4.5
5.0
5.5
6.0
0.6 -55
25
125
0.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (_C)
OUTPUT VOLTAGE (V)
TYPICAL POWER ON CURRENT vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING NORMALIZED ICC vs. CYCLE TIME
3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0
30.0 25.0 20.0 15.0 10.0 5.0 0.0 VCC = 4.5V TA = 25_C
1.25
(ns)
NORMALIZED I CC
NORMALIZED I PO
VCC = 5.0V 1.00 TA = 25_C VIN = 0.5V
DELTA t
AA
0.75
0
200
400
600
800
1000
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
7
7c198: 10/25/89 Revision: February 29, 1996
CY7C198
Truth Table
CE WE OE Inputs/Outputs Mode Power
H L L L
X H L H
X L X H
High Z Data Out Data In High Z
Deselect/Power Down Read Write Deselect, Output Disabled
Package Name
Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Operating Range
Ordering Information
Speed (ns)
15 20 25 35 45
Shaded area contains preliminary information.
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter Subgroups
CY7C198-15LMB CY7C198-20ZC CY7C198-20LMB CY7C198-25DMB CY7C198-25LMB CY7C198-35DMB CY7C198-35LMB CY7C198-45DMB CY7C198-45LMB
Ordering Code
L55 Z32 L55 D16 L55 D16 L55 D16 L55
32 PinRectangularLeadless Chip Carrier 32 Lead Thin Small Outline Package 32 PinRectangularLeadless Chip Carrier 28 Lead (600 Mil) CerDIP 32 PinRectangularLeadless Chip Carrier 28 Lead (600 Mil) CerDIP 32 PinRectangularLeadless Chip Carrier 28 Lead (600 Mil) CerDIP 32 PinRectangularLeadless Chip Carrier
Package Type
Military Commercial Military Military Military Military
Switching Characteristics
Parameter READ CYCLE Subgroups
VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
tRC tAA tOHA tACE tDOE
WRITE CYCLE
7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
tWC tSCE tAW tHA tSA tPWE tSD tHD
Document #: 38-00077-L
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7c198: 10/25/89 Revision: February 29, 1996
CY7C198
Package Diagrams
28 Lead (600 Mil) CerDIP D16
MIL-STD-1835 D-10 Config. A
32 Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
32 Lead Thin Small Outline Package Z32
E
Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice.
Cypress Semiconductor Corporatio n assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under pa tent or other rights. Cypress Semicon ductor does not authorize its products for use as critical components in life support systems where a malfunction or failure of the product may reasona bly be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life support systems applications implies that the manufacturer assumes all r isk of such use and in so doing indemnifies Cypress Semiconductor against all damages.
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