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| HSP50016-EV User's Manual January 1999 File Number 3637.1 DDC Evaluation Platform The HSP50016-EV is the evaluation board for the HSP50016 Digital Down Converter (DDC). It provides a mechanism for rapid evaluation and prototyping. The HSP50016-EV consists of a series of busses which provide input, output, and control to the DDC. These busses are brought out through dual 96 Pin connectors to support daisy chaining HSP50016-EVs with other Intersil evaluation boards for multichip prototyping and evaluation. For added flexibility, the input and control busses can be driven by registers on-board the HSP50016-EV which have been down loaded with data via the parallel printer port of an IBM PCTM or compatible. In addition, the DDC output can be read into the PC via the status lines of the parallel port. Together, the I/O and Control Registers can be used to drive the target DDC with a PC based vector set while collecting output data on the PC's disk. Jumper selectable clock sources provide three different methods of clocking the part under evaluation. In mode one, the clock signal is generated under PC based software control. In mode two, the HSP50016-EV's on-board oscillator may be selected as the clock source. In mode three, the user may provide an external clock through the 96 pin input connector. The HSP50016-EV was built into a 3U Euro-Card form factor with dual 96 Pin Input/Output connectors. The I/O connectors conform to the VME J2/P2 Connector Standard. Features * Single HSP50016-EV May be Used to Evaluate the HSP50016 * May be Daisy Chained to Support Evaluation of Multi-Chip Solutions * Parallel Port Interface to Support IBM PCTM Based Evaluation and Control * Three Clocking Modes for Flexibility in Performance Analysis and Prototyping * Dual 96-Pin Input/Output Connectors Conforming to the VME J2/P2 Connector Standard Applications * PC Based Performance Analysis of HSP50016 * Rapid Prototyping HSP50016 Evaluation Platform 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 HSP50016-EV Getting Started This section describes the initial evaluation system setup for the HSP50016-EV evaluation board. The system setup consists of the evaluation board, software installation, and system test to verify proper operation of the board. Change current directory to the DDCSOFT directory t CD \DDCSOFT Assembly As part of the initial assembly, the HSP50016-EV must be provided with the default jumper configuration to ensure proper operation with the system test software. Each board leaving the factory is supplied with the default configuration as shown in Figure 1. Before using the board with the supplied software, power must be supplied to the board, and the HSP50016-EV must be connected to the parallel port of the PC. t Power is provided to the board by connecting the wall mount power supply provided to connector J2. As an alternative, power may be supplied by a standard 5V 5% supply through the J3 header or the HSP50016-EV's 96 Pin DIN connectors P1 or P2. t The HSP50016-EV is connected to the target PC by connecting the HSP50016-EV's 26 Pin connector J1 to the PC's parallel port using the supplied ribbon cable. Modifications to AUTOEXEC.BAT To run the DDC-SOFT programs, DOS must be able to find the executable files. To ensure that DOS can always find the DDC-SOFT executables, modify the search path to include the location of the DDC-SOFT directory. For example, if the DDC-SOFT programs are installed on drive C: in a subdirectory called\DDCSOFT, add the following line to the end of the existing Path command in the AUTOEXEC.BAT file: t ;C:\DDCSOFT If your AUTOEXEC.BAT file does not contain a PATH command, add the following command to the file: PATH=C:\DDCSOFT t Reboot the PC so that the search path changes will take effect. System Requirements for the Evaluation Board Software The PC system targeted to run the HSP50016-EV software (DDC-SOFT) and interface with the evaluation board must meet the following requirements: t IBM PC/XT/AT, PS/2, or 100% compatible with a minimum of 640K of random access memory (RAM) (DDC-SOFT does not require extended memory) t At least 250kB of free disk space on the hard disk t DOS Version 3.0 or higher t One parallel port with 27 Pin D-Sub connector System Test Test software is provided to verify operation of the HSP50016-EV Board. Prior to performing the system test, it is assumed that the evaluation board has been assembled and configured as described above, power has been applied to the board, and the 26 Pin Connector J1 on board the HSP50016-EV has been connected to the parallel port of the target PC via the supplied cable. The system test is initiated by the following: Change the current directory to that which contains the software required for the system test by typing: t CD C:\DDCSOFT\DDC_CHK Software Installation The distribution diskette contains a program called INSTALL.EXE which installs the DDC-SOFT software onto the target hard disk. Note: The steps in this section assume you are installing DDC-SOFT from a diskette in drive A: onto a hard drive C:. If a different configuration is used, substitute the letter of the drive where the diskette is located for drive A: Substitute the letter for the hard drive for drive C:. To start the installation program: Make sure computer is on and the DOS prompt is displayed. t Type: C: 2 HSP50016-EV When a successful compare has been done, the software message returned is: - Comparing files TEST_OUT.DAT and CMPRFILE.DAT - FC: No differences encountered The most common causes of test failures are incorrect board jumper settings, incorrect comm port selection, or a corrupted eval.cfg file. It is helpful to delete the file TEST_OUT.DAT, prior to the test, to ensure that DDC.CHK runs properly and that a new TEST_OUT.DAT file was created. NOTE: if the operating system precedes DOS 6.0, the user should answer NO to the COMP command prompt to compare additional files. DOS Version 6.0 and above use a different file compare command, so this step is not necessary. DDCCHK checks the version automatically and executes the proper compare routine. The DDCCHK system test assumes that the LPT1 printer port is being used for communication with the HSP50016-EV. If another printer port is used, the Command Line Interface, DDCCMD, must be used to configure the software for using the correct port (see DDCCMD's PPC and PP# command). P2 J1 IQSTB SELECT 1 QOUT SELECT JP20 JP19 1 CABLE J3 J2 JP1 JP2 JP3 JP5 JP6 JP7 JP8 JP9 JP10 JP11 JP12 JP13 JP14 JP15 JP16 JP17 JP18 EXT_CLK OSC_CLK PC_CLK DATA_OE ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 DDC_CLK_INV OUT_CLK_INV CLK_OUT CLK_IN TAP_SEL CLOCK SELECT OUTPUT ENABLE BOARD ADDRESS CLOCK SELECT P1 FIGURE 1. LAYOUT OF HSP50016-EV SHOWING DEFAULT JUMPER CONFIGURATION 3 HSP50016-EV HSP50016-EV Control Panel Software The HSP50016-EV Control Panel is a graphical user interface for controlling the operation of the HSP50016-EV Board via an IBM PC or compatible. The control panel, shown in Figure 3, supports loading the HSP50016's control words; setting the state of control inputs; and specifying files which serve as the sources and destinations for the HSP50016's data and TAP inputs and outputs. Operation of the control panel software is dependent on the clock source provided to the HSP50016-EV as specified in the clock select portion of the control panel. The HSP50016-EV Control Panel is invoked by typing: DDCCTRL Port Configuration Communication between the Control Panel software and the evaluation board requires that the software knows which one of the PC's parallel ports is being used for communication with the HSP50016-EV and which board address the HSP50016-EV has been configured for. The default configuration assumes that LPT1 is being used and that the HSP50016-EV has been configured for a board address of 0. The Port Configuration can be inspected by opening up the port configuration window using the F9 function key. As shown in Figure 4, the window displays the available parallel ports and their addresses. Also displayed are the current port and HSP50016-EV board address being used by the Control Panel software. The current port and HSP50016-EV address are changed by opening up the Port Configuration Window, using the up/down arrow keys to select the desired parameter, and toggling the space bar to change the selection. Proper operation of the control panel software requires that the HSP50016-EV board address specified in the port configuration window matches the address jumpered in the Address Selection Section of the HSP50016-EV's headers JP6-13. Clock Select The Clock Select portion of the control panel is used to tell the Control Panel software which of four different clock sources is being supplied to the HSP50016-EV. The choices include one of two different software generated clocks (Manual CLK or Port CLK), an oscillator clock provided by the HSP50016-EV (Oscillator CLK), or an externally supplied clock (External CLK). The clock mode selected must be consistent with the Clock Select jumper position in the HSP50016-EV's headers JP1-3. If either Manual CLK or Port CLK are specified in the Control Panel, the clock select jumper must be inserted in JP3. If either Oscillator CLK or External CLK is specified, the jumper must be inserted in JP2 or JP1 respectively. In Manual CLK mode, single clock pulses are sent to the HSP50016 by depressing the F2 function key. The clock pulse is software generated by setting and clearing the PCCLK bit of File I/O Select The File I/O Select portion of the Control Panel allows the user to specify files which can be used as an input data source or an output data destination for the HSP50016-EV. The input data is loaded on to the input bus prior to the software generated clock and the output data is read from the output bus following the software generated clock. If file based input is selected, the Control Panel software down loads data from the specified file to registers on the HSP50016-EV and clocks the data into the DATA0-15 inputs of the DDC. The Loop Count allows the user to simulate long data streams by repeatedly sending the same input file. If file based output is specified, the software reads the data on the I and Q outputs of the HSP50016 and stores the data in the specified file. The software automatically reads the 4 HSP50016-EV output data and writes it into the output file as two's complement complex or real data. The configuration of the I, Q, IQCLK and IQSTB pins is transparent to the user, provided that none of the pins are three-stated and the DDC Control Word fields Real Output, HDF Decimation Rate, Number of Output Bits, I followed by Q and IQCLK rate are compatible with each other. All valid output modes are supported. File based I/O is activated by using the space bar to toggle the "check mark" symbol in the window proceeding the input and output file identifiers in the control panel's file I/O Section. If either file input or output is activated, the respective file name must be entered in the window to the right of the file identifier. File input or output may be disabled at any time by toggling the respective "check mark". Control Words In the lower left hand corner of the control panel is a data window which contains the hexadecimal values loaded into the HSP50016's eight control words. The contents of a particular control word may be updated by moving the cursor to the data window which is to be modified, selecting the control word by pressing the space bar (which moves the check mark to the desired control word) and depressing the F4 key. A submenu pops up which parses that control word into its various fields so that they may be examined or modified individually. The value entered into the data window is down loaded to the HSP50016 and the submenu disappears when the user depresses the F2 key. Leaving the window via the Note: File I/O is only valid when either the `Manual CLK' or `Port CLK' clocking modes are selected and it is disabled if other clocking modes are specified. Input and output data files are ASCII files whose format is described in Appendix A. There is no limitation to the input and output file size. Care must be taken if file output is specified since data is collected in the file until file output is deactivated or the DDCCTRL Program is exited. TAP I/O files are similar, except that the TAP is available regardless of the CLK setting. The format for the TAP input and output files is given in Appendix B. Note that all values displayed in this window are the last values written to the control words, as opposed to having been read from the DDC itself. Help Help windows are provided as a source of information for control panel usage. The help window is activated by the F1 function key, and contains information based on the window which is currently active. HSP50016 Data Inputs The data window to the left of the HSP50016 icon is used to specify hexadecimal values which drive the DDC's data inputs DATA0-15. Data is entered into this window in hexadecimal format starting with the most significant digit. The contents of a particular data window may be edited by following the window editing instructions in Appendix C. If file input is selected, the data input is driven with data from the specified file. On each clock the data window is updated with the data sample down loaded from the file. In this mode the data input window may not be manually updated. Command Line Interface As an alternative to the control panel, a command line interface is provided which allows the user to control the HSP50016-EV by issuing commands from the DOS prompt. The commands perform basic I/O and configuration functions by up or down loading data to the HSP50016 through the HSP50016-EV. The Command Line Program has the following usage: DDCCMD [Command] [ARG 1] [ARG 2] [ARG 3] The Command specifies the action to be taken, and the Arguments (ARG1, ARG2) represent additional data required by the command. For example, to load Control Word 1 with a value of 200000005(HEX) and set the update bit, the user would type: DDCCMD WCW 1 1 200000005 HSP50016 Data I&Q Outputs There are 32 bits available at P2. The control software for the evaluation board performs a serial read via the PC Port. Control Signals The control signal portion of the control panel is used to define the state of the DDC control signals RESET and IQSTRT. The logical state of a control signal is set by using the space bar to toggle the signal state in the window preceding the specified control signal. When the evaluation board is in Port CLK mode and RESET is set either low or high, the DDC is automatically clocked five times. See the HSP50016 Data Sheet for a complete description of the control signals. RESET must be toggled low and high once after power up. The software DOES NOT do this automatically. 5 HSP50016-EV that the software automatically updates the control words from the EVAL.CFG file upon entering the interactive mode. Leaving the interactive mode is accomplished by typing "quit" or "exit." DDCCMD gives the user the ability to control the evaluation board via DOS batch files or system calls from a programming language. The DDC_CHK6.BAT file discussed in the System Test Section is an example of how the Command Line Program might be used in a DOS batch file. connector or the P2 connector. If jumpers are inserted as shown in Figure 2, a clock signal supplied through the CLK_IN pin of the P1 input header drives a buffer whose output clocks the HSP50016. The jumper inserted on JP16 feeds the buffered clock signal to the CLK_OUT pin of the P2 connector. If jumpers are inserted as shown in Figure 3, the CLK_OUT pin of the P2 connector drives the clock buffer which in turn drives the clock input of the HSP50016. The jumper inserted between JP16 pin 2 and JP17 pin 2 allows the CLKIN pin to be driven by the buffer output. NOTE: The jumper placement shown in Figure 2 is the standard configuration. It is possible to configure the DDC so that the I, Q, IQCLK and IQSTB outputs are in a high impedance state. Except for IQSTB, these pins are pulled up on the evaluation board so that they will not float under these conditions. Since IQSTB can be either active high or low, it must be capable of being pulled either way. JP19 determines whether IQSTB is pulled up or down when it is three-stated. This jumper should be installed such that IQSTB is pulled to its inactive state. Configuration Jumpers The Configuration Jumpers consists of the jumper headers JP1-3 and JP5-20 as shown in Figure 1 and Table 1. Refer to the evaluation board schematic found in the Appendices. Most of these are self-explanatory, but the following bear further discussion. JP16 JP17 JP18 FIGURE 2. JUMPER CONFIGURATION IF CLOCK IS SUPPLIED THROUGH P1 INPUT HEADER Note: The position of JP20 comes into play only when parallel output from P2 is desired. The jumper should be placed between pins 1 and 2 when the DDC is configured for I followed by Q mode; the jumper should be from JP20-2 to JP20-3 when I and Q are output separately. The HSP50016-EV is shipped from the factory with the default jumper configuration shown in Figure 1 and Table 1. For the supplied software to properly control operation of the HSP50016, it is assumed that the jumpers are as specified in the default configuration; of course, once the user is familiar with the operation of the board, this configuration may be modified as required. The system test software, DDCCHK, must be run using the default configuration. JP15 JP16 JP17 JP18 FIGURE 3. JUMPER CONFIGURATION IF CLOCK IS SUPPLIED THROUGH P2 OUTPUT HEADER The jumpers JP16 and JP17 are used to select whether the HSP50016's clock source is provided through the P1 TABLE 1. DESCRIPTION OF JUMPER CONNECTIONS JP 1 2 3 5 6-13 14 15 16 17 18 19 20 DESCRIPTION DDC CLK driven from external source when this jumper is installed. DDC CLK driven from on board oscillator when this jumper is installed. DDC CLK driven from PC software when this jumper is installed. Only one of JP1, JP2 and JP3 selected at a time. DEFAULT Installed Installed JP6 Installed Installed Installed JP16-1 to JP16-2, JP17-1 to JP17-2 Installed JP19-1 to JP19-2 JP20-2 to JP20-3 DDC DATA0-15 driven from PC software when installed, otherwise data is from external source. Must be installed or DATA0-15 lines must be driven to avoid damage to DDC. Selects evaluation board address. Only one of these jumpers should be installed at a time. Selects input clock as inverted. Installed = non-inverted. Selects output clock as inverted. Installed = non-inverted. Direct flow of input and output clocks. JP16-1 is shorted to JP16-2 and JP17-1 is shorted to JP17-2 for the DDC CLK to be driven by the PC, on board oscillator, or connector pin P1C-20. To drive CLK from P2C20, jumper JP16-1 to JP17-1 and JP16-2 to JP17-2. JP1 must be installed in this configuration. TAP inputs driven by PC (installed) or from P2 (not installed). IQSTB pulled up (JP19-1 shorted to JP19-2) or pulled down (JP19-2 to JP19-3). Must be installed (in either position) to avoid damage to evaluation board. Serial to parallel converters configured for up to 32-bit, I followed by Q (JP20-1 to JP20-2) or 16 bit, I and Q output separately (JP20-2 to JP20-3). 6 HSP50016-EV HSP50016-EV CONTROL PANEL CLOCK SELECT MANUAL CLK DATA FILE I/O SELECT PORT CLK OSC. CLK EXTERNAL CLK CONTROL SIGNALS 1 RESET 0 IQSTRT INPUT FILE: INPUT.DAT LOOP COUNT: 1 OUTPUT FILE: OUTPUT.DAT DATA FORMAT: HEX DATA0-15 7FFF HSP50016 DDC (I) (Q) 0000000000 0000000000 CONTROL WORDS 0 2 3 4 5 6 7 000000000 000000000 000000000 00000006E 00D002100 000000000 000000002 CLOCK NUMBER 0 1 200000001 JTAG FILE I/O SELECT INPUT FILE: J_INPUT.DAT OUTPUT FILE: J_OUTPUT.DAT F1 - HELP F2 - START CLOCK F3 - START JTAG F4 - CONTROL WORD F9 - PORT CFG F10 - QUIT FIGURE 4. CONTROL PANEL SCREEN AS DISPLAYED ON PC HSP50016-EV CONTROL PANEL PORT CONFIGURATION CLOCK SELECT MANUAL CLK FILE I/O SELECT PORT CLK OSC. CLK EXTERNAL CLK CONTROL SIGNALS 1 0 RESET# IQSTRT# INPUT FILE: INPUT.DAT AVAILABLE PRINTER PORTS OUTPUT FILE: OUTPUT.DAT LPT1 LPT2 LPT3 CURRENT PORT SELECTION : LPT1 ADDRESS (HEX) 0x3BC 0x378 0x3BC (i) (Q) 0 0000000000 0000000000 CONTROL WORDS 0 2 3 4 5 6 7 000000000 000000000 000000000 00000006E 00D002100 000000000 000000002 CURRENT HSP50016-EV ADDRESS : 1 200000001 INPUT FILE: J_INPUT.DAT OUTPUT FILE: J_OUTPUT.DAT F1 - HELP F2 - START CLOCK F3 - START JTAG F4 - CONTROL WORD F9 - PORT CFG F10 - QUIT FIGURE 5. PORT CONFIGURATION WINDOW AS DISPLAYED ON PC 7 HSP50016-EV TABLE 2. COMMAND LIST FOR COMMAND LINE INTERFACE SOFTWARE COMMAND WCW ARGUMENT #1 WORD NUMBER WORD NUMBER CONTROL REGISTER CONTENTS ARGUMENT #2 UPDATE BIT ARGUMENT #3 CONTROL WORD COMMAND DESCRIPTION Loads the specified control word of the HSP50016 with the 36-bit hexadecimal value specified in Argument #3. Setting the update bit = 1 updates the configuration of the DDC; update bit = 0 only modifies the control word. Reads one of the HSP50016's control words to the screen. If Argument #1 is omitted, all control words are displayed. Loads the evaluation board's control register with a 16-bit hexadecimal value. RCW WCS RCS DIN CLK RES IQS RDO PDF INPUT FILE NAME OUTPUT FILE NAME COUNT 0/1 INPUT DATA COUNT Displays the last value loaded into the evaluation board's control register. Does not read the current contents of the register. Loads the HSP50016's DATA0-15 input with the 16-bit value specified in Argument #1. Toggles PCCLK, the software clock to the DDC, the specified number of times. If Argument #1 is omitted, COUNT = 1. Resets the DDC and cycles CLK five times. Sets the state of the IQSTRT line. Reads the output I and Q data of the DDC to the screen. Process Data File: Read one sample from input file, write it to DATA0-15, repeat until output data becomes available, then read outputs, write to output file. Repeat until all samples in the data input file have been read. Perform this entire process for the number of times specified by Argument #3. If Argument #3 is omitted, input file is read one time. Output data file format: 0 = hexadecimal, 1 = floating point. Toggle TCLK one cycle. Write TRST low, then high. 0/1 0/1 Write one bit to TMS pin. Write one bit to TDI pin. Read one bit from TDO pin. INPUT FILE NAME PORT NUMBER (1 - 3) OUTPUT FILE NAME BOARD ADDRESS (0 - 7) S Process Test File: Write bit patterns specified in input file to TAP; read TAP output and store in output file. See Appendix B for TAP file format. Change the printer port and HSP50016-EV board address that the DDCCMD program is using for communication between the PC and the evaluation board to those specified in arguments 1 and 2. The board address is set by inserting a jumper one of the headers JP6-13. Display the printer port and HSP50016-EV board address that the DDCCMD Program is using for communication to the PC. Display the state of the error bit: 0 =...No error. 1 =...Software unable to execute command; e.g., a syntax error was detected in the command line, an RDO command was executed while DDC was executing a data output cycle, and so on. A correctly executed command clears the bit, except for ERR, BYE, EXIT and QUIT, which have no effect on the error bit. List available commands together with a brief description. Any one of these terminates interactive mode. ODF TCK TRS TMS TDI TDO PTF 0/1 PP PPC ERR ? BYE, EXIT, QUIT 8 HSP50016-EV Hardware Overview The HSP50016-EV was designed to facilitate prototyping with the HSP50016 Digital Down Converter. It can be used in a stand alone mode, in conjunction with other Intersil evaluation boards, or be inserted into a card cage and operate as a part of a larger system. The following description of the board references both the Block Diagram in Figure 6 and the Schematic Diagrams, which are included at the back of this manual. controlled through the 96 Pin DIN connectors, the user must emulate the operation of the PC interface. A description of this operation is given below in the section describing the Parallel Port Bus. The DDC output is available through three different paths: It is connected to the Select line of the PC Parallel Port through the eight to one multiplexer U6; it is connected to the 96 Pin DIN connector P2 through the buffer U1; finally, it is converted to parallel data by the Shift Registers U2-5 and driven out on P2. The mapping for P2 is given in Table 4. Bus Structure The HSP50016-EV utilizes a set of busses for DDC input, output and control as shown in Figure 6. The input and output busses connect the DDC to the outside world through 96 Pin DIN connectors conforming to the VME J2/P2 Connector Standard. DDC control information is provided either by control registers down loaded via the parallel port of a PC or from the 96 Pin DIN connectors The DDC's input data bus, DIN0-15, is driven from the 96 Pin DIN connector P1 (Pinout shown in Table 3). DIN0-15 may be driven by Registers U12 and U13 which have been down loaded with data through the Parallel Port Bus. The source of the input data is selected by jumper JP5. Installing the shorting jumper on JP5 selects the PC as the data source. Removing the jumper puts the registers driving the DIN0-15 bus in a high impedance state so that the input data can be driven from P1. The control lines of the DDC and the board are driven by the outputs of the Control Registers (U11, U16). These registers are down loaded with data via the Parallel Port Bus or through the PCD0-7 lines on P1 or P2. when the board is Parallel Port Bus The Parallel Port Bus carries the write only parallel data and signals required to support bidirectional data transfers between the HSP50016-EV and the parallel port of the PC. This bus contains eight data lines, PCD0-7, two control lines, PCWR0-1, and the serial output line PCRD1. The control and data lines are used to down load data into the on board registers of the HSP50016-EV. The serial output line carries the DDC output data back to the PC. The Parallel Port Bus is attached to the PC by connecting the ribbon cable provided to the PC's parallel port and to the 26 pin connector J1 on the DDC Evaluation Board. The ribbon cable maps the Parallel Port Bus signals to the PC's parallel port as shown in Table 5. The Parallel Port Bus is brought out through each of the 96 Pin DIN connectors (P1, P2) so that multiple Intersil evaluation boards can be daisy chained. This allows all of the evaluation boards in the chain to be controlled through a single board which has been connected to a host PC. SHIFT REGISTER INPUT BUS 1 (DIN0-15) CLK IN 96 PIN INPUT CONNECTOR (P1) 16 HSP50016JC-52 I0-15 16 Q0-15 16 96 PIN OUTPUT CONNECTOR (P2) CLK OUT CONTROL BUS INPUT REG 1 CONTROL REG PARALLEL PORT INTERFACE PARALLEL PORT BUS EXT CLK CLK SELECT OSC CONFIGURATION JUMPER FIELD (JP1-3, 5-18) ADDRESS SELECT OUTPUT ENABLE 13 PARALLEL PORT CONNECTOR (J1) 26 PIN CONNECTOR FIGURE 6. BLOCK DIAGRAM OF HSP50016-EV 9 HSP50016-EV TABLE 3. PIN ASSIGNMENTS FOR 96 PIN INPUT CONNECTOR P1 PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ROW A SIGNAL MNEMONIC N.C. DIN0 DIN2 DIN4 DIN6 GND DIN9 DIN11 DIN13 DIN15 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. GND GND GND GND GND GND PCD0 PCD2 PCD4 PCD6 PCWR0 PCWR1 PCRD1 ROW B SIGNAL MNEMONIC VCC GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. GND VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. GND VCC ROW C SIGNAL MNEMONIC GND DIN1 DIN3 DIN5 DIN7 DIN8 DIN10 DIN12 DIN14 GND N.C. N.C. N.C. N.C. GND N.C. N.C. N.C. N.C. CLKIN N.C. N.C. N.C. N.C. N.C. PCD1 PCD3 PCD5 PCD7 GND PCRD0 PCRD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TABLE 4. PIN ASSIGNMENTS FOR 96 PIN OUTPUT CONNECTOR P2 PIN NUMBER ROW A SIGNAL MNEMONIC N.C. QO0 QO2 QO4 QO6 GND QO9 QO11 QO13 QO15 N.C. IO1 IO3 IO5 IO7 IO8 IO10 IO12 IO14 TCK.E TMS.E TRST.E TDI.E TDO.B GND PCD0 PCD2 PCD4 PCD6 PCWR0 PCWR1 PCRD1 ROW B SIGNAL MNEMONIC VCC GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. GND VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. GND VCC ROW C SIGNAL MNEMONIC GND QO1 QO3 QO5 QO7 QO8 QO10 QO12 QO14 GND IO0 IO2 IO4 IO6 GND IO9 IO11 IO13 IO15 CLKOUT IQSTB.B IQCLK.B IOUT.B QOUT.B GND PCD1 PCD3 PCD5 PCD7 GND PCRD0 PCRD2 10 HSP50016-EV TABLE 5. SIGNAL MAPPING FOR CONNECTOR J1 PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 J1A SIGNAL MNEMONIC N.C. PCD0 (D0) PCD1 (D1) PCD2 (D2) PCD3 (D3) PCD4 (D4) PCD5 (D5) PCD6 (D6) PCD7 (D7) N.C. PCRD0 (BUSY) PCRD2 (PAPER END) PCRD1 (SELECT) J1B SIGNAL MNEMONIC N.C. N.C. PCWR0 (INIT PRINTER) PCWR1 (SELECT IN) GND GND GND GND GND GND GND GND GND register. The On-Board Registers are down loaded by first writing data to the Parallel Port Interface's Holding Register U17 followed by two writes to the Address Register U18. By writing the address register, data in the holding register is loaded into one of the Registers U11, 12, 13, 16. The address register specifies the particular register for loading as well as the board address of the HSP50016-EV targeted for the data download. The HSP50016-EV board address is selected by placing a shorting jumper on one of the headers JP6-13 (see Configuration Jumper Field Section), and the memory map for the 8 data registers is shown in Table 6. The bit map for the Parallel Port Interface's Address Register is given in Table 7. The Parallel Port Interface's Address and Holding Registers are loaded with data from the PCD0-7 data lines of the parallel port bus by a "low" to "high" transition on the appropriate bus control line. Specifically, the address register is loaded with data when a "low" to "high" transition occurs on the PCWR0 line of the Parallel Port Bus, and the holding register is loaded by a like transition on the PCWR1 line. The mapping of the parallel port bus signals to the PC's parallel port is given in Table 5. As an example, consider the loading of the least significant byte of the data input, Register U13, as shown by the Timing Diagram in Figure 7. First, data is down loaded to the Parallel Port Interface's Holding Register. Next, the address register is written with a value which contains the address of U13 (see Table 6 for memory map), the HSP50016-EV board address (assumed to be zero in this example), and a "high" in the LD bit position (see Table 7 for Address Register Bit Map). Finally, data is latched into the targeted register by rewriting the address register with the same board and register address but with a "low" in the LD bit position. The "high/low" transition of the LD bit loads the data in the holding register into the target data register on the specified HSP50016-EV. PCRD = PC Read; PCD = PC Data TABLE 6. REGISTER TO INPUT/CONTROL BUS MAPPINGS REGISTER ADDRESS 0 1 2 3 4-7 DESTINATION REGISTER U16 U11 U13 U12 Not Used REGISTER FUNCTION Clock and control DDC Control, TAP DDC Data input LS Byte DDC Data Input MS Byte N.C. TABLE 7. ADDRESS REGISTER BIT MAP LOAD ADDRESS RANGE D6 BOARD ADDRESS D5-3 REGISTER ADDRESS D2-0 PCWR0 NOT USED D7 PCWR1 Register Structure The HSP50016-EV provides a set of registers which may be used as a source for DDC input and control. They can be loaded from either the parallel port or from the P1 connector. PCD0-7 DATA 0x42 (HEX) 0x02 (HEX) Down Loading Data via Parallel Port Interface The control and input registers are down loaded from the PC by a series of single byte writes to the to the Parallel Port Interface. The Parallel Port Interface consists of two decoders, an 8-bit address register, and an 8-bit holding DATA FOR ADDRESS OF CODE TO TOGLSBYTE OF DATA INPUT GLE LOAD DATA LINE FOR U13 DATA INPUT REG WRITWRITTEN TO TEN TO HOLDING REG ADDRESS REG FIGURE 7. TIMING DIAGRAM FOR LOADING DATA INTO LSBYTE OF DATA INPUT REGISTER 11 HSP50016-EV Up Loading Data via PC's Parallel Port Data is up loaded to the host PC through the "Select" serial status line of the PC's parallel port. The PC up loads data by monitoring the state of the PCRD1 serial output line on the HSP50016-EV's Parallel Port Bus. The mapping of the evaluation board signals to the PC's parallel port is given in Table 5. The on-board oscillator is selected as a clock source by JP2. In this mode, the oscillator on board the HSP50016-EV is supplied as a clock to the DDC. Since data transfers to the DDC via the HSP50016-EV's I/O Registers are much slower than the DDC's data rate using the oscillator clock, the PC can only be used to provide the DDC with asynchronous control in this mode. The LSB of the Control Register U16 is selected as the clock source if a jumper is inserted in the header JP3. In this mode, the clock signal is generated by using register writes to toggle the PCCLK bit. Since the clock may be controlled by software, input and control register writes and the output shift register reads can be performed synchronously with the clock. Consequently, the HSP50016-EV can be used as a hardware modeler where input and output data vectors are transferred via the PC's parallel port. DDC Data and Control via P1 Connector When it is desired to use P1 connector for data input, the registers driving the data bus are three-stated by removing the jumper JP5 (see Configuration Jumper Field Section). The DIN0-15 pins on P1 are then used to drive the input pins of the HSP50016. If all 16 pins are not used, then the DIN bus should be loaded starting from bit 15 down. When JP5 is not installed, all data input pins must either be driven by an external data source or grounded to avoid damage to the board. To control the DDC from the P1 or P2 connector, the PCD07 bus is exercised via the connector. In this case, the user must operate this bus in the same manner as the PC exercises it from the parallel port as described above. No jumper selection is necessary in this case; it is only necessary to leave the parallel port connector J1 unconnected. To operate the Test Access Port from P2, the shorting jumper on JP18 is removed. The TAP pins are then controlled directly from P2 according to the TAP Specification. In this case, the SEL0-2 lines should be set to 0, 0, and 1 respectively. Configuration Jumper Field The HSP50016-EV is configured for operation by placing jumpers in the headers JP1-3 and JP5-18. As shown in Table 1, the jumper field has areas dedicated for clock selection, register output enables and board address selection. The default jumper placement is shown in Figure 1 and Table 1. Each HSP50016-EV leaves the factory jumpered with the default configuration. The Clock Select jumpers are used to specify one of the three available DDC clocking modes. These include EXT_CLK for selection of an external clock source, OSC_CLK for selection of the on board oscillator clock, and PC_CLK for selection of a register driven clock using the LSB of the CTL Control Register. The clocking modes are described in the DDC Clocking Modes Section of this manual. Note: Normally, only one clock source may be selected at a time. In any mode, the input and output clocks may be negated independently by removing the jumpers on JP14 and JP15. The output of the Input Registers U12 and U13 are enabled by placing a jumper on JP5 (see Bus and Register Structure Sections) If a jumper is removed, the output of the respective register is three stated. The Board Address Jumpers are used to specify the HSP50016-EV board address used for data transfers via the Parallel Port Bus. An address from 0 to 7 may be selected by inserting a jumper in positions ADDR0 thru ADDR7 respectively. Only one jumper may be inserted in this field. The jumper JP18 is used to select the source of data for the IEEE 1149.1 Test Access Port (TAP) bus. Inserting this jumper enables the PC to drive this bus, while removing it enables control from the P1 connector. JP19 selects whether the IQSTB line is pulled up or down. Placing the jumper between header pins 1 and 2 pulls IQSTB up, while shorting pins 2 and 3 pulls IQSTB down. The position of the jumper is only meaningful when IQSTB is DDC Clocking Modes The HSP50016-EV provides the DDC with one of three jumper selectable clock sources. The three clock choices consist of an on-board oscillator, a user provided external clock, and a clock generated by toggling the LSB of the Control Register U16. The clock source is select by placing a jumper on either JP1, 2 or 3. To support applications in which multiple evaluation boards are daisy chained together, a clock output line is routed to the HSP50016-EV's output connector P2. An external clock may be selected by inserting a jumper on the header JP1. In this mode, an external clock supplied to the CLKIN pin of the 96 pin Input Connector is provided to the DDC. This configuration supports the use of a common clock between daisy-chained evaluation boards by wiring CLKOUT from the P2 Output Connector of one board to the CLKIN pin of another board's P1 Input Connector. Since there is no synchronization between the externally provided clock and data transfers to the HSP50016-EV's I/O Registers, the PC would typically provide the DDC with asynchronous control in this mode. 12 HSP50016-EV three stated, which can be programmed by setting the proper control bits of the DDC. Even if the user has no intention of operating in this mode, it is recommended that JP19 be put in one position or the other to avoid the possibility of this line floating after power up or due to being inadvertently placed in the high impedance state. If the shorting jumper is not installed on JP19, the IQSTB line may oscillate and cause damage to U6. When parallel output is desired from the P2 connector, JP20 controls the flow of data to the Shift Registers U4 and U5. The user may read the I and Q outputs separately with 16 bits of precision by configuring the DDC to output data separately over the I and Q pins, setting the output precision to 16 bits and inserting a shorting jumper on header pins 2 and 3. The parallel outputs can be read with any precision by setting the DDC for I followed by Q and setting the jumper on header pins 1 and 2. For this circuit to operate correctly, the DDC must also be set for IQCLK Rate > 1, and data stable on the falling edge of IQCLK. Note that in the schematic, the parallel output lines are numbered assuming that the DDC output is MSB first, although the circuit will work just as well in LSB first mode. HSP50016-EV Software License Agreement In return for the purchase price of the HSP50016-EV product, the Purchaser receives from Intersil Corporation ("Intersil") a non-exclusive nontransferable (except as set forth below) license under Intersil copyrights to use the software subject to the following terms and conditions: [1] The Software is protected by both United States Copyright Law and International Treaty Provisions. Therefore, you must treat the Software like any other copyrighted material (e.g., a book) and may not copy, distribute or make derivatives of any part thereof except that the you may either a) make one copy of the Software solely for archival purposes, or b) transfer the Software to a single hard disk provided you keep the original solely for backup or archival purposes. [2] The Software may be transferred to a third party on a permanent basis, provided you retain no copies and the recipient agrees, in writing to Intersil, to the terms of this Agreement. [3] If the software package contains both 3.5" and 5.25" disks, then you may use only the disks appropriate for your single-user computer. You may not use the other disks on another computer or loan, rent, lease, or transfer them to another user except as part of the permanent transfer (as provided above) of all Software. HSP50016-EV Limited Warranty Intersil warrants the HSP50016-EV to be free of defects in material and workmanship under normal use for a period of ninety (90) days. Intersil also warrants that the HSP50016EV User's Manual is substantially complete and contains all the information which Intersil considers necessary to use the HSP50016-EV, and that the HSP50016-EV functions substantially as described in the HSP50016-EV User's Manual. Intersil will replace the HSP50016-EV as Intersil's sole duty under this warranty only if you ship it, postage prepaid, to Intersil within 90 days of such acquisition and provide proof of date of acquisition. This limited warranty does not extend to any products which have been damaged as a result of accident, misuse, abuse, or as a result of service or modification by anyone other than Intersil or Intersil's authorized representatives. Intersil makes no other express or implied warranty with respect to the HSP50016-EV other than the limited warranty set forth above. Intersil disclaims all implied warranties of merchantability and/or fitness for a particular purpose. In any event, all implied warranties shall be limited to the duration of this warranty. The liability of Intersil, if any, shall under any tort, contract or other legal theory be limited to the actual price paid for such product and shall in no event include incidental, consequential, special or indirect damages of any kind, even if Intersil is aware of the possibility of such damages. Intersil reserves the right to revise and make changes to this manual and the HSP50016-EV from time to time without obligation to notify any person of, or to provide any person with, such revisions or changes. 13 HSP50016-EV Appendix A Data File Structures The Input/Output data files used by the HSP50016-EV Control Panel and Command Line Interface Software contain data samples. The data files consist of a seven line header followed by the data itself. The Header Section must follow this format: Comment #1 Comment #2 Comment #3 Comment #4 Comment #6 r1n * * * The `n' on the 7th line of the header should be replaced by the number of data samples in the file. Following the header, the data samples are listed one per row. The data sample is represented as a two's complement floating point value bounded by +1.0 and -1.0. The output file format is similar, except that the data samples are usually complex, with the real part in the first column and the imaginary part in the second column. In this case, the "r" int line 7 of the file header is replaced with a "c". The exception to this is when the DDC is in real output mode, in which case the output file consists of one column of real data as shown above. The file CMPRFILE.DAT installed in the DDC_CHK subdirectory is an example of the output data file structure. Line 1: Line 2: Line 3: Line 4: Line 5: Line 7: (Data sample) Appendix B: TAP File Format The input test vector file is read line by line; each set of inputs is supplied to the part simultaneously. On the falling edges of TCK, the output pins are read and their states are stored in the output file. Input and output files are ASCII text. The input file has no header or trailer, but for purposes of clarity, it is recommended that the user include a header such as the one shown in the example below. The first column of bits is applied to the TDI pin, the next to TRST, and so on as shown. Input file example: # Comment lines denoted by # in column 1 #T #D #I # 1 1 1 1 1 T R S T 1 0 0 1 1 T M S 1 1 1 1 1 T C K 0 1 0 1 0 The output file is similar in format, with each column corresponding to an output pin and each row representing the state of the pins on each falling edge of TCK. Output file example: I Q S T B 0 1 0 I Q C L K 0 0 0 T D O 1 1 1 I 1 0 0 Q 1 1 1 Appendix C: Window Editing KEY Control-Y Insert Any Character Delete Backspace Right/Left Arrow Home End Enter/Up/Down Arrow Keys Space Bar Deletes contents of field. Toggles insert/overwrite editing modes. Inserts or replaces character at current cursor location. Deletes character at current cursor location. Deletes character to the left of the cursor. Moves cursor right or left. Positions cursor at the beginning of the current line. Positions cursor at the end of the current line. Enter edited data and exit window. DDCCTRL does not accept changes until window is exited. Toggles control signals FUNCTION All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 14 Schematic DDCCLK DDCCLK R2 IQ CLK TSELR# ON EDI IO UT Q UT O PCCLK SEL0 SEL1 SEL2 SRRST# SRO E# VCC 1 U10 1A 2B 3C 6G 1 4G 2A 5G 2B 74ACT138 74ACT574 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 11 CLK 1O C 15 14 13 12 11 10 9 7 IQ STB. P VCC PCCLK SEL0 SEL1 SEL2 SRRST# SRO E# 1 10 9 8 7 6 5 4 3 2 RNG SEL RNG SEL 15 D0 D1 D2 D3 D4 D5 D6 D7 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 2 3 4 5 6 7 8 9 PCCLK SEL0 SEL1 SEL2 SRRST# SRO E# IQ STRT# RESET# U16 D1 D2 D3 D4 D5 D6 D7 D8 19 18 17 16 15 14 13 12 DDCCLK DI N0 DI N1 DI N2 DI N3 DI N4 DI N5 DI N6 DI N7 DI N8 DI N9 DI N10 DI N11 DI N12 DI N13 DI N14 DI N15 14 17 16 15 11 10 9 8 29 30 31 32 33 35 36 37 38 IQ STB IQ CLK I 2 IQ STRT# 26 RESET# Q U7 CLK DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 41 44 42 43 CCLK CDATA CSTB CS# D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 11 CLK 1O C 74ACT574 19 18 17 16 15 14 13 12 U11 D1 D2 D3 D4 D5 D6 D7 D8 CCLK CDATA CSTB CS# TCK. R TM R S. TRST. R# TDI . R 25 24 21 20 TCK TM S TRST# TDI U14 1A 2B 3C 6G 1 4G 2A 5G 2B 74ACT138 11 1 CLK O C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 D0 D1 D2 D3 D4 D5 D6 D7 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 2 3 4 5 6 7 8 9 DI N0 DI N1 DI N2 DI N3 DI N4 DI N5 DI N6 DI N7 U13 D1 D2 D3 D4 D5 D6 D7 D8 19 18 17 16 15 14 13 12 15 14 13 12 11 10 9 7 ADRNG0 ADRNG1 ADRNG2 ADRNG3 ADRNG4 ADRNG5 ADRNG6 ADRNG7 DATA OUTPUT ENABLE JP5 1 2 HSP50016 1Y 2Y 3Y 4 7 9 4Y 12 A/B G 74ACT157 DI N8 DI N9 DI N10 DI N11 DI N12 DI N13 DI N14 DI N15 2 3 4 5 6 7 8 9 11 CLK 1O C TCK. R TCK. E TM R S. TM E S. TRST. R# TRST. E# TDI . R TDI . E TSEL. R# D0 D1 D2 D3 D4 D5 D6 D7 74ACT574 U12 1 D1 Q 19 2 D2 Q 18 3 D3 Q 17 4 D4 Q 16 5 D5 Q 15 6 D6 Q 14 7 D7 Q 13 8 D8 Q 12 2 3 5 6 11 10 14 13 1 15 D0 D1 D2 D3 D4 D5 D6 D7 U8 1A 1B 2A 2B 3A 3B 4A 4B D[ 0. . 7] ADRNG 0. . 7] [ 74ACT574 TSELR# JP18 1 2 TAP SELECT R1 PCD0 PCD1 PCD2 PCD3 PCD4 PCD5 PCD6 PCD7 JP19 1 IQSTB SELECT 2 MUST BE 3 INSTALLED! R4 10K 1 3 4 5 IQ STB IQ CLK IO UT Q UT O 2 3 4 5 6 7 8 9 10 IQ STB IQ CLK IO UT Q UT O PCD0 PCD1 PCD2 PCD3 PCD4 PCD5 PCD6 PCD7 2 3 4 5 6 7 8 9 U18 D1 D2 D3 D4 D5 D6 D7 D8 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 19 18 17 16 15 14 13 12 PCW R0 PCW R0 11 CLK 1O C 74ACT574 TDO 22 TDO TDO HSP50016-EV DI N[ 0. . 15] DI N[ 0. . 15] PCD0 PCD1 PCD2 PCD3 PCD4 PCD5 PCD6 PCD7 2 3 4 5 6 7 8 9 U17 D1 D2 D3 D4 D5 D6 D7 D8 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 19 18 17 16 15 14 13 12 PCW R1 PCW R1 11 1 CLK O C 74ACT574 PCD[ 0. . 7] PCD[ 0. . 7] ADRNG 0. . 7] [ TCK. E TCK. E TM E S. TM E S. TRST. E# TRST. E# TDI . E TDI . E JP19: SELECT IQSTB# TO INACTIVE STATE WHEN 3-STATED. WARNING: IN ORDER TO AVOID DAMAGE TO BOARD THIS JUMPER MUST BE INSTALLED ON POWER UP! JP18: WHEN INSTALLED, IEEE-1149 BUS IS CONTROLLED THROUGH PCD0-7; ELSE CONTROL IS EXTERNAL SHADING INDICATES INSTALLED FOR PC OPERATION. VCC vcc vcc gnd gnd Schematic (Continued) W Y PCRD1 5 PCRD1 6 TDO TDO I OUT QOUT I QSTB I QCLK TDO 4 3 2 1 15 14 13 12 U6 D0 D1 D2 D3 D4 D5 D6 D7 A B C G I QSTB. B I QCLK. B I OUT. B QOUT. B TDO. B 74ACT151 I QSTB I QCLK I OUT QOUT TDO 2 4 6 8 11 13 15 17 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 18 16 14 12 9 7 5 3 1 19 1G 2G 74F244 SEL0 SEL0 11 10 9 7 SEL1 SEL1 SEL2 SEL2 I QSTB. B I QCLK. B I OUT. B QOUT. B TDO. B 16 14 11 10 12 13 U3 SER I I I I I I I I O0 O1 O2 O3 O4 O5 O6 O7 QA 15 1 QB 2 SRCLK QC 3 SRCLR QD 4 QE 5 QF RCLK 6 QG G 7 QH 9 QH' 74F595 14 11 10 12 13 QA 15 1 QB 2 SRCLK QC 3 SRCLR QD 4 QE 5 RCLK QF 6 G QG 7 QH 9 QH' O8 O9 O10 O11 O12 O13 O14 O15 U2 SER I I I I I I I I 74F595 J P20 1 2 3 QOUT SELECT U1 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 I OUT I OUT I QCLK I QCLK I QSTB I QSTB SRRST# SRRST# SROE# SROE# I O[ 0. . 15] I O[ 0. . 15] HSP50016-EV QOUT 14 11 10 12 13 QO0 QO1 QO2 QO3 QO4 QO5 QO6 QO7 U5 SER QOUT JUMPER PINS 1 - 2 FOR I FOLLOWED BY Q (UP TO 32-BIT OUTPUT). NOTE THAT THIS IS LESS THAN THE 38 BITS THE DDC IS CAPABLE OF OUTPUTTING. 74F595 QA 15 1 QB 2 SRCLK QC 3 SRCLR QD 4 QE 5 QF RCLK 6 G QG 7 QH 9 QH' U9 OUT OSC 8 OSCOUT OSCOUT 14 11 10 12 13 U4 SER QO8 QO9 QO10 QO11 QO12 QO13 QO14 QO15 QA 15 1 QB 2 SRCLK QC 3 SRCLR QD 4 QE 5 QF RCLK 6 QG G 7 QH 9 QH' QO[ 0. . 15] QO[ 0. . 15] 74F595 JUMPER PINS 2 - 3 FOR SEPARATE I, Q 16-BIT OUTPUT ONLY. THE IQCLK RATE 0, BECAUSE THIS WILL DISABLE IQCLK WHEN SET TO ZERO. VCC vcc vcc gnd gnd Schematic (Continued) CKOUT VCC VCC CKOUT QO0 QO2 QO4 QO6 DI DI DI DI DI DI DI DI N9 N1 1 N1 3 N1 5 N0 N2 N4 N6 DI DI DI DI DI DI DI DI N1 N3 N5 N7 N8 N1 0 N1 2 N1 4 QO9 QO1 1 QO1 3 QO1 5 I I I I O0 O2 O4 O6 QO1 QO3 QO5 QO7 QO8 QO1 0 QO1 2 QO1 4 17 I O9 I O1 1 I O1 3 I O1 5 CKOUT I QSTB. B I QCLK. B I OUT. B QOUT. B CLKI N PCD1 PCD3 PCD5 PCD7 PCRD1 PCRD2 PCD0 PCD2 PCD4 PCD6 PCW R0 PCW R1 PCRD0 PCD1 PCD3 PCD5 PCD7 PCRD1 PCRD2 VCC vcc vcc gnd gnd I O1 I O3 I O5 I O7 I O8 I O1 0 I O1 2 I O1 4 TCK. E TMS. E TRST. E# TDI . E TDO. B CLKI N P2 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PCD0 PCD2 PCD4 PCD6 PCW R0 PCW R1 PCRD0 P2 B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P2 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1 B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P1 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I O[ 0 . . 1 5 ] I O[ 0 . . 1 5 ] DI N[ 0 . . 1 5 ] DI N[ 0 . . 1 5 ] PCD[ 0 . . 7 ] PCD[ 0 . . 7 ] PCRD[ 0 . . 2 ] TCK. E TMS. E TRST. E# TDI . E PCRD[ 0 . . 2 ] TCK. E TMS. E TRST. E# TDI . E PCW R0 PCW R1 HSP50016-EV QO[ 0 . . 1 5 ] QO[ 0 . . 1 5 ] TDO. B TDO. B PCW R0 PCW R1 I QSTB. B I QSTB. B I QCLK. B I QCLK. B I OUT. B I OUT. B QOUT. B QOUT. B Schematic 9 10 74ACT86 TCK. E TCK. E TDI . E TM E S. TRST. E# PCW R1 PCW R0 TDI . E TM E S. TRST. E# PCW R1 1 2 74ACT86 PCD0 PCD1 PCD2 PCD3 PCD4 PCD5 PCD6 PCD7 PCRD0 PCRD2 PCRD1 3 U15A PCW R0 74ACT86 8 13 11 U15C 12 U15D (Continued) VCC 1 R3 TCK. E PCW R1 TDI . E 2 3 4 5 6 7 8 9 10 TM E S. TRST. E# JP14 18 J1A 1 2 3 4 5 6 7 8 9 10 11 12 13 JP17 1 2 CONNECTER TO COMPUTER CLKIN CONNECTER TO COMPUTER PCD[ 0. . 7] PCRD[ 0. . 2] J1B 1 2 3 4 5 6 7 8 9 10 11 12 13 4 5 74ACT86 CKI N 6 U15B CLKOUT JP16 CKOUT 1 2 JP1 1 EXT CLK 2 DDCCLK DDCCLK RNGSEL VCC JP2 1 OSC CLK 2 RNGSEL JP3 1 PC CLK 2 ADDR 0 ADRNG0 JP6 1 2 J2 1 2 3 C22 22 uF ADDR 1 ADRNG1 JP7 1 2 J3 1 2 C1 . 01 uF C2 . 01 uF C3 . 01 uF ADDR 2 JP8 1 2 ADRNG2 C8 . 01 uF ADRNG3 C15 . 01 uF ADRNG4 C16 . 01 uF C17 . 01 uF C9 . 01 uF C10 . 01 uF ADDR 3 JP9 1 2 ADDR 4 JP10 1 2 VCC ADDR 5 JP11 1 2 ADRNG5 ADDR 6 JP12 1 2 ADRNG6 ADDR 7 JP13 1 2 ADRNG7 DDC CLK INV 1 2 SHADING INDICATES INSTALLED FOR PC OPERATION CKOUT CKOUT JP15 1 OUTCLK INV 2 PCD[ 0. . 7] PCRD[ 0. . 2] CLKI N CLKI N OSCOUT OSCOUT HSP50016-EV PCCLK PCCLK JP14, 15: INVERT CLOCKS JP16, 17: NORMALLY CONNECT PIN 1 TO PIN 2 ON BOTH HEADERS; TO SOURCE CLOCK FROM CKOUT, CONNECT JP6-1 TO JP7-1 AND JP6-2 TO JP7-2 C4 . 01 uF C5 . 01 uF C6 . 01 uF C7 . 01 uF JP1, 2, 3: SELECT EXTERNAL CLOCK, OSCILLATOR CLOCK OR PC CLOCK WITH JUMPER OR APPROPRIATE HEADER JP6-13: SELECT BOARD ADDRESS WITH JUMPER ACROSS ONE HEADER C11 . 01 uF C12 . 01 uF C13 . 01 uF C14 . 01 uF C18 . 01 uF C19 . 01 uF C20 . 01 uF C21 . 01 uF vcc vcc gnd gnd ADRNG[ 0. . 7] |
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