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Integrated Circuit Systems, Inc.
ICS9169C-40
System Clock Chip
General Description
The ICS9169C-40 is a Clock Synthesizer chip for Pentium or Cyrix CPU based motherboards using PCI. Features include eight CPU clocks and six PCI clocks. A Reference Output is available equal to the crystal frequency. The device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. The ICS9169C-40 clock output are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits and innovative circuit layout techniques enable the ICS9169C-40 to have lower EMI than other clock devices. The ICS9169C-40 accepts a 14.318MHz reference crystal or clock as its input and runs from a 3.3V supply.
Features
8 selectable CPU clocks up to 75MHz Six synchronous PCI clocks One Referance Clock at 14.318MHz Power-up stabilization time = 2ms on all CPU and PCI clocks, which meets Intel PentiumPro power-up Low CPU and PCI clock jitter <500ps Low skew output Improved output drivers are designed for low EMI Test Mode Optional common or mixed supply mode: (VDD = VDDL1 =VDDL2 = 3.3V) (VDD = 3.3V, VDDL1=VDDL2 = 2.5) (VDD = 3.3V, VDDL1 = 3.3V, VDDL2 = 2.5V) Space saving and low cost 34-pin SSOP package
Block Diagram
Pin Configuration
34-Pin SSOP
FS2 0 0 0 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU 50MHz 55MHz REF/2 75MHz 50MHz 55MHz 60MHz 66.6MHz PCI 33.3MHz 36.67MHz REF/4 37.5MHz 25MHz 27.6MHz 30MHz 33.3MHz
Functionality
3.3V10%, 0-70C Crystal (X1, X2) = 14.31818 MHz
Pentium is a trademark on Intel Corporation. 9169C-40RevA072897P
0 1 1 1 1
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS169C-40
Pin Descriptions
PIN NUMBER 1, 9 2 3, 5, 18, 26, 32 4 6, 7, 8, 10, 11, 12 13, 19, 20 14 15 16 17 21 22, 23, 24, 25, 27, 28, 29, 30 31 33 34 PIN NAME VDD REF GND N/C PCI (1:6) FS (0:2) PD# AGND N/C AVDD VDDL1 CPU (1:8) VDDL2 X2 X1 TYPE PWR OUT PWR OUT IN IN PWR PWR PWR OUT PWR OUT IN Power supply Buffered output reference. 3.3V Digital Ground. Not connected. Clock outputs - controlled by 3.3V V DD Frequency select inputs, these inputs have internal pull-ups. Input for tristate. If PD# = 0, then all outputs are tristated and the device is in shutdown mode (VCO's off, crystal oscillator is off and all logic is reset) When PD# = 1, the device is in normal operating mode. Has internal pull-up Analog Ground Not connected Analog Power Supply 3.3/2.5V Power Supply for CPU (1:4) Clock outputs. 3.3/2.5V Power Supply for CPU (5:8) Reference oscillator Reference oscillator DESCRIPTION
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ICS169C-40
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage1 Output High Voltage1 Output Low Voltage1 Output High Voltage1 Output Low Voltage1 Output High Voltage1 Supply Current SYMBOL VIL VIH IIL IIH VOL VOH VOL VOH VOL VOH IDD VIN=0V VIN=VDD IOL=12mA; for CPU, PCI IOH=-12mA; for CPU, PCI IOL=7.5mA; for Ref CLK IOH=-15mA; for Ref CLK IOL=7.5mA: CPU only; VDDL (1:2) = 2.5V IOH=-13mA; CPU only; VDDL (1:2) = 2.5V @66.6 MHz; all outputs unloaded PD#=0 All Logic Inputs to VDD Other All Logic Inputs to GND TEST CONDITIONS MIN 0.7VDD -50.0 -5.0 2.4 2.4 2.0 TYP 25.0 0.3 2.8 0.3 2.8 0.3 2.2 35 244 371 MAX 0.2VDD 50 5.0 0.4 0.4 0.4 65 500 700 UNITS V V A A V V V V V V mA A A
Power Down Current
IDD(PD)
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS169C-40
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
AC Characteristics PARAMETER Rise Time1 Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma1 Jitter, Absolute1 SYMBOL Tr1 Tf1 Tr2 Tf2 Dt Dt Tj1s1 Tjab1 Tj1s2 Tjab2 TEST CONDITIONS 15pF load, 0.4 to 2.0V; VDD=VDDL for All Outputs 15pF load, 2.0 to 0.4V; VDD=VDDL for All Outputs 15pF load, 0.4 to 2.0V; VDDL=2.5V & VDD = 2.3V; CPU 15pF load, 2.0 to 0.4V; VDDL=2.5V & VDD = 3.3V; CPU 15pF load CPU, PCI, REF @ VOUT=1.5V 15pF load; VDDL (1:2)=2.5V VTH=1.25V CPU & PCI Clocks; Load=15pF, VDD=VDDL CPU & PCI Clocks; Load=15pF, VDD=VDDL Ref; Load=15pF Ref Load=15pF VDD=VDDL; @ 60MHz Jitter, Cycle to Cycle (for CPU only) VDD=VDDL; @ 66MHz TCC VDD=VDDL; @ 75MHz VDD=3.3V; VDDL=2.5; for All Frequencies Input Frequency1 Logic Input Capacitance1 Crystal Oscillator Capacitance1 Power-on Time1 Frequency Settling Time1 Clock Skew Window1 Clock Skew1 Clock Skew1 Fi CIN CINX ton ts Tsk1 Tsk2 Tsk3 Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.6 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to < 1% settling CPU to CPU & PCI to PCI; Load=15pF; @1.5V CPU to PCI; Load=15pF; @1.5V; VDD=VDDL; CPU is early CPU to PCI; Load=15pF; (CPU is early) VDDL=2.5V, VTH=1.25V; VDD=3.3V, VTH=1.5V MIN 45 45 -220 -500 -400 -350 -250 400 12.0 -250 1.0 0.50 TYP 0.9 0.8 1.5 1.4 50 49 50 200 14.318 5 18 2.5 1.8 14.5 2.0 1.5 MAX 1.4 1.2 2.0 2.0 55 55 150 220 300 500 +400 350 250 400 16.0 4.5 2.0 250 4.0 3.0 UNITS ns ns ns ns % % ps ps ps ps ps ps ps ps MHz pF pF ms ms ps ns ns
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS169C-40
Technical Pin Function Descriptions
VDD/AVDD This is the power supply to the internal logic of the device as well as the following clock output buffers: PCI (1:6) REF This pin may be operated at any voltage between 3.0 and 5.5 volts. Clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. For the actual guaranteed high and low voltage levels of these clocks, please consult the AC parameter table in this data sheet. GND/AGND This is the power supply ground return pin for the chip. XIN This pin serves one of two functions. When the device is used with a crystal, XIN acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, XIN is the device input pin for that reference clock. This pin also implements an internal crystal loading capacitor that is connected to ground. See the data tables for the value of the capacitor. XOUT This pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, XOUT is an output signal that drives (or excites) the discrete crystal. This pin also implements an internal crystal loading capacitor that is connected to ground. See the data tables for the value of the capacitor. CPU (1:8) These pins are the clock outputs that drive processor and other CPU related circuitry that require clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these clocks is controlled by that which is applied to the VDDL (1:2) pin of the device. See the Functionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. PCI (1:6) Outputs for PCI bus with a skew 250pS. A high current rate of 60mA is available at 3.3V. These outputs are supplied from VDD. FS0, FS1, FS2 These pins control the frequency of the clocks at the CPU, PCI pins. See the Funtionality table at the beginning of this data sheet for a list of the specific frequencies, and the selection codes that are necessary to produce these frequencies. The device reads these pins at power-up. If a "1" value is desired for a specific frequency selection bit,a 10K ohm restor must be connected from the apporapriate FS pin to the VDD supply. If a "0" value is desired, then the 10K resistor must be connected to ground. REF This is a fixed frequency clock that runs at the same frequency as the input reference clock (typically 14.31818 MHz) is and typically used to drive Video and ISA BUS requirements. VDDL (1:2) This is the power supply to the CPU clock drivers. This pin may be operated "at any voltage" between 2.5 and 3.3 volts. Clocks from the buffers that it supplies will have a voltage swing form ground to this level. For the actual guaranteed high and low voltage levels of these clocks. Please consult the AC parameter table in this data sheet.
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ICS169C-40
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .097 .101 .104 .005 .009 .0115 .090 .092 .094 .014 .016 .019 .0091 .010 .0125 See Variations .292 .296 .299 .040 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AA MIN. .701
D NOM. .706
N MAX. .711 34
Ordering Information
ICS9169CF-40 ICS XXXX F - PPP
Example:
Dimensions are in Inches
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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