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Integrated Circuit Systems, Inc.
ICS9169-01
Frequency Generator and Integrated Buffers for Intel Pentium and Pentium ProTM P's
General Description
The ICS9169-01 generates all clocks required for high speed RISC or CISC microprocessor systems such as 486, Pentium/ Pentium ProTM, PowerPCTM, etc. Four different reference frequency multiplying factors are externally selectable with smooth frequency transitions. These multiplying factors can be customized for specific applications. A test mode is provided to drive all clocks directly. High drive BCLK outputs typically provide greater than 1V/ ns slew rate into 30pF loads. PCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 505% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.
Features
* Generates four processor, six bus, three 14.318 MHz and one 48 MHz clock for ISA bus, audio, super I/O and bus bridge devices Supports the Intel MARS chip set Synchronous clocks skew matched to 250ps window on PCLKs and 500ps window on BCLKs Test clock mode eases system design Selectable multiplying ratios Custom configurations available Output frequency ranges to 100 MHz (depending on option) 3.0V - 5.5 V supply range 28-pin SOIC and 28-pin SSOP (209-mil) packages
* * * * * * * *
Applications
* Ideal for high-speed RISC or CISC systems such as 486, Pentium, Pentium Pro, PowerPC, etc.
Block Diagram
PLL CLOCK GEN
48 MHz
X2 X1
XTAL OSC
REF(0:2) OEN
FS0 FS1
PLL CLOCK GEN
SYNC REG
PCLK(0:3) BCLK(0:5)
Pentium is a trademark of Intel Corporation PowerPC is a trademark of Motorola Corporation 9169-01RevE 08/28/98
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9169-01
Pin Configuration
Functionality
FS1 0 0 1 1 FS0 0 1 0 1 *VCO 230/33x X1 212/23x X1 176/21x X1 Test mode X1, REF (MHz) 14.31818 14.31818 14.31818 TCLK PCLK(0:3) (MHz) 50 (49.7) 66 (66.5) 60 (59.9) TCLK/2
*VCO range is limited from 60 - 200 MHz
PCLK(0:3) VCO/2 TCLK/2 BCLK(0:5) PCLK/2 TCLK/4 48 MHz 48 MHz TCLK/2
28 Pin SOIC 28 Pin SSOP Pin Descriptions
PIN NUMBER 2 3 4, 11, 23 17 1, 8, 26 14, 20 6, 7, 9, 10 13, 12 15, 16, 18 19, 21, 22 5 24 28, 27, 25 PIN NAME X1 X2 GND GND VDD VDD PCLK(0:3) FS(0:1) BCLK(0:5) OEN 48MHz REF(0:2) TYPE IN OUT PWR PWR PWR PWR OUT IN OUT IN OUT OUT DESCRIPTION XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12.16 MHz crystal, nominally 14.31818 XTAL output which includes XTAL load capacitance. Ground for logic, PCLK and fixed frequency output buffers. Ground for BCLK output buffers. Power for logic, PCLK and fixed frequency output buffers. Power for BCLK output buffers. Processor clock outputs which are a multiple of the input reference frequency as shown in the table above. Frequency multiplier select pins. See table above. These inputs have internal pull-up devices. Bus clock outputs are fixed at 1/2 the PCLK frequency. OEN tristates all outputs when low. This input has an internal pull-up device. Fixed 48 MHz clock (with 14.318 MHz input). REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz.
Note 1: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being supplied with 3.3 volts
2
ICS9169-01
Absolute Maximum Ratings
Supply Voltage.................................................................................................................................................................. 7.0 V Logic Inputs ............................................................................................................................ GND - 0.5 V to VDD + 0.5 V . Ambient Operating Temperature ........................................................................................................................... 0 to +70 C Storage Temperature ......................................................................................................................................... -65 to +150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stess specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Stresses a stess spec operation periods m
Electrical Characteristics at 3.3 V
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current1 Output High Current1 Output Low Current1 Output High Current1 Output Low Voltage1 Output High Voltage1 Output Low Voltage1 Output High Voltage1 Supply Current
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD
TEST CONDITIONS
MIN 0.7VDD
TYP -10.5 47.0 -66.0 38.0 -47.0 0.3 2.8 0.3 2.8 55
MAX 0.2VDD 5.0 -42.0 -30.0 0.4 0.4 110
UNITS V V
A A
VIN = 0 V VIN = VDD VOL = 0.8 V; for PCLKs & BCLKs VOL = 2.0 V; for PCLKs & BCLKs VOL=0.8V; for fixed CLKs VOL=2.0V; for fixed CLKs IOL = 15 mA; for PCLKs & BCLKs IOH = -30 mA; for PCLKs & BCLKs IOL=12.5mA; for fixed CLKs IOH = -20mA; for fixed CLKs @ 66.5 MHz; all outputs unloaded
-28.0 -5.0 30.0 25.0 2.4 2.4 -
mA mA mA mA V V V V mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
ICS9169-01
Electrical Characteristics at 3.3 V
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
AC Characteristics
PARAMETER Rise Time1 Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma1 Jitter, Absolute
1 1
SYMBOL Tr1 Tf1 Tr2 Tf2 Dt Tj1s1 Tjab1 Tj1s2 Tjab2 Fj CIN CINX ton ts Tsk1 Tsk2 Tsk3
TEST CONDITIONS 20pF load, 0.8 to 2.0V PCLK & BCLK 20pF load, 2.0 to 0.8V PCLK & BCLK 20pF load, 20% to 80% PCLK & BCLK 20pF load, 80% to 20% PCLK & BCLK 20pF load @ VOUT = 1.4 V PCLK & BCLK Clocks; Load=20pF, FOUT >25 MHz PCLK & BCLK Clocks; Load=20pF, FOUT >25 MHz Fixed CLK; Load=20pF Fixed CLK; Load=20pF
MIN 45 -250 -5 12.0
TYP 0.9 0.8 1.5 1.4 50 50 1 2 14.318 5 18 2.5 2.0 150 300 2.6
MAX 1.5 1.4 2.5 2.4 55 150 250 3 5 16.0 4.5 4.0 250 500 5
UNITS ns ns ns ns % ps ps % % MHz pF pF ms ms ps ps ns
Input Frequency Logic Input Capacitance1 Crystal Oscillator Capacitance1 Power-on Time1 Frequency Settling Time1 Clock Skew Window1 Clock Skew Window1 Clock Skew Window1
Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.5 MHz VDD supply ramp < 40 ms From 1st crossing of acquisition to < 1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V 1
-
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9169-01
Electrical Characteristics at 5.0 V
VDD = 4.5 - 5.5 V, TA = 0 - 70 oC unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current1 Output High Current1 Output Low Current1 Output High Current1 Output Low Voltage1 Output High Voltage1 Output Low Voltage1 Output High Voltage Supply Current1
1
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD
TEST CONDITIONS
MIN 2.4
TYP -15 62.0 -152 50.0 -110.0 0.25 4.0 0.2 4.7 80.0
MAX 0.8 5.0 -90.0 -65.0 0.4 0.4 160.0
UNITS V V
A A
VIN = 0 V VIN = VDD VOL = 0.8 V; for PCLKs & BCLKs VOL = 2.0 V; for PCLKs & BCLKs VOL = 0.8V; for fixed CLKs VOL=2.0V; for fixed CLKs IOL = 20 mA; for PCLKs & BCLKs IOH = -70 mA; for PCLKs & BCLKs IOL = 15mA; for fixed CLKs IOH=-50mA; for fixed CLKs @ 66.5 MHz; all outputs unloaded
-45 -5.0 36.0 30.0 2.4 2.4 -
mA mA mA mA V V V V mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
ICS9169-01
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1) All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf RC termination should be used at 50MHz and higher clock loads. 3) Optional crystal load capacitors are recommended.
Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic
Connections to VDD:
6
ICS9169-01
Electrical Characteristics at 5.0 V
VDD = 4.5 - 5.5 V, TA = 0 - 70 oC unless otherwise stated
AC Characteristics
PARAMETER Rise Time1 Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Duty Cycle1 Jitter, One Sigma1
SYMBOL Tr1 Tf1 Tr2 Tf2 Dt1 Dt2 Tj1s1
TEST CONDITIONS 20pF load, 0.8 to 2.0V PCLK & BCLK 20pF load, 2.0 to 0.8V PCLK & BCLK 20pF load, 20% to 80% PCLK & BCLK 20pF load, 80% to 20% PCLK & BCLK 20pF load @ VOUT = 50% of VDD 20pF load @ VOUT = 1.4 V PCLK & BCLK Clocks; Load=20pF; R=33 FOUT > 25 MHz PCLK & BCLK Clocks; Load=20pF; R=33 FOUT > 25 MHz Fixed CLK; Load=20pF R=33 Fixed CLK; Load=20pF R=33
MIN 45 50 -
TYP 0.55 0.52 1.2 1.1 50 55 50
MAX 0.95 0.90 2.1 2.0 55 60 150
UNITS ns ns ns ns % % ps
Jitter, Absolute1 Jitter, One Sigma1 Jitter, Absolute1 Input Frequency1 Logic Input Capacitance1 Crystal Oscillator Capacitance1 Power-on Time1
Tjab1 Tjis2 Tjab2 Fi CIN CINX ton
-250 -5 12.0
1 2 14.318 5 18 2.5
250 3 5 16.0 4.5
ps % % MHz pF pF ms
Logic input pins X1, X2 pins From V=1.6V to 1st crossing of 66.5 MHz VDD supply ramp < 40 ms From 1st crossing of acquisition to < 1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V
-
Frequency Settling Time1 Clock Skew Window1 Clock Skew Window1 Clock Skew Window1
ts Tsk1 Tsk2 Tsk3
1
2.0 150 300 2.6
4.0 250 500 5
ms ps ps ns
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
7
ICS9169-01
0.029 Typ.
L 0.008 0.018
5 Typ. 5 5 Typ.
0.047R 0.296 0.005 0.406 0.010 0.015 x 45 .0.328 0.010
Pin 1 0.020 0.041 0.003 0.010 0.092 0.005 0.101 0.010
LEAD COUNT DIMENSION L
0.050 Pitch typ. 0.008 0.006
28L 0.704
SOIC Package
Ordering Information
ICS9169M-01
Example:
ICS XXXX M-PPP
Pattern Number (2 or 3-digit number for parts with ROM code pattern) Package Type
M = SOIC
Device Type (consists of 3 or 4-digit numbers) Prefix
ICS, AV=Standard Device
8
ICS9169-01
1.14
D/2 2.36 DIA. PIN
E/2 1.14 H
TOP VIEW
D
BOTTOM VIEW
C A1
A
SEATING PLANE
A2 C E
e
B
SEE DETAIL A
SIDE VIEW
PARTING LINE
END VIEW
L
DETAIL A
SSOP Package
9
ICS9169-01
Package dimensions - SSOP package
SYMBOL COMMON DIMENSIONS NOTE MIN. A A A B C D E e H L N 0.301 0.022 See Variations 0 4 8 0.205 0.68 0.002 0.066 0.010 0.005 NOM. 0.73 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 0.311 0.037 5 6 0.212 MAX. 0.78 0.008 0.070 0.015 0.008 4 4 AA AB AC AD AE AF NOTE VARIATIONS MIN. 0.239 0.239 0.278 0.318 0.397 0.397 4 D NOM. 0.244 0.244 0.284 0.323 0.402 0.402 MAX. 0.249 0.249 0.289 0.328 0.407 0.407 14 16 20 24 28 30 6
Table dimensions in inches
Ordering Information
ICS9169F-01
Example:
ICS XXXX M-PPP
Pattern Number (2 or 3-digit number for parts with ROM code pattern) Package Type
F=SSOP
Device Type (consists of 3 or 4-digit numbers) Prefix
ICS, AV=Standard Device
10
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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