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INTEGRATED CIRCUITS
P87C51RA2/RB2/RC2/RD2 80C51 8-bit microcontroller family
8KB/16KB/32KB/64KB OTP, 512B/512B/512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
Product data
Supersedes data of 2002 Oct 28
2003 Jan 24
Philips Semiconductors
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
DESCRIPTION
The devices are Single-Chip 8-Bit Microcontrollers manufactured in an advanced CMOS process and are derivatives of the 80C51 microcontroller family. The instruction set is 100% compatible with the 80C51 instruction set. The devices support 6-clock/12-clock mode selection by programming an OTP bit (OX2) using parallel programming. In addition, an SFR bit (X2) in the clock control register (CKCON) also selects between 6-clock/12-clock mode. The devices also have four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P87C51RA2/RB2/RC2/RD2 make it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control.
* CMOS and TTL compatible * Two speed ranges at VCC = 5 V
- 0 to 30 MHz with 6-clock operation - 0 to 33 MHz with 12-clock operation
* Parallel programming with 87C51 compatible hardware interface
to programmer
* RAM expandable externally to 64 kbytes * Programmable Counter Array (PCA)
- PWM - Capture/compare
FEATURES
* 80C51 Central Processing Unit
- 8 kbytes OTP (87C51RA2) - 16 kbytes OTP (87C51RB2) - 32 kbytes OTP (87C51RC2) - 64 kbytes OTP (87C51RD2) - 512 byte RAM (87C51RA2/RB2/RC2) - 1 kbyte RAM (87C51RD2) - Boolean processor - Fully static operation - Low voltage (2.7 V to 5.5 V at 16 MHz) operation
* PLCC, LQFP, or DIP package * Extended temperature ranges * Dual Data Pointers * Security bits (3 bits) * Encryption array - 64 bytes * Seven interrupt sources * 4 interrupt priority levels * Four 8-bit I/O ports * Full-duplex enhanced UART
- Framing error detection - Automatic address recognition
* Three 16-bit timers/counters T0, T1 (standard 80C51) and
additional T2 (capture and compare)
* 12-clock operation with selectable 6-clock operation (via software
or via parallel programmer)
* Memory addressing capability
- Up to 64 kbytes ROM and 64 kbytes RAM
* Programmable clock-out pin * Asynchronous port reset * Low EMI (inhibit ALE, slew rate controlled outputs, and 6-clock
mode)
* Power control modes:
- Clock can be stopped and resumed - Idle mode - Power-down mode
* Wake-up from Power Down by an external interrupt
2003 Jan 24
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853-2391 29335
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
SELECTION TABLE
Type Memory
# of Timers
Timers
Serial Interfaces
Default Clock Rate ADC bits/ch. Interrupts (Ext.)/Levels Reset active low/high? Optional Clock Rate Max. Freq. at 6-clk / 12-clk (MHz) 30/33 30/33 30/33 30/33 Freq. Range at 3V (MHz) 0-16 0-16 0-16 0-16 Freq. Range at 5V (MHz) 0-30/33 0-30/33 0-30/33 0-30/33
P87C51RD2 P87C51RC2 P87C51RB2 P87C51RA2
1K 512B 512B 512B
- - - -
64K 32K 16K 8K
- - - -
4 4 4 4

- - - -
- - - -
- - - -
- - - -
32 32 32 32
7(2)/4 7(2)/4 7(2)/4 7(2)/4
Program Security
I/O Pins
UART
Flash
PWM
ROM
RAM
CAN
OTP
PCA
WD
I 2C
SPI
12-clk 12-clk 12-clk 12-clk
6-clk 6-clk 6-clk 6-clk
H H H H
ORDERING INFORMATION
PHILIPS (EXCEPT NORTH AMERICA) ( ) PART ORDER NUMBER PART MARKING P87C51RA2BA P87C51RA2FA P87C51RA2BBD P87C51RB2BA P87C51RB2FA P87C51RB2BBD P87C51RB2BN P87C51RB2FN P87C51RC2BA P87C51RC2FA P87C51RC2BBD P87C51RC2BN P87C51RC2FN P87C51RD2BA P87C51RD2FA P87C51RD2BBD P87C51RD2FBD P87C51RD2BN MEMORY OTP 8 KB 8 KB 8 KB 16 KB 16 KB 16 KB 16 KB 16 KB 32 KB 32 KB 32 KB 32 KB 32 KB 64 KB 64 KB 64 KB 64 KB 64 KB RAM 512B 512B 512B 512B 512B 512B 512B 512B 512B 512B 512B 512B 512B 1 KB 1 KB 1 KB 1 KB 1 KB TEMPERATURE RANGE (C) AND PACKAGE 0 to +70, PLCC -40 to +85, PLCC 0 to +70, LQFP 0 to +70, PLCC -40 to +85, PLCC 0 to +70, LQFP 0 to +70, DIP40 -40 to +85, DIP40 0 to +70, PLCC -40 to +85, PLCC 0 to +70, LQFP 0 to +70, DIP40 -40 to +85, DIP40 0 to +70, PLCC -40 to +85, PLCC 0 to +70, LQFP -40 to +85, LQFP 0 to +70, DIP40 VOLTAGE RANGE DWG #
2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V
SOT187-2 SOT187-2 SOT389-1 SOT187-2 SOT187-2 SOT389-1 SOT129-1 SOT129-1 SOT187-2 SOT187-2 SOT389-1 SOT129-1 SOT129-1 SOT187-2 SOT187-2 SOT389-1 SOT389-1 SOT129-1
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
BLOCK DIAGRAM 1
ACCELERATED 80C51 CPU (12-CLK MODE, 6-CLK MODE)
8K / 16K / 32K / 64 KBYTE CODE OTP FULL-DUPLEX ENHANCED UART 512 / 1024 BYTE DATA RAM TIMER 0 TIMER 1 PORT 3 CONFIGURABLE I/Os TIMER 2 PORT 2 CONFIGURABLE I/Os PROGRAMMABLE COUNTER ARRAY (PCA)
PORT 1 CONFIGURABLE I/Os
WATCHDOG TIMER PORT 0 CONFIGURABLE I/Os
CRYSTAL OR RESONATOR
OSCILLATOR
su01657
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
BLOCK DIAGRAM (CPU-ORIENTED)
P0.0-P0.7 P2.0-P2.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 2 LATCH
OTP MEMORY
8 B REGISTER STACK POINTER
ACC
TMP2
TMP1
PROGRAM ADDRESS REGISTER
ALU SFRs TIMERS PSW P.C.A. 8
BUFFER
PC INCREMENTER 16 PROGRAM COUNTER
PSEN ALE EAVPP RST PD TIMING AND CONTROL
INSTRUCTION REGISTER
DPTR'S MULTIPLE
PORT 1 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT 3 DRIVERS
P3.0-P3.7
SU01658
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
LOGIC SYMBOL
VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS
Plastic Leaded Chip Carrier
6 1 40
7
39
LCC
XTAL2 T2 T2EX PORT 1 RST EA/VPP PSEN SECONDARY FUNCTIONS ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD
17
29
18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
28 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC
PORT 3
PORT 2
ADDRESS BUS
SU01672
PINNING Plastic Dual In-Line Package
* NO INTERNAL CONNECTION
SU00023
Plastic Quad Flat Pack
T2/P1.0 1 T2EX/P1.1 2 ECI/P1.2 3 CEX0/P1.3 4 CEX1/P1.4 5 CEX2/P1.5 6 CEX3/P1.6 7 CEX4/P1.7 8 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 DUAL IN-LINE PACKAGE 40 VCC 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA/VPP 30 ALE/PROG 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 * NO INTERNAL CONNECTION 21 P2.0/A8 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 12 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7 22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 11 23 1 33 44 34
LQFP
SU01400
SU00021
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
PIN DESCRIPTIONS
MNEMONIC PDIP VSS VCC P0.0-0.7 20 40 39-32 PIN NUMBER PLCC 22 44 43-36 LQFP 16 38 37-30 I I I/O Ground: 0 V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions for P87C51RA2/RB2/RC2/RD2 Port 1 include: T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control ECI (P1.2): External Clock Input to the PCA CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the P87C51RA2/RB2/RC2/RD2, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal resistor to VSS permits a power-on reset using only an external capacitor to VCC. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted twice every machine cycle, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. TYPE NAME AND FUNCTION
P1.0-P1.7
1-8
2-9
40-44, 1-3
I/O
1 2 3 4 5 6 7 8 P2.0-P2.7 21-28
2 3 4 5 6 7 8 9 24-31
40 41 42 43 44 1 2 3 18-25
I/O I I I/O I/O I/O I/O I/O I/O
P3.0-P3.7
10-17
11, 13-19
5, 7-13
I/O
10 11 12 13 14 15 16 17 RST 9
11 13 14 15 16 17 18 19 10
5 7 8 9 10 11 12 13 4
I O I I I I O O I
ALE
30
33
27
O
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
MNEMONIC PDIP PSEN 29
PIN NUMBER PLCC 32 LQFP 26
TYPE O
NAME AND FUNCTION Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations. If EA is held high, the device executes from internal program memory. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. This pin also receives the programming supply voltage (VPP) during programming. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.
EA/VPP
31
35
29
I
XTAL1 XTAL2
19 18
21 20
15 14
I O
NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin (other than VPP) must not be higher than VCC + 0.5 V or less than VSS - 0.5 V.
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
SPECIAL FUNCTION REGISTERS
SYMBOL ACC* AUXR# AUXR1# B* CCAP0H# CCAP1H# CCAP2H# CCAP3H# CCAP4H# CCAP0L# CCAP1L# CCAP2L# CCAP3L# CCAP4L# CCAPM0# CCAPM1# CCAPM2# CCAPM3# CCAPM4# DESCRIPTION Accumulator Auxiliary Auxiliary 1 B register Module 0 Capture High Module 1 Capture High Module 2 Capture High Module 3 Capture High Module 4 Capture High Module 0 Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low Module 0 Mode Module 1 Mode Module 2 Mode Module 3 Mode Module 4 Mode DIRECT ADDRESS E0H 8EH A2H F0H FAH FBH FCH FDH FEH EAH EBH ECH EDH EEH DAH DBH DCH DDH DEH - - - - - DF CCON*# CH# CKCON# CL# CMOD# DPTR: DPH DPL IE* IP* IPH# PCA Counter Control PCA Counter High Clock control PCA Counter Low PCA Counter Mode Data Pointer (2 bytes) Data Pointer High Data Pointer Low Interrupt Enable 0 Interrupt Priority Interrupt Priority High D8H F9H 8FH E9H D9H 83H 82H AF A8H B8H B7H EA BF - B7 - 87 P0* P1* P2* P3* Port 0 Port 1 Port 2 Port 3 80H 90H A0H B0H AD7 97 CEX4 A7 AD15 B7 RD AE EC BE PPC B6 PPCH 86 AD6 96 CEX3 A6 AD14 B6 WR SMOD0 AD ET2 BD PT2 B5 PT2H 85 AD5 95 CEX2 A5 AD13 B5 T1 - AC ES BC PS B4 PSH 84 AD4 94 CEX1 A4 AD12 B4 T0 POF AB ET1 BB PT1 B3 PT1H 83 AD3 93 CEX0 A3 AD11 B3 INT1 GF1 AA EX1 BA PX1 B2 PX1H 82 AD2 92 ECI A2 AD10 B2 INT0 GF0 A9 ET0 B9 PT0 B1 PT0H 81 AD1 91 T2EX A1 AD9 B1 TxD PD A8 EX0 B8 PX0 B0 PX0H 80 AD0 90 T2 A0 AD8 B0 RxD IDL FFH 00xxx000B FFH FFH FFH x0000000B x0000000B 00H CF - CIDL ECOM ECOM ECOM ECOM ECOM DE CR - WDTE CAPP CAPP CAPP CAPP CAPP DD - - - CAPN CAPN CAPN CAPN CAPN DC CCF4 - - MAT MAT MAT MAT MAT DB CCF3 - - TOG TOG TOG TOG TOG DA CCF2 - CPS1 PWM PWM PWM PWM PWM D9 CCF1 - CPS0 ECCF ECCF ECCF ECCF ECCF D8 CCF0 X2 ECF 00x00000B 00H x0000000B 00H 00xxx000B 00H 00H BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB E7 - - F7 E6 - - F6 E5 - - F5 E4 - - F4 E3 - GF2 F3 E2 - 0 F2 E1
EXTRAM
LSB E0 AO DPS F0
RESET VALUE 00H xxxxxx00B xxxxxxx0B 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB x0000000B x0000000B x0000000B x0000000B x0000000B
- F1
PCON#1 Power Control 87H SMOD1 * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. 1. Reset value depends on reset source.
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
SPECIAL FUNCTION REGISTERS (Continued)
SYMBOL DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB D7 PSW* RCAP2H# RCAP2L# SADDR# SADEN# SBUF SCON* SP TCON* Program Status Word Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control D0H CBH CAH A9H B9H 99H 9F 98H 81H 88H
SM0/FE
LSB D6 AC D5 F0 D4 RS1 D3 RS0 D2 OV D1 F1 D0 P
RESET VALUE
CY
00000000B 00H 00H 00H 00H xxxxxxxxB
9E SM1 8E TR1 CE EXF2 -
9D SM2 8D TF0 CD RCLK -
9C REN 8C TR0 CC TCLK -
9B TB8 8B IE1 CB EXEN2 -
9A RB8 8A IT1 CA TR2 -
99 TI 89 IE0 C9 C/T2 T2OE
98 RI 88 IT0 C8 CP/RL2 DCEN 00H xxxxxx00B 00H 00H 00H 00H 00H 00H 00H 00H 07H
8F TF1 CF T2CON* T2MOD# TH0 TH1 TH2# TL0 TL1 TL2# Timer 2 Control Timer 2 Mode Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 C8H C9H 8CH 8DH CDH 8AH 8BH CCH TF2 -
TMOD Timer Mode 89H GATE WDTRST Watchdog Timer Reset A6H * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits.
C/T
M1
M0
GATE
C/T
M1
M0
00H
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. Minimum and maximum high and low times specified in the data sheet must be observed.
This device is configured at the factory to operate using 12 clock periods per machine cycle, referred to in this datasheet as "12-clock mode". It may be optionally configured on commercially available parallel programming equipment or via software to operate at 6 clocks per machine cycle, referred to in this datasheet as "6-clock mode". (This yields performance equivalent to twice that of standard 80C51 family devices). Also see next page.
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
CLOCK CONTROL REGISTER (CKCON)
This device allows control of the 6-clock/12-clock mode by means of both an SFR bit (X2) and an OTP bit. The OTP clock control bit
OX2, when programmed (6-clock mode), supersedes the X2 bit (CKCON.0). The CKCON register is shown below in Figure 1.
CKCON
Address = 8Fh Not Bit Addressable
Reset Value = x0000000B
7 - BIT CKCON.7 CKCON.6 CKCON.5 CKCON.4 CKCON.3 CKCON.2 CKCON.1 CKCON.0 SYMBOL -
6 -
5 -
4 -
3 -
2 -
1 -
0 X2
X2
FUNCTION Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. CPU clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle
SU01689
Figure 1. Clock control (CKCON) register Also please note that the clock divider applies to the serial port for modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3 (variable baud rate modes) use either Timer 1 or Timer 2. Below is the truth table for the CPU clock mode.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (12 oscillator periods in 6-clock mode, or 24 oscillator periods in 12-clock mode), while the oscillator is running. To ensure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 (min.) is applied to RST. The value on the EA pin is latched when RST is deasserted and has no further effect.
Table 1.
OX2 clock mode bit (can only be set by parallel programmer) erased erased programmed X2 bit (CKCON.0) 0 1 X CPU clock mode
12-clock mode (default) 6-clock mode 6-clock mode
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
LOW POWER MODES Stop Clock Mode
The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested.
Design Consideration
When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
ONCETM Mode
The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated. Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency in 12-clock mode (122 Hz to 8 MHz in 6-clock mode). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: n
n=
Oscillator Frequency (65536 * RCAP2H, RCAP2L)
2 in 6-clock mode 4 in 12-clock mode
POWER-ON FLAG
The Power-On Flag (POF) is set by on-chip circuitry when the VCC level on the P87C51RA2/RB2/RC2/RD2 rises from 0 to 5 V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3 V for the POF to remain unaffected by the VCC level. Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.
Table 2. External Pin Status During Idle and Power-Down Mode
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
2003 Jan 24
12
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
TIMER 0 AND TIMER 1 OPERATION Timer 0 and Timer 1
The "Timer" or "Counter" function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text. Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 3 shows the Mode 0 operation. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The counted input is enabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in the Special Function Register TCON (Figure 4). The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers. Mode 0 operation is the same for Timer 0 as for Timer 1. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). TMOD Address = 89H Not Bit Addressable 7 GATE 6 C/T 5 M1 4 M0
Mode 1 Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits. Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 5. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which is preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 as for Timer 1. Mode 3 Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 6. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, and TF0 as well as pin INT0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the "Timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer on the counter. With Timer 0 in Mode 3, an 80C51 can look like it has three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.
Reset Value = 00H
3 GATE
2 C/T
1 M1
0 M0
TIMER 1 BIT TMOD.3/ TMOD.7 TMOD.2/ TMOD.6 SYMBOL GATE C/T M1 0 0 1 1 1 M0 0 1 0 1 1
TIMER 0
FUNCTION Gating control when set. Timer/Counter "n" is enabled only while "INTn" pin is high and "TRn" control pin is set. when cleared Timer "n" is enabled whenever "TRn" control bit is set. Timer or Counter Selector cleared for Timer operation (input from internal system clock.) Set for Counter operation (input from "Tn" input pin). OPERATING 8048 Timer: "TLn" serves as 5-bit prescaler. 16-bit Timer/Counter: "THn" and "TLn" are cascaded; there is no prescaler. 8-bit auto-reload Timer/Counter: "THn" holds a value which is to be reloaded into "TLn" each time it overflows. (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. (Timer 1) Timer/Counter 1 stopped.
SU01580
Figure 2. Timer/Counter 0/1 Mode Control (TMOD) Register
2003 Jan 24
13
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
OSC
/ d* C/T = 0 C/T = 1 Tn Pin TRn Control TLn (5 Bits) THn (8 Bits)
TFn
Interrupt
Timer n Gate bit INTn Pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode.
SU01618
Figure 3. Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter
TCON
Address = 88H Bit Addressable
Reset Value = 00H
7 TF1 BIT TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 SYMBOL TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
6 TR1
5 TF0
4 TR0
3 IE1
2 IT1
1 IE0
0 IT0
FUNCTION Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
SU01516
Figure 4. Timer/Counter 0/1 Control (TCON) Register
2003 Jan 24
14
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
OSC
/ d* C/T = 0 TLn (8 Bits) C/T = 1 Tn Pin Control TFn Interrupt
TRn Timer n Gate bit THn (8 Bits) INTn Pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode.
Reload
SU01619
Figure 5. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload
OSC
/ d* C/T = 0 TL0 (8 Bits) C/T = 1 T0 Pin Control TF0 Interrupt
TR0 Timer 0 Gate bit INT0 Pin
OSC
/ d* Control TR1
TH0 (8 Bits)
TF1
Interrupt
*d = 6 in 6-clock mode; d = 12 in 12-clock mode.
SU01620
Figure 6. Timer/Counter 0 Mode 3: Two 8-Bit Counters
2003 Jan 24
15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
TIMER 2 OPERATION Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON (see Figure 1). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 3.
Counter Enable) which is located in the T2MOD register (see Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 4 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.
Capture Mode
In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/6 pulses (osc/12 in 12-clock mode).).
Auto-Reload Mode (Up or Down Counter)
In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2 in T2CON]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down
(MSB) TF2 Symbol TF2 EXF2 Position T2CON.7 T2CON.6 EXF2 RCLK TCLK EXEN2 TR2 C/T2
(LSB) CP/RL2
Name and Significance Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select. (Timer 2) 0 = Internal timer (OSC/6 in 6-clock mode or OSC/12 in 12-clock mode) 1 = External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. SU01251 Figure 1. Timer/Counter 2 (T2CON) Control Register
RCLK TCLK EXEN2
T2CON.5 T2CON.4 T2CON.3
TR2 C/T2
T2CON.2 T2CON.1
CP/RL2
T2CON.0
2003 Jan 24
16
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Table 3. Timer 2 Operating Modes
RCLK + TCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE
OSC
/ n*
C/T2 = 0 TL2 (8 BITS) C/T2 = 1 TH2 (8 BITS) TF2
T2 Pin
Control
TR2 Transition Detector
Capture Timer 2 Interrupt RCAP2L RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU01252
* n = 6 in 6-clock mode, or 12 in 12-clock mode. Figure 2. Timer 2 in Capture Mode
T2MOD
Address = 0C9H Not Bit Addressable -- Bit 7 -- 6 -- 5 -- 4 -- 3 -- 2 T2OE 1
Reset Value = XXXX XX00B
DCEN 0
Symbol -- T2OE DCEN *
Function Not implemented, reserved for future use.* Timer 2 Output Enable bit. Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 3. Timer 2 Mode (T2MOD) Control Register
SU00729
2003 Jan 24
17
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
OSC
/ n*
C/T2 = 0 TL2 (8 BITS) C/T2 = 1 TH2 (8 BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION DETECTOR
RCAP2L
RCAP2H TF2 TIMER 2 INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU01253
* n = 6 in 6-clock mode, or 12 in 12-clock mode. Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
(DOWN COUNTING RELOAD VALUE) FFH FFH
TOGGLE EXF2
OSC
/ n*
C/T2 = 0 OVERFLOW TL2 TH2 TF2 INTERRUPT
T2 PIN
C/T2 = 1 CONTROL TR2 COUNT DIRECTION 1 = UP 0 = DOWN RCAP2L RCAP2H T2EX PIN
(UP COUNTING RELOAD VALUE)
* n = 6 in 6-clock mode, or 12 in 12-clock mode. Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
SU01254
2003 Jan 24
18
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Timer 1 Overflow
n = 1 in 6-clock mode n = 2 in 12-clock mode
/2
"0" C/T2 = 0 TL2 (8-bits) C/T2 = 1 TH2 (8-bits) "1" "0" RCLK "1" SMOD
OSC
/n
T2 Pin
Control "1" Reload "0"
/ 16
RX Clock
TR2
TCLK
Transition Detector
RCAP2L
RCAP2H
/ 16
TX Clock
T2EX Pin
EXF2
Timer 2 Interrupt
Control EXEN2 Note availability of additional external interrupt.
SU01629
Figure 6. Timer 2 in Baud Rate Generator Mode
Table 4.
Timer 2 Generated Commonly Used Baud Rates
Timer 2 Osc Freq RCAP2H 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 6 MHz 6 MHz FF FF FF FF FE FB F2 FD F9 RCAP2L FF D9 B2 64 C8 1E AF 8F 57 6-clock mode 750 k 19.2 k 9.6 k 4.8 k 2.4 k 600 220 600 220
The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate given below: Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate 16 The timer can be configured for either "timer" or "counter" operation. In many applications, it is configured for "timer" operation (C/T2=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e., the oscillator frequency in 6-clock mode, 1/12 the oscillator frequency in 12-clock mode). As a baud rate generator, it increments at the oscillator frequency in 6-clock mode (OSC/2 in 12-clock mode). Thus the baud rate formula is as follows:
1/ 6
Baud Rate 12-clock mode 375 k 9.6 k 4.8 k 2.4 k 1.2 k 300 110 300 110
Modes 1 and 3 Baud Rates = Oscillator Frequency [ n * [65536 * (RCAP2H, RCAP2L)]]
*n= 16 in 6-clock mode 32 in 12-clock mode
Baud Rate Generator Mode
Bits TCLK and/or RCLK in T2CON (Table 4) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates - one generated by Timer 1, the other by Timer 2. Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode,in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode shown in Figure 6, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.
2003 Jan 24
19
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 4 shows commonly used baud rates and how they can be obtained from Timer 2.
If Timer 2 is being clocked internally, the baud rate is: Baud Rate + f OSC [65536 * (RCAP2H, RCAP2L)]]
16 in 6-clock mode 32 in 12-clock mode
[ n*
*n=
Where fOSC= Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: RCAP2H, RCAP2L + 65536 * f OSC Baud Rate
Summary of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2 (P1.0) the baud rate is: Baud Rate + Timer 2 Overflow Rate 16
n*
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 5 for set-up of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a counter.
Table 5.
Timer 2 as a Timer
T2CON MODE INTERNAL CONTROL (Note 1) 00H 01H 34H 24H 14H EXTERNAL CONTROL (Note 2) 08H 09H 36H 26H 16H
16-bit Auto-Reload 16-bit Capture Baud rate generator receive and transmit same baud rate Receive only Transmit only
Table 6.
Timer 2 as a Counter
TMOD MODE INTERNAL CONTROL (Note 1) 02H 03H EXTERNAL CONTROL (Note 2) 0AH 0BH
16-bit Auto-Reload
NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode.
2003 Jan 24
20
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
FULL-DUPLEX ENHANCED UART Standard UART operation
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency in 12-clock mode or 1/6 the oscillator frequency in 6-clock mode. 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in 12-clock mode or 1/16 or 1/32 the oscillator frequency in 6-clock mode. 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable.
The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. Serial Port Control Register The serial port control and status register is the Special Function Register SCON, shown in Figure 7. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Baud Rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator Frequency / 12 (12-clock mode) or / 6 (6-clock mode). The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. In 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively. Mode 2 Baud Rate = 2 SMOD n Where: n = 64 in 12-clock mode, 32 in 6-clock mode The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator (T2CON.RCLK = 0, T2CON.TCLK = 0), the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Mode 1, 3 Baud Rate = 2 SMOD n Where: n = 32 in 12-clock mode, 16 in 6-clock mode The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either "timer" or "counter" operation, and in any of its 3 running modes. In the most typical applications, it is configured for "timer" operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1, 3 Baud Rate = 2 SMOD n Where: n = 32 in 12-clock mode, 16 in 6-clock mode One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Figure 8 lists various commonly used baud rates and how they can be obtained from Timer 1. Oscillator Frequency 12 [256-(TH1)] (Timer 1 Overflow Rate) (Oscillator Frequency)
Mode 1:
Mode 2:
Mode 3:
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming.
2003 Jan 24
21
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
SCON
Address = 98H Bit Addressable
Reset Value = 00H 7 SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Where SM0, SM1 specify the serial port mode, as follows: SM0 0 0 1 1 SM2 SM1 0 1 0 1 Mode 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate fOSC/12 (12-clock mode) or fOSC/6 (6-clock mode) variable fOSC/64 or fOSC/32 (12-clock mode) or fOSC/32 or fOSC/16 (6-clock mode) variable
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
SU01626
REN TB8 RB8 TI RI
Figure 7. Serial Port Control (SCON) Register Baud Rate Mode Mode 0 Max Mode 2 Max Mode 1, 3 Max Mode 1, 3 12-clock mode 1.67 MHz 625 k 104.2 k 19.2 k 9.6 k 4.8 k 2.4 k 1.2 k 137.5 110 110 6-clock mode 3.34 MHz 1250 k 208.4 k 38.4 k 19.2 k 9.6 k 4.8 k 2.4 k 275 220 220 fOSC 20 MHz 20 MHz 20 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.986 MHz 6 MHz 12 MHz SMOD C/T X 1 1 1 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 Mode X X 2 2 2 2 2 2 2 2 1 Reload Value X X FFH FDH FDH FAH F4H E8H 1DH 72H FEEBH Timer 1
Figure 8. Timer 1 Generated Commonly Used Baud Rates More About Mode 0 Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed a 1/12 the oscillator frequency (12-clock mode) or 1/6 the oscillator frequency (6-clock mode). Figure 9 shows a simplified functional diagram of the serial port in Mode 0, and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "write to SBUF" and activation of SEND. SEND enables the output of the shift register to the alternate output function line of P3.0 and also enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At 2003 Jan 24 22 S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are shifted to the right one position. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control block to do one last shift and then deactivate SEND and set T1. Both of these actions occur at S1P1 of the 10th machine cycle after "write to SBUF." Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared as RI is set. More About Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the 80C51 the baud rate is determined by the Timer 1 or Timer 2 overflow rate. Figure 10 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal.) The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after "write to SBUF." Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. R1 = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time,
whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. More About Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9the data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 (12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock mode) the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1 or Timer 2. Figures 11 and 12 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "write to SUBF." Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input.
2003 Jan 24
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
80C51 Internal Bus
Write to SBUF D
S CL
Q
SBUF
RxD P3.0 Alt Output Function
Zero Detector
Start TX Control S6 Serial Port Interrupt RX Clock R1 RX Control REN RI Start LSB Input Shift Register 1 1 1 1 1 1 1 TX Clock T1
Shift
Send
Receive Shift 0 MSB
Shift Clock
TxD P3.1 Alt Output Function
Shift Load SBUF
RxD P3.0 Alt Input Function
LSB
SBUF
MSB
Read SBUF
80C51 Internal Bus
S4 . . ALE
S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1
Write to SBUF Send Shift S6P2 Transmit D0 D1 D2 D3 D4 D5 D6 D7
RxD (Data Out) TxD (Shift Clock) TI
S3P1
S6P1
Write to SCON (Clear RI) RI Receive Shift RxD (Data In) D0 S5P2 TxD (Shift Clock) D1 D2 D3 D4 D5 D6 D7 Receive
SU00539
Figure 9. Serial Port Mode 0
2003 Jan 24
24
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Timer 1 Overflow TB8
80C51 Internal Bus
/2 SMOD = 0 SMOD = 1
Write to SBUF D CL
S
Q
SBUF TxD
Zero Detector
Start TX Control / 16 Serial Port Interrupt / 16 TX Clock T1
Shift
Data
Send
Sample 1-to-0 Transition Detector Start
RX Clock RI RX Control
Load SBUF Shift 1FFH
Bit Detector Input Shift Register (9 Bits) Shift RxD Load SBUF
SBUF
Read SBUF
80C51 Internal Bus TX Clock Write to SBUF Send Data Shift TxD TI / 16 Reset RX Clock RxD Bit Detector Sample Times Shift RI Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Receive Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit S1P1 Transmit
SU00540
Figure 10. Serial Port Mode 1
2003 Jan 24
25
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
80C51 Internal Bus TB8
Write to SBUF D CL Phase 2 Clock (1/2 fOSC)
S
Q
SBUF
TxD
Zero Detector
Mode 2 Start / 16 Serial Port Interrupt SMOD = 0 (SMOD is PCON.7) Sample 1-to-0 Transition Detector Start / 16
Stop Bit Gen. TX Control T1
Shift
Data
SMOD = 1 /2
TX Clock
Send
RX Clock
R1
Load SBUF Shift 1FFH
RX Control
Bit Detector Input Shift Register (9 Bits) Shift RxD Load SBUF
SBUF
Read SBUF
80C51 Internal Bus TX Clock Write to SBUF Send Data Shift TxD TI Stop Bit Gen. / 16 Reset RX Clock RxD Bit Detector Sample Times Shift RI Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Receive Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit S1P1 Transmit
SU00541
Figure 11. Serial Port Mode 2 2003 Jan 24 26
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Timer 1 Overflow TB8
80C51 Internal Bus
/2
SMOD = 0 SMOD = 1
Write to SBUF D CL
S
Q
SBUF TxD
Zero Detector
Start TX Control
Shift
Data
/ 16
Serial Port Interrupt
TX Clock
T1
Send
/ 16
R1 Load SBUF Shift 1FFH
Sample 1-to-0 Transition Detector Start
RX Clock
RX Control
Bit Detector Input Shift Register (9 Bits) Shift RxD Load SBUF
SBUF
Read SBUF
80C51 Internal Bus TX Clock Write to SBUF Send Data Shift TxD TI Stop Bit Gen. RX Clock RxD Bit Detector Sample Times Shift RI / 16 Reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit S1P1 Transmit
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
RB8
Stop Bit Receive
SU00542
Figure 12. Serial Port Mode 3 2003 Jan 24 27
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Enhanced Features
The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 13. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 14. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0
Slave 1
SADDR = SADEN = Given =
1100 0000 1111 1110 1100 000X
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX
Slave 1
Slave 2
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.
2003 Jan 24
28
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
D0
D1
D2
D3
D4
D5
D6
D7
D8
START BIT
DATA BYTE
ONLY IN MODE 2, 3
STOP BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL
SM0 / FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98H)
SMOD1
SMOD0
-
POF
LVF
GF0
GF1
IDL
PCON (87H)
0 : SCON.7 = SM0 1 : SCON.7 = FE
SU00044
Figure 13. UART Framing Error Detection
D0
D1
D2
D3
D4
D5
D6
D7
D8
SM0 1 1
SM1 1 0
SM2 1
REN 1
TB8 X
RB8
TI
RI
SCON (98H)
RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" - WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES - WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 14. UART Multiprocessor Communication, Automatic Address Recognition
2003 Jan 24
29
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Interrupt Priority Structure
The P87C51RA2/RB2/RC2/RD2 has a 7 source four-level interrupt structure (see Table 7). There are 3 SFRs associated with the four-level interrupt. They are the IE, IP, and IPH. (See Figures 15, 16, and 17.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible. The IPH is located at SFR address B7H. The structure of the IPH register and a description of its bits is shown in Figure 17. The function of the IPH SFR, when combined with the IP SFR, determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS IPH.x 0 0 1 1 IP.x 0 1 0 1 INTERRUPT PRIORITY LEVEL Level 0 (lowest priority) Level 1 Level 2 Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels rather than two as on the 80C51. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed.
Table 7.
Interrupt Table
POLLING PRIORITY 1 2 3 4 5 6 7 REQUEST BITS IE0 TP0 IE1 TF1 CF, CCFn n = 0-4 RI, TI TF2, EXF2 HARDWARE CLEAR? N (L)1 Y N (L) Y (T) Y N N N Y (T)2 VECTOR ADDRESS 03H 0BH 13H 1BH 33H 23H 2BH X0 T0 X1 T1 PCA SP T2
SOURCE
NOTES: 1. L = Level activated 2. T = Transition activated 7 IE (0A8H) EA 6 EC 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it. BIT IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 SYMBOL EA EC ET2 ES ET1 EX1 ET0 EX0 FUNCTION Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. PCA interrupt enable bit Timer 2 interrupt enable bit. Serial Port interrupt enable bit. Timer 1 interrupt enable bit. External interrupt 1 enable bit. Timer 0 interrupt enable bit. External interrupt 0 enable bit.
SU01290
Figure 15. IE Registers
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
7 IP (0B8H) -
6 PPC
5 PT2
4 PS
3 PT1
2 PX1
1 PT0
0 PX0
Priority Bit = 1 assigns high priority Priority Bit = 0 assigns low priority BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL - PPC PT2 PS PT1 PX1 PT0 PX0 FUNCTION - PCA interrupt priority bit Timer 2 interrupt priority bit. Serial Port interrupt priority bit. Timer 1 interrupt priority bit. External interrupt 1 priority bit. Timer 0 interrupt priority bit. External interrupt 0 priority bit. Figure 16. IP Registers
SU01291
7 IPH (B7H) -
6 PPCH
5 PT2H
4 PSH
3 PT1H
2 PX1H
1 PT0H
0 PX0H
Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IPH.7 IPH.6 IPH.5 IPH.4 IPH.3 IPH.2 IPH.1 IPH.0 SYMBOL - PPCH PT2H PSH PT1H PX1H PT0H PX0H FUNCTION - PCA interrupt priority bit Timer 2 interrupt priority bit high. Serial Port interrupt priority bit high. Timer 1 interrupt priority bit high. External interrupt 1 priority bit high. Timer 0 interrupt priority bit high. External interrupt 0 priority bit high. Figure 17. IPH Registers
SU01292
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the ALE output unless the CPU needs to perform an off-chip memory access.
The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit.
Reduced EMI Mode
AUXR (8EH)
7 - 6 - 5 - 4 - 3 - 2 - 1 EXTRAM 0 AO DPS BIT0 AUXR1
DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY
AUXR.1 AUXR.0
EXTRAM AO
See more detailed description in Figure 32.
Dual DPTR
The dual DPTR structure (see Figure 18) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them. Figure 18.
SU00745A
* New Register Name: AUXR1# * SFR Address: A2H * Reset Value: xxxxxxx0B
AUXR1 (A2H)
7 - 6 - 5 - 4 -
DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR MOV DPTR, #data16 Increments the data pointer by 1 Loads the DPTR with a 16-bit constant Move code byte relative to DPTR to ACC Move external RAM (16-bit address) to ACC Move ACC to external RAM (16-bit address) Jump indirect relative to DPTR
3 GF2
2 0
1 -
0 DPS
MOV A, @ A+DPTR MOVX A, @ DPTR MOVX @ DPTR , A JMP @ A + DPTR
Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPTR0 DPTR1 DPS 0 1
The DPS bit status should be saved by software when switching between DPTR0 and DPTR1.
The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See Application Note AN458 for more details.
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Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Programmable Counter Array (PCA)
The Programmable Counter Array available on the P87C51RA2/RB2/RC2/RD2 is a special 16-bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3 (CEX0), module 1 to P1.4 (CEX1), etc. The basic PCA configuration is shown in Figure 19. The PCA timer is a common time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see Figure 22): CPS1 CPS0 PCA Timer Count Source 0 0 1/6 oscillator frequency (6-clock mode); 1/12 oscillator frequency (12-clock mode) 0 1 1/2 oscillator frequency (6-clock mode); 1/4 oscillator frequency (12-clock mode) 1 0 Timer 0 overflow 1 1 External Input at ECI pin In the CMOD SFR are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. These functions are shown in Figure 20. The watchdog timer function is implemented in module 4 (see Figure 29). The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (refer to Figure 23). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when
the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. The PCA interrupt system shown in Figure 21. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Figure 24). The registers contain the bits that control the mode that each module will operate in. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Figure 25 shows the CCAPMn settings for the various PCA functions. There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output.
16 BITS MODULE 0 P1.3/CEX0
MODULE 1 16 BITS PCA TIMER/COUNTER TIME BASE FOR PCA MODULES MODULE 3 MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED OUTPUT 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY) MODULE 2
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
MODULE 4
P1.7/CEX4
SU00032
Figure 19. Programmable Counter Array (PCA)
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
OSC/6 (6 CLOCK MODE) OR OSC/12 (12 CLOCK MODE) OSC/2 (6 CLOCK MODE) OR OSC/4 (12 CLOCK MODE)
TO PCA MODULES
OVERFLOW CH CL INTERRUPT
TIMER 0 OVERFLOW
16-BIT UP COUNTER
EXTERNAL INPUT (P1.2/ECI) 00 01 10 11
DECODE
IDLE CIDL WDTE -- -- -- CPS1 CPS0 ECF CMOD (C1H)
CF
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (C0H)
SU01256
Figure 20. PCA Timer/Counter
CF PCA TIMER/COUNTER
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (C0H)
MODULE 0 IE.6 EC MODULE 1 IE.7 EA TO INTERRUPT PRIORITY DECODER
MODULE 2
MODULE 3
MODULE 4
CMOD.0
ECF
CCAPMn.0
ECCFn
SU01097
Figure 21. PCA Interrupt System
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
CMOD Address = D9H
Reset Value = 00XX X000B
CIDL Bit: Symbol CIDL WDTE - CPS1 CPS0 Function 7
WDTE 6
- 5
- 4
- 3
CPS1 2
CPS0 1
ECF 0
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. Not implemented, reserved for future use.* PCA Count Pulse Select bit 1. PCA Count Pulse Select bit 0. CPS1 CPS0 Selected PCA Input** 0 0 1 1 0 1 0 1 0 1 2 3 Internal clock, fOSC/6 in 6-clock mode (fOSC/12 in 12-clock mode) Internal clock, fOSC/2 in 6-clock mode (fOSC/4 in 12-clock mode) Timer 0 overflow External clock at ECI/P1.2 pin (max. rate = fOSC/4 in 6-clock mode, fOCS/8 in 12-clock mode)
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF.
NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. ** fOSC = oscillator frequency
SU01318
Figure 22. CMOD: PCA Counter Mode Register
CCON Address = D8H Bit Addressable CF Bit: Symbol CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Function 7 CR 6 - 5 CCF4 4 CCF3 3 CCF2 2 CCF1 1 CCF0 0
Reset Value = 00X0 0000B
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. Not implemented, reserved for future use*. PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01319
Figure 23. CCON: PCA Counter Control Register
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
CCAPMn Address
CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4
0DAH 0DBH 0DCH 0DDH 0DEH
Reset Value = X000 0000B
Not Bit Addressable - Bit: Symbol - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Function Not implemented, reserved for future use*. Enable Comparator. ECOMn = 1 enables the comparator function. Capture Positive, CAPPn = 1 enables positive edge capture. Capture Negative, CAPNn = 1 enables negative edge capture. Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. 7 ECOMn 6 CAPPn 5 CAPNn 4 MATn 3 TOGn 2 PWMn 1 ECCFn 0
NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01320
Figure 24. CCAPMn: PCA Modules Compare/Capture Registers - X X X X X X X X ECOMn 0 X X X 1 1 1 1 CAPPn 0 1 0 1 0 0 0 0 CAPNn 0 0 1 1 0 0 0 0 MATn 0 0 0 0 1 1 0 1 TOGn 0 0 0 0 0 1 0 X PWMn 0 0 0 0 0 0 1 0 ECCFn 0 X X X X X 0 X No operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger on CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer 16-bit High Speed Output 8-bit PWM Watchdog Timer MODULE FUNCTION
Figure 25. PCA Module Modes (CCAPMn Register) PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Refer to Figure 26. 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 27). High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (see Figure 28). Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 29 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
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Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
CF
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (D8H)
PCA INTERRUPT (TO CCFn) PCA TIMER/COUNTER CH CL
CEXn
CAPTURE
CCAPnH
CCAPnL
--
ECOMn 0
CAPPn
CAPNn
MATn 0
TOGn 0
PWMn 0
ECCFn
CCAPMn, n= 0 to 4 (DAH - DEH)
SU01608
Figure 26. PCA Capture Mode
CF WRITE TO CCAPnH RESET
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (D8H)
WRITE TO CCAPnL 0 1 ENABLE
CCAPnH
CCAPnL
PCA INTERRUPT (TO CCFn)
16-BIT COMPARATOR
MATCH
CH
CL
PCA TIMER/COUNTER
--
ECOMn
CAPPn 0
CAPNn 0
MATn
TOGn 0
PWMn 0
ECCFn
CCAPMn, n= 0 to 4 (DAH - DEH)
SU01609
Figure 27. PCA Compare Mode
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
CF WRITE TO CCAPnH RESET CCAPnH
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (D8H)
WRITE TO CCAPnL 0 1 ENABLE
CCAPnL
PCA INTERRUPT (TO CCFn)
MATCH 16-BIT COMPARATOR
TOGGLE CH CL CEXn
PCA TIMER/COUNTER
--
ECOMn
CAPPn 0
CAPNn 0
MATn
TOGn 1
PWMn 0
ECCFn
CCAPMn, n: 0..4 (DAH - DEH)
SU01610
Figure 28. PCA High Speed Output Mode
CCAPnH
CCAPnL 0 CL < CCAPnL ENABLE 8-BIT COMPARATOR CL >= CCAPnL 1 OVERFLOW CL PCA TIMER/COUNTER CEXn
--
ECOMn
CAPPn 0
CAPNn 0
MATn 0
TOGn 0
PWMn
ECCFn 0
CCAPMn, n: 0..4 (DAH - DEH)
SU01611
Figure 29. PCA PWM Mode
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
CIDL WRITE TO CCAP4L RESET
WDTE
--
--
--
CPS1
CPS0
ECF
CMOD (D9H)
WRITE TO CCAP4H 1 0 ENABLE
CCAP4H
CCAP4L
MODULE 4
MATCH 16-BIT COMPARATOR RESET
CH
CL
PCA TIMER/COUNTER
--
ECOMn
CAPPn 0
CAPNn 0
MATn 1
TOGn X
PWMn 0
ECCFn X
CCAPM4 (DEH)
SU01612
Figure 30. PCA Watchdog Timer mode (Module 4 only) PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 30 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the PCA timer, 2. periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. Figure 31 shows the code for initializing the watchdog timer. Module 4 can be configured in either compare mode, and the WDTE bit in CMOD must also be set. The user's software then must periodically change (CCAP4H,CCAP4L) to keep a match from occurring with the PCA timer (CH,CL). This code is given in the WATCHDOG routine in Figure 31. This routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 216 count of the PCA timer.
2003 Jan 24
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
INIT_WATCHDOG: MOV CCAPM4, #4CH MOV CCAP4L, #0FFH MOV CCAP4H, #0FFH
ORL CMOD, #40H
; ; ; ; ; ; ; ;
Module 4 in compare mode Write to low byte first Before PCA timer counts up to FFFF Hex, these compare values must be changed Set the WDTE bit to enable the watchdog timer without changing the other bits in CMOD
; ;******************************************************************** ; ; Main program goes here, but CALL WATCHDOG periodically. ; ;******************************************************************** ; WATCHDOG: CLR EA ; Hold off interrupts MOV CCAP4L, #00 ; Next compare value is within MOV CCAP4H, CH ; 255 counts of the current PCA SETB EA ; timer value RET Figure 31. PCA Watchdog Timer Initialization Code
2003 Jan 24
40
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Expanded Data RAM Addressing
The P87C51RA2/RB2/RC2/RD2 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 256 bytes expanded RAM (ERAM) (768 bytes for the RD2). The four segments are: 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. 4. The 256/768-bytes expanded RAM (ERAM, 00H - 1FFH/2FFH) are indirectly accessed by move external instruction, MOVX, and with the EXTRAM bit cleared, see Figure 32. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV 0A0H,#data accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0,acc where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). The ERAM can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory is physically located on-chip, logically occupies the first 256/768 bytes of external data memory in the P87C51RA2/RB2/RC2/RD2. With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not affect ports P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external addressing. For example, with EXTRAM = 0, MOVX @R0,acc where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory. An access to external data memory locations higher than the ERAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 33. With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a 16-bit address. Port 2 outputs the high-order eight address bits (the contents of DPH) while Port 0 multiplexes the low-order eight address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM.
AUXR
Address = 8EH Not Bit Addressable -- Bit: 7 -- 6 -- 5 -- 4 -- 3 -- 2 EXTRAM 1 AO 0
Reset Value = xxxx xx00B
Symbol AO
Function Disable/Enable ALE AO Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (12-clock mode; 1/3 fOSC in 6-clock mode). 1 ALE is active only during off-chip memory access. Internal/External RAM access using MOVX @Ri/@DPTR EXTRAM Operating Mode 0 Internal ERAM access using MOVX @Ri/@DPTR 1 External data memory access. Not implemented, reserved for future use*.
EXTRAM
--
NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01613
Figure 32. AUXR: Auxiliary Register
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
FF
FF
FFFF
UPPER 128 BYTES INTERNAL RAM
SPECIAL FUNCTION REGISTER
EXTERNAL DATA MEMORY
ERAM 256 or 768 BYTES
80
80
LOWER 128 BYTES INTERNAL RAM
100
00
00
0000
SU01293
Figure 33. Internal and External Data Memory Address Space with EXTRAM = 0
HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR P87C51RA2/RB2/RC2/RD2)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When the WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When the WDT overflows, it will drive an output reset HIGH pulse at the RST-pin (see the note below).
Using the WDT
To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When the WDT overflows, it will generate an output RESET pulse at the reset pin (see note below). The RESET pulse duration is 98 x TOSC (6-clock mode; 196 in 12-clock mode), where TOSC = 1/fOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin
4
RATING 0 to +70 or -40 to +85 -65 to +150 0 to +13.0 -0.5 to +6.0 15
UNIT C C V V mA
Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 4. Transient voltage only.
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C or -40C to +85C CLOCK FREQUENCY RANGE SYMBOL 1/tCLCL FIGURE 38 PARAMETER Oscillator frequency OPERATING MODE 6-clock 6-clock 12-clock 12-clock POWER SUPPLY VOLTAGE 5 V " 10% 2.7 V to 5.5 V 5 V " 10% 2.7 V to 5.5 V MIN 0 0 0 0 MAX 30 16 33 16 UNIT MHz MHz MHz MHz
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
DC ELECTRICAL CHARACTERISTICS
Tamb = 0 C to +70 C or -40 C to +85 C; VCC = 2.7 V to 5.5 V; VSS = 0 V (16 MHz max. CPU clock) SYMBOL PARAMETER TEST CONDITIONS 4.0 V < VCC < 5.5 V 2.7 V < VCC < 4.0 V VIH VIH1 VOL VOL1 VOH VOH1 IIL ITL ILI ICC Input high voltage (ports 0, 1, 2, 3, EA) Input high voltage, XTAL1, RST11 Output low voltage, ports 1, 2, 8 Output low voltage, port 0, ALE, PSEN8, 7 Output high voltage, ports 1, 2, 3
3
LIMITS MIN TYP1 MAX 0.2 VCC-0.1 0.7 VCC VCC+0.5 VCC+0.5 0.4 0.4 - - - -50 -650 10
UNIT
VIL
Input low
voltage11
-0.5 -0.5 0.2 VCC+0.9 0.7 VCC
V V V V V V V V V mA mA mA
VCC = 2.7 V; IOL = 1.6 mA2 VCC = 2.7 V; IOL = 3.2 mA2 VCC = 2.7 V; IOH = -20 mA VCC = 4.5 V; IOH = -30 mA
- - VCC - 0.7 VCC - 0.7 VCC - 0.7 -1 - -
Output high voltage (port 0 in external bus VCC = 2.7 V; IOH = -3.2 mA mode), ALE9, PSEN3 Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 36 Input leakage current, port 0 Power supply current (see Figure 41 and Source Code): Active mode @ 16 MHz Idle mode @ 16 MHz Power-down mode or clock stopped (see Figure 37 for conditions) 12 Tamb = 0 C to 70 C Tamb = -40 C to +85 C VIN = 0.4 V VIN = 2.0 V; See note 4 0.45 < VIN < VCC - 0.3
mA mA 2 3 1.2 40 - 225 15 30 50 mA mA V k pF
VRAM RRST CIO
RAM keep-alive voltage Internal reset pull-down resistor Pin capacitance10 (except EA)
NOTES: 1. Typical ratings are not guaranteed. Values listed are based on tests conducted on limited number of samples at room temperature. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC-0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 43 through 46 for ICC test conditions and Figure 41 for ICC vs. Frequency 12-clock mode characteristics: Active mode (operating): ICC = 1.0 mA + 1.1 mA x FREQ.[MHz] Active mode (reset): ICC = 7.0 mA + 0.6 mA FREQ.[MHz] FREQ.[MHz] Idle mode: ICC = 1.0 mA + 0.22 mA 6. This value applies to Tamb = 0 C to +70 C. For Tamb = -40 C to +85 C, ITL = -750 mA. 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15 mA (*NOTE: This is 85 C specification.) Maximum IOL per port pin: Maximum IOL per 8-bit port: 26 mA 71 mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection. 12. Power down mode for 3 V range: Commercial Temperature Range - typ: 0.5 mA, max. 20 mA; Industrial Temperature Range - typ. 1.0 mA, max. 30 mA;
2003 Jan 24
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
DC ELECTRICAL CHARACTERISTICS
Tamb = 0 C to +70 C or -40 C to +85 C; VCC = 5 V 10%; VSS = 0 V (30/33 MHz max. CPU clock) SYMBOL PARAMETER TEST CONDITIONS 4.5 V < VCC < 5.5 V RST11 VCC = 4.5 V; IOL = 1.6 mA2 VCC = 4.5 V; IOL = 3.2 mA2 VCC = 4.5 V; IOH = -30 mA VCC = 4.5 V; IOH = -3.2 mA VIN = 0.4 V VIN = 2.0 V; See note 4 0.45 < VIN < VCC - 0.3 LIMITS MIN VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ITL ILI ICC Input low voltage11 Input high voltage (ports 0, 1, 2, 3, EA) Input high voltage, XTAL1, Output low voltage, ports 1, 2, 3 8 Output low voltage, port 0, ALE, PSEN 7, 8 Output high voltage, ports 1, 2, 3 3 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 36 Input leakage current, port 0 Power supply current Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Figure 46 for conditions) VRAM RRST CIO RAM keep-alive voltage Internal reset pull-down resistor Pin capacitance10 (except EA) Tamb = 0 C to 70 C Tamb = -40 C to +85 C 1.2 40 - 225 15 2 3 30 50 mA mA V k pF -0.5 0.2 VCC+0.9 0.7 VCC - - VCC - 0.7 VCC - 0.7 -1 - - TYP1 MAX 0.2 VCC-0.1 VCC+0.5 VCC+0.5 0.4 0.4 - - -50 -650 10 V V V V V V V mA mA mA UNIT
NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC-0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 43 through 46 for ICC test conditions and Figure 41 for ICC vs. Frequency. 12-clock mode characteristics: Active mode (operating): ICC = 1.0 mA + 1.1 mA x FREQ.[MHz] Active mode (reset): ICC = 7.0 mA + 0.6 mA FREQ.[MHz] FREQ.[MHz] Idle mode: ICC = 1.0 mA + 0.22 mA 6. This value applies to Tamb = 0C to +70C. For Tamb = -40C to +85C, ITL = -750 . 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA (*NOTE: This is 85 C specification.) 26 mA Maximum IOL per 8-bit port: Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.
2003 Jan 24
45
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 5 V 10% OPERATION)
Tamb = 0 C to +70 C or -40 C to +85 C ; VCC = 5 V 10%, VSS = 0 V1,2,3,4 Symbol Figure Parameter Limits MIN 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX tXHDV 38 34 34 34 34 34 34 34 34 34 34 34 35 36 35 35 35 35 35 35, 36 35, 36 36 36 36 35 35, 36 38 38 38 38 37 37 37 37 37 Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid5 12 tCLCL 10 tCLCL -25 2 tCLCL -15 0 10 tCLCL -133 tCLCL -10 0.32 tCLCL 0.32 tCLCL 3 tCLCL -15 4 tCLCL -15 tCLCL -25 tCLCL -15 7 tCLCL -5 0 tCLCL +10 tCLCL - tCLCX tCLCL - tCHCX 5 5 750 600 110 0 492 52.5 0 2 tCLCL -10 8 tCLCL -35 9 tCLCL -35 3 tCLCL +15 172.5 235 37.5 47.5 432.5 0 72.5 6 tCLCL -20 6 tCLCL -20 5 tCLCL -35 0 115 465 527.5 202.5 0 tCLCL -10 5 tCLCL -35 10 355 355 277.5 tCLCL -10 3 tCLCL -10 3 tCLCL -35 0 52.5 277.5 10 0 2 tCLCL-8 tCLCL -13 tCLCL -20 4 tCLCL -35 52.5 177.5 152.5 16 MHz Clock MAX 33 117 49.5 42.5 215 MIN MAX MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Data Memory
External Clock
Shift register
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Below 16 MHz this parameter is 8 tCLCL - 133.
2003 Jan 24
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 2.7 V TO 5.5 V OPERATION)
Tamb = 0 C to +70 C or -40 C to +85 C ; VCC = 2.7 V to 5.5 V, VSS = 0 V1,2,3,4 Symbol Figure Parameter Limits MIN 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX tXHDV 38 34 34 34 34 34 34 34 34 34 34 34 35 36 35 35 35 35 35 35, 36 35, 36 36 36 36 35 35, 36 38 38 38 38 37 37 37 37 37 Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid5 12 tCLCL 10 tCLCL -25 2 tCLCL -15 0 10 tCLCL -133 tCLCL -15 0.32 tCLCL 0.32 tCLCL 3 tCLCL -20 4 tCLCL -20 tCLCL -30 tCLCL -20 7 tCLCL -10 0 tCLCL +15 tCLCL - tCLCX tCLCL - tCHCX 5 5 750 600 110 0 492 47.5 0 2 tCLCL -20 8 tCLCL -55 9 tCLCL -50 3 tCLCL +20 167.5 230 32.5 42.5 427.5 0 77.5 6 tCLCL -25 6 tCLCL -25 5 tCLCL -50 0 105 445 512.5 207.5 0 tCLCL -10 5 tCLCL -50 10 350 350 262.5 tCLCL -15 3 tCLCL -15 3 tCLCL -55 0 52.5 262.5 10 0 2tCLCL-10 tCLCL -15 tCLCL -25 4 tCLCL -55 47.5 172.5 132.5 MAX 16 115 47.5 37.5 195 16 MHz Clock MIN MAX MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Data Memory
External Clock
Shift register
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Below 16 MHz this parameter is 8 tCLCL - 133.
2003 Jan 24
47
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 5 V 10% OPERATION)
Tamb = 0 C to +70 C or -40 C to +85 C ; VCC = 5 V 10%, VSS = 0 V1,2,3,4,5 Symbol Figure Parameter Limits MIN 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV 38 34 34 34 34 34 34 34 34 34 34 Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid6 6 tCLCL 5 tCLCL -25 tCLCL -15 0 5 tCLCL -133 0.5 tCLCL -10 0.4 tCLCL 0.4 tCLCL 1.5 tCLCL -15 2 tCLCL -15 0.5 tCLCL -25 0.5 tCLCL -15 3.5 tCLCL -5 0 0.5 tCLCL +10 tCLCL - tCLCX tCLCL - tCHCX 5 5 375 287.5 47.5 0 179.5 21.25 0 tCLCL -10 4 tCLCL -35 4.5 tCLCL -35 1.5 tCLCL +15 78.75 110 6.25 16.25 213.75 0 41.25 3 tCLCL -20 3 tCLCL -20 2.5 tCLCL -35 0 52.5 215 246.25 108.75 0 0.5 tCLCL -10 2.5 tCLCL -35 10 167.5 167.5 121.25 0.5 tCLCL -10 1.5 tCLCL -10 1.5 tCLCL -35 0 21.25 121.25 10 0 tCLCL-8 0.5 tCLCL -13 0.5 tCLCL -20 2 tCLCL -35 21.25 83.75 58.75 16 MHz Clock MAX 30 54.5 18.25 11.25 90 MIN MAX MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tPLAZ 34 Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ 35 36 35 35 35 35 35 35, 36 35, 36 36 36 36 35
tWHLH 35, 36 External Clock tCHCX tCLCX tCLCH 38 38 38
tCHCL 38 Shift register tXLXL tQVXH tXHQX tXHDX tXHDV 37 37 37 37 37
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. 6. Below 16 MHz this parameter is 4 tCLCL - 133
2003 Jan 24
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Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 2.7 V TO 5.5 V OPERATION)
Tamb = 0 C to +70 C or -40 C to +85 C ; VCC=2.7 V to 5.5 V, VSS = 0 V1,2,3,4,5 Symbol Figure Parameter Limits MIN 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV 38 34 34 34 34 34 34 34 34 34 34 Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid6 6 tCLCL 5 tCLCL -25 tCLCL -15 0 5 tCLCL -133 0.5 tCLCL -15 0.4 tCLCL 0.4 tCLCL 1.5 tCLCL -20 2 tCLCL -20 0.5 tCLCL -30 0.5 tCLCL -20 3.5 tCLCL -10 0 0.5 tCLCL +15 tCLCL - tCLCX tCLCL - tCHCX 5 5 375 287.5 47.5 0 179.5 16.25 0 tCLCL -20 4 tCLCL -55 4.5 tCLCL -50 1.5 tCLCL +20 73.75 105 1.25 11.25 208.75 0 46.25 3 tCLCL -25 3 tCLCL -25 2.5 tCLCL -50 0 42.5 195 231.25 113.75 0 0.5 tCLCL -10 2.5 tCLCL -50 10 162.5 162.5 106.25 0.5 tCLCL -15 1.5 tCLCL -15 1.5 tCLCL -55 0 21.25 101.25 10 0 tCLCL-10 0.5 tCLCL -15 0.5 tCLCL -25 2 tCLCL -55 16.25 78.75 38.75 MAX 16 52.5 16.25 6.25 70 16 MHz Clock MIN MAX MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tPLAZ 34 Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ 35 36 35 35 35 35 35 35, 36 35, 36 36 36 36 35
tWHLH 35, 36 External Clock tCHCX tCLCX tCLCH 38 38 38
tCHCL 38 Shift register tXLXL tQVXH tXHQX tXHDX tXHDV 37 37 37 37 37
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. 6. Below 16 MHz this parameter is 4 tCLCL - 133
2003 Jan 24
49
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 34. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH
SU00025
Figure 35. External Data Memory Read Cycle
2003 Jan 24
50
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX tQVWH
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPF
A0-A15 FROM PCH
SU00026
Figure 36. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 37. Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 38. External Clock Drive
2003 Jan 24
51
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
VCC-0.5
0.2VCC+0.9 VLOAD 0.2VCC-0.1
VLOAD+0.1V VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V
NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00717
SU00718
Figure 39. AC Testing Input/Output
Figure 40. Float Waveform
40
35 MAX ACTIVE MODE ICCMAX = 1.1 FREQ. + 1.0 30
ICC(mA)
25
20
15
TYP ACTIVE MODE MAX IDLE MODE ICCMAX = 0.22 FREQ. + 1.0
10
5
TYP IDLE MODE
4
8
12
16
20
24
28
32
36
FREQ AT XTAL1 (MHz)
SU01684
Figure 41. ICC vs. FREQ for 12-clock operation Valid only within frequency specifications of the specified operating voltage
2003 Jan 24
52
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
/* ## as31 version V2.10 / *js* / ## ## ## source file: idd_ljmp1.asm ## list file: idd_ljmp1.lst created Fri Apr 20 15:51:40 2001 ## ########################################################## #0000 # AUXR equ 08Eh #0000 # CKCON equ 08Fh # # #0000 # org 0 # # LJMP_LABEL: 0000 /75;/8E;/01; # MOV AUXR,#001h ; turn off ALE 0003 /02;/FF;/FD; # LJMP LJMP_LABEL ; jump to end of address space 0005 /00; # NOP # #FFFD # org 0fffdh # # LJMP_LABEL: # FFFD /02;/FD;FF; # LJMP LJMP_LABEL #; NOP # # */" Figure 42. Source code used in measuring IDD operational
SU01499
2003 Jan 24
53
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC
VCC ICC
VCC
RST
SU00719
SU00720
Figure 43. ICC Test Condition, Active Mode All other pins are disconnected
Figure 44. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 45. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC
SU00016
Figure 46. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2 V to 5.5 V
2003 Jan 24
54
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
EPROM CHARACTERISTICS
All these devices can be programmed by using a modified Improved Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The family contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as being manufactured by Philips. Table 8 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 47 and 48. Figure 49 shows the circuit configuration for normal program memory verification.
Program Verification If security bits 2 and 3 have not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 49. The other pins are held at the `Verify Code Data' levels indicated in Table 8. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the 64 byte encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = CAH indicates 87C51RA2 CBH indicates 87C51RB2 CCH indicates 87C51RC2 CDH indicates 87C51RD2 (060H) = NA
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 47. Note that the device is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 47. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 8 are held at the `Program Code Data' levels indicated in Table 8. The ALE/PROG is pulsed low 5 times as shown in Figure 48. To program the encryption table, repeat the 5 pulse programming sequence for addresses 0 through 1FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 5 pulse programming sequence using the `Pgm Security Bit' levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bits can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 8, and which satisfies the timing specifications, is suitable.
Security Bits
With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 9) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled.
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
TMTrademark phrase of Intel Corporation. 2003 Jan 24 55
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Table 8. EPROM Programming Modes
MODE Read signature Program code data Verify code data Pgm encryption table Pgm security bit 1 Pgm security bit 2 Pgm security bit 3 Program to 6-clock mode Verify 6-clock4 Verify security bits5 RST 1 1 1 1 1 1 1 1 1 1 PSEN 0 0 0 0 0 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* 0* 0* 0* 1 1 EA/VPP 1 VPP 1 VPP VPP VPP VPP VPP 1 1 P2.7 0 1 0 1 1 1 0 0 e e P2.6 0 0 0 0 1 1 1 0 0 0 P3.7 0 1 1 1 1 0 0 1 0 1 P3.6 0 1 1 0 1 0 1 0 1 0 P3.3 X X X X X X X 0 1 X
NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75 V 0.25 V. 3. VCC = 5 V10% during programming and verification. 4. Bit is output on P0.4 (1 = 12x, 0 = 6x). 5. Security bit one is output on P0.7. Security bit two is output on P0.6. Security bit three is output on P0.3. * ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while VPP is held at 12.75 V. Each programming pulse is low for 100 s (10 s) and high for a minimum of 10 s.
Table 9. Program Security Bits for EPROM Devices
PROGRAM LOCK BITS1, 2 SB1 1 2 U P SB2 U U SB3 U U PROTECTION DESCRIPTION No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. Same as 2, also verify is disabled. Same as 3, external execution is disabled. Internal data RAM is not accessible.
3 4
P P
P P
U P
NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined.
2003 Jan 24
56
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
+5V
A0-A7 1 1 1
P1 RST P3.6 P3.7 OTP XTAL2
VCC P0 PGM DATA +12.75V 5 PULSES TO GROUND 0 1 0 A8-A13 A14 A15 (RD2 ONLY)
EA/VPP ALE/PROG PSEN P2.7 P2.6
4-6MHz XTAL1 VSS A8-A15 are programming addresses (not external memory addresses per device pin out)
P2.0-P2.5 P3.4 P3.5
SU01659
Figure 47. Programming Configuration
5 PULSES 1 ALE/PROG: 0 1 2 3 4 5
SEE EXPLODED VIEW BELOW tGHGL = 10s MIN tGLGH = 100s10s 1 ALE/PROG: 0 1
SU00875
Figure 48. PROG Waveform
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 OTP XTAL2 4-6MHz XTAL1 VSS A8-A15 are programming addresses (not external memory addresses per device pin out) ALE/PROG PSEN P2.7 P2.6 P2.0-P2.5 P3.4 P3.5 P0 PGM DATA 1 1 0 0 ENABLE 0 A8-A13 A14 A15 (RD2 ONLY)
EA/VPP
SU01660
Figure 49. Program Verification
2003 Jan 24
57
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21C to +27C, VCC = 5V10%, VSS = 0V (See Figure 50) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL NOTE: 1. Not tested. Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s PARAMETER MIN 12.5 MAX 13.0 50 6
1
UNIT V mA MHz
PROGRAMMING* P1.0-P1.7 P2.0-P2.5 P3.4 (A0 - A14) ADDRESS
VERIFICATION* ADDRESS
tAVQV
DATA IN DATA OUT
PORT 0 P0.0 - P0.7 (D0 - D7)
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC 1 EA/VPP LOGIC 0
LOGIC 1
tEHSH
P2.7 **
tELQV
tEHQZ
SU00871
NOTES: * FOR PROGRAMMING CONFIGURATION SEE FIGURE 47.
FOR VERIFICATION CONDITIONS SEE FIGURE 49. ** SEE TABLE 8.
Figure 50. EPROM Programming and Verification
2003 Jan 24
58
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
MASK ROM DEVICES Security Bits
With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 10) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled.
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
Table 10. Program Security Bits
PROGRAM LOCK BITS1, 2 SB1 1 2 U P SB2 U U PROTECTION DESCRIPTION No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.
NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined.
ROM CODE SUBMISSION FOR 8K ROM DEVICES (87C51RA2)
When submitting ROM code for the 8k ROM devices, the following must be specified: 1. 8 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS 0000H to 1FFFH 2000H to 203FH 2040H CONTENT DATA KEY SEC BIT(S) 7:0 7:0 0 COMMENT User ROM Data ROM Encryption Key FFH = no encryption ROM Security Bit 1 0 = enable security 1 = disable security ROM Security Bit 2 0 = enable security 1 = disable security
2040H
SEC
1
Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.
If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption:
V V V
Enabled Enabled No
V V V
Disabled Disabled Yes If Yes, must send key file.
2003 Jan 24
59
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
ROM CODE SUBMISSION FOR 16K ROM DEVICES (87C51RB2)
When submitting ROM code for the 16K ROM devices, the following must be specified: 1. 16 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS 0000H to 3FFFH 4000H to 403FH 4040H CONTENT DATA KEY SEC BIT(S) 7:0 7:0 0 COMMENT User ROM Data ROM Encryption Key FFH = no encryption ROM Security Bit 1 0 = enable security 1 = disable security ROM Security Bit 2 0 = enable security 1 = disable security
4040H
SEC
1
Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.
If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption:
V V V
Enabled Enabled No
V V V
Disabled Disabled Yes If Yes, must send key file.
2003 Jan 24
60
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
ROM CODE SUBMISSION FOR 32K ROM DEVICES (87C51RC2)
When submitting ROM code for the 32K ROM devices, the following must be specified: 1. 32 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS 0000H to 7FFFH 8000H to 803FH 8040H CONTENT DATA KEY SEC BIT(S) 7:0 7:0 0 COMMENT User ROM Data ROM Encryption Key FFH = no encryption ROM Security Bit 1 0 = enable security 1 = disable security ROM Security Bit 2 0 = enable security 1 = disable security
8040H
SEC
1
Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.
If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption:
V V V
Enabled Enabled No
V V V
Disabled Disabled Yes If Yes, must send key file.
2003 Jan 24
61
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
ROM CODE SUBMISSION FOR 64K ROM DEVICE (87C51RD2)
When submitting ROM code for the 64K ROM devices, the following must be specified: 1. 64 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS 0000H to FFFFH 10000H to 1003FH 10040H CONTENT DATA KEY SEC BIT(S) 7:0 7:0 0 COMMENT User ROM Data ROM Encryption Key FFH = no encryption ROM Security Bit 1 0 = enable security 1 = disable security ROM Security Bit 2 0 = enable security 1 = disable security
10040H
SEC
1
Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.
If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption:
V V V
Enabled Enabled No
V V V
Disabled Disabled Yes If Yes, must send
2003 Jan 24
62
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
2003 Jan 24
63
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
2003 Jan 24
64
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm
SOT389-1
2003 Jan 24
65
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
REVISION HISTORY
Rev _3 Date 20030124 Description Product data (9397 750 10994); ECN 853-2391 29335 dated 07 Jan 2003.
* Updated ordering information table.
_2 20021028 Product data (9397 750 10393); ECN 853-2391 29117 dated 28 Oct 2002.
Modifications:
2003 Jan 24
66
Philips Semiconductors
Product data
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P87C51RA2/RB2/RC2/RD2
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 01-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 10994
Philips Semiconductors
2003 Jan 24 67

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