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| DATA SHEET MOS INTEGRATED CIRCUIT PD75516 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The PD75516 is a product in the 75X series(of 4-bit single-chip microcomputers). The 75X series has an architecture which is comparable to that of 8-bit microcomputers. The PD75516 possesses high class processing capacities as a 4-bit single-chip microcomputer with built-in A/D converter and serial interface, including the capability to process data in lengths of 1, 4 and 8 bits in addition to its high speed operation. Details of functions are described in the User's Manual shown below. Be sure to read in design. PD75516 User's Manual: IEM-5049 FEATURES q q q q A large Built-in Built-in Built-in number of I/O Lines: 64 lines (Internal pull-up/pull- down resistor specifiable: 47) 8-bit serial interface: 2 channels NEC standard serial bus interface (SBI) 8-bit AD converter: 8 channels q q q High speed operation and a instruction execution time variation function which is effective for saving power. * 0.95 s/1.91 s/15.3 s (at 4.19 MHz operation), 122 s (at 32.768 kHz operation) Program memory (ROM) capacity: 16256 x 8 bits Data memory (RAM) capacity: 512 x 4 bits Powerful timer function: 4 channels * 8-bit timer/event counter * Watch timer * 8-bit basic interval timer * Timer/pulse generator: 14-bit PWM with variable output Ultra low power consumption clock operation is possible (5 A TYP.: During operation at 3 V) Devices with built-in PROM are available (PD75P516) q q USES VCRs and CD players, telephones, cameras, etc. The information in this document is subject to change without notice. Document No. IC-2471D (O. D. No. IC-7580D) Date Published November 1993 P Printed in Japan The mark 5 shows major revised points. (c) NEC Corporation 1989 PD75516 ORDERING INFORMATION Ordering Code Package 80-pin plastic QFP (14 x 20 mm) Quality Grade Standard PD75516GF-xxx-3B9 Remarks "xxx" means the specified ROM code. Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. LIST OF PD75516 FUNCTIONS Item ROM On-chip memory General registers Instruction cycle Total CMOS input Input/ output ports N-ch open-drain input/output A/D converter 20 (LED drive: 8; 10 V withstand voltage, mask option pull-up capability: 20) 8-bit resolution x 8 channels (successive approximation type) * Operating voltage: VDD = 3.5 to 6.0 V *Timer/event counter * Basic interval timer * Timer/pulse generator (14-bit PWM output capability) * Watch timer * NEC standard serial bus interface (SBI)/3-wire SIO: 1 channel 2 channels * Normal clocked serial interface (3-wire SIO): 1 channel CMOS input/output RAM 16256 x 8 bits 512 x 4bits (4 bits x 8 or 8 bits x 4) x 4 banks * 0.95 s/1.91 s/15.3 s (Main system clock: 4.19 MHz operation) * 122 s (Subsystem clock: 32.768 kHz operation) 64 16 (dual function and analog input as INT, SIO, PPO, software pull-up capability: 7) 28 (LED drive: 4) * Software pull-up capability : 16 * Mask option pull-down capability: 4 Function Timer/counters 4 channels Serial Interface Vectored interrupt Test input External: 3, internal: 4 External: 1, internal: 1 * Bit data set/reset/test/Boolean operations * 4-bit data transfer, operation, increment/ decrement, compare * 8-bit data transfer, operation, increment/ decrement, compare * Ceramic/crystal oscillator for main system clock oscillation: 4.19 MHz * Crystal oscillator for subsystem clock oscillation: 32.768 kHz VDD = 2.7 to 6.0 V 80-pin plastic QFP (14 x 20 mm) Instruction set System clock oscillator Operating voltage Package 2 PD75516 CONTENTS 1. 2. 3. 4. PIN CONFIGURATION ................................................................................................................................ 4 EXAMPLE OF SYSTEM CONFIGURATION ..............................................................................................5 INTERNAL BLOCK DIAGRAM .................................................................................................................... 6 PIN FUNCTIONS ......................................................................................................................................... 7 4.1 4.2 4.3 4.4 4.5 PORT PINS ........................................................................................................................................................... 7 NON-PORT PINS .................................................................................................................................................. 9 PIN INPUT/OUTPUT CIRCUIT LIST ................................................................................................................. 10 RECOMMENDED CONNECTIONS OF UNUSED PINS .................................................................................. 13 MASK OPTION SELECTION ............................................................................................................................. 14 5. 6. MEMORY CONFIGURATION ................................................................................................................... 15 PERIPHERAL HARDWARE FUNCTIONS ................................................................................................. 18 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 PORTS ................................................................................................................................................................. 18 CLOCK GENERATOR ......................................................................................................................................... 19 CLOCK OUTPUT CIRCUIT ................................................................................................................................. 20 BASIC INTERVAL TIMER .................................................................................................................................. 21 WATCH TIMER ................................................................................................................................................... 22 TIMER/EVENT COUNTER ................................................................................................................................. 22 TIMER/PULSE GENERATOR ............................................................................................................................ 24 SERIAL INTERFACE ........................................................................................................................................... 25 A/D CONVERTER .............................................................................................................................................. 29 BIT SEQUENTIAL BUFFER ............................................................................................................................... 30 7. 8. 9. INTERRUPT FUNCTIONS ......................................................................................................................... 31 STANDBY FUNCTIONS ............................................................................................................................ 33 RESET FUNCTIONS .................................................................................................................................. 34 10. INSTRUCTION SET ................................................................................................................................... 36 11. ELECTRICAL SPECIFICATIONS ............................................................................................................... 45 12. CHARACTERISTIC CURVES ..................................................................................................................... 59 13. PACKAGE INFORMATION ....................................................................................................................... 65 14. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 66 APPENDIX A. DEVELOPMENT TOOLS ........................................................................................................ 67 APPENDIX B. RELATED DOCUMENTS ....................................................................................................... 68 3 PD75516 1. PIN CONFIGURATION AV0 AVREF VDD * VDD P113 P112 P111 P110 P103 P102 P101 P100 P93 P92 P91 P90 SI1/P83 SO1/P82 SCK1/P81 PPO/P80 KR7/P73 KR6/P72 KR5/P71 KR4/P70 AN1 AN2 AN3 AN4/P150 AN5/P151 AN6/P152 AN7/P153 AVSS P120 P121 P122 P123 P130 P131 P132 P133 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P140 P141 P142 P143 RESET X2 X1 IC XT2 XT1 VSS P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30 IC: Internally Connected (Connect to VSS directly.) * Be sure to supply power to both VDD pins. 4 KR3/P63 KR2/P62 KR1/P61 KR0/P60 P53 P52 P51 P50 VSS P43 P42 P41 P40 P33 P32 P31 PD75516GF-xxx-3B9 PD75516 2. EXAMPLE OF SYSTEM CONFIGURATION VTR (Voltage Synthesizer Tuner) PD75516 Remote Control IC INT0 SIO OSD Input Port Mechanism Servo IC Mechanism Control Mechanism Computer/ Timer Output Port Analog Input Tuner PPO LPF Port4, 5 Key Matrix KR0-KR7 SIO FIP Driver FIP System Clock Watch Clock 5 6 BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 BUZ/P23 WATCH TIMER INTW GENERAL REG. PPO/P80 TIMER PULSE GENERATOR INTTPG SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 SERIAL INTERFACE0 INTCSI SI1/P83 SO1/P82 SCK1/P81 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60KR7/P73 8 BIT SEQ. BUFFER(16) AN0-AN3 AN4/P150-AN7/P15 AVREF AV SS RESET VDD A/D CONVERTER VSS ROM PROGRAM MEMORY 16256x8 BITS BANK PROGRAM COUNTER (14) ALU CY SP (8) PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 DECODE AND CONTROL PORT8 RAM DATA MEMORY 512x 4 BITS PORT9 PORT10 PORT11 SERIAL INTERFACE1 fx/2N INTERRUPT CONTROL CLOCK OUTPUT CONTROL CLOCK GENERATOR SUB MAIN CPU CLOCK PORT12 PORT13 PORT14 PORT15 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 P00-P03 P10-P13 P20-P23 P30-P33 P40-P43* P50-P53* P60-P63 P70-P73 P80-P83 P90-P93 P100-P103 P110-P113 P120-P123 * P130-P133 * P140-P143 * P150-P153 CLOCK DIVIDER STAND BY CONTROL PCL/P22 XT1XT2 X1 X2 3. INTERNAL BLOCK DIAGRAM PD75516 * PORTs 4 , 5 and 12 to 14 are 10 V middle-high voltage N-ch open-drain input/output ports. PD75516 4. PIN FUNCTIONS 4.1 PORT PINS (1/2) Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 *2 P31 *2 P32 *2 P33 *2 *2 P40 to P43 I/O DualFunction Pin INT4 Function Input / Output 8-Bit After Reset Circuit Type *1 I/O B Input SCK0 SO0/SB0 SI0/SB1 INT0 4-bit input port (PORT0). Internal pull-up resistor can be specified in 3-bit units by software for P01 to P03. Noise removing function available 4-bit input port (PORT1). Internal pull-up resistor can be specified in 4-bit units by software. x F -A Input F -B M-C Input INT1 INT2 TI0 PTO0 x Input B -C Input/ output -- PCL BUZ -- 4-bit input/ output port (PORT2). Internal pull-up resistor can be specified in 4-bit units by software. x Input E-B Input/ output -- -- -- Programmable 4-bit input/ output port (PORT3). Input/ output specifiable in 1-bit units. Internal pull-up resistor can be specified in 4-bit units by software. N-ch open-drain 4-bit input/output port (PORT4). Pull-up resistor can be incorporated in 1-bit units (mask option). 10 V withstand voltage with open-drain. x Input E-C Input/ output -- q *2 P50 to P53 Input/ output -- N-ch open-drain 4-bit input/ output port (PORT5). Pull-up resistor can be incorporated in 1-bit units (mask option). 10 V withstand voltage with open-drain. Programmable 4-bit input/output port (PORT6). Input/output specifiable in 1-bit units. Internal pull-up resistor can be specified in 4-bit units by software. High level (when a pullup resistor is incorporated) or high impedance High level (when a pullup resistor is incorporated) or high impedance M M P60 P61 P62 P63 P70 P71 P72 P73 Input/ output Input/ output KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 Input F-C q 4-bit input/output port (PORT7). Internal pull-up resistor can be specified in 4-bit units by software. Input F -A * 1. 2. Schmitt trigger inputs are circled. Can drive LED directly. 7 PD75516 4.1 PORT PINS (2/2) DualFunction Pin PPO SCK1 Input P82 P83 Input/ output SO1 SI1 4-bit input/output port (PORT9) Pull-up resistor can be incorporated in 1-bit units (mask option). 4-bit input port (PORT8). 8-Bit After Reset I/O Input / Output Circuit Type * E Pin Name P80 P81 I/O Function x Input F E B P90 to P93 x Low level (when a pull down resistor is incorporated) or high impedance V P100 to P103 Input/ output Input/ output 4-bit input/output port (PORT10). Input E x 4-bit input/output port (PORT11). N-ch open-drain 4-bit input/ output port (PORT12). Pull-up resistor can be incorporated in 1-bit units (mask option). 10 V withstand voltage with open-drain. N-ch open-drain 4-bit input/ output port (PORT13). Pull-up resistor can be incorporated in 1-bit units (mask option). 10 V withstand voltage with open-drain. N-ch open-drain 4-bit input/ output port (PORT14). Pull-up resistor can be incorporated in 1-bit units (mask option). 10 V withstand voltage with open-drain. AN4 to AN7 4-bit input/output port (PORT15). Input High level (when a pullup resistor is incorporated) or high impedance High level (when a pullup resistor is incorporated) or high impedance High level (when a pullup resistor is incorporated) or high impedance P110 to P113 E P120 to P123 Input/ output x M P130 to P133 Input/ output x M P140 to P143 Input/ output Input x x M P150 to P153 Input Y-A * Schmitt trigger inputs are circled. 8 PD75516 4.2 NON-PORT PINS DualFunction Pin P13 P20 P22 P23 Input / Output Circuit Type * B -C E-B E-B E-B Pin Name TI0 PTO0 PCL BUZ I/O Input Output Output Output Input/ output Input/ output Input/ output Input Function External event pulse input pin to the timer/event counter. Timer/event counter output pin. Clock output pin. Fixed frequency output pin (for buzzer or system clock trimming). Serial clock input/output pin. Serial data output pin. Serial bus input/output pin. Serial data input pin. Serial bus input/output pin. Edge-detected vectored interrupt input pin (valid for detection of rising and falling edges). Edge-detected vectored interrupt input pin (detected edge selection possible). Edge-detected testable input pin (rising edge detection). Clocked After Reset -- Input Input Input SCK0 SO0/SB0 P01 P02 Input F -A Input Input F -B SI0/SB1 P03 M-C INT4 INT0 P00 P10 -- B Input INT1 INT2 KR0 to KR3 KR4 to KR7 SCK1 SO1 SI1 AN0 to AN3 AN4 to AN7 AVREF AVSS Input Input -- Input Input Input Input/ output Output Input P11 P12 P60 to P63 P70 to P73 P81 P82 P83 -- -- Asynchronous Asynchronous -- Input Input Input Input Input -- B-C B -C F -C F -A F E B Y Serial falling edge detection testable input pin. Serial falling edge detection testable input pin. Serial clock input/output pin. Serial data output pin. Serial data input pin. A/D converter analog input pin. P150 to P153 -- -- A/D converter reference voltage input pin. A/D converter reference GND potential pin. Main system clock oscillation crystal/ceramic connection pin. An external clock is input to X1 and an antiphase clock is input to X2. Subsystem clock oscillation crystal connection pin. An external clock is input to XT1 and XT2 is leave open. System reset input pin. Timer/pulse generator pulse output pin. Internally Connected. Connect to VSS directly. Positive power supply pin. GND potential pin. -- -- Y-A Z -- X1, X2 Input -- -- -- XT1 XT2 RESET PPO IC VDD VSS Input -- -- Input Output -- -- -- -- P80 -- -- -- -- -- Input -- -- -- -- B E -- -- -- * Schmitt trigger inputs are circled. 9 PD75516 4.3 PIN INPUT/OUTPUT CIRCUIT LIST Use of simplified forms of the input/output circuit for each pin of the PD75516 are shown as follows. Fig. 4-1 Pin Input/Output Circuit List (1/3) TYPE A TYPE D VDD data VDD P-ch OUT N-ch IN P-ch N-ch output disable CMOS Specified Input Buffer TYPE B Push-Pull Output which can be Set to Output High Impedance (with Both P-ch and N-ch Set to OFF) TYPE E data Type D IN output disable Type A IN/OUT Schmitt Trigger Input Having Hysteresis Characteristics TYPE B-C VDD Input/Output Circuit Consisting of Type D Push-Pull Output and Type A Input Buffer TYPE B VDD P.U.R. P.U.R. P-ch P.U.R. enable data IN P.U.R. enable P-ch IN/OUT Type D output disable P.U.R. : Pull-Up Resistor Type A Schmitt Trigger Input Having Hysteresis Characteristics P.U.R. : Pull-Up Resistor 10 PD75516 Fig. 4-1 Pin Input/Output Circuit List (2/3) TYPE E-C VDD P.U.R. TYPE F-B VDD P.U.R. VDD P-ch IN/OUT P-ch P.U.R. enable data Type D output disable Type A P-ch output disable (P-ch) data output disable output disable (N-ch) IN/OUT N-ch Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor TYPE F TYPE F-C VDD P.U.R. data Type D output disable Type B IN/OUT P.U.R. enable data Type D output disable Type B Input/Output Circuit Consisting of Type D Push-Pull Output and Type B Schmitt Trigger input TYPE F-A TYPE M P.U.R. (Mask Option) data IN/OUT Type D output disable Type B Middle-High Voltage Input Buffer (+10 V Withstand Voltage) P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor output disable P-ch IN/OUT P.U.R. : Pull-Up Resistor VDD IN/OUT N-ch (+10 V Withstand Voltage) VDD P.U.R. P.U.R. enable P-ch data 11 PD75516 Fig. 4-1 Pin Input/Output Circuit List (3/3) TYPE M-C VDD P.U.R. TYPE Y-A In Instruction P.U.R. enable P-ch VDD IN/OUT IN VDD P-ch N-ch Sampling C AVss data output disable N-ch + AVss P.U.R. : Pull-Up Resistor input enable Reference Voltage (from the Series Resistance String Voltage Tap) TYPE V data Type D output disable Type A P.D.R. (Mask Option) TYPE Z AVREF IN/OUT Reference Voltage P.D.R.: Pull-Down Resistor AVSS TYPE Y VDD IN VDD P-ch N-ch Sampling C AVss AVss Reference Voltage (from the Series Resistance String Voltage Tap) + - input enable 12 PD75516 4.4 RECOMMENDED CONNECTIONS OF UNUSED PINS Table 4-1 Recommended Connection of Unused Pins Pin P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI1/SB1 P10/INT0 to P12/INT2 Connect to VSS P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30 to P33 P40 to P43 P50 to P53 P60/KR0 to P63/KR3 P70/KR4 to P73/KR7 P80/PPO P81/SCK1 Connect to VSS or VDD P82/SO1 P83/SI1 P90 to P93 P100 to P103 P110 to P113 P120 to P123 P130 to P133 P140 to P143 P150/AN4 to P153/AN7 Connect to VSS AN0 to AN3 XT1 XT2 AVREF AVSS IC Connect to VSS Connect to VSS or VDD Leave open Ouput state : Leave open Input state : Connect to VSS or VDD Ouput state : Leave open Input state : Connect to VSS or VDD Connect to VSS or VDD Connect to VSS Recommended Connection 13 PD75516 4.5 MASK OPTION SELECTION The following mask options are available for the pins. (1) Specification of internal pull-up/pull-down resistor Table 4-2 Pull-Up/Pull-Down Resistor Selection Pins P40 to P43, P50 to P53, P120 to P123, P130 to P133, P140 to P143 With pull-down resistor P90 to P93 (specifiable bit-wise) Without pull-down resistor (specifiable bit-wise) With pull-up resistor (specifiable bit-wise) Without pull-up resistor (specifiable bit-wise) Mask Option (2) Specification of internal feedback resistor for subsystem clock oscillation Table 4-3 Feedback Resistor Selection Pins XT1, XT2 With feedback resistor (subsystem clock used) Mask Option Without feedback resistor (subsystem clock not used) Note When the subsystem clock is not used, operation is not affected if a feedback resistor is incorporated, but the supply current IDD is increased. 14 PD75516 5. MEMORY CONFIGURATION * Program memory (ROM) ...... 12160 x 8 bits (0000H to 2F7FH) * 0000H, 0001H : Vector table in which the program start addresses by reset are written. * 0002H to 000DH : Vector table in which the program start addresses by interrupt are written. * 0020H to 007FH : Table area referred by the GETI instruction. * Data memory * Data area ... 512 x 4 bits (000H to 1FFH) * Peripheral hardware area ... 128 x 4 bits (F80H to FFFH) 15 PD75516 Fig. 5-1 Program Memory Map Address 7 0000H MBE 6 RBE 0 Internal Reset Start Address (High-Order 6 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE RBE INTBT/INT4 Start Address (High-Order 6 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE RBE INT0 Start Address (High-Order 6 Bits) INT0 Start Address (Low-Order 8 Bits) 0006H MBE RBE INT1 Start Address (High-Order 6 Bits) INT1 Start Address (Low-Order 8 Bits) 0008H MBE RBE INTCSI0 Start Address (High-Order 6 Bits) INTCSI0 Start Address (Low-Order 8 Bits) 000AH MBE RBE INTT0 Start Address (High-Order 6 Bits) INTT0 Start Address (Low-Order 8 Bits) 000CH MBE RBE INTTPG Start Address (High-Order 6 Bits) INTTPG Start Address (Low-Order 8 Bits) BRCB ! caddr Instruction Branch Address BR !addr Instruction Branch Address CALLF ! faddr Instruction Entry Address CALL !addr Instruction Subroutine Entry Address 0020H GETI Instruction Reference Table 007FH 0080H 07FFH 0800H BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) BRCB !caddr Instruction Branch Address Branch Destination Address and Subroutine Entry Address by GETI Instruction 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H BRCB !caddr Instruction Branch Address 3F7FH BRCB !caddr Instruction Branch Address Remarks In cases other than above, the program can branch to an address for which only the lower 8-bit of the PC have been changed, by a BR PCDE or BR PCXA instruction. 16 PD75516 Fig. 5-2 Data Memory Map Data Memory General Register Area 000H (32 x 4) 01FH 008H 256 x 4 Memory Bank Stack Area 0 Data Area Static RAM (512 x 4) 0FFH 100H 256 x 4 1 1FFH Not On-Chip F80H Peripheral Hardware Area FFFH 128 x 4 15 17 PD75516 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 PORTS There are the following 3 types of I/O ports. * * * CMOS input (PORT0, 1, 8, 15) CMOS input/output (PORT2, 3, 6, 7, 9, 10, 11) : 16 : 28 N-ch open-drain input/output (PORT4, 5, 12, 13, 14) : 20 Total 64 Table 6-1 Port Functions Port (Pin name) Function Operation/Features Remarks Shares the use of the pin with INT4, SCK0, SO0/SB0, SI0/SB1. Shares the use of the pin with INT0 to INT2 and TI0. Shares the use of the pin with PTO0, PCL, BUZ PORT 0 4-bit input PORT 1 PORT 2 4-bit input/output PORT 3 * PORT 4 * PORT 5 * PORT 6 4-bit input/output PORT 7 Can always be read or tested regardless of the operating mode of the dual function pin. Can be set in the input or output mode as a 4-bit unit. Can be set in the input or the output mode in 1/4-bit units 4-bit input/output Can be set in input or (N-ch open-drain 10 V output mode in 4-bit withstand voltage) units With ports 4 and 5 as a With a mask option, the internal pair, data can be input pull-up resistance can be speciand output in 8-bit units. fied in 1-bit units. Shares the use of the pin with KR0 to KR3. Can be set in input or output mode in 1/4-bit With ports 6 and 7 as a units pair, data can be input and output in 8-bit units. Can be set in input or output mode in 4-bit units Can always be read or tested regardless of the operating mode of the dual function pin. Shares the use of the pin with KR4 to KR7. Shares the use of the pin with PPO, SCK1, SO1 and SI1. With a mask option, the internal pull-up resistance can be specified in 1-bit units. PORT 8 4-bit input PORT 9 4-bit input/output Can be set in input or output mode in 4-bit units. Can be set in input or output mode in 4-bit units. PORT 10 4-bit input/output PORT 11 PORT 12 PORT 13 PORT 14 PORT 15 4-bit input/output Can be set in input or output mode in 4-bit (N-ch open-drain 10 V units. withstand voltage) 4-bit input Can always be read or tested regardless of the operating mode of the dual function pin. With a mask option, the internal pull-up resistance can be specified in 1-bit units. Shares the use of the pin with AN4 to AN7. * Can drive a LED directly. 18 PD75516 CLOCK GENERATOR The clock generator operation is determined by the processor clock control register (PCC) and the system clock control register (SCC). 2 kinds of clocks such as a main system clock and a subsystem clock are available. In addition, the instruction execution time can be changed. * 0.95 s, 1.91 s, 15.3 s (Main system clock: 4.19 MHz operation) * 122 s (Subsystem clock: 32.768 kHz operation) Fig. 6-1 Clock Generator Block Diagram XT1 Subsystem f XT Clock Oscillation Circuit Watch Timer Timer/Pulse Generator Main System fX Clock Oscillation Circuit 1/ 2 1/ 16 * Basic Interval Timer (BT) * Timer/Event Counter * Serial Interface * Watch Timer * Clock Output Circuit * A/D Converter * INT0 Noise Eliminator 6.2 XT2 X1 1/8~1/4096 Frequency Divider X2 SCC SCC3 SCC0 Oscillation Stop Selector Selector Frequency Divider 1/4 * CPU * Clock Output Circuit * INT0 Noise Eliminator Internal Bus PCC PCC0 PCC1 4 HALT F/F HALT* STOP* PCC2 PCC3 R Q S PCC2 and PCC3 Clear STOP F/F Q S Wait Release Signal from BT RESET Signal R * Instruction execution 1. 2. 3. 4. 5. 6. fX = Main system clock frequency fXT = Subsystem clock frequency = CPU clock PCC: Processor clock control register SCC: System clock control register Standby Release Signal from Interrupt Control Circuit Remarks One clock cycle (tCY) of is 1 machine cycle of the instruction. With tCY, refer to "AC CHARACTERISTICS" in 11. "Electrical Specifications". 19 5 PD75516 6.3 CLOCK OUTPUT CIRCUIT The clock output circuit is a circuit which outputs a clock pulse from P22/PCL pin and is used to supply clock pulses to remote control outputs or peripheral LSI's. * Clock output (PCL) : , 524, 262, 65.5 kHz (4.19 MHz operation) * Buzzer output (BUZ) : 2 kHz (4.19 MHz, or 32.768 kHz operation) Fig. 6-2 Clock Output Circuit Configuration Form Clock Generator f x /23 Selector f x /24 f x /2 6 Output Buffer PCL/P22 PORT2.2 CLOM CLOM CLOM CLOM CLOM 2 3 1 0 P22 Output Latch Bit 2 of PMGB Port 2 Input/ Output Mode Specification Bit 4 Internal Bus Remarks Consideration is given so that a low amplitude pulse is not output when switching between clock output enable and disable. 20 PD75516 6.4 BASIC INTERVAL TIMER The basic interval timer includes the following functions. * It operates as an interval timer which generates reference time interrupts. * It can be applied as a watchdog timer which detects when a program is out of control. * Selects and counts wait times when the standby mode is released. * It reads count contents. Fig. 6-3 Basic Interval Timer Configuration From Clock Generator fX/2 5 Clear Clear fX/2 7 MPX fX/2 fX/2 9 Basic Interval Timer (8-Bit Frequency Divider) Set BT Interrupt Request Flag 12 BT IRQBT Vectored Interrupt Request Signal 3 Wait Release Signal during Standby Release BTM3 BTM2 BTM1 BTM0 BTM SET1* 4 Internal Bus 8 * Instruction execution. 21 PD75516 6.5 WATCH TIMER The PD75516 incorporates one channel of watch timer which has the following functions. * Sets test flags (IRQW) at 0.5-second intervals. The standby mode can be released with IRQW. * 0.5-second time intervals can be created in either the main system clock or the subsystem clock. * In the rapid feed mode, time intervals which are 128 times normal (3.91 ms) can be set, making this function convenient for program debugging and testing. * A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin for use in generating buzzer sounds and trimming system clock oscillator frequencies. * The frequency divider can be cleared, so this watch can be started at 0 second. Fig. 6-4 Watch Timer Block Diagram fW (256 Hz : 3.91 ms) 7 2 Selector INTW IRQW Set Signal From Clock Generator fW 128 (32.768 kHz) fXT (32.768 kHz) Selector fW (32.768 kHz) fW 14 2 Frequency Divider 2Hz 0.5 sec fW 16 (2.048 kHz) Clear Output Buffer P23/BUZ WM WM7 0 0 0 0 WM2 WM1 WM0 PORT2.3 P23 Output Latch Bit 2 of PMGB Port 2 Input/Output Mode 8 Bit Test Instruction Internal Bus Remarks 6.6 Values in parentheses are when fX = 4.194304 MHz and fXT = 32.768 kHz. TIMER/EVNET COUNTER The PD75516 incorporates one channel of timer/event counter which has the following functions. * Operates as a programmable interval timer. * Outputs square waves in the desired frequency to the PTO0 pin. * Operates as an event counter. * Divides the TI0 pin input into N divisions and outputs it to the PTO0 pin (frequency divider operation). * Supplies a serial shift clock to the serial interface circuit. * Count status read function. 22 Fig. 6-5 Timer/Event Counter Block Diagram Internal Bus SET1 * 8 TM07 TM06 TM05 TM04 TM03 TM02 TM0 TM01 TM00 8 8 Modulo Register (8) TMOD0 TOE0 TO Enable Flag PORT2.0 Bit 2 of PGMB Port 2 P20 Input/ Output Output Latch Mode To Serial Interface P20/PTO0 Output Buffer INTT0 IRQT0 Set Signal PORT1.3 8 Comparator (8) Match TOUT F/F Reset T0 Input Buffer P13/TI0 MPX 8 Count Register (8) CP Clear Timer Operation Start From Clock Generator RESET IRQT0 Clear Signal * Instruction execution PD75516 23 PD75516 6.7 TIMER/PULSE GENERATOR The PD75516 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse generator. The timer/pulse generator has the following functions. (a) Functions available in the timer mode * 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels * Square wave output to PPO pin Functions available in the PWM pulse generate mode * 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to analog converter and applicable to tuning) * Interrupt generation of fixed time interval If pulse output is not necessary, the PPO pin can be used as a 1-bit output port. Note If the STOP mode is set while the timer/pulse generator is in operation, miss-operation may result. To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode register. Fig. 6-6 Block Diagram of Timer/Pulse Generator (Timer Mode) (b) Internal Bus 8 MODL Modulo Register L (8) TPGM3 (Set to "1") 8 MODH Modulo Register H (8) Modulo Lach H (8) 8 Match Comparator (8) Frequency Divider fX 1/2 TPGM1 Prescalar Select Latch (5) Clear T F/F Selector INTTPG IRQTPG Set Signal Output Buffer PPO CP 8 Count Register (8) Clear Set TPGM4TPGM5 TPGM7 24 PD75516 Fig. 6-7 Timer/Pulse Generator Block Diagram (PWM Pulse Generator Mode) Internal Bus 8 MODH Modulo Register H (8) TPGM3 8 MODL Modulo Register L (8) MODH (8) Modulo Latch (14) MODL7-2 (6) Output Buffer TPGM1 fx 1/2 PWM Pulse Generator Selector PPO Frequency Divider INTTPG (IRQTPG Set Signal) 15 ( 2 = 7.81 ms : fX = 4.19 MHz operation) fX TPGM5 TPGM7 6.8 SERIAL INTERFACE The PD75516 has two serial interface channels on chip. The differences between channel 0 and channel 1 are shown in Table 6-2. Table 6-2 Differences between Channels 0 and 1 Serial Transfer Mode and Function Clock selection Channel 0 fX/24 , fX/23 , TOUT F/F, external clock Channel 1 fX/24, fX/23, external clock MSB first Serial transfer end flag (EOT) 3-wire serial I/O Transfer mode MSB first/LSB first switchable Transfer end flag 2-wire serial I/O Serial bus interface (SBI) Serial transfer end interrupt request flag (IRQCSI0) Use enabled None (1) Serial interface (channel 0) functions The following 4 modes are available to the PD75516 serial interface (channel 0). * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode (serial bus interface mode) 25 Selector P02/SO/SB0 Selector Busy/ Acknowledge Output Circuit Bus Release/ Command/ Acknowledge Detection Circuit RELD CMDD ACKD P01/SCK0 ACKT ACKE BSYE 26 P03/SI/SB1 P01 Output Latch Fig. 6-8 Serial Interface (Channel 0) Block Diagram Internal Bus 8/4 Bit Test CSIM0 8 8 8 Slave Address Register (SVA) Bit Manipulation (8) Match Signal (8) RELT CMDT SBIC Bit Test Addres Comparator Shift Register (SIO0) (8) SO0 SET CLR Latch D Q Serial Clock Counter INTCSI0 Control Circuit IRQCSI0 Set Signal INTCSI0 Serial Clock Control Circuit MPX fX/24 fX/2 6 fX/2 TOUT F/F (From Timer/ Event Counter) External SCK0 3 PD75516 PD75516 (2) Serial interface (channel 1) functions The following 2 modes are available to the PD75516 serial interface (channel 1). * Operation stop mode * 3-wire serial I/O mode 27 28 bit0 P83/SI1 P82/SO1 P81/SCK1 Fig. 6-9 Serial Interface (Channel 1) Block Diagram Internal Bus Bit Manipulation bit7 SIO1 Shift Register 1 (8) Serial Operating Mode Register 1 (8) Bit Manipulation 0 CSIM1 8 SIO1 Write Signal (Serial Start Signal) 7 8 Clear Overflow Serial Clock Counter (3) Set Serial Transfer End Flag (EOT) Clear R Q S MPX fx/24 fx/23 PD75516 PD75516 6.9 A/D CONVERTER The PD75516 incorporates an 8-bit resolution A/D converter with 8-channel analog inputs (AN0 to AN7). The A/D converter employs successive approximation. Fig. 6-10 A/D Converter Block Diagram Internal Bus 8 0 ADM6 ADM5 ADM4 SOC EOC ADM1 0 ADM 8 AN0 AN1 AN2 AN3 Multiplexer AN4 AN5 AN6 AN7 Simple & Hold Circuit Control Circuit + - Comparator SA Register (8) 8 Tap Decoder AV REF R/2 R R R R/2 AV SS 29 PD75516 6.10 BIT SEQUENTIAL BUFFER: 16 BITS The bit sequential buffer is a special data memory for bit manipulation. In particular it facilitates bit manipulation switch the address and bit specifications sequentially modified, and is thus useful for bit-wise processing of data comprising many bits. Fig. 6-11 Bit Sequential Buffer Format Address Bit Symbol FC3H 3 2 1 0 3 2 FC2H 1 BSB2 0 3 2 FC1H 1 BSB1 0 3 2 1 FC0H 0 BSB0 BSB3 L Register L=F L=C L=B INCS L L=8 L=7 L=4 L=3 DECS L L=0 Remarks In pmem.@L addressing, the specified bit shifts in accordance with the L register. 30 PD75516 7. INTERRUPT FUNCTIONS The PD75516 has nine types of interrupt sources and can generate multiple interrupts with priority order. 2 kind of test sources are also available. INT2 of these test sources is an edge detection testable input. The PD75516 interrupt control circuit has the following functions: * Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt enable flag (IExxx) and the interrupt master enable flag (IME). * Function of setting any interrupt start address. * Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS). * Interrupt request flag (IRQxxx) test function (Interrupt generation can be checked by software). * Standby mode release function (Interrupt to be released by interrupt enable flag can be selected). 31 INT2 /P12 KR0/P60 KR7/P73 Rising Edge Detection Circuit Falling Edge Detection Circuit Selector 32 Fig. 7-1 Interrupt Control Circuit Block Diagram Internal Bus 2 IM2 2 IM1 2 IM0 (IME) Interrupt Enable Flag (IEXXX) Decoder IRQBT IRQ4 IRQ0 IRQ1 IRQCSI0 IRQT0 IRQTPG IRQW IRQ2 Standby Release Signal Priority Control Circuit Vector Table Address Generator Circuit VRQn 4 IPS 2 IST Noise Eliminator INT4 /P00 INT0 /P10 INT1 /P11 INT BT Both Edges Detection Circuit Edge Detection Circuit Edge Detection Circuit INTCSI0 INTT0 INTTPG INTW IM2 PD75516 PD75516 8. STANDBY FUNCTIONS Two standby modes (STOP mode and HALT mode) are available for the PD75516 to decrease power consumption in the program standby mode. Table 8-1 Operation Status in Standby Mode STOP Mode Set instruction System clock when set STOP instruction Setting enabled only with main system clock. Oscillator stops only with main system clock. Operation stopped. Operation enabled only when external SCK0 input is selected for serial clock. Operation enabled only when external SCK1 input is selected for serial clock. Operation enabled only when TI0 pin input is specified for count clock. HALT Mode HALT instruction Setting enabled with either main system clock or subsystem clock. Stops only with CPU clock (Oscillation continued). Operation (IRQBT set at reference time intervals). Operation enabled when the main system clock oscillates or with external SCK0. Operation enabled only when the main system clock oscillates. Operation enabled only when the main system clock oscillates. Clock generator Basic interval timer Serial interface (channel 0) Serial interface (channel 1) Operating state Timer/event counter Watch timer Operation enabled only fXT is selected for Operation enabled. count clock. Operation stopped. Operation enabled only when the main system clock oscillates. Operation enabled only when the main system clock oscillates. INT1, 2, and 4 operation enabled. INT0 operation disabled. Operation stopped. Interrupt request signal or RESET input from operational hardware enabled by interrupt enable flag. A/D converter Timer/pulse generator Operation stopped. External interrupt CPU Release signal 33 PD75516 9. RESET FUNCTION The PD75516 is reset and the hardware is initialized as shown in Table 9-1 by RESET input. The reset operation timing is shown in Fig. 9-1. Fig. 9-1 Reset Operation by RESET Input Wait (31.3 ms/4.19 MHz) RESET Input Operating Mode or Standby Mode HALT Mode Operating Mode Internal Reset Operation Table 9-1 Status of Each Hardware after Resetting (1/2) Hardware RESET Input in Standby Mode Low-order 6 bits of program memory address 0000H are set in PC13 to 8 and the contents of address 0001H are set in PC7 to 0. Held 0 0 Bit 6 of program memory address 0000H is set in RBE, and bit 7 is set in MBE. Undefined Held* Held 0, 0 Undefined 0 0 FFH 0 0, 0 Held 0 0 RESET Input during Operation Program counter (PC) Same as the left Carry flag (CY) Skip flag (SK0 to 2) PSW Interrupt status flag (IST0, 1) Undefined 0 0 Bank enable flag (MBE, RBE) Same as the left Stack pointer (SP) Data memory (RAM) General register (X, A, H, L, D, E, B, C) Bank selection register (MBS, RBS) Basic interval timer Counter (BT) Mode register (BTM) Counter (T0) Timer/event counter Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer/pulse generator Watch timer Modulo register Mode register Mode register (WM) Undefined Undefined Undefined 0, 0 Undefined 0 0 FFH 0 0, 0 Held 0 0 * Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input. 34 PD75516 Table 9-1 Hardware Statuses after Reset (2/2) RESET Input in Standby Mode Held 0 0 Held 1 04H (EOC = 1) 7FH 0 0 0 Held 0 0 Reset (0) 0 0 0, 0, 0 Off Clear (0) 0 0 Held Hardware Shift register (SIO0) Operating mode register 0 (CSIM0) Serial interface (channel 0) SBI control register (SBIC) Slave address register (SVA) P01/SCK0 output latch Mode register (ADM), EOC A/D converter SA register Clock generator and clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM) Shift register (SIO1) Serial interface (channel 1) Operating mode register 1 (CSIM1) Serial transfer end flag (EOT) Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt function Interrupt master enable flag (IME) INT0, 1, and 2 mode registers (IM0, 1, 2) RESET Input during Operation Undefined 0 0 Undefined 1 04H (EOC = 1) 7FH 0 0 0 Undefined 0 0 Reset (0) 0 0 0, 0, 0 Off Clear (0) 0 0 Undefined Output buffer Output latch Digital port Input/output mode register (PMGA, B, C) Pull-up resistor specify register (POGA) Bit sequential buffer (BSB0 to BSB3) 35 PD75516 10. INSTRUCTION SET (1) Operand identifier and description Enter an operand in the operand column of each instruction using the description method relating to the operand identifier of the instruction (For details, refer to "RA75X Assembler Package User's Manual - Language Volume" (EEU-730)). If more than one description method is available, select one. Capital alphabetic letters, plus and minus signs are keywords. Describe them as they are. In the case of immediate data, describe appropriate numerical values or labels. Identifier reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L Description Method XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label* 2-bit immediate data or label FB0H to FBFH and FF0H to FFFH immediate data or labels FC0H to FFFH immediate data or labels 0000H to 3F7FH immediate data or labels 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (bit0 = 0) or label PORT0 to PORT15 IEBT, IECSI0, IET0, IE0, IE1, IE2, IE4, IEW, IETPG RB0 to RB3 MB0, MB1, MB2, MB15 * For 8-bit data processing, only even addresses can be specified. 36 PD75516 (2) Legend for operation description A : A register; 4-bit accumulator B : B register C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : C register D register E register H register L register X register Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Expanded register pair (XA') Expanded register pair (BC') Expanded register pair (DE') Expanded register pair (HL') Program counter Stack pointer Carry flag; Bit accumulator Program status word Memory bank enable flag Register bank enable flag Port n (n Interrupt Interrupt Interrupt = 0 to 15) master enable flag priority select register enable flag Register bank select register Memory bank select register Processor clock control register Address and bit delimiter : Contents addressed by xx : Hexadecimal data 37 PD75516 (3) Description of symbols in the addressing area column *1 *2 MB = MBE * MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 3F7FH addr = (Current PC) - 15 to (Current PC) - 1, (Current PC) + 2 to (Current PC) + 16 caddr = 0000H 1000H 2000H 3000H to to to to 0FFFH 1FFFH 2FFFH 3F7FH (PC13, 12 (PC13, 12 (PC13, 12 (PC13, 12 = = = = 00B) or 01B) or 10B) or 11B) Program Memory Addressing *3 Data Memory Addressing *4 *5 *6 *7 *8 *9 *10 faddr = 0000H to 07FFH taddr = 0020H to 007FH Remarks 1. 2. 3. 4. (4) MB indicates accessible memory bank. In *2, MB = 0 irrespective of MBE and MBS. In *4 and *5, MB = 15 irrespective of MBE and MBS. *6 to *10 indicate addressable areas. Description of the machine cycle column S indicates the number of machine cycles required for skip operation by an instruction having skip function. The S value varies as follows: * When not skipped ...................................................................................................... S = 0 * When 1-byte or 2-byte instructions are skipped .................................................... S = 1 * When 3-byte instructions are skipped (BR !adder, CALL !adder instruction) ... S = 2 Note GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle (= tCY) of CPU clock and three time periods are available according to PCC setting. 38 PD75516 Note 1 Mnemonic Operands A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL No. of Machine Bytes Cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 An4 reg1n4 XAn8 HLn8 rp2n8 A(HL) Operation Addressing Area Skip Condition Stack A Stack A Stack B *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH A(HL), then LL+1 A(HL), then LL-1 A(rpa1) XA(HL) (HL)A (HL)XA A(mem) XA(mem) (mem)A (mem)XA Areg XArp' reg1A rp'1XA A(HL) A(HL), then LL+1 A(HL), then LL-1 A(rpa1) XA(HL) A(mem) XA(mem) Areg1 XArp' XA(PC13-8+DE)ROM XA(PC13-8+XA)ROM MOV @HL, A @HL, XA A, mem Transfer XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA A, @HL A, @HL+ A, @HL- A, @rpa1 XCH XA, @HL A, mem XA, mem A, reg1 XA, rp' XA, @PCDE Note 2 MOVT XA, @PCXA *1 *1 *1 *2 *1 *3 *3 L=0 L = FH Note 1. Instruction Group 2. Table reference 39 PD75516 Note Mnemonic Operand CY, fmem.bit No. of Machine Bytes Cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 Operation CY(fmem.bit) CY(pmem7-2+L3-2.bit(L1-0)) CY(H+mem3-0.bit) (fmem.bit)CY (pmem7-2+L3-2.bit(L1-0))CY (H+mem3-0.bit)CY AA+n4 XAXA+n8 AA+(HL) XAXA+rp' rp'1rp'1+XA A, CYA+(HL)+CY XA, CYXA+rp'+CY rp'1, CYrp'1+XA+CY AA-(HL) XAXA-rp' rp'1rp'1-XA A, CYA-(HL)-CY XA, CYXA-rp'-CY rp'1, CYrp'1-XA-CY AA n4 AA (HL) XAXA rp' rp'1rp'1 XA AA AA n4 (HL) rp' XA Addressing Area *4 *5 *1 *4 *5 *1 Skip Condition Bit transfer CY, pmem.@L CY, @H+mem.bit MOV1 fmem.bit, CY pmem.@L, CY @H+mem.bit, CY A, #n4 XA, #n8 ADDS A, @HL XA, rp' rp'1, XA A, @HL ADDC XA, rp' rp'1, XA A, @HL SUBS XA, rp' rp'1, XA A, @HL SUBC XA, rp' rp'1, XA A, #n4 A, @HL AND XA, rp' rp'1, XA A, #n4 A, @HL OR XA, rp' rp'1, XA A, #n4 A, @HL XOR XA, rp' rp'1, XA carry carry *1 carry carry carry *1 *1 borrow borrow borrow Operation *1 *1 *1 XAXA rp'1rp'1 AA AA n4 (HL) rp' XA *1 XAXA rp'1rp'1 Note Instruction Group 40 PD75516 Note 1 Mnemonic Note 2 RORC NOT A A reg rp1 INCS Operands No. of Machine Bytes Cycle 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 Operation CYA0, A3CY, An-1An AA regreg+1 rp1rp1+1 (HL)(HL)+1 (mem)(mem)+1 regreg-1 rp'rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY1 CY0 Skip if CY = 1 CYCY Addressing Area Skip Condition Increment/decrement reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' @HL mem reg DECS rp' reg, #n4 @HL, #n4 Compare A, @HL SKE XA, @HL A, reg XA.rp' Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY CY = 1 Note 1. Instruction Group 2. Accumulator manipulation 41 PD75516 Note Mnemonic Operands mem.bit fmem.bit No. of Machine Bytes Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Operation (mem.bit)1 (fmem.bit)1 (pmem7-2+L3-2.bit(L1-0))1 (H+mem3-0.bit)1 (mem.bit)0 (fmem.bit)0 (pmem7-2+L3-2.bit(L1-0))0 (H+mem3-0.bit)0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 Skip if (H+mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2+L3-2.bit(L1-0)) = 0 Skip if (H+mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CYCY (fmem.bit) CYCY (pmem7-2+L3-2.bit(L1-0)) CYCY (H+mem3-0.bit) CYCY (fmem.bit) CYCY (pmem7-2+L3-2.bit(L1-0)) CYCY (H+mem3-0.bit) CYCY CYCY CYCY (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit) Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 Skip Condition SET1 pmem.@L @H + mem.bit mem.bit fmem.bit CLR1 pmem.@L @H+mem.bit mem.bit fmem.bit (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit)=1 SKT Memory bit manipulation pmem.@L @H+mem.bit mem.bit fmem.bit SKF pmem.@L @H+mem.bit fmem.bit SKTCLR pmem.@L @H+mem.bit CY, fmem.bit AND1 CY, pmem.@L CY, @H+mem.bit CY, fmem.bit OR1 CY, pmem.@L CY, @H+mem.bit CY, fmem.bit XOR1 CY, pmem.@L CY, @H+mem.bit PC13-0addr addr BR Branch !addr $addr BRCB BR !caddr PCDE PCXA 3 1 2 2 2 3 2 2 3 3 -- -- (Optimum instruction is selected from among BR !addr, BRCB !caddr and BR $addr by an assembler.) PC13-0addr PC13-0addr PC13-0PC13,12+caddr11-0 PC13-0PC13-8+DE PC13-0PC13-8+XA *6 *6 *7 *8 Note Instruction Group 42 PD75516 Note Mnemonic Operands No. of Machine Bytes Cycle Operation (SP-4) (SP-1) (SP-2)PC11-0 (SP-3) MBE, RBE, PC13, 12 PC13-0addr, SPSP-4 (SP-4) (SP-1) (SP-2)PC11-0 (SP-3) MBE, RBE, PC13, 12 PC13-000, faddr, SPSP-4 MBE, RBE, PC13, 12(SP+1) Addressing Area Skip Condition CALL !addr 3 3 *6 CALLF !faddr 2 2 *9 RET Subroutine stack control 1 3 PC11-0(SP) (SP+3) (SP+2) SPSP+4 MBE, RBE, PC13, 12(SP+1) PC11-0(SP) (SP+3) (SP+2) SPSP+4 then skip unconditionally PC13, 12(SP+1) PC11-0(SP) (SP+3) (SP+2) PSW(SP+4) (SP+5), SPSP+6 (SP-1) (SP-2)rp, SPSP-2 (SP-1)MBS, (SP-2)RBS, SPSP-2 rp(SP+1) (SP), SPSP+2 MBS(SP+1), RBS(SP), SPSP+2 IME(IPS.3)1 IExxx1 IME(IPS.3)0 IExxx0 APORTn (n = 0 to 15) (n = 4, 6) RETS 1 3+S Unconditional RETI 1 3 rp PUSH BS rp POP BS EI IExxx DI IExxx Input/output IN * A, PORTn XA, PORTn OUT * PORTn, A PORTn, XA HALT STOP NOP RBn SEL MBn 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 Interrupt control 2 2 2 2 2 2 2 2 2 1 2 2 XAPORTn+1, PORTn PORTnA (n = 2 to 7, 9 to 14) (n = 4, 6) PORTn+1, PORTnXA Special CPU control Set HALT Mode (PCC.21) Set STOP Mode (PCC.31) No Operation RBSn (n = 0 to 3) MBSn (n = 0, 1, 15) * MBE = 0 or MBE = 1 and MBE = 15 must be set for execution of IN/OUT instruction Instruction Group Note 43 PD75516 Note Mnemonic Operands No. of Machine Bytes Cycle Operation * TBR instruction PC13-0(taddr)4-0+(taddr+1) ---------------------------------------------------* TCALL instruction (SP-4)(SP-1)(SP-2)PC11-0 (SP-3) MBE, RBE, PC13, 12 PC13-0(taddr)5-0+(taddr+1) SPSP-4 ---------------------------------------------------* (taddr) (taddr+1) instruction executed in the case of instruction except TBR and TCALL instructions Addressing Area Skip Condition ------------------------ Special GETI * taddr 1 3 *10 -----------------------Depends on instructions referred to. * TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table. Instruction Group Note 44 PD75516 11. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 C) PARAMETER Power supply voltage SYMBOL VDD VI1 Input voltage VI2 Output voltage Output current high VO IOH 1 pin All pins 1 pin Peak value Effective value Peak value Total of ports 0, 2, 3 and 4 Output current low VOL* Total of ports 5 to 11 Effective value Peak value Effective value Peak value Effective value Except ports 4, 5 and 12 to 14 Ports 4, 5 and 12 to 14 Internal pull-up resistor Open-drain TEST CONDITIONS RATING -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to +11 -0.3 to VDD +0.3 -15 -30 30 15 100 60 100 60 40 25 -40 to +85 -65 to +150 UNIT V V V V V mA mA mA mA mA mA mA mA mA mA C C Total of ports 12 to 14 Operating temperature Storage temperature Topt Tstg * Calculate the effective value with the formula [Effective value] = [Peak value] x duty. OPERATING VOLTAGE PARAMETER A/D converter Power supply voltage Ambient temperature Power supply voltage Ambient temperature Power supply voltage Ambient temperature SYMBOL VDD Ta VDD Ta VDD Ta TEST CONDITIONS MIN. 3.5 -10 4.5 -40 2.7 -40 MAX. 6.0 +70 6.0 +85 6.0 +85 UNIT V C V C V C Timer/pulse generator Other circuits CAPACITANCE (Ta = 25 C, VDD = 0 V) TEST CONDITIONS MIN. TYP. MAX. 15 f = 1 MHz Unmeasured pin returned to 0 V 15 15 UNIT pF pF pF PARAMETER Input capacitance Output capacitance Input /output capacitance SYMBOL CI CO CIO 45 PD75516 MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fX) *1 TEST CONDITIONS VDD = Oscillation voltage range After VDD reaches the minimum value in the oscillation voltage range 1.0 VDD = 4.5 to 6.0 V 4.19 MIN. 1.0 TYP. MAX. 5.0*3 UNIT MHz X1 Ceramic resonator X2 C1 C2 Oscillation stabilization time *2 4 ms X1 Crystal resonator X2 Oscillator frequency (fX) *1 5.0*3 10 30 MHz ms ms C1 C2 Oscillation stabilization time *2 X1 External clock X2 X1 input frequency (fX) *1 1.0 5.0*3 MHz PD74HCU04 X1 high and low level widths (tXH, tXL) 100 500 ns SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fXT) *1 TEST CONDITIONS MIN. 32 TYP. 32.768 MAX. 35 UNIT kHz XT1 Crystal resonator XT2 R VDD = 4.5 to 6.0 V Oscillation stabilization time *2 1.0 2 s C3 C4 10 s XT1 XT2 XT1 input frequency (fXT) *1 32 100 kHz External clock Leave Open XT1 high and low level widths (tXTH, tXTL) 5 15 s * 1. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution time. 2. Time required for oscillation to become stabilized after VDD reaches MIN. of the oscillation voltage range or after STOP mode release. When the oscillator frequency is 4.19 MHz < fX 5.0 MHz, PPC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 s, and the specification MIN. value of 0.95 s will not be achieved. 3. 46 PD75516 Note When the system clock oscillator is used, the following points should be noted concerning wiring in the section enclosed by dots, in order to prevent the effects of wiring capacitance, etc. * Keep the wiring as short as possible. * Do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows. * Ensure that oscillator capacitor connection points are always at the same potential as VDD. Do not connect in a power supply pattern in which a high current flows. * Do not take a signal from the oscillator. The subsystem clock oscillator is designed to be a circuit with the low amplification factor to achieve low consumption current, with the result that it is more prone to misoperation due to noise than the main system clock oscillator. Therefore, when using the subsystem clock, special care is required for the wiring method. 5 RECOMMENDED OSCILLATOR CONSTANTS MAIN SYSTEM CLOCK : CERAMIC RESONATOR (Ta = -40 to +85 C) EXTERNAL CAPACITANCE (pF) C1 KBR-1000H Kyocera Corp. KBR-2.0MS KBR-4.0MS CSA 2.00MG CSA 4.00MGU CSA 4.19MG093 CSA 4.91MGU Murata Mfg. Co., Ltd. CSA 4.91MG CST 2.00MG CST 4.00MGU CST 4.19MG093 CST 4.91MGU CST 4.91MG CRHF 3.00 Toko, Inc. CRHF 4.19 On-chip 27 On-chip 27 3.0 3.0 6.0 On-chip On-chip 2.7 30 30 3.0 6.0 30 30 2.7 100 47 33 C2 100 47 33 2.7 6.0 OSCILLATION VOLTAGE RANGE (V) MIN. MAX. MANUFACTURER PRODUCT NAME REMARKS MAIN SYSTEM CLOCK : CRYSTAL RESONATOR (Ta = -20 to +70 C) EXTERNAL CAPACITANCE (pF) C1 Kinseki HC-49/U 27 C2 27 OSCILLATION VOLTAGE RANGE (V) MIN. 2.7 MAX. 6.0 MANUFACTURER PRODUCT NAME REMARKS 47 PD75516 DC CHARACTERISTICS (Ta = -40 to 85 C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL VIH1 VIH2 TEST CONDITIONS Ports 2, 3, 9 to 11, P80, P82 Ports 0, 1, 6, 7, 15, P81, P83, RESET Internal pull-up resistor Port 4, 5, 12 to 14 Open-drain MIN. 0.7 VDD 0.8 VDD 0.7 VDD 0.7 VDD VDD-0.5 0 0 0 VDD-1.0 VDD-0.5 TYP. MAX. VDD VDD VDD 10 VDD 0.3 VDD 0.2 VDD 0.4 UNIT V V V V V V V V V V Input voltage high VIH3 VIH4 VIL1 Input Voltage low VIL2 VIL3 Output voltage high VOH X1, X2, XT1 Ports 2 to 5, 9 to 14, P80, P82 Ports 0, 1, 6, 7, 15, P81, P83, RESET X1, X2, XT1 VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = 100 A Ports 3, 4, 5 VDD = 4.5 to 6.0V, IOL = 15 mA 0.4 2.0 0.4 0.5 V V V V VDD = 4.5 to 6.0 V, IOL = 1.6 mA Output voltage low VOL IOL = 400 A SB0, 1 ILIH1 VI = VDD Input leakage current high ILIH2 ILIH3 Input leakage current low ILIL1 VI = 0 V ILIL2 ILOH1 Output leakage current high ILOH2 VO = VDD VO = 9 V X1, X2, XT1 Except below Ports 4, 5, 12 to 14 (when open-drain) VI = 9 V X1, X2, XT1 Ports 4, 5, 12 to 14 (when open-drain) Except below Open-drain pull-up resistance 1k Except below 0.2 VDD 3 20 20 -3 -20 3 20 A A A A A A A Output leakage current low ILOL VO = 0 V Ports 0, 1, 2, 3, 6, 7 (except P00) VI = 0 V Ports 4, 5, 12 to 14 VO = VDD -2.0 V VO = 2 V VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% Port 9 15 30 15 10 20 70 40 40 -3 80 300 70 60 140 A k k k k k RU1 Internal pull-up resistor RU2 Internal pull-down resistor RD 48 PD75516 DC CHARACTERISTICS (Ta = -40 to 85 C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL IDD1 TEST CONDITIONS VDD = 5 V 10% *3 Operating 4.19 MHz crystal mode VDD = 3 V 10% *4 oscillation C1 = C2 = 22 pF VDD = 5 V 10% *2 HALT mode VDD = 3 V 10% 32.768 kHz crystal oscillation *5 Operating mode VDD = 3 V 10% MIN. TYP. 3 0.55 600 200 40 5 0.5 0.3 Ta = 25 C MAX. 9 1.5 1800 600 120 15 20 10 5 UNIT mA mA IDD2 Supply current *1 A A A A A A A IDD3 IDD4 HALT mode VDD = 3 V 10% VDD = 5 V 10% IDD5 XT1 = 0 V STOP mode VDD = 3 V 10% * 1. 2. 3. 4. 5. Current flowing to the internal pull-up resistor excluded. Subsystem clock oscillation also included. When operated in the high speed mode with the processor clock control register (PCC) set to 0011. When operated in the low speed mode with PCC = 0000. When operated on the subsystem clock after the main system clock oscillation stop with the system clock control register (SCC) set to 1001. 49 PD75516 AC CHARACTERISTICS (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V) (1) Basic Operation PARAMETER CPU clock cycle time (minimum instruction execution time = 1 machine cycle )*1 SYMBOL TEST CONDITIONS Operation with main system clock VDD = 4.5 to 6.0 V MIN. 0.95 3.8 114 0 0 TI0 input high and lowlevel widths tTIH, tTIL INT0 Interrupt input high and low-level widths tINTH, INT1, 2, 4 tINTL KR0-7 RESET low-level width tRSL 10 10 10 VDD = 4.5 to 6.0 V 0.48 1.8 *2 122 TYP. MAX. 64 64 125 1 275 UNIT s s s MHZ kHz tCY Operation with subsystem clock VDD = 4.5 to 6.0 V fTI TI0 input frequency s s s s s s * 1. The CPU clock () cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The cycle time tCY characteristics for power supply voltage VDD when the main system clock is in operation is shown below. tCY 70 64 60 6 5 4 Cycle Time tCY [s] 3 VS VDD (Main System Clock in Operation) 2. 2tCY or 128/fX is set by interrupt mode register (IM0) setting. Operation Guaranteed Range 2 1 0.5 0 1 2 3 4 5 6 Power Supply Voltage VDD [V] 50 PD75516 (2) Serial Transfer Operation (a) 2-wire and 3-wire serial I/O mode (SCK...Internal clock output) SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 1600 3800 TYP. MAX. UNIT ns ns ns ns ns ns 250 1000 ns ns PARAMETER SCK cycle time tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 RL = 1 k CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V (tKCY1/2)-50 (tKCY1/2)-150 150 400 SCK high and low level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK * RL and CL are SO output line load resistance and load capacitance, respectively. (b) 2-wire and 3-wire serial I/O mode (SCK...External clock input) SYMBOL tKCY2 3200 SCK high and low level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL2 tKH2 tSIK2 tKSI2 tKSO2 RL = 1 k CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 400 300 1000 ns ns ns ns ns ns ns TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. 800 TYP. MAX. UNIT ns PARAMETER * RL and CL are SO output line load resistance and load capacitance, respectively. 51 PD75516 (c) SBI mode (SCK...Internal clock output (master)) PARAMETER SCK cycle time SYMBOL tKCY3 TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 1600 3800 TYP. MAX. UNIT ns ns ns ns ns ns SCK high and low level widths SB0 and SB1 setup time (to SCK) tKL3 tKH3 tSIK3 tKSI3 tKSO3 VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 150 tKCY3/2 SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths RL = 1 k CL = 100 pF* VDD = 4.5 to 6.0 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns tKSB tSBK tSBL tSBH * RL and CL are SO output line load resistance and load capacitance, respectively. (d) SBI mode (SCK...External clock input (slave)) SYMBOL tKCY4 3200 ns ns ns ns ns 300 1000 ns ns ns ns ns ns tKL4 tKH4 tSIK4 tKSI4 tKSO4 RL = 1 k CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. UNIT ns PARAMETER SCK cycle time SCK high and low level widths SB0 and SB1 setup time (to SCK) SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths tKSB tSBK tSBL tSBH * RL and CL are SO output line load resistance and load capacitance, respectively. 52 PD75516 (3) A/D Converter (Ta = -10 to +70 C, VDD = 3.5 to 6.0 V, AVSS = VSS = 0V) PARAMETER Resolution Absolute accuracy*1 Conversion time*3 Sampling time*4 Analog input voltage Analog input impedance AVREF current SYMBOL TEST CONDITIONS MIN. 8 TYP. 8 MAX. 8 1.5 168/fX 44/fX UNIT bit LSB 2.5 V AVREF VDD*2 tCONV tSAMP VIAN RAN IREF AVSS 1000 1.0 s s V M AVREF 2.0 mA * 1. 2. Absolute accuracy with the quantization error (1/2 LSB) excluded. ADM1 is set as shown below with regard to the A/D converter reference voltage (AVREF). 2.5 V AVREF 0.6 V DD 0.65 VDD VDD (3.5 to 6.0V) ADM1 = 0 ADM1 = 1 3. When 0.6 VDD AVREF 0.65 VDD, the ADM1 can be set either to 0 or 1. This is the time form the execution of the conversion start instruction to the conversion end (EOC = 1) (operating at 40.1 s : fX = 4.19 MHz). 4. This is the time from the execution of the conversion start instruction to the sampling end (operating at 10.5 s : fX = 4.19 MHz). 53 PD75516 AC Timing Test Points (Except X1 and XT1 Inputs) 0.8 VDD 0.2 VDD Test Points 0.8 VDD 0.2 VDD Clock Timing 1/fX tXL tXH X1 Input V DD - 0.5 V 0.4 V 1/fXT tXTL tXTH XT1 Input VDD - 0.5 V 0.4 V TI0 Timing 1/fTI tTIL tTIH TI0 54 PD75516 Serial Transfer Timing 3-wire serial I/O mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 SI Input Data tKSO1 SO Output Data 2-wire serial I/O mode: tKCY2 tKL2 SCK tSIK2 tKSO2 tKSI2 tKH2 SB0,1 55 PD75516 Serial Transfer Timing Bus release signal transfer: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSBK tSIK3,4 tKSI3,4 SB0,1 tKSO3,4 Command signal transfer: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBK tSIK3,4 tKSI3,4 SB0,1 tKSO3,4 Interrupt Input Timing tINTL tINTH INT0,1,2,4 KR0-7 RESET Input Timing tRSL RESET 56 PD75516 DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to +85 C) PARAMETER Data retention power supply voltage Data retention power supply current *1 Release signal set time Oscillation stabilization wait time *2 SYMBOL VDDDR IDDDR tSREL VDDDR = 2.0 V TEST CONDITIONS MIN. 2.0 TYP. MAX. 6.0 UNIT V 0.1 0 10 A s Release by RESET tWAIT Release by interrupt request 2 /fX *3 17 ms ms * 1. 2. 3. Current to the internal pull-up resistor is not included. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation start. According to the setting of the basic interval timer mode register (BTM) (see below). Wait Time BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 (Values at fX = 4.19 MHz in parentheses) 0 1 1 1 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms) Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR STOP Instruction Execution tSREL RESET tWAIT 57 PD75516 Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT tSREL 58 PD75516 12. CHARACTERISTIC CURVES IDD vs VDD (Main System Clock : Crystal Oscillation) (Ta=25 C) 5000 High-Speed Mode PCC=0011 Medium-Speed Mode PCC=0010 Low-Speed Mode PCC=0000 1000 Main System Clock HALT Mode 500 Power Supply Current IDD [A] Subsystem Clock Operating Mode 100 50 Main System Clock STOP Mode + 32 kHz Oscillation and Subsystem Clock HALT Mode 10 X1 X2 XT1 XT2 R C4 Crystal Resonator 4.19 MHz Crystal Resonator 32.768 kHz 5 C1 C2 C3 1 0 1 2 3 4 5 6 7 Power Supply Voltage VDD [V] 59 PD75516 IDD vs VDD (Main System Clock : Crystal Oscillation) (Ta=25 C) 5000 High-Speed Mode PCC=0011 Medium-Speed Mode PCC=0010 Low-Speed Mode PCC=0000 1000 Main System Clock HALT Mode* 500 Power Supply Current IDD [A] Subsystem Clock Operating Mode 100 50 Main System Clock STOP Mode + 32 kHz Oscillation and Subsystem Clock HALT Mode 10 X1 X2 XT1 XT2 R C4 Ceramic Oscillator 4.19 MHz Crystal Resonator 32.768 kHz 5 C1 C2 C3 1 0 1 2 3 4 5 6 7 Power Supply Voltage VDD [V] * This is larger than the crystal oscillation by about 10%. 60 PD75516 I IDD vs VDD (Main System Clock : Crystal Oscillation) (Ta=25 C) 5000 High-Speed Mode PCC=0011 Medium-Speed Mode PCC=0010 Low-Speed Mode PCC=0000 1000 Main System Clock HALT Mode 500 Power Supply Current IDD [A] Subsystem Clock Operating Mode 100 50 Main System Clock STOP Mode + 32 kHz Oscillation and Subsystem Clock HALT Mode 10 X1 X2 XT1 XT2 R C4 Ceramic Oscillator 2.0 MHz Crystal Resonator 32.768 kHz 5 C1 C2 C3 1 0 1 2 3 4 5 6 7 Power Supply Voltage VDD [V] 61 PD75516 IDD vs VDD (Main System Clock : Crystal Oscillation) (Ta=25 C) 5000 1000 High-Speed Mode PCC=0011 Medium-Speed Mode PCC=0010 Low-Speed Mode PCC=0000 Main System Clock HALT Mode 500 Power Supply Current IDD [A] Subsystem Clock Operating Mode 100 50 Main System Clock STOP Mode + 32 kHz Oscillation and Subsystem Clock HALT Mode 10 X1 X2 XT1 XT2 R C4 Ceramic Oscillator 1.0 MHz Crystal Resonator 32.768 kHz 5 C1 C2 C3 1 0 1 2 3 4 5 6 7 Power Supply Voltage VDD [V] 62 PD75516 IDD VS fX (VDD = 5V, Ta = 25C) 3 X1 X2 IDD VS fX (VDD = 3V, Ta = 25C) 2 High-Speed Mode PCC = 0011 Medium-Speed Mode PCC = 0010 IDD [mA] Low-Speed Mode PCC = 0000 Main System Clock HALT Mode 0 1 2 3 4 5 fX [MHz] 0.2 Main System Clock HALT Mode 0.5 High-Speed Mode PCC = 0011 MediumSpeed Mode PCC = 0010 X1 X2 IDD [mA] 0.4 0.3 1 Low-Speed Mode PCC = 0000 0.1 0 1 2 3 4 5 fX [MHz] VOL VS IOL (Port 0, 2, 6, 7) (Ta = 25C) 40 40 VOL VS IOL (Port 3, 4 ,5) (Ta = 25C) 30 VDD = 6 V VDD = 5 V VDD = 4 V 30 VDD = 5 V VDD = 6V VDD = 4 V IOL [mA] 20 IOL [mA] 20 VDD = 3 V VDD = 3 V VDD = 2.7 V 10 10 VDD = 2.7 V 0 1 2 3 VOL [V] 4 5 0 1 2 3 VOL [V] 4 5 63 PD75516 VOH VS IOH 20 (Ta = 25C) 15 IOH [mA] VDD = 6 V VDD = 5 V VDD = 4 V 10 VDD = 3 V 5 VDD = 2.7 V 0 1 2 3 4 5 VDD - VOH [V] 64 PD75516 13. PACKAGE INFORMATION 80 PIN PLASTIC QFP (14x20) A B 64 65 41 40 detail of lead end D C S 80 1 25 24 F G H IM J K P N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. L P80GF-80-3B9-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 0.8 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.15 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.006 0.106 0.004 0.004 0.119 MAX. +0.008 M 55 Q 65 PD75516 5 14. RECOMMEDED SOLDERING CONDITIONS The PD75516 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions for the surface mounting type, refer to the document "Semiconductor Device Mount Technology" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 4-1 Surface Mount Type Soldering Conditions PD75516GF-xxx-3B9: 80-pin plastic QFP (14 x 20 mm) Soldering Method Soldering Conditions Package peak temperature: 230 C Duration: 30 sec. max. (at 210 C or above) Number of times: Once Package peak temperature: 215 C Duration: 40 sec. max. (at 200 C or above) Number of times: Once Solder bath temperature: 260 C or less Duration: 10 sec. max. Number of times: Once Preheating temperature: 120 C max. (package surface temperature) Pin part temperature: 300 C or less Duration: 3 sec. max. (Per device side) Recommended Condition Symbol Infrared reflow IR30-00-1 VPS VP15-00-1 Wave Soldering WS60-00-1 Pin part heating Note Use of more than one soldering method should be avoided (except in the case of pin part heating). For Your Information Products to improve the recommended soldering conditions are available. (Improvements: Extension of the infrared reflow peak temperature to 235oC, doubled frequency, increased life, etc.) For further details, consult our sales personnel. - 66 PD75516 APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for the development of systems using the PD75516. IE-75000-R *1 IE-75001-R IE-75000-R-EM *2 Hardware EP-75516GF-R EV-9200G-80 PG-1500 PA-75P516GF IE control program Software PG-1500 controller RA75X relocatable assembler Host machine PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A *3) IBM PC/ATTM (PC DOSTM Ver. 3.1) In-circuit emulator for use with the 75X series Emulation board for use with the IE-75000-R and the IE-75001-R Emulation probe for use with the PD75516. 80-pin conversion socket EV-9200G-80 included PROM programmer Connect to PG-1500 with PROM programmer adapter for use with the PD75P516GF * 1. Maintenance product 2. Not a built-in component in the IE-75001-R 3. Ver. 5.00/5.00A has a task swapping function, which cannot be used with this software. Refer to the "75X Series Selection Guide" (IF-151) for third-party development tools. Remarks 67 PD75516 5 APPENDIX B. RELATED DOCUMENTS Device Related Documents Document Name User's Manual Instruction Application Table Basic Volume Application Note A/D Converter Volume 75X Series Selection Guide IEA-630 IF-151 Document Number IEM-5049 IEM-5036 IEM-5104 Development Tools Documents Document Name IE-75000-R/IE-75000-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75516GF-R User's Manual PG-1500 User's Manual Software Operation Volume RA75X Assembler Package User's Manual Language Volume PG-1500 Controller User's Manual EEU-730 EEU-704 Document Number EEU-846 EEU-673 EEU-703 EEU-651 EEU-731 Other Documents Document Name Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Device Quality Guide Guarantee Guide Microcomputer Related Products Guide - Other Manufacturers Volume Document Number IEI-635 IEI-1207 IEI-1209 IEM-5068 MEM-539 MEI-603 MEI-604 Note The information in these related documents is subject to change without notice. For design purpose, etc., be sure to use the latest ones. 68 PD75516 69 PD75516 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Special Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of MicroSoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. |
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