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| DATA SHEET MOS INTEGRATED CIRCUIT PD75P0016 4-BIT SINGLE-CHIP MICROCONTROLLER The PD75P0016 replaces the PD750008's internal mask ROM with a one-time PROM and features expanded ROM capacity. Because the PD75P0016 supports programming by users, it is suitable for use in prototype testing for system development using the PD750004, 750006, or 750008 products, and for use in small-lot production. Detailed information about product features and specifications can be found in the following document PD750008 User's Manual: U10740E FEATURES * Compatible with PD750008 * Memory capacity: * PROM : 16384 x 8 bits * RAM : 512 x 4 bits * Can operate in same power supply voltage as the mask ROM version PD750008 * VDD = 2.2 to 5.5 V * Supports QTOPTM microcontroller Remark QTOP Microcontroller is the general name for a total support service that includes imprinting, marking, screening, and verifying one-time PROM single-chip microcontrollers offered by NEC. ORDERING INFORMATION Part number Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 44-pin plastic QFP (10 x 10 mm, 0.8-mm pitch) ROM (x 8 bits) 16384 16384 PD75P0016CU PD75P0016GB-3BS-MTX Caution On-chip pull-up resistors by mask option cannot be provided. The information in this document is subject to change without notice. Document No. U10328EJ3V1DS00 (3rd edition) Date Published August 2000 N CP(K) Printed in Japan The mark shows major revised points. (c) 1995 PD75P0016 FUNCTION LIST Item Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (main system clock: at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: at 6.0 MHz operation) * 122 s (subsystem clock: at 32.768 kHz operation) PROM RAM General register I/O port CMOS input CMOS I/O N-ch open drain I/O Total Timer 16384 x 8 bits 512 x 4 bits * In 4-bit operation: 8 x 4 banks * In 8-bit operation: 4 x 4 banks 8 18 8 34 4 channels * * * * Serial interface 8-bit timer/event counter: 1 channel 8-bit timer counter: 1 channel Basic interval timer/watchdog timer: 1 channel Watch timer: 1 channel Connection of on-chip pull-up resistor specifiable by software: 7 Direct LED drive capability Connection of on-chip pull-up resistor specifiable by software: 18 Direct LED drive capability 13 V withstand voltage On-chip memory * 3-wire serial I/O mode ... Switching of MSB/LSB-first * 2-wire serial I/O mode * SBI mode 16 bits * , 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) * 2, 4, 32 kHz (main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) External: 3 Internal: 4 External: 1 Internal: 1 * Main system clock oscillation ceramic/crystal oscillation circuit * Subsystem clock oscillation crystal oscillation circuit STOP/HALT mode TA = -40 to +85C VDD = 2.2 to 5.5 V 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 44-pin plastic QFP (10 x 10 mm, 0.8-mm pitch) Bit sequential buffer (BSB) Clock output (PCL) Buzzer output (BUZ) Vectored interrupt Test input System clock oscillation circuit Standby function Operating ambient temperature Supply voltage Package 2 Data Sheet U10328EJ3V1DS00 PD75P0016 TABLE OF CONTENTS 1. 2. 3. PIN CONFIGURATION ........................................................................................................................ 4 BLOCK DIAGRAM ............................................................................................................................. 6 PIN FUNCTIONS ................................................................................................................................ 7 3.1 3.2 3.3 3.4 Port Pins ..................................................................................................................................................... 7 Non-port Pins ............................................................................................................................................. 8 I/O Circuits for Pins ................................................................................................................................... 9 Handling of Unused Pins ........................................................................................................................ 11 4. SWITCHING BETWEEN MK I AND MK II MODES .......................................................................... 12 4.1 4.2 Differences between Mk I Mode and Mk II Mode ................................................................................... 12 Setting of Stack Bank Selection (SBS) Register ................................................................................... 13 5. 6. 7. 8. DIFFERENCES BETWEEN PD75P0016 AND PD750004, 750006, AND 750008 ...................... 14 MEMORY CONFIGURATION ........................................................................................................... 15 INSTRUCTION SET .......................................................................................................................... 17 ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 28 8.1 8.2 8.3 8.4 Operation Modes for Program Memory Write/Verify ............................................................................ 28 Steps in Program Memory Write Operation .......................................................................................... 29 Steps in Program Memory Read Operation ........................................................................................... 30 One-Time PROM Screening .................................................................................................................... 31 9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 32 10. CHARACTERISTIC CURVES (REFERENCE VALUE) .................................................................... 46 11. PACKAGE DRAWINGS .................................................................................................................... 48 12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50 APPENDIX A. FUNCTION LIST OF PD75008, 750008, 75P0016 ....................................................... 51 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 53 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 57 Data Sheet U10328EJ3V1DS00 3 PD75P0016 1. PIN CONFIGURATION (Top View) * 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) PD75P0016CU XT1 XT2 RESET X1 X2 P33/MD3 P32/MD2 P31/MD1 P30/MD0 P81 P80 P03/SI/SB1 P02/SO/SB0 P01/SCK P00/INT4 P13/TI0 P12/INT2 P11/INT1 P10/INT0 VPPNote VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS P40/D0 P41/D1 P42/D2 P43/D3 P50/D4 P51/D5 P52/D6 P53/D7 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ Note Directly connect VPP to VDD in the normal operation mode. * 44-pin plastic QFP (10 x 10 mm, 0.8-mm pitch) PD75P0016GB-3BS-MTX P73/KR7 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ VDD VPPNote P10/INT0 P11/INT1 P12/INT2 NC P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 P53/D7 P52/D6 P51/D5 P50/D4 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 P13/TI0 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P80 P81 P30/MD0 P31/MD1 P32/MD2 P33/MD3 NC P43/D3 P42/D2 P41/D1 P40/D0 VSS XT1 XT2 RESET Note Directly connect VPP to VDD in the normal operation mode. 4 Data Sheet U10328EJ3V1DS00 X1 X2 PD75P0016 PIN IDENTIFICATIONS P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80, P81 KR0-KR7 VDD VSS VPP NC : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Port7 : Port8 : Key Return 0-7 : Positive Power Supply : Ground : Programming Power Supply : No Connection SCK SI SO SB0, SB1 RESET TI0 PTO0, PTO1 BUZ PCL INT0, 1, 4 INT2 X1, X2 XT1, XT2 MD0-MD3 D0-D7 : Serial Clock : Serial Input : Serial Output : Serial Data Bus 0,1 : Reset : Timer Input 0 : Programmable Timer Output 0, 1 : Buzzer Clock : Programmable Clock : External Vectored Interrupt 0, 1, 4 : External Test Input 2 : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 : Mode Selection 0-3 : Data Bus 0-7 Data Sheet U10328EJ3V1DS00 5 PD75P0016 2. BLOCK DIAGRAM BASIC INTERVAL TIMER/ WATCHDOG TIMER BIT SEQ. BUFFER (16) PROGRAM COUNTER (14) CY ALU INTBT TI0/P13 PTO0/P20 8-BIT TIMER/EVENT COUNTER #0 INTT0 TOUT0 SP (8) SBS PORT0 4 P00-P03 BANK PORT1 4 P10-P13 PTO1/P21 8-BIT TIMER COUNTER #1 INTT1 PORT2 GENERAL REGISTER PORT3 PROGRAM MEMORY (PROM) 16384 x 8 BITS 4 P20-P23 4 P30/MD0-P33/MD3 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI TOUT0 DECODE AND CONTROL DATA MEMORY (RAM) 512 x 4 BITS PORT4 4 P40/D0-P43/D3 PORT5 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60KR7/P73 INTERRUPT CONTROL 8 4 P50/D4-P53/D7 PORT6 4 P60-P63 PORT7 fx/2N WATCH TIMER INTW CLOCK CLOCK OUTPUT DIVIDER CONTROL CPU CLOCK SYSTEM CLOCK GENERATOR SUB MAIN PORT8 STAND BY CONTROL 4 P70-P73 BUZ/P23 2 P80, P81 PCL/P22 XT1XT2 X1 X2 VPP VDD VSS RESET 6 Data Sheet U10328EJ3V1DS00 PD75P0016 3. PIN FUNCTIONS 3.1 Port Pins Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P40 Note 2 P41 Note 2 P42 Note 2 P43 Note 2 P50 Note 2 P51 Note 2 P52 Note 2 P53 Note 2 P60 P61 P62 P63 P70 P71 P72 P73 P80 P81 I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I Shared by INT4 SCK SO/SB0 SI/SB1 INT0 INT1 INT2 TI0 PTO0 PTO1 PCL BUZ MD0 MD1 MD2 MD3 D0 D1 D2 D3 D4 D5 D6 D7 KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 -- -- This is a 2-bit I/O port (PORT8). On-chip pull-up resistor connections are softwarespecifiable in 2-bit units. x Input E-B This is a 4-bit I/O port (PORT7). On-chip pull-up resistor connections are softwarespecifiable in 4-bit units. Input Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs. 2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed. Data Sheet U10328EJ3V1DS00 7 PD75P0016 3.2 Non-port Pins Pin name TI0 PTO0 PTO1 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 I I I/O I/O I O Shared by P13 P20 P21 P22 P23 P01 P02 P03 P00 P10 Function External event pulse input to timer/event counter Timer/event counter output Timer counter output Clock output Outputs any frequency (for buzzer or system clock trimming) Serial clock I/O Serial data output Serial data bus I/O Serial data input Serial data bus I/O Edge-triggered vectored interrupt input (Detects both rising and falling edges). Edge-triggered vectored interrupt input With noise eliminator (detected edge is selectable). /asynch selectable INT0/P10 can select noise elimination circuit. Asynch Rising edge-triggered testable input Falling edge-triggered testable input Falling edge-triggered testable input Ceramic/crystal resonator connection for main system clock. If using an external clock, input it to X1 and input the inverted clock to X2. Crystal resonator connection for subsystem clock. If using an external clock, input it to XT1 and input the inverted clock to X2. XT1 can be used as a 1-bit (test) input. System reset input (low level active) Mode selection for program memory (PROM) write/verify. Data bus pin for program memory (PROM) write/verify. Asynch Input Input -- INT1 INT2 KR0-KR3 KR4-KR7 X1 X2 XT1 XT2 RESET MD0-MD3 D0-D3 D4-D7 VPP Note 2 -- I I I -- I -- I I I/O P11 P12 P60-P63 P70-P73 -- -- -- -- -- P30-P33 P40-P43 P50-P53 -- -- Input Input E-B M-E Programmable voltage supply in program memory (PROM) write/verify mode. In normal operation mode, connect directly to VDD. Apply +12.5 V in PROM write/verify mode. Positive power supply Ground potential -- -- VDD VSS -- -- -- -- -- -- -- -- Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs. 2. During normal operation, the VPP pin will not operate normally unless connected to VDD pin. 8 Data Sheet U10328EJ3V1DS00 PD75P0016 3.3 I/O Circuits for Pins The I/O circuits for the PD75P0016's pin are shown in schematic diagrams below. TYPE A TYPE D VDD VDD Data P-ch IN Output disable N-ch P-ch OUT N-ch CMOS standard input buffer TYPE B Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). TYPE E-B VDD P.U.R. P.U.R. enable P-ch IN Data Type D Output disable IN/OUT Schmitt trigger input with hysteresis characteristics. Type A P.U.R. : Pull-Up Resistor TYPE B-C VDD P.U.R. P.U.R. enable TYPE F-A VDD P.U.R. P.U.R. enable Data IN Type D Output disable P-ch P-ch IN/OUT P.U.R. : Pull-Up Resistor Type B P.U.R. : Pull-Up Resistor (Continued) Data Sheet U10328EJ3V1DS00 9 PD75P0016 TYPE F-B VDD IN/OUT P.U.R. P.U.R. enable output disable (P) data output disable output disable (N) Note P.U.R. : Pull-Up Resistor N-ch Voltage limitation (+13 V) circuit VDD P-ch IN/OUT Input instruction P-ch data output disable VDD P-ch P.U.R.Note N-ch (+13 V) TYPE M-E Pull-up resistor that operates only when an input instruction has been executed. (Current flows from VDD to the pins when at low level) TYPE M-C VDD P.U.R. P.U.R. enable P-ch IN/OUT data output disable N-ch P.U.R. : Pull-Up Resistor 10 Data Sheet U10328EJ3V1DS00 PD75P0016 3.4 Handling of Unused Pins Table 3-1. Handling of Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ P30/MD0-P33/MD3 P40/D0-P43/D3 P50/D4-P53/D7 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80, P81 XT1Note XT2 VPP Note Recommended connection Connect to VSS or VDD Individually connect to VSS or VDD via resistor Connect to VSS Connect to VSS or VDD : individually connect to VSS or VDD via resistor Output mode : open Input mode Connect to VSS : individually connect to VSS or VDD via resistor Output mode : open Input mode Connect to VSS Open Make sure to connect directly to VDD Note When the subsystem clock is not used, set SOS. 0 to 1 (not to use the internal feedback resistor). Data Sheet U10328EJ3V1DS00 11 PD75P0016 4. SWITCHING BETWEEN MK I AND MK II MODES Setting a stack bank selection (SBS) register for the PD75P0016 enables the program memory to be switched between the Mk I mode and the Mk II mode. This capability enables the evaluation of the PD750004, 750006, or 750008 using the PD75P0016. When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of PD750004, 750006, and 750008) When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of PD750004, 750006, and 750008) 4.1 Differences between Mk I Mode and Mk II Mode Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the PD75P0016. Table 4-1. Differences between Mk I Mode and Mk II Mode Item Program counter Program memory (bytes) Data memory (bits) Stack Stack bank Stack bytes Instruction Instruction BRA !addr1 CALLA !addr1 CALL !addr PC13-0 16384 512 x 4 Selectable from memory banks 0 and 1 2 bytes None 3 machine cycles 2 machine cycles Mk I mode of PD750004, 750006, and 750008 3 bytes Provided 4 machine cycles 3 machine cycles Mk II mode of PD750004, 750006, and 750008 Mk I mode Mk II mode execution time CALLF !faddr Supported mask ROM versions and mode Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This mode enhances the software compatibility with products which have more than 16K bytes. When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode. 12 Data Sheet U10328EJ3V1DS00 PD75P0016 4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 100xB Note at the beginning of the program. When using the Mk II mode, be sure to initialize it to 000xB Note. Note Set the desired value for x. Figure 4-1. Format of Stack Bank Selection Register Address F84H 3 SBS3 2 SBS2 1 SBS1 0 SBS0 Symbol SBS Stack area specification 0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Setting prohibited 0 Be sure to set 0 for bit 2. Mode selection specification 0 1 Mk II mode Mk I mode Caution SBS3 is set to "1" after RESET input, and consequently the CPU operates in the Mk I mode. When using instructions for the Mk II mode, set SBS3 to "0" to enter the Mk II mode before using the instructions. Data Sheet U10328EJ3V1DS00 13 PD75P0016 5. DIFFERENCES BETWEEN PD75P0016 AND PD750004, 750006, AND 750008 The PD75P0016 replaces the internal mask ROM in the PD750004, 750006, and 750008 with a one-time PROM and features expanded ROM capacity. The PD75P0016's Mk I mode supports the Mk I mode in the PD750004, 750006, and 750008 and the PD75P0016's Mk II mode supports the Mk II mode in the PD750004, 750006, and 750008. Table 5-2 lists differences among the PD75P0016 and the PD750004, 750006, and 750008. Be sure to check the differences between corresponding versions beforehand, especially when a PROM version is used for debugging or prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production. Please refer to the PD750008 User's Manual (U10740E) for details on CPU functions and on-chip hardware. Table 5-1. Differences between PD75P0016 and PD750004, 750006, and 750008 Item Program counter Program memory (bytes) Data memory (x 4 bits) Mask options Pull-up resistor for port 4 and port 5 Wait time when RESET Feedback resistor for subsystem clock Pin connection Pins 6-9 (CU) Pins 23-26 (GB) Pin 20 (CU) Pin 38 (GB) Pins 34-37 (CU) Pins 8-11 (GB) Pins 38-41 (CU) Pins 13-16 (GB) Other Noise resistance and noise radiation may differ due to the different circuit complexities and mask layouts. P43-P40 P43/D3-P40/D0 P53-P50 P53/D7-P50/D4 IC VPP PD750004 12-bit Mask ROM 4096 512 PD750006 13-bit Mask ROM 6144 PD750008 PD75P0016 14-bit Mask ROM 8192 One-time PROM 16384 Yes (On-chip/not on-chip can be specified.) Yes (217/fx or 215/fx) Note Yes (can select usable or unusable.) P33-P30 No (On-chip not possible) No (fixed at 215/fx) Note No (usable) P33/MD3-P30/MD0 Note 217/fx : 21.8 ms @ 6.0 MHz, 31.3 ms @ 4.19 MHz 215/fx : 5.46 ms @ 6.0 MHz, 7.81 ms @ 4.19 MHz Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using a mask ROM version instead of the PROM version for processes between prototype development and full production, be sure to fully evaluate the CS of the mask ROM version (not ES). 14 Data Sheet U10328EJ3V1DS00 PD75P0016 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map 7 0000H MBE 6 RBE 0 Internal reset start address (higher 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (higher 6 bits) INTBT/INT4 start address (lower 8 bits) CALLF !faddr instruction entry address 0004H MBE RBE INT0 start address (higher 6 bits) INT0 start address (lower 8 bits) 0006H MBE RBE INT1 start address (higher 6 bits) INT1 start address (lower 8 bits) BRCB !caddr instruction branch address 0008H MBE RBE INTCSI start address (higher 6 bits) INTCSI start address (lower 8 bits) 000AH MBE RBE INTT0 start address (higher 6 bits) INTT0 start address (lower 8 bits) 000CH MBE RBE INTT1 start address (higher 6 bits) INTT1 start address (lower 8 bits) Branch address for the following instructions * BR BCDE * BR BCXA * BR !addr * CALL !addr * BRA !addr1Note * CALLA !addr1 Note Branch/call address by GETI BR $addr instruction relative branch address (-15 to -1, +2 to +16) 0020H Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address Note Can be used only at Mk II mode. Remark For instructions other than those noted above, the "BR PCDE" and "BR PCXA" instructions can be used to branch to addresses with changes in the PC's lower 8 bits only. Data Sheet U10328EJ3V1DS00 15 PD75P0016 Figure 6-2. Data Memory Map Data memory General register area 000H (32 x 4) 01FH 020H Memory bank Stack area Note 256 x 4 (224 x 4) 0 Data area static RAM (512 x 4) 0FFH 100H 256 x 4 1 1FFH Unimplemented F80H 128 x 4 Peripheral hardware area FFFH 15 Note For the stack area, one memory bank can be selected from memory bank 0 or 1. 16 Data Sheet U10328EJ3V1DS00 PD75P0016 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's operand representations (for further description, refer to the RA75X Assembler Package User's Manual [EEU-1363]). When there are several codes, select and use just one. Upper-case letters, and + and - symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Instead of mem, fmem, pmem, bit, etc, a register flag symbol can be described as a label descriptor. (For further description, refer to the PD750008 User's Manual [U10740E]) Labels that can be entered for fmem and pmem are restricted. Representation reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label Note 2-bit immediate data or label FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-3FFFH immediate data or label 0000H-3FFFH immediate data or label (in Mk II mode only) 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (however, bit0 = 0) or label PORT0-PORT8 IEBT, IECSI, IET0, IET1, IE0-IE2, IE4, IEW RB0-RB3 MB0, MB1, MB15 Coding format Note When processing 8-bit data, only even addresses can be specified. Data Sheet U10328EJ3V1DS00 17 PD75P0016 (2) Operation legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS IExxx RBS MBS PCC . (xx) xxH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Register pair (XA); 8-bit accumulator : Register pair (BC) : Register pair (DE) : Register pair (HL) : Expansion register pair (XA') : Expansion register pair (BC') : Expansion register pair (DE') : Expansion register pair (HL') : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority select register : Interrupt enable flag : Register bank select register : Memory bank select register : Processor clock control register : Delimiter for address and bit : Contents of address xx : Hexadecimal data PORTn : Port n (n = 0 to 8) 18 Data Sheet U10328EJ3V1DS00 PD75P0016 (3) Description of symbols used in addressing area MB = MBE * MBS *1 MBS = 0, 1, 15 *2 MB = 0 MBE = 0 *3 MBE = 1 : MB = MBS MBS = 0, 1, 15 *4 *5 *6 *7 (Current PC) +2 to (Current PC) +16 caddr = 0000H-0FFFH (PC13, 12 = 00B) or 1000H-1FFFH (PC13, 12 = 01B) or *8 2000H-2FFFH (PC13, 12 = 10B) or 3000H-3FFFH (PC13, 12 = 11B) *9 *10 *11 faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-3FFFH (Mk II mode only) Program memory addressing MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-3FFFH addr, addr1 = (Current PC) -15 to (Current PC) -1 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) Data memory addressing Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas. Data Sheet U10328EJ3V1DS00 19 PD75P0016 (4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. * No skip .......................................................................... S = 0 * Skipped instruction is 1-byte or 2-byte instruction ......... S = 1 * Skipped instruction is 3-byte instruction Note ................. S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle. One machine cycle equals one cycle (= tCY) of the CPU clock . Use the PCC setting to select among four cycle times. 20 Data Sheet U10328EJ3V1DS00 PD75P0016 Group Transfer Mnemonic MOV Operand A, # n4 reg1, # n4 XA, # n8 HL, # n8 rp2, # n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA No. of Machine bytes cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 1 2 2 2 2 1 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) Operation Addressing area Skip condition String-effect A String-effect A String-effect B *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH 2 + S A (HL), then L L + 1 2 + S A (HL), then L L - 1 1 2 1 2 2 2 2 2 2 2 2 2 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) XCH A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH 2 + S A (HL), then L L + 1 2 + S A (HL), then L L - 1 1 2 2 2 1 2 3 3 3 3 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC13-8 + DE)ROM XA (PC13-8 + XA)ROM XA (BCDE)ROM Note XA (BCXA)ROM Note Table reference MOVT XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA *6 *6 Note As for the B register, only the lower 2 bits are valid. Data Sheet U10328EJ3V1DS00 21 PD75P0016 Group Bit transfer Mnemonic MOV1 Operand CY, fmem.bit CY, pmem.@L CY, @H + mem.bit fmem.bit, CY pmem.@L, CY @H + mem.bit, CY No. of Machine bytes cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 Operation CY (fmem.bit) CY (pmem7-2 + L3-2.bit(L1-0)) CY (H + mem3-0.bit) (fmem.bit) CY (pmem7-2 + L3-2.bit(L1-0)) CY (H + mem3-0.bit) CY Addressing area *4 *5 *1 *4 *5 *1 Skip condition Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA 1 + S A A + n4 2 + S XA XA + n8 1 + S A A + (HL) 2 + S XA XA + rp' 2 + S rp'1 rp'1 + XA 1 2 2 A, CY A + (HL) + CY XA, CY XA + rp' + CY rp'1, CY rp'1 + XA + CY *1 *1 *1 carry carry carry carry carry ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA 1 + S A A - (HL) 2 + S XA XA - rp' 2 + S rp'1 rp'1 - XA 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 A, CY A - (HL) - CY XA, CY XA - rp' - CY rp'1, CY rp'1 - XA - CY A A ^ n4 A A ^ (HL) XA XA ^ rp' rp'1 rp'1 ^ XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA borrow borrow borrow SUBC A, @HL XA, rp' rp'1, XA *1 AND A, #n4 A, @HL XA, rp' rp'1, XA *1 OR A, #n4 A, @HL XA, rp' rp'1, XA *1 XOR A, #n4 A, @HL XA, rp' rp'1, XA *1 22 Data Sheet U10328EJ3V1DS00 PD75P0016 Group Accumulator manipulate Increment/ decrement Mnemonic RORC NOT INCS A A reg rp1 Operand No. of Machine bytes cycle 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 1 2 Operation CY A0, A3 CY, An-1 An AA Addressing area Skip condition 1 + S reg reg + 1 1 + S rp1 rp1 + 1 2 + S (HL) (HL) + 1 2 + S (mem) (mem) + 1 1 + S reg reg - 1 2 + S rp' rp' - 1 2 + S Skip if reg = n4 2 + S Skip if (HL) = n4 1 + S Skip if A = (HL) 2 + S Skip if XA = (HL) 2 + S Skip if A = reg 2 +S 1 1 Skip if XA = rp' CY 1 CY 0 *1 *1 *1 *1 *3 reg = 0 rp1 = 00H (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' @HL mem DECS reg rp' Compare SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag manipulate SET1 CLR1 SKT NOT1 CY CY CY CY 1 + S Skip if CY = 1 1 CY CY CY = 1 Data Sheet U10328EJ3V1DS00 23 PD75P0016 Group Memory bit manipulate Mnemonic SET1 Operand mem.bit fmem.bit pmem.@L @H + mem.bit No. of Machine bytes cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (mem.bit) 1 (fmem.bit) 1 Operation Addressing area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 Skip condition (pmem7-2 + L3-2.bit(L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit(L1-0)) 0 (H + mem3-0.bit) 0 CLR1 mem.bit fmem.bit pmem.@L @H + mem.bit SKT mem.bit fmem.bit pmem.@L @H + mem.bit 2 + S Skip if(mem.bit) = 1 2 + S Skip if(fmem.bit) = 1 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1 2 + S Skip if(H + mem3-0.bit) = 1 2 + S Skip if(mem.bit) = 0 2 + S Skip if(fmem.bit) = 0 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 0 2 + S Skip if(H + mem3-0.bit) = 0 2 + S Skip if(fmem.bit) = 1 and clear 2 + S Skip if(pmem7-2 + L3-2.bit (L1-0)) = 1 and clear 2 + S Skip if(H + mem3-0.bit) = 1 and clear 2 2 2 2 2 2 2 2 2 CY CY ^ (fmem.bit) CY CY ^ (pmem7-2 + L3-2.bit(L1-0)) CY CY ^ (H + mem3-0.bit) CY CY v (fmem.bit) CY CY v (pmem7-2 + L3-2.bit(L1-0)) CY CY v (H + mem3-0.bit) CY CY v (fmem.bit) CY CY v (pmem7-2 + L3-2.bit(L1-0)) CY CY v (H + mem3-0.bit) (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H + mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 SKF mem.bit fmem.bit pmem.@L @H + mem.bit SKTCLR fmem.bit pmem.@L @H + mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H + mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H + mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H + mem.bit 24 Data Sheet U10328EJ3V1DS00 PD75P0016 Group Branch Mnemonic BR Note 1 Operand addr No. of Machine bytes cycle -- -- Operation PC13-0 addr Assembler selects the most appropriate instruction among the following: * BR !addr * BRCB !caddr * BR $addr PC13-0 addr1 Assembler selects the most appropriate instruction among the following: * BRA !addr1 * BR !addr * BRCB !caddr * BR $addr1 PC13-0 addr PC13-0 addr PC13-0 addr1 PC13-0 PC13-8 + DE PC13-0 PC13-8 + XA PC13-0 BCDE Note 2 PC13-0 BCXA Note 2 PC13-0 addr1 PC13-0 PC13, 12 + caddr11-0 Addressing area *6 Skip condition addr1 -- -- *11 !addr $addr $addr1 PCDE PCXA BCDE BCXA BRA Note 1 BRCB !addr1 !caddr 3 1 1 2 2 2 2 3 2 3 2 2 3 3 3 3 3 2 *6 *7 *6 *6 *11 *8 Notes 1. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only. 2. As for the B register, only the lower 2 bits are valid. Data Sheet U10328EJ3V1DS00 25 PD75P0016 Group Subroutine stack control Mnemonic Operand No. of Machine bytes cycle 3 3 Operation (SP - 5) 0, 0, PC13,12 (SP - 6)(SP - 3)(SP - 4) PC11-0 (SP - 2) x, x, MBE, RBE PC13-0 addr1, SP SP - 6 Addressing area *11 Skip condition CALLA Note !addr1 CALL Note !addr 3 3 (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) (MBE, RBE, PC13, 12) PC13-0 addr, SP SP - 4 *6 4 (SP - 5) 0, 0, PC13,12 (SP - 6)(SP - 3)(SP - 4) PC11-0 (SP - 2) x, x, MBE, RBE PC13-0 addr, SP SP - 6 CALLF Note !faddr 2 2 (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) (MBE, RBE, PC13, 12) PC13-0 000 + faddr, SP SP - 4 *9 3 (SP - 5) 0, 0, PC13,12 (SP - 6)(SP - 3)(SP - 4) PC11-0 (SP - 2) x, x, MBE, RBE PC13-0 000 + faddr,SP SP - 6 RET Note 1 3 (MBE, RBE, PC13, 12) (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4 x, x, MBE, RBE (SP + 4) 0, 0, PC13-12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 6 RETS Note 1 3 + S (MBE, RBE, PC13, 12) (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 4 then skip unconditionally x, x, MBE, RBE (SP + 4) 0, 0, PC13-12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) SP SP + 6 then skip unconditionally Unconditional RETI Note 1 3 MBE, RBE, PC13, 12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) PSW (SP + 4)(SP + 5), SP SP + 6 0, 0, PC13, 12 (SP + 1) PC11-0 (SP)(SP + 3)(SP + 2) PSW (SP + 4)(SP + 5), SP SP + 6 Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only. 26 Data Sheet U10328EJ3V1DS00 PD75P0016 Group Subroutine stack control Mnemonic PUSH rp BS POP rp BS Operand No. of Machine bytes cycle 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 Operation (SP - 1)(SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) RBS, SP SP - 2 rp (SP + 1)(SP), SP SP + 2 MBS (SP + 1), RBS (SP), SP SP + 2 IME(IPS.3) 1 IExxx 1 IME(IPS.3) 0 IExxx 0 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA (n = 0 - 8) (n = 4, 6) (n = 2 - 8) (n = 4, 6) Addressing area Skip condition Interrupt control EI IExxx DI IExxx 2 2 2 2 2 2 2 2 2 1 I/O IN Note 1 A, PORTn XA, PORTn OUT Note 1 PORTn, A PORTn, XA CPU control HALT STOP NOP Special SEL RBn MBn GETI Note 2, 3 taddr Set HALT Mode(PCC.2 1) Set STOP Mode(PCC.3 1) No Operation RBS n MBS n (n = 0 - 3) (n = 0, 1, 15) *10 ----------- 2 2 1 * When using TBR instruction PC13-0 (taddr)5-0 + (taddr + 1) ------------------------- * When using TCALL instruction (SP - 4)(SP - 1)(SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, 12 PC13-0 (taddr)5-0 + (taddr + 1) ------------------------- SP SP - 4 ----------- * When using instruction other than TBR or TCALL Execute (taddr)(taddr + 1) instructions 1 3 * When using TBR instruction PC13-0 (taddr)5-0 + (taddr + 1) *10 Determined by referenced instruction ---------------------------------------------- 4 * When using TCALL instruction (SP - 5) 0, 0, PC13, 12 (SP - 6)(SP - 3)(SP - 4) PC11-0 (SP - 2) x, x, MBE, RBE PC13-0 (taddr)5-0 + (taddr + 1) SP SP - 6 ---------------------------------------------- 3 * When using instruction other than TBR or TCALL Execute (taddr)(taddr + 1) instructions Determined by referenced instruction Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15. 2. TBR and TCALL are assembler directives for the GETI instruction's table definitions. 3. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only. Data Sheet U10328EJ3V1DS00 27 PD75P0016 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The program memory in the PD75P0016 is a 16384 x 8-bit electronic write-enabled one-time PROM. The pins listed in the table below are used for this PROM's write/verify operations. Clock input from the X1 pins is used instead of address input as a method for updating addresses. Pin name VPP X1, X2 MD0/P30-MD3/P33 Function Pin (usually VDD) where programming voltage is applied during program memory write/verify Clock input pin for address updating during program memory write/verify. Input the X1 pin's inverted signal to the X2 pin. Operation mode selection pin for program memory write/verify D0/P40-D3/P43 (lower 4) 8-bit data I/O pin for program memory write/verify D4/P50-D7/P53 (higher 4) VDD Pin where power supply voltage is applied. Power voltage range for normal operation is 2.2 to 5.5 V. Apply 6.0 V for program memory write/verify. Caution Pins not used for program memory write/verify should be processed as follows. * All unused pins except XT2 ...... Connect to Vss via a pull-down resistor * XT2 pin ........................................ Leave open 8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the PD75P0016's VDD pin and +12.5 V is applied to its VPP pin, program write/verify modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown below. Operation mode specification VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L x MD2 H H H H MD3 L H H H Zero-clear program memory address Write mode Verify mode Program inhibit mode Operation mode Remark x: L or H 28 Data Sheet U10328EJ3V1DS00 PD75P0016 8.2 Steps in Program Memory Write Operation High-speed program memory write can be executed via the following steps. (1) Pull down unused pins to VSS via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V to VDD and +12.5 V power to VPP. (6) Write data using 1-ms write mode. (7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7). (8) X [= number of write operations from steps (6) and (7)] x 1 ms additional write (9) 4 pulse inputs to the X1 pin updates (increments +1) the program memory address. (10) Repeat steps (6) to (9) until the last address is completed. (11) Zero-clear mode for program memory addresses. (12) Apply +5 V to the VDD and VPP pins. (13) Power supply OFF The following diagram illustrates steps (2) to (9). X repetitions Write Verify Additional write Address increment VPP VPP VDD VDD + 1 VDD VDD X1 D0/P40-D3/P43 D4/P50-D7/P53 Data input Data output Data input MD0/P30 MD1/P31 MD2/P32 MD3/P33 Data Sheet U10328EJ3V1DS00 29 PD75P0016 8.3 Steps in Program Memory Read Operation The PD75P0016 can read out the program memory contents via the following steps. (1) Pull down unused pins to VSS via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V power to VDD and +12.5 V to VPP. (6) Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based on a cycle of four pulse inputs. (7) Zero-clear mode for program memory addresses. (8) Apply +5 V power to the VDD and VPP pins. (9) Power supply OFF The following diagram illustrates steps (2) to (7). VPP VPP VDD VDD + 1 VDD VDD X1 D0/P40-D3/P43 D4/P50-D7/P53 Data output Data output MD0/P30 MD1/P31 "L" MD2/P32 MD3/P33 30 Data Sheet U10328EJ3V1DS00 PD75P0016 8.4 One-Time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends the screening process, that is, after the required data is written to the PROM and the PROM is stored under the hightemperature conditions shown below, the PROM should be verified. Storage temperature 125C Storage time 24 hours At present, a fee is charged by NEC for one-time PROM after-programming imprinting, screening, and verify service for the QTOP Microcontroller. For details, contact your sales representative. Data Sheet U10328EJ3V1DS00 31 PD75P0016 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage PROM supply voltage Input voltage Symbol VDD VPP VI1 VI2 Output voltage High-level output current VO IOH Per pin Total of all pins Low-level output current IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Tstg Other than port 4, 5 Port 4, 5 (N-ch open drain) Conditions Ratings -0.3 to + 7.0 -0.3 to + 13.5 -0.3 to VDD + 0.3 -0.3 to + 14 -0.3 to VDD + 0.3 -10 -30 30 220 -40 to + 85 -65 to + 150 Unit V V V V V mA mA mA mA C C Caution If the absolute maximum rating of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. Be sure that these values are never exceeded when using the product. Capacitance (TA = 25C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Pins other than tested pins: 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 32 Data Sheet U10328EJ3V1DS00 PD75P0016 Main System Clock Oscillation Circuit Characteristics (TA = - 40 to +85C) Recommended constants X1 X2 Resonator Ceramic resonator Parameter Oscillation frequency (fX) Note 1 Conditions VDD = 2.2 to 5.5 V After VDD has reached MIN. value of oscillation voltage range VDD = 2.2 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V MIN. 1.0 TYP. MAX. Unit 6.0 Note 2 MHz 4 ms C1 C2 Oscillation stabilization time Note 3 Crystal resonator X1 X2 Oscillation frequency (fX) Note 1 Oscillation stabilization time Note 3 1.0 6.0 Note 2 MHz 10 30 ms ms C1 C2 External clock X1 input frequency (fX) Note 1 VDD = 1.8 to 5.5 V 1.0 6.0 Note 4 MHz X1 X2 X1 input high-, low-level widths (tXH, tXL) VDD = 1.8 to 5.5 V 83.3 500 ns Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. 2. If the oscillation frequency is 4.7 MHz < fX 6.0 MHz at 2.2 V VDD < 2.7 V of the supply voltage, please do not set processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle is less than 0.85 s, falling short of the rated value of 0.85 s. 3. The oscillation stablilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released. 4. If the X1 input frequency is 4.19 MHz < fx 6.0 MHz at 1.8 V VDD < 2.7 V of the supply voltage, please do not set PCC = 0011. If PCC = 0011, one machine cycle time is less than 0.95 s, falling short of the rated value of 0.95 s. Caution When using the main system clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VDD. Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillation circuit. Data Sheet U10328EJ3V1DS00 33 PD75P0016 Subsystem Clock Oscillation Circuit Characteristics (TA = -40 to +85C) Recommended constants Resonator Crystal resonator Parameter Oscillation frequency (fXT) Note 1 R Conditions VDD = 2.2 to 5.5 V MIN. 32 TYP. 32.768 MAX. 35 Unit kHz XT1 XT2 C3 C4 Oscillation stabilization time Note 2 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V 1.0 2 10 s s kHz External clock XT1 XT2 XT1 input frequency (fXT) Note 1 VDD = 1.8 to 5.5 V 32 100 XT1 input high-, low-level widths (tXTH, tXTL) VDD = 1.8 to 5.5 V 5 15 s Notes 1. The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VDD. Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit. Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit. RECOMMENDED OSCILLATION CIRCUIT CONSTANT Main System Clock: Ceramic Resonator (TA = -40 to +85C) Oscillation Circuit Constant (pF) C1 10 C2 10 Oscillation Voltage Range (VDD) MIN. (V) 2.3 MAX. (V) 5.5 -- Manufacturer Part Number Frequency (MHz) Remark TDK Corp. CCR4.0MC32 4.0 Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 34 Data Sheet U10328EJ3V1DS00 PD75P0016 DC Characteristics (TA = -40 to + 85C, VDD = 2.2 to 5.5 V) Parameter Low-level output current High-level input voltage VIH2 Ports 0, 1, 6, 7, RESET VIH1 Symbol IOL Per pin Total of all pins Ports 2, 3, 8 2.7 VDD 5.5 V 2.2 VDD 2.7 V 2.7 VDD 5.5 V 2.2 VDD 2.7 V VIH3 Ports 4, 5 (N-ch open drain) 2.7 VDD 5.5 V 2.2 VDD 2.7 V VIH4 Low-level input voltage VIL2 Ports 0, 1, 6, 7, RESET VIL1 X1, XT1 Ports 2-5, 8 2.7 VDD 5.5 V 2.2 VDD 2.7 V 2.7 VDD 5.5 V 2.2 VDD 2.7 V VIL3 High-level output voltage Low-level output voltage VOL2 VOH VOL1 X1, XT1 SCK, SO, ports 2, 3, 6-8 IOH = -1.0 mA SCK, SO, ports 2-8 SB0, SB1 IOL = 15 mA, VDD = 4.5 to 5.5 V IOL = 1.6 mA N-ch open drain Pull-up resistor 1 k High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 VIN = 13 V VIN = 0 V VIN = VDD Pins other than X1 and XT1 X1, XT1 Ports 4, 5 (N-ch open drain) Pins other than ports 4, 5, X1 and XT1 X1, XT1 Ports 4, 5 (N-ch open drain) When input instruction is not executed Ports 4, 5 (N-ch open drain) When input instruction is executed High-level output leakage current Low-level output leakage current Internal pull-up resistor RL VIN = 0 V Ports 0-3, 6-8 (except P00 pin) 50 100 200 k ILOH1 ILOH2 ILOL VOUT = VDD VDD = 3.0 V -3 -8 3 20 -3 VDD = 5.0 V -10 -27 3 20 20 -3 -20 -3 0.7 VDD 0.9 VDD 0.8 VDD 0.9 VDD 0.7 VDD 0.9 VDD VDD-0.1 0 0 0 0 0 VDD-0.5 0.2 2.0 0.4 0.2 VDD Conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD 13 13 VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 Unit mA mA V V V V V V V V V V V V V V V V A A A A A A A A A A A A -30 SCK, SO/SB0, SB1, Ports 2, 3, 6-8 VOUT = 13 V Ports 4, 5 (N-ch open drain) VOUT = 0 V Data Sheet U10328EJ3V1DS00 35 PD75P0016 DC Characteristics (TA = -40 to + 85C, VDD = 2.2 to 5.5 V) Parameter Supply current Note 1 Symbol IDD1 6.0 MHz Note 2 crystal oscillation C1 = C2 = 22 pF Conditions VDD = 5.0 V 10 % Note 3 VDD = 3.0 V 10 % Note 4 HALT mode VDD = 5.0 V 10 % VDD = 3.0 V 10 % % Note 3 MIN. TYP. 3.7 0.73 0.92 0.3 2.7 0.57 0.9 0.28 42 23 42 39 39 8.5 5.0 8.5 3.5 3.5 0.05 0.02 MAX. 11.0 2.2 2.6 0.9 8.0 1.7 2.5 0.8 126 69 84 117 78 25 15 17 12 7 10 5 3 Unit mA mA mA mA mA mA mA mA IDD2 IDD1 4.19 MHz Note 2 crystal oscillation C1 = C2 = 22 pF VDD = 5.0 V 10 VDD = 3.0 V 10 % Note 4 HALT mode VDD = 5.0 V 10 % VDD = 3.0 V 10 % IDD2 IDD3 32.768 kHz Note 5 crystal oscillation VDD = 3.0 V 10 % Lowvoltage VDD = 2.5 V 10 % mode Note 6 VDD = 3.0 V, TA = 25 C Low current dissipation mode Note 7 A A A A A A A A A A A A A VDD = 3.0 V 10 % VDD = 3.0 V, TA = 25 C Lowvoltage VDD = 2.5 V 10 % mode Note 6 VDD = 3.0 V, TA = 25 C Low current VDD = 3.0 V 10 % consumption mode Note 7 VDD = 3.0 V, TA = 25 C IDD4 HALT mode VDD = 3.0 V 10 % IDD5 XT1 = 0V Note 8 STOP mode VDD = 5.0 V 10 % VDD = 3.0 V 10 % TA = 25 C 0.02 Notes 1. The current flowing through the internal pull-up resistor is not included. 2. Including the case when the subsystem clock oscillates. 3. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 4. When the device operates in low-speed mode with PCC set to 0000. 5. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 6. When the suboscillation circuit control register (SOS) is set to 0000. 7. When SOS is set to 0010. 8. When SOS is set to 00x1, and the suboscillation circuit feedback resistor is not used (x: don't care). 36 Data Sheet U10328EJ3V1DS00 PD75P0016 AC Characteristics (TA = -40 to + 85C, VDD = 2.2 to 5.5 V) Parameter CPU clock cycle timeNote 1 (minimum instruction execution time = 1 machine cycle) TI0 input frequency fTI Operates with subsystem clock VDD = 2.7 to 5.5 V Symbol tCY Operates with main system clock Conditions with ceramic oscillator or crystal resonator with external clock MIN. VDD = 2.7 to 5.5 V 0.67 0.85 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V 0.67 0.95 114 0 0 TI0 high-, low-level widths Interrupt input high-, tINTH, low-level widths tINTL INT1, 2, 4 KR0-KR7 RESET low-level width tRSL INT0 IM02 = 0 IM02 = 1 tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 1.8 Note 2 10 10 10 10 122 TYP. MAX. 64 64 64 64 125 1.0 275 Unit s s s s s MHz kHz s s s s s s s Notes 1. The cycle time of the CPU clock () is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock. 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0). tCY vs VDD (with main system clock) 64 60 6 5 Operation guaranteed range 4 Cycle time tCY ( s) 3 2 1 0.95 0.85 0.67 0.5 0 1 1.8 2 2.2 2.7 3 4 5 Supply voltage VDD [V] 5.5 6 Remark Shaded area indicates operation when external clock is used. Data Sheet U10328EJ3V1DS00 37 PD75P0016 Serial Transfer Operation 2-wire and 3-wire serial I/O modes (SCK *** internal clock output): (TA = -40 to +85C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level widths SI Note 1 tKL1, tKH1 setup time tSIK1 VDD = 2.7 to 5.5 V (vs. SCK ) SI Note 1 hold time (vs. SCK ) SCK SONote 1 output delay time tKSO1 RL = 1 kNote 2 CL = 100 pF VDD = 2.7 to 5.5 V tKSI1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKCY1/2-50 tKCY1/2-150 150 500 400 600 0 0 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns Notes 1. 2. Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 2-wire and 3-wire serial I/O modes (SCK *** external clock input): (TA = -40 to +85C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level widths SI Note 1 setup time (vs. SCK ) SI Note 1 hold time (vs. SCK ) SCK SONote 1 output delay time tKSO2 RL = 1 k Note 2 CL = 100 pF VDD = 2.7 to 5.5 V tKSI2 VDD = 2.7 to 5.5 V tKL2, tKH2 tSIK2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 400 1600 100 150 400 600 0 0 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns Notes 1. 2. Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 38 Data Sheet U10328EJ3V1DS00 PD75P0016 SBI mode (SCK *** internal clock output (master)): (TA = -40 to +85C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level widths tKL3 tKH3 SB0, 1 setup time (vs. SCK ) SB0, 1 hold time (vs. SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI3 tKSO3 RL = 1 k Note CL = 100 pF VDD = 2.7 to 5.5 V tSIK3 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKCY3/2-50 tKCY3/2-150 150 500 tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. SBI mode (SCK *** external clock input (slave)): (TA = -40 to +85C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level widths tKL4 tKH4 SB0, 1 setup time (vs. SCK ) SB0, 1 hold time (vs. SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI4 tKSO4 RL = 1 k Note CL = 100 pF VDD = 2.7 to 5.5 V tSIK4 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 400 1600 100 150 tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. Data Sheet U10328EJ3V1DS00 39 PD75P0016 AC Timing Test Points (except X1 and XT1 inputs) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Clock timing 1/fX tXL tXH VDD - 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD - 0.1 V XT1 input 0.1 V TI0 timing 1/fTI tTIL tTIH TI0 40 Data Sheet U10328EJ3V1DS00 PD75P0016 Serial Transfer Timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SI Input data tKSO1, 2 SO Output data 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0, 1 tKSO1, 2 Data Sheet U10328EJ3V1DS00 41 PD75P0016 Serial Transfer Timing Bus release signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET input timing tRSL RESET 42 Data Sheet U10328EJ3V1DS00 PD75P0016 Data Retention Characteristics of Data Memory in STOP Mode and at Low Supply Voltage (TA = -40 to +85C) Parameter Release signal setup time Oscillation stabilization wait time Note 1 Symbol tSREL tWAIT Released by RESET Released by interrupt request Conditions MIN. 0 215/fx Note 2 TYP. MAX. Unit s ms ms Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Set by the basic interval timer mode register (BTM). (Refer to the table below.) BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 fx = 4.19 MHz 0 1 1 1 Wait Time fx = 6.0 MHz 220/fx (approx. 175 ms) 217/fx (approx. 21.8 ms) 215/fx (approx. 5.46 ms) 213/fx (approx. 1.37 ms) 220/fx (approx. 250 ms) 217/fx (approx. 31.3 ms) 215/fx (approx. 7.81 ms) 213/fx (approx. 1.95 ms) Data retention timing (when STOP mode released by RESET) Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD STOP instruction execution tSREL RESET tWAIT Data retention timing (standby release signal: when STOP mode released by interrupt signal) HALT mode STOP mode Data retention mode Operation mode VDD STOP instruction execution Standby release signal (interrupt request) tSREL tWAIT Data Sheet U10328EJ3V1DS00 43 PD75P0016 DC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0V) Parameter Input voltage, high Symbol VIH1 VIH2 Input voltage, low VIL1 VIL2 Input leakage current Output voltage, high Output voltage, low VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions Other than X1, X2 pins X1, X2 Other than X1, X2 pins X1, X2 VIN = VIL or VIH IOH = - 1 mA IOL = 1.6 mA VDD - 1.0 0.4 30 30 MIN. 0.7 VDD VDD - 0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V A V V mA mA Cautions 1. Keep VPP to within +13.5 V, including overshoot. 2. Apply VDD before VPP and turn it off after VPP. AC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Parameter Address setup time (vs. MD0 ) Note 2 Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX t1 tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR -- -- -- -- -- -- -- tACC tOH -- -- Conditions MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 TYP. MAX. Unit s s s s s 130 ns MD1 setup time (vs. MD0 ) Data setup time (vs. MD0 ) Address hold time (vs. MD0 ) Note 2 Data hold time (vs. MD0 ) MD0 data output float delay time VPP setup time (vs. MD3 ) VDD setup time (vs. MD3 ) Initial program pulse width Additional program pulse width MD0 setup time (vs. MD1 ) MD0 data output delay time MD1 hold time (vs. MD0 ) MD1 recovery time (vs. MD0 ) Program counter reset time X1 input high-, low-level width X1 input frequency Initial mode set time MD3 setup time (vs. MD1 ) MD3 hold time (vs. MD1 ) MD3 setup time (vs. MD0 ) Address delay time Note 2 s s 1.0 1.05 21.0 ms ms s 1 MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125 s s s s s 4.19 2 2 2 When program memory is read When program memory is read When program memory is read When program memory is read When program memory is read 0 2 2 2 2 130 MHz s s s s s ns data output Address Note 2 data output hold time MD3 hold time (vs. MD0 ) MD3 data output float delay time s s Notes 1. 2. Symbol of corresponding PD27C256A The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not connected to a pin. 44 Data Sheet U10328EJ3V1DS00 PD75P0016 Program Memory Write Timing tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL Data input tI MD0/P30 tPW MD1/P31 tPCR MD2/P32 tM3S MD3/P33 tM3H tM1S tM1H tM1R tM0S tOPW tDS tDH tDV tDF Data output Data input tDS tDH tAH tAS Data input tXH D0/P40-D3/P43 D4/P50-D7/P53 Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL tHAD D0/P40-D3/P43 D4/P50-D7/P53 tI MD0/P30 tDV tM3HR Data output Data output tDFR tDAD tXH MD1/P31 tPCR MD2/P32 tM3SR MD3/P33 Data Sheet U10328EJ3V1DS00 45 PD75P0016 10. CHARACTERISTICS CURVES (REFERENCE VALUE) IDD vs VDD (Main system clock : 6.0 MHz crystal resonator) 10 (TA = 25C) 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 Main system clock HALT mode +32-kHz oscillation 0.5 Supply Current IDD (mA) 0.1 Subsystem clock operation mode (SOS.1 = 0) 0.05 Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 1) 0.01 0.005 X1 X2 XT1 XT2 330 k Crystal resonator Crystal resonator 6.0 MHz 22 pF 22 pF 32.768 kHz 22 pF 22 pF 0.001 0 1 2 3 4 Supply Voltage VDD (V) 5 6 7 8 46 Data Sheet U10328EJ3V1DS00 PD75P0016 IDD vs VDD (Main system clock : 4.19 MHz crystal resonator) 10 (TA = 25C) 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 Main system clock HALT mode +32-kHz oscillation 0.5 Supply Current IDD (mA) 0.1 Subsystem clock operation mode (SOS.1 = 0) 0.05 Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 1) 0.01 0.005 X1 X2 XT1 XT2 330 k Crystal resonator Crystal resonator 4.19 MHz 22 pF 22 pF 32.768 kHz 22 pF 22 pF 0.001 0 1 2 3 4 Supply Voltage VDD (V) 5 6 7 8 Data Sheet U10328EJ3V1DS00 47 PD75P0016 11. PACKAGE DRAWINGS 42PIN PLASTIC SHRINK DIP (600 mil) 42 22 1 A 21 K L I G J H F C D N M B M R NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N R MILLIMETERS 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 0~15 INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.007 0~15 P42C-70-600A-1 48 Data Sheet U10328EJ3V1DS00 PD75P0016 44 PIN PLASTIC QFP ( 10) A B 33 34 23 22 detail of lead end C D S R Q 44 1 12 11 F J G H I M K P N NOTE Each lead centerline is located within 0.16 mm (0.007 inch) of its true position (T.P.) at maximum material condition. M L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 13.20.2 10.00.2 10.00.2 13.20.2 1.0 1.0 0.37 +0.08 -0.07 0.16 0.8 (T.P.) 1.60.2 0.80.2 0.17 +0.06 -0.05 0.10 2.7 0.1250.075 3 +7 -3 3.0 MAX. INCHES 0.520 +0.008 -0.009 0.394 +0.008 -0.009 0.394 +0.008 -0.009 0.520 +0.008 -0.009 0.039 0.039 0.015 +0.003 -0.004 0.007 0.031 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.007 +0.002 -0.003 0.004 0.106 0.0050.003 3 +7 -3 0.119 MAX. S44GB-80-3BS Data Sheet U10328EJ3V1DS00 49 PD75P0016 12. RECOMMENDED SOLDERING CONDITIONS Solder the PD75P0016 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 12-1. Soldering Conditions of Surface Mount Type PD75P0016GB-3BS-MTX: 44-pin plastic QFP (10 x 10 mm, 0.8-mm pitch) Symbol of recommended condition IR35-00-3 VP15-00-3 WS60-00-1 Soldering method Infrared reflow VPS Wave soldering Soldering conditions Package peak temperature: 235C, Time: 30 seconds max. (210C min.), Number of times: 3 max. Package peak temperature: 215C, Time: 40 seconds max. (200C min.), Number of times: 3 max. Soldering bath temperature: 260C max., Time: 10 seconds max., Number of times: 1 Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per side of device) - Caution Do not use two or more soldering methods in combination (except the partial heating method). Table 12-2. Soldering Conditions of Insertion Type PD75P0016CU: 42-pin plastic Shrink DIP (600 mil, 1.778-mm pitch) Soldering method Wave soldering (pin only) Partial heating Soldering conditions Soldering bath temperature: 260C max., Time: 10 seconds max. Pin temperature: 300C max., Time: 3 seconds max. (per pin) Caution Apply wave soldering to the pins only. Be careful not to allow solder jet to come into direct contact with the body of the chip. 50 Data Sheet U10328EJ3V1DS00 PD75P0016 APPENDIX A. FUNCTION LIST OF PD75008, 750008, 75P0016 (1/2) Item Program memory PD75008 Mask ROM 0000H - 1F7FH (8064 x 8 bits) 000H - 1FFH (512 x 4 bits) 75X Standard CPU 4 bits x 8 or 8 bits x 4 * 0.95, 1.91, 15.3 s (at 4.19 MHz operation) PD750008 Mask ROM 0000H - 1FFFH (8192 x 8 bits) PD75P0016 One-time PROM 0000H - 3FFFH (16384 x 8 bits) Data memory CPU General register Instruction execution time When main system clock is selected When subsystem clock is selected SBS register Stack area Stack operation of subroutine call instruction Instructions BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr CALLF !faddr Timer 75XL CPU (4 bits x 8 or 8 bits x 4) x 4 banks * 0.95, 1.91, 3.81, 15.3 s (at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (at 6.0 MHz operation) 122 s (at 32.768 kHz operation) None 000H - 0FFH 2-byte stack Yes SBS.3 = 1: Mk I mode selected SBS.3 = 0: Mk II mode selected n00H - nFFH (n = 0, 1) In Mk I mode: 2-byte stack In Mk II mode: 3-byte stack In Mk I mode: Unusable In Mk II mode: Usable Usable Stack Unusable 3 machine cycles 2 machine cycles 3 channels * Basic interval timer: 1 channel * 8-bit timer/event counter: 1 channel * Watch timer: 1 channel * , 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) * 2 kHz Mk I mode: 3 machine cycles Mk II mode: 4 machine cycles Mk I mode: 2 machine cycles Mk II mode: 3 machine cycles 4 channels * Basic interval timer/watchdog timer: 1 channel * 8-bit timer/event counter: 1 channel * 8-bit timer counter: 1 channel * Watch timer: 1 channel * , 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) * 2, 4, 32 kHz (main system clock: at 4.19 MHz operation) * 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) Clock output (PCL) BUZ output (BUZ) Data Sheet U10328EJ3V1DS00 51 PD75P0016 (2/2) Item Serial interface PD75008 PD750008 PD75P0016 Compatible with 3 kinds of mode * 3-wire serial I/O mode ... MSB/LSB-first can be switched * 2-wire serial I/O mode * SBI mode Feedback resistor cut flag (SOS.0) Sub oscillator current cut flag (SOS.1) On-chip feedback resistor specifiable by mask option None None Not possible External: 3 Internal: 3 PCC = 0, 2, 3 can be used VDD = 2.7 to 6.0 V TA = -40 to +85C * 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) * 44-pin plastic QFP (10 x 10 mm, 0.8-mm pitch) On chip Yes Possible External: 3 Internal: 4 PCC = 0 to 3 can be used VDD = 2.2 to 5.5 V On chip SOS register Register bank selection register (RBS) Standby release by INT0 Vectored interrupt Processor clock control register (PCC) Supply voltage Operating ambient temperature Package 52 Data Sheet U10328EJ3V1DS00 PD75P0016 APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the PD75P0016. The 75XL series uses a common relocatable assembler, in combination with a device file matching each machine. RA75X relocatable assembler Host machine OS PC-9800 series MS-DOS TM Part number Supply medium 3.5" 2HD (product name) S5A13RA75X Ver.3.30 to Ver.6.2 Note IBM PC/ATTM or compatible Refer to OS for IBM PCs 3.5" 2HC S7B13RA75X Device file Host machine OS PC-9800 series MS-DOS Ver.3.30 to Ver.6.2 Note IBM PC/AT or compatible Refer to OS for IBM PCs 3.5" 2HC Supply medium 3.5" 2HD Part number (product name) S5A13DF750008 S7B13DF750008 Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swap function, but it does not work with this software. Remark The operation of the assembler and device file is guaranteed only on the above host machines and OSs. Data Sheet U10328EJ3V1DS00 53 PD75P0016 PROM Write Tools Hardware PG-1500 A stand-alone system can be configured of a single-chip microcomputer with on-chip PROM when connected to an auxiliary board (companion product) and a programmer adapter (separately sold). Alternatively, a PROM programmer can be operated on a host machine for programming. In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed. This is a PROM programmer adapter for the PD75P0016CU/GB. It can be used when connected to a PG-1500. This is a PROM programmer adapter for the PD75P0016GB-3BS-MTX. It can be used when connected to a PG-1500. Establishes serial and parallel connections between the PG-1500 and a host machine for hostmachine control of the PG-1500. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2 Note IBM PC/AT or compatible Refer to OS for IBM PCs 3.5" 2HD Supply medium 3.5" 2HD Part number (product name) PA-75P008CU PA-75P0016GB Software PG-1500 controller S5A13PG1500 S7B13PG1500 Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work with this software. Remark Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs. 54 Data Sheet U10328EJ3V1DS00 PD75P0016 Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the PD75P0016. Various system configurations using these in-circuit emulators are listed below. Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. For development of the PD750008 subseries, the IE-75000-R is used with a separately sold emulation board IE75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R. These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. The IE-75000-R can include a connected emulation board (IE-75000-R-EM). The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. The IE-75001-R is used with a separately sold emulation board (IE-75300-R-EM) and emulation probe EP75008CU-R or EP-75008GB-R. These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. This is an emulation board for evaluating application systems that use the PD750008 subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator. This is an emulation probe for the PD75P0016CU. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. This is an emulation probe for the PD75P0016GB. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a 44-pin conversion socket (EV-9200G-44) to facilitate connections with various target systems. This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics I/F. Host machine OS PC-9800 series MS-DOS Ver.3.30 to Ver.6.2 Note 2 IBM PC/AT or compatible Refer to OS for IBM PCs 3.5" 2HC Supply medium 3.5" 2HD Part number (product name) IE-75001-R IE-75300-R-EM EP-75008CU-R EP-75008GB-R EV-9200G-44 Software IE control program S5A13IE75X S7B13IE75X Notes 1. This is a service part provided for maintenance purpose only. 2. Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work with this software. Remarks 1. Operation of the IE control program is guaranteed only on the above host machine and OSs. 2. The PD75000 subseries consists of the PD750004, 750006, 750008 and 75P00016. Data Sheet U10328EJ3V1DS00 55 PD75P0016 OS for IBM PCs The following operating systems for the IBM PC are supported. OS PC DOS TM Version Ver.3.1 to Ver.6.3 J6.1/VNote to J6.3/VNote MS-DOS Ver.5.0 to Ver.6.22 5.0/VNote to J6.2/VNote IBM DOSTM J5.02/VNote Note Supports English version only. Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function. 56 Data Sheet U10328EJ3V1DS00 PD75P0016 APPENDIX C. RELATED DOCUMENTS Some of the following related documents are preliminary. This document, however, is not indicated as preliminary. Device Related Documents Document No. Japanese English U10738E This document U10740E - U10453E Document name PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Data Sheet PD75P0016 Data Sheet PD750008 User's Manual PD750008, 750108 Instruction List 75XL Series Selection Guide U10738J U10328J U10740J U11456J U10453J Development Tool Related Documents Document No. Japanese IE-75000 R/IE-75001-R User's Manual IE-75300-R-EM User's Manual Hardware EP-750008CU-R User's Manual EP-750008GB-R User's Manual PG-1500 User's Manual RA75X Assembler Package User's Manual Software PG-1500 Controller User's Manual Operation Language PC-9800 Series (MS-DOS) Base IBM PC Series (PC DOS) Base EEU-846 U11354J EEU-699 EEU-698 U11940J U12622J U12385J EEU-704 EEU-5008 English EEU-1416 U11354E EEU-1317 EEU-1305 U11940E U12622E U12385E EEU-1291 U10540E Document name Other Documents Document No. Japanese SEMICONDUCTOR SELECTION GUIDE Products & Package (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices Electrostatic Discharge (ESD) Guide for Products Related to Microcomputer : Other Companies X13769X C10535J C11531J C10983J C11892J C11416J C10535E C11531E C10983E C11892E - English Document name Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. Data Sheet U10328EJ3V1DS00 57 PD75P0016 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. bare hands. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 58 Data Sheet U10328EJ3V1DS00 PD75P0016 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 Data Sheet U10328EJ3V1DS00 59 PD75P0016 QTOP is a trademark of NEC Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is current as of August, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 |
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