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| SEMICONDUCTOR DG200, DG201 CMOS Dual/Quad SPST Analog Switches Description The DG200 and DG201 solid state analog gates are designed using an improved, high voltage CMOS monolithic technology. They provide ease-of-use and performance advantages not previously available from solid state switches. Destructive latch-up of solid state analog gates has been eliminated by Harris's CMOS technology. The DG200 and DG201 are completely specification and pinout compatible with the industry standard devices. December 1993 Features * Switches Greater than 28VP-P Signals with 15 Supplies * Break-Before-Make Switching tOFF 250ns, tON 700ns Typical * TTL, DTL, CMOS, PMOS Compatible * Non-Latching with Supply Turn-Off * Complete Monolithic Construction * Industry Standard (DG200, DG201) Ordering Information Applications * Data Acquisition * Sample and Hold Circuits * Operational Amplifier Gain Switching Networks PART NUMBER DG200AA DG200AK DG200BA DG200BK DG200CJ DG200AA/883B DG200AK/883B DG201AK DG201BK DG201CJ DG201AK/883B TEMPERATURE -55oC -55oC -25oC to to to +125oC +125oC +85oC PACKAGE 10 Pin Metal Can 14 Lead Ceramic DIP 10 Pin Metal Can 14 Lead Ceramic DIP 14 Lead Plastic DIP 10 Pin Metal Can 14 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Ceramic DIP 16 Lead Plastic DIP 16 Lead Ceramic DIP -25oC to +85oC 0oC -55oC -55oC to to to +70oC +125oC +125oC -55oC to +125oC -25oC 0oC -55oC to +85oC to to +70oC +125oC Pinouts DG200 (CDIP, PDIP) TOP VIEW DG200 (TO-100 METAL CAN) TOP VIEW V+ (SUBSTRATE AND CASE) IN2 1 NC 2 GND 3 NC 4 S2 5 D2 6 V- 7 14 IN1 13 NC 12 V+ (SUBSTRATE) 11 NC GND 10 S1 9 D1 8 VREF S2 4 5 D2 6 V3 7 VREF IN2 IN1 2 1 10 9 S1 8 D1 IN1 1 D1 S1 2 3 DG201 (CDIP, PDIP) TOP VIEW 16 IN2 15 D2 14 S2 13 V+(SUBSTRATE) 12 VREF 11 S3 10 D3 9 IN3 V- 4 GND 5 S4 D4 6 7 IN4 8 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright (c) Harris Corporation 1993 File Number 3115 9-13 DG200, DG201 Schematic Diagram (1/2 DG200, 1/4 DG201) V+ V- Q3 Q7 Q5 Q14 Q15 Q8 V+ Q1 VREF Q10 Q12 Q13 Q2 Q9 GATE PROTECTION RESISTOR Q4 Q6 S1 Q11 D1 INPUT V- Functional Diagram S IN N P D DG200, DG201 SWITCH CELL 9-14 Specifications DG200 Absolute Maximum Ratings V+, V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V V+ - VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD - V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD - VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <28V VIN - GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Thermal Information Thermal Resistance JA JC Ceramic DIP Package . . . . . . . . . . . . . . . 95oC/W 24oC/W Plastic DIP Package . . . . . . . . . . . . . . . . 100oC/W Metal Can Package . . . . . . . . . . . . . . . . . 136oC/W 65oC/W Operating Temperature Range "A" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC "B" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to +85oC "C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications (TA = +25oC, V+ = +15V, V- = -15V) MILITARY COMMERCIAL / INDUSTRIAL +125oC 10 10 100 0oC TO -25oC 80 +25oC 10 10 80 30 (Typ) 15V +70oC TO +85oC 10 10 100 UNITS A A V PARAMETER Input Logic Current, IIN(ON) Input Logic Current, IN(OFF) Drain-Source On Resistance, rDS(ON) Channel-to-Channel rDS(ON) Match, rDS(ON) Minimum Analog Signal Handling Capability, VANALOG Switch OFF Leakage Current, ID(OFF) Switch OFF Leakage Current, IS(OFF) TEST CONDITIONS VIN = 0.8V (Notes 2, 3) VIN = 2.4V (Notes 2, 3) IS = 10mA, VANALOG = 10V -55oC 10 10 70 - +25oC 1 1 70 25 (Typ) 15V VANALOG = -14V to +14V VANALOG = -14V to +14V - 2 2 2 1.0 0.5 15 (Typ) 54 (Typ) 100 100 200 - - 5 5 10 1.0 0.5 20 (Typ) 50 (Typ) 100 100 200 - nA nA nA s s mV dB Switch ON Leakage Cur- VD = VS = -14V to +14V rent, ID(ON) + IS(ON) Switch "ON" Time (Note 1), tON Switch "OFF" Time, tOFF Charge Injection, Q(INJ.) Minimum Off Isolation Rejection Ratio, OIRR +Power Supply Quiescent Current, IV1 -Power Supply Quiescent Current, IV2 Minimum Channel to Channel Cross Coupling Rejection Ratio, CCRR NOTES: 1. Pull Down Resistor must be 2k. One Channel Off RL = 1k, VANALOG = -10V to +10V (Figure 5) RL = 1k, VANALOG = -10V to +10V (Figure 5) Figure 6 f = 1MHz, RL = 100, CL 5pF (Figure 7, Note 1) VIN = 0V or VIN = 5V 1000 1000 - 1000 1000 54 (Typ) 2000 2000 - 1000 1000 - 1000 1000 50 (Typ) 2000 2000 - A A dB 2. Typical values are for design aid only, not guaranteed and not subject to production testing. 3. All channels are turned off by high "1" logic inputs and all channels are turned on by low "0" inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -120A. 9-15 Specifications DG201 Absolute Maximum Ratings V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V V+ to VD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <28V VREF to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V VREF to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30mA Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Thermal Information Thermal Resistance JA JC Ceramic DIP Package . . . . . . . . . . . . . . . 80oC/W 24oC/W Plastic DIP Package . . . . . . . . . . . . . . . . 145oC/W Operating Temperature Range "A" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC "B" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to +85oC "C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications (TA = +25oC, V+ = +15V, V- = -15V) MILITARY COMMERCIAL / INDUSTRIAL +125oC 10 10 125 0oC TO -25oC 1 1 100 +25oC 1 1 100 30 (Typ) 15 (Typ) +70oC TO +85oC 10 10 125 UNITS A A V PARAMETER Input Logic Current, IIN(ON) Input Logic Current, IN(OFF) Drain-Source On Resistance, rDS(ON) Channel-to-Channel rDS(ON) Match, rDS(ON) Minimum Analog Signal Handling Capability, VANALOG Switch OFF Leakage Current, ID(OFF) Switch OFF Leakage Current, IS(OFF) TEST CONDITIONS VIN = 0.8V (Note 1) VIN = 2.4V (Note 1) IS = 10mA, VANALOG = 10V -55oC +25oC 1 1 80 25 (Typ) 15 (Typ) 10 10 80 - VANALOG = -14V to +14V VANALOG = -14V to +14V 2000 2000 1 1 2 1.0 0.5 15 (Typ) 54 (Typ) 1000 1000 54 (Typ) 100 100 200 2000 2000 - 2000 2000 - 5 5 5 1.0 0.5 20 (Typ) 50 (Typ) 1000 1000 50 (Typ) 100 100 200 2000 2000 - nA nA nA s s mV dB A A dB Switch ON Leakage Cur- VD = VS = -14V to +14V rent, ID(ON) + IS(ON) Switch "ON" Time (Note 2), tON Switch "OFF" Time (Note 2), tOFF Charge Injection, Q(INJ.) Minimum Off Isolation Rejection Ratio, OIRR +Power Supply Quiescent Current, I+Q -Power Supply Quiescent Current, I-Q Minimum Channel to Channel Cross Coupling Rejection Ratio, CCRR NOTES: One Channel Off RL = 1k, VANALOG = -10V to +10V (Figure 5) RL = 1k, VANALOG = -10V to +10V (Figure 5) Figure 6 f = 1MHz, RL = 100, CL 5pF, (Figure 7) VIN = 0V or VIN = 5V - 1. Typical values are for design aid only, not guaranteed and not subject to production testing. 2. All channels are turned off by high "1" logic inputs and all channels are turned on by low "0" inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -120A. 9-16 DG200, DG201 Performance Curves DRAIN SOURCE ON RESISTANCE () 100 DRAIN SOURCE ON RESISTANCE () V+ = +15V V- = -15V 100 D +125oC C B 50 50 +25oC A A: B: C: D: V+ = +15V, V- = -15V V+ = +12V, V- = -12V V+ = +10V, V- = -10V V+ = +8V, V- = -8V 10 15 -55oC 0 -15 -10 -5 0 5 DRAIN VOLTAGE (V) 10 15 0 -15 -10 -5 0 5 DRAIN VOLTAGE (V) FIGURE 1. RDS(ON) vs VD AND TEMPERATURE 10 CHANNEL ON LEAKAGE CURRENT (nA) FIGURE 2. rDS(ON) vs VD AND POWER SUPPLY VOLTAGE SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA) 10 1 1 0.1 0.1 0.01 25 45 65 85 TEMPERATURE (oC) 105 125 0.01 25 45 65 85 TEMPERATURE (oC) 105 125 FIGURE 3. ID(ON) vs TEMPERATURE FIGURE 4. IS(OFF) OR ID(OFF) vs TEMPERATURE Pin Description DG200 (14 LEAD DIP) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL IN2 NC GND NC S2 D2 VVREF D1 S1 NC V+ NC IN1 DESCRIPTION Logic control for switch 2 No Connection Ground Terminal (Logic Common) No Connection Source (input) terminal for switch 2 Drain (output) terminal for switch 2 Negative power supply terminal Logic reference voltage Drain (output) terminal for switch 1 Source (input) terminal for switch 1 No Connection Positive power supply terminal (substrate) No Connection Source (input) terminal for switch 1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL IN1 D1 S1 VGND S4 D4 IN4 IN3 D3 S3 VREF V+ S2 D2 IN2 DG201 (16 LEAD DIP) DESCRIPTION Logic control for switch 1 Drain (output) terminal for switch 1 Source (input) terminal for switch 1 Negative power supply terminal Ground terminal (Logic Common) Source (input) terminal for switch 4 Drain (output) terminal for switch 4 Logic control for switch 4 Logic control for switch 3 Drain (output) terminal for switch 3 Source (input) terminal for switch 3 Logic reference voltage Positive power supply terminal (substrate) Source (input) terminal for switch 2 Drain (output) terminal for switch 2 Logic control for switch 2 9-17 DG200, DG201 Test Circuits ANALOG INPUT 10V ANALOG INPUT 10V 3V 0V LOGIC INPUT VOUT 3V 10pF 1k 0V LOGIC INPUT NOTE: All channels are turned off by high "1" logic inputs and all channels are turned on by low "0" inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -120A. 10,000pF VOUT 2k FIGURE 5. FIGURE 6. LOGIC INPUT * 2VP-P AT 1MHz 51 VOUT 100 * Pull Down Resistor must be 2k. FIGURE 7. Typical Applications Using the VREF Terminal The DG200 and DG201 have an internal voltage divider setting the TTL threshold on the input control lines for V+ equal to +15V. The schematic shown in Figure 8 with nominal resistor values, gives approximately 2.4V on the VREF pin. As the TTL input signal goes from +0.8V to +2.4V, Q1 and Q2 switch states to turn the switch ON and OFF. V+ (+15V) If the power supply voltage is less than +15V, then a resistor must be added between V+ and the VREF pin, to restore +2.4V at VREF. The table shows the value of this resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels on a +5V supply are being used, the threshold shifts are less critical, but a separate column of suitable values is given in the table. For logic swings of -5V to + 5V, no resistor is needed. In general, the "low" logic level should be <0.8V to prevent Q1 and Q2 from both being ON together (this will cause incorrect switch function). TABLE 1. 31k Q1 VREF REXT V+ SUPPLY (V) +15 +12 6k TTL RESISTOR (k) 100 51 (34) (27) 18 CMOS RESISTOR (k) 34 27 18 +10 +9 Q2 +8 +7 GATE PROTECTION RESISTOR INPUT FIGURE 8. 9-18 DG200 Metallization Topology DIE DIMENSIONS: 74 x 77 x 14 1mils METALLIZATION: Type: Al Thickness: 10kA 1kA GLASSIVATION: Type: SiO2/Si3N4 SiO2 Thickness: 7kA 1.4kA Si3N4 Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 1 x 105 A/cm2 Metallization Mask Layout DG200 D1 (9) V(7) D2 (6) S1 (10) (5) S2 V- (SUBSTRATE)* (12) (14) IN1 * Backside of Chip is V+ (1) IN2 (3) GND 9-19 DG201 Metallization Topology DIE DIMENSIONS: 94 x 101 x 14 1mils METALLIZATION: Type: Al Thickness: 10kA 1kA GLASSIVATION: Type: SiO2/Si3N4 SiO2 Thickness: 7kA 1.4kA Si3N4 Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 1 x 105 A/cm2 Metallization Mask Layout DG201 D1 (2) S1 (3) IN1 (1) IN2 (16) D2 (15) (14) S2 V- (4) (13) V+ (SUBSTRATE)* GND (5) S4 (6) (7) D4 (8) IN4 (9) IN3 (10) D3 (11) S3 * Backside of Chip is V+ 9-20 |
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