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| FIN1019 3.3V LVDS High Speed Differential Driver/Receiver April 2001 Revised September 2001 FIN1019 3.3V LVDS High Speed Differential Driver/Receiver General Description This driver and receiver pair are designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signals to LVDS levels with a typical differential output swing of 350mV and the receiver translates LVDS signals, with a typical differential input threshold of 100mV, into LVTTL levels. LVDS technology provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed clock or data transfer. Features s Greater than 400Mbs data rate s 3.3V power supply operation s 0.5ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s 100mV receiver input sensitivity s Fail safe protection open-circuit, shorted and terminated conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Flow-through pinout simplifies PCB layout s 14-Lead SOIC and TSSOP packages save space Ordering Code: Order Number FIN1019M FIN1019MTC Package Number M14A MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Function Table Inputs RIN+ L H X DIN L H X Open-Circuit or Z H = HIGH Logic Level Z = High Impedance Connection Diagram Outputs RE L L H L DE H H L H DOUT+ L H Z L ROUT L H Z H DOUT- H L Z H RIN- H L X Fail Safe Condition Pin Descriptions Pin Name DIN DOUT+ DOUT- DE RIN+ RIN- ROUT RE VCC GND NC Description LVTTL Data Input Non-inverting LVDS Output Inverting LVDS Output Driver Enable (LVTTL, Active HIGH) Non-Inverting LVDS Input Inverting LVDS Input LVTTL Receiver Output Receiver Enable (LVTTL, Active LOW) Power Supply Ground No Connect L = LOW Logic Level X = Don't Care Fail Safe = Open, Shorted, Terminated (c) 2001 Fairchild Semiconductor Corporation DS500506 www.fairchildsemi.com FIN1019 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) LVTTL DC Input Voltage (DIN, DE, RE) LVDS DC Input Voltage (RIN+, RIN-) LVTTL DC Output Voltage (ROUT) LVDS DC Output Voltage (DOUT+, DOUT-) LVDS Driver Short Circuit Current (IOSD) LVTTL DC Output Current (IO) Storage Temperature Range (TSTG) Max Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 10 seconds) ESD (Human Body Model) ESD (Machine Model) 260C -0.5V to +4.6V -0.5V to +6V -0.5V to 4.7V -0.5V to +6V -0.5V to 4.7V Continuous 16 mA Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VIN) Magnitude of Differential Voltage (|VID|) Common-Mode Input Voltage (VIC) Operating Temperature (TA) 100 mV to VCC 0.05V to 2.35V 3.0V to 3.6V 0 to VCC -40C to +85C -65C to +150C 150C 6500V 300V Note 1: The "Absolute Maximum Ratings": are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Test Conditions Min Typ (Note 2) 250 RL = 100, See Figure 1 1.125 1.25 350 450 25 1.375 25 VOUT = VCC or GND, DE = 0V VCC = 0V, VOUT = 0V or 3.6V VOUT = 0V, DE = VCC VOD = 0V, DE = VCC LVTTL Driver Characteristics VOH Output HIGH Voltage IOH = -100 A, RE = 0V, See Figure 6 and Table 1 IOH = -8 mA, RE = 0V, VID = 400 mV VID = 400 mV, VIC = 1.2V, see Figure 6 VOL Output LOW Voltage IOL = 100 A, RE = 0V, VID = -400 mV See Figure 6 and Table 1 IOL = -8 mA, RE = 0V, VID = -400 mV VID = -400 mV, VIC = 1.2V, see Figure 6 IOZ VTH VTL IIN II(OFF) VIH VIL IIN II(OFF) VIK Disabled Output Leakage Current Differential Input Threshold HIGH Differential Input Threshold LOW Input Current Power-OFF Input Current Input HIGH Voltage Input LOW Voltage Input Current Power-OFF Input Current Input Clamp Voltage VIN = 0V or VCC VCC = 0V, VIN = 0V or 3.6V IIK = -18 mA -1.5 VOUT = VCC or GND, RE = VCC See Figure 6 and Table 1 See Figure 6 and Table 1 VIN = 0V or VCC VCC = 0V, VIN = 0V or 3.6V 2.0 GND -100 20 20 VCC 0.8 20 20 VCC -0.2 V 2.4 20 20 -8 8 Max Units LVDS Differential Driver Characteristics VOD VOD VOS VOS IOZD IOFF IOS Output Differential Voltage VOD Magnitude Change from Differential LOW-to-HIGH Offset Voltage Offset Magnitude Change from Differential LOW-to-HIGH Disabled Output Leakage Current Power Off Output Current Short Circuit Output Current mV mV V mV A A mA 0.2 V 0.5 20 100 A mV mV A A V V A A V LVDS Receiver Characteristics LVTTL Driver and Control Signals Characteristics www.fairchildsemi.com 2 FIN1019 DC Electrical Characteristics Device Characteristics ICC Power Supply Current (Continued) Driver Enabled, Driver Load: RL = 100 Receiver Disabled, No Receiver Load Driver Enabled, Driver Load: RL = 100 , Receiver Enabled, (RIN+ = 1V and RIN- = 1.4V) or (RIN+ = 1.4V and ROUT- = 1V) Driver Disabled, Receiver Enabled, (RIN+ = 1V and RIN- = 1.4V) or (RIN+ = 1.4V and RIN- = 1V) Driver Disabled, Receiver Disabled 12.5 mA 12.5 mA 7.0 7.0 4 6 mA mA pF pF CIN COUT Input Capacitance Output Capacitance Any LVTTL or LVDS Input Any LVTTL or LVDS Output Note 2: All typical values are at TA = 25C and with VCC = 3.3V. AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Test Conditions Min Typ (Note 3) Max Units Driver Timing Characteristics tPLHD tPHLD tTLHD tTHLD tSK(P) tSK(PP) tZHD tZLD tHZD tLZD tPLH tPHL tTLH tTHL tSK(P) tSK(PP) tZH tZL tHZ tLZ Differential Propagation Delay LOW-to-HIGH Differential Propagation Delay HIGH-to-LOW Differential Output Rise Time (20% to 80%) Differential Output Fall Time (80% to 20%) Pulse Skew |tPLH - tPHL| Part-to-Part Skew (Note 4) Differential Output Enable Time from Z to HIGH RL = 100, CL = 10 pF, Differential Output Enable Time from Z to LOW See Figure 4 and Figure 5 Differential Output Disable Time from HIGH to Z Differential Output Disable Time from LOW to Z Propagation Delay LOW-to-HIGH Propagation Delay HIGH-to-LOW Output Rise time (20% to 80%) Output Fall time (80% to 20%) Pulse Skew | tPLH - tPHL | Part-to-Part Skew (Note 4) LVTTL Output Enable Time from Z to HIGH LVTTL Output Enable Time from Z to LOW LVTTL Output Disable Time from HIGH to Z LVTTL Output Disable Time from LOW to Z RL = 500 , CL = 10 pF, See Figure 8 |VID| = 400 mV, CL = 10 pF, See Figure 6 and Figure 7 0.9 0.9 0.5 0.5 0.5 1.0 5.0 5.0 5.0 5.0 RL = 100 , CL = 10 pF, See Figure 2 and Figure 3 0.5 0.5 0.4 0.4 1.5 1.5 1.0 1.0 0.5 1.0 5.0 5.0 5.0 5.0 2.5 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Receiver Timing Characteristics Note 3: All typical values are at TA = 25C and with VCC = 5V. Note 4: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. 3 www.fairchildsemi.com FIN1019 Note A: Input pulses have frequency = 10 MHz, tR or tF = 2 ns Note B: C L includes all probe and fixture capacitances FIGURE 1. Differential Driver DC Test Circuit FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit Note B: Input pulses have the frequency = 10 MHz, tR or tF = 2 ns Note A: C L includes all probe and fixture capacitances FIGURE 3. AC Waveforms for Differential Driver FIGURE 4. Differential Driver Enable and Disable Test Circuit FIGURE 5. Enable and Disable AC Waveforms www.fairchildsemi.com 4 FIN1019 Note A: Input pulses have frequency = 10 MHz, tR or tF = 1ns Note B: CL includes all probe and fixture capacitance FIGURE 6. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) VIA 1.25 1.15 2.4 2.3 0.1 0 1.5 0.9 2.4 1.8 0.6 0 VIB 1.15 1.25 2.3 2.4 0 0.1 0.9 1.5 1.8 2.4 0 0.6 Resulting Differential Input Voltage (mV) VID 100 -100 100 -100 100 -100 600 -600 600 -600 600 -600 Resulting Common Mode Input Voltage (V) VIC 1.2 1.2 2.35 2.35 0.05 0.05 1.2 1.2 2.1 2.1 0.3 0.3 5 www.fairchildsemi.com FIN1019 FIGURE 7. LVDS Input to LVTTL Output AC Waveforms Test Circuit for LVTTL Outputs Voltage Waveforms Enable and Disable Times FIGURE 8. LVTTL Outputs Test Circuit and AC Waveforms www.fairchildsemi.com 6 FIN1019 DC / AC Typical Performance Curves Drivers FIGURE 9. Output High Voltage vs. Power Supply Voltage FIGURE 10. Output Low Voltage vs. Power Supply Voltage FIGURE 11. Output Short Circuit Current vs. Power Supply Voltage FIGURE 12. Differential Output Voltage vs. Power Supply Voltage FIGURE 13. Differential Output Voltage vs. Load Resistor FIGURE 14. Offset Voltage vs. Power Supply Voltage 7 www.fairchildsemi.com FIN1019 DC / AC Typical Performance Curves (Continued) FIGURE 15. Power Supply Current vs. Frequency FIGURE 16. Power Supply Current vs. Power Supply Voltage FIGURE 17. Power Supply Current vs. Ambient Temperature FIGURE 18. Differential Propagation Delay vs. Power Supply FIGURE 19. Differential Propagation Delay vs. Ambient Temperature FIGURE 20. Differential Skew (tPLH - tPHL) vs. Power Supply Voltage www.fairchildsemi.com 8 FIN1019 DC / AC Typical Performance Curves (Continued) FIGURE 21. Differential Pulse Skew (tPLH - tPHL) vs. Ambient Temperature FIGURE 22. Transition Time vs. Power Supply Voltage FIGURE 23. Transition Times vs. Ambient Temperature 9 www.fairchildsemi.com FIN1019 DC / AC Typical Performance Curves Receiver FIGURE 24. Output High Voltage vs. Power Supply Voltage FIGURE 25. Output Low Voltage vs. Power Supply Voltage FIGURE 26. Output Short Circuit Current vs. Power Supply Voltage FIGURE 27. Power Supply Current vs. Frequency FIGURE 28. Power Supply Current vs. Power Supply Voltage FIGURE 29. Power Supply Current vs. Ambient Temperature www.fairchildsemi.com 10 FIN1019 DC / AC Typical Performance Curves (Continued) FIGURE 30. Differential Propagation Delay vs. Power Supply Voltage FIGURE 31. Differential Propagation Delay vs. Ambient Temperature FIGURE 32. Differential Skew (tPHL - tPHL) vs. Power Supply Voltage FIGURE 33. Differential Skew (tPLH - tPHL) vs. Ambient Temperature FIGURE 34. Differential Propagation Delay vs. Differential Input Voltage FIGURE 35. Differential Propagation Delay vs. Common-Mode Voltage 11 www.fairchildsemi.com FIN1019 DC / AC Typical Performance Curves (Continued) FIGURE 36. Transition Time vs. Power Supply Voltage FIGURE 37. Transition Time vs. Ambient Temperature FIGURE 38. Differential Propagation Delay vs. Load FIGURE 39. Transition Time vs. Load www.fairchildsemi.com 12 FIN1019 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 13 www.fairchildsemi.com FIN1019 3.3V LVDS High Speed Differential Driver/Receiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 14 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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