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19-1979; Rev 0a; 3/01
Quad-Output TFT LCD DC-DC Converters with Buffer
General Description
The MAX1778/MAX1880-MAX1885 multiple-output DC-DC converters provide the regulated voltages required by active matrix thin-film transistor (TFT) liquid crystal displays (LCD) in a low-profile TSSOP package. One high-power step-up converter and two low-power charge pumps convert the 2.7V to 5.5V input voltage into three independent output voltages. A built-in linear regulator and VCOM buffer complete the power-supply requirements. The main step-up converter accurately generates an externally set output voltage up to 13V that can supply the display's row/column drivers. The converter's high switching frequency and current-mode PWM architecture provide fast transient response and allow the use of small low-profile inductors and ceramic capacitors. The low-power BiCMOS control circuitry and internal 14V switch (0.35 N-channel MOSFET) enable efficiencies up to 91%. The dual low-power charge pumps (MAX1778/ MAX1880/MAX1881/MAX1882 only) independently regulate one positive output (VPOS) and one negative output (V NEG ). These low-power outputs use external diode and capacitor stages (as many stages as required) to regulate output voltages up to +40V and -40V. A unique control scheme minimizes output ripple as well as capacitor sizes for both charge pumps. A resistor-programmable, 40mA, low-dropout linear regulator (MAX1778/MAX1881/MAX1883/MAX1884 only) provides preregulation or postregulation for any of the supplies. For higher current applications, an external transistor can be added. Additionally, the VCOM buffer provides a high current output that is ideal for driving the capacitive backplane of TFT LCD panels. The VCOM buffer's output voltage is preset with an internal 50% resistive-divider or can be externally adjusted for other voltages. The MAX1778/MAX1880-MAX1885 are protected against output undervoltage and thermal overload conditions by a latched fault detection circuit that shuts down the device. All devices are available in the ultrathin TSSOP package (1.1mm max height).
Features
o 500kHz/1MHz Current-Mode PWM Step-Up Regulator Up to +13V Main High-Power Output 1% Accurate High Efficiency (91%) o Dual Regulated Charge-Pump Outputs (MAX1778/MAX1880/MAX1881/MAX1882 only) Up to +40V Positive Charge-Pump Output Up to -40V Negative Charge-Pump Output o Low-Dropout 40mA Linear Regulator (MAX1778/MAX1881/MAX1883/MAX1884 only) Up to +15V LDO Input o Optional Higher Current with External Transistor o 2.7V to 5.5V Input Supply o Internal Supply Sequencing and Soft-Start o Power-Ready Output o Adjustable Fault-Detection Latch o Thermal Protection (+160C) o 0.1A Shutdown Current o 0.7mA IN Quiescent Current o Ultra-Small External Components o Thin TSSOP Package (1.1mm max height)
MAX1778/MAX1880-MAX1885
Ordering Information
PART MAX1778EUG MAX1880EUG MAX1881EUG MAX1882EUG MAX1883EUP MAX1884EUP MAX1885EUP TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 24 TSSOP 24 TSSOP 24 TSSOP 24 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP
Applications
TFT LCD Notebook Displays TFT LCD Desktop Monitor Panels
Typical Operating Circuit appears at end of data sheet. Pin Configurations and Selector Guide appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
ABSOLUTE MAXIMUM RATINGS
IN, SHDN, TGND, FLTSET to GND...........................-0.3V to +6V DRVN to GND .........................................-0.3V to (VSUPN + 0.3V) DRVP to GND..........................................-0.3V to (VSUPP + 0.3V) PGND to GND.....................................................................0.3V RDY, SUPB to GND ................................................-0.3V to +14V LX, SUPP, SUPN to PGND .....................................-0.3V to +14V SUPL to GND..........................................................-0.3V to +18V LDOOUT to GND ....................................-0.3V to (VSUPL + 0.3V) INTG, REF, FB, FBN, FBP to GND ...............-0.3V to (VIN + 0.3V) FBL to GND .............-0.3V to the lower of (VSUPL + 0.3V) or +6V BUFOUT, BUF+, BUF- to GND ...............-0.3V to (VSUPB + 0.3V) Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 10.9mW/C above +70C) ......879mW 24-Pin TSSOP (derate 12.2mW/C above +70C) ......975mW Operating Temperature Range MAX1778EUG, MAX1883EUP ........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER Input Supply Range Input Undervoltage Threshold SYMBOL VIN VUVLO VIN rising, 40mV hysteresis (typ) MAX1778/MAX1880/ MAX1883 (fOSC = 1MHz) MAX1881/MAX1882/ MAX1884/MAX1885 (fOSC = 500kHz) MAX1778/MAX1880 (fOSC = 1MHz) MAX1881/MAX1882 (fOSC = 500kHz) MAX1778/MAX1880 (fOSC = 1MHz) MAX1881/MAX1882 (fOSC = 500kHz) CONDITIONS MIN 2.7 2.2 2.4 0.7 TYP MAX 5.5 2.6 1 mA 0.6 1 UNITS V V
IN Quiescent Supply Current
IIN
VFB = VFBP = 1.5V, VFBN = -0.2V
0.4 0.3 0.4 0.3 0.1 0.1 0.1 0.1 6
0.7 mA 0.5 0.7 mA 0.5 10 10 10 10 13 A A A A A
SUPP Quiescent Current
ISUPP
VFBP = 1.5V
SUPN Quiescent Current
ISUPN
VFBN = -0.2V
IN Shutdown Current SUPP Shutdown Current SUPN Shutdown Current SUPL Shutdown Current SUPB Shutdown Current
VSHDN = 0, VIN = 5V VSHDN = 0, VSUPP = 13V, MAX1778/MAX1880/MAX1881/MAX1882 VSHDN = 0, VSUPN = 13V, MAX1778/MAX1880/MAX1881/MAX1882 VSHDN = 0, VSUPL = 13V MAX1778/MAX1881/MAX1883/MAX1884 VSHDN = 0, VSUPB = 13V
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Quad-Output TFT LCD DC-DC Converters with Buffer
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER MAIN STEP-UP CONVERTER Main Output Voltage Range FB Regulation Voltage FB Input Bias Current Operating Frequency Oscillator Maximum Duty Cycle Integrator enabled, CINTG = 1000pF Integrator disabled (INTG = REF) VMAIN VFB IFB fOSC Integrator enabled, CINTG = 1000pF Integrator disabled (INTG = REF) VFB = 1.25V, INTG = GND MAX1778/MAX1880/MAX1883 MAX1881/MAX1882/MAX1884/MAX1885 VIN 1.234 1.220 -50 0.85 425 80 1 500 85 0.01 % 0.2 0.1 317 RLX(ON) ILX ILX = 100mA VLX = 13V Phase I = soft-start (1024/fOSC) LX Current Limit ILIM Phase II = soft-start (1024/fOSC) Phase III = soft-start (1024/fOSC) Phase IV = fully-on (after 3072/fOSC) Maximum RMS LX Current Soft-Start Period FB Fault Trip Level tSS Power-up to the end of Phase III Falling edge, FLTSET = GND Falling edge, FLTSET = 1V 1.07 0.955 2.7 0.5 x fOSC 1.2 VFBP = 1.5V VFBP = 1.2V VFBP = 1.3V Rising edge Falling edge, FLTSET = GND Falling edge, FLTSET = 1V 20 0.1 1.09 1.08 0.955 1.125 1.11 0.99 1.16 1.16 1.025 -50 5 2 1.25 1.3 +50 10 4 1.15 0.275 0.35 0.01 0.38 0.75 1.12 1.5 1 3072 / fOSC 1.1 0.99 1.14 1.025 13 1.85 A s V 0.7 20 0.5 A %/V s A 1.247 13 1.260 1.280 +50 1.15 575 91 V V nA MHz kHz % SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1778/MAX1880-MAX1885
Load Regulation
ILX = 0 to 200mA, VMAIN = 10V
Line Regulation Integrator Transconductance LX Switch On-Resistance LX Leakage Current
POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 ONLY) VSUPP SUPP Input Supply Range Operating Frequency FBP Regulation Voltage FBP Input Bias Current DRVP PCH On-Resistance DRVP NCH On-Resistance Maximum RMS DRVP Current FBP Power-Ready Trip Level FBP Fault Trip Level fCHP VFBP IFBP RPCH(ON) RNCH(ON)
V Hz V nA k A V V
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER SUPN Input Supply Range Operating Frequency FBN Regulation Voltage FBN Input Bias Current DRVN PCH On-Resistance DRVN NCH On-Resistance Maximum RMS DRVN Current FBN Power-Ready Trip Level FBN Fault Trip Level SUPL Input Supply Range SUPL Undervoltage Lockout SUPL Quiescent Current Dropout Voltage (Note 1) FBL Regulation Voltage LDO Load Regulation LDO Line Regulation FBL Input Bias Current LDO Current Limit VCOM BUFFER SUPB Input Supply Range SUPB Quiescent Current BUFOUT Leakage Current Power-Supply Rejection Ratio Input Common-Mode Voltage Range Common-Mode Rejection Ratio Input Bias Current Input Offset Current Gain Bandwidth Product PSRR VCM CMRR IBIAS IOS GBW VSUPB = 4.5V to 13V, VCM = 2.25V |VOS| < 10mV VCM = 1.2V to 8.8V VCM = 5V VCM = 5V CBUF = 1F VSUPB ISUPB VSUPB = 13V -10 85 1.2 75 -100 -100 13 -10 +100 +100 98 8.8 4.5 420 13 850 +10 V A A dB V dB nA nA kHz IFBL ILDOLIM ISUPL VDROP VFBL VSUPL Rising edge, 50mV hysteresis (typ) ILDO = 100A LDO is set to regulate at 9V ILDO = 40mA ILDO = 5mA 1.235 Falling edge Rising edge 80 80 4.5 3.8 4 120 130 70 1.25 1.265 1.2 0.02 -0.8 40 130 +0.8 220 SYMBOL VSUPN fCHP VFBN IFBN RPCH(ON) RNCH(ON) VFBN = +50mV VFBN = -50mV 20 0.1 125 140 165 190 15 4.3 220 300 VFBN = 0 -50 -50 5 2 CONDITIONS MIN 2.7 0.5 x fOSC 0 +50 +50 10 4 TYP MAX 13 UNITS V Hz mV nA k A mV mV V V A mV V % %/V A mA
NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 ONLY)
LOW-DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 ONLY)
VSUPL = 10V, LDO regulating at 9V, ILDO = 15mA VSUPL = 10V, LDO regulating at 9V, ILDO = 100A to 40mA VSUPL = 4.5V to 15V, FBL = LDOOUT, ILDO = 15mA VFBL = 1.25V VSUPL = 10V, VLDOOUT = 9V, VFBL = 1.2V
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER Output Voltage SYMBOL VBUFOUT BUF+ = GND CONDITIONS IBUFOUT = 0 IBUFOUT = 5mA IBUFOUT = 45mA Input Offset Voltage Output Voltage Swing High Output Voltage Swing Low Peak Buffer Output Current BUF+ Dual ModeTM Threshold Voltage REFERENCE Reference Voltage Reference Undervoltage Threshold LOGIC SIGNALS SHDN Input Low Voltage SHDN Input High Voltage SHDN Input Current FLTSET Input Voltage Range FLTSET Threshold Voltage FLTSET Input Current RDY Output Low Voltage RDY Output High Leakage Thermal Shutdown Rising edge, 25mV hysteresis (typ) VFLTSET = 1V ISINK = 2mA V RDY = 13V Rising temperature ISHDN 0.67 x VREF 80 125 0.1 0.25 0.01 160 2.1 0.01 1 0.85 x VREF 170 50 0.5 1 0.9 V V A V mV nA V A C VREF -2A < IREF < 50A 1.231 0.9 1.25 1.05 1.269 1.2 V V Falling edge, 20mV hysteresis (typ) 80 VOS VOH VOL VSUPB = 4.5V to 13V, VCM = 1.2V to (VSUPB -1.2V) IBUFOUT = 5mA IBUFOUT = 45mA MIN 4.99 4.97 4.93 -30 -70 9 9.6 0.4 150 125 170 1 TYP MAX 5.01 5.03 5.07 30 mV 70 V V mA mV V UNITS
IBUFOUT = -45mA, VOS = 1V IBUFOUT = +45mA, VOS = 1V
Dual Mode is a registered trademark of Maxim Integrated Products, Inc.
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
ELECTRICAL CHARACTERISTICS
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER Input Supply Range Input Undervoltage Threshold SYMBOL VIN VUVLO VIN Rising, 40mV hysteresis (typ) VFB = VFBP = 1.5V, VFBN = -0.2V MAX1778/MAX1880/ MAX1883 (fOSC = 1MHz) MAX1881/MAX1882/MAX1884/ MAX1885 (fOSC = 500kHz) MAX1778/MAX1880 (fOSC = 1MHz) MAX1881/MAX1882 (fOSC = 500kHz) MAX1778/MAX1880 (fOSC = 1MHz) MAX1881/MAX1882 (fOSC = 500kHz) CONDITIONS MIN 2.7 2.2 MAX 5.5 2.6 1 mA 1 0.7 mA 0.5 0.7 mA 0.5 10 10 10 10 13 VIN Integrator enabled, CINTG = 1000pF Integrator disabled (INTG = REF) VFB = 1.25V, INTG = GND MAX1778/MAX1880/MAX1883 MAX1881/MAX1882/MAX1884/MAX1885 1.223 1.21 -50 0.75 375 79 RLX(ON) ILX ILIM ILX = 100mA VLX = 13V Phase I = soft-start (1024/fOSC) Phase IV = fully on (after 3072/fOSC) Falling edge, FLTSET = GND 0.275 1.1 1.07 13 1.269 1.29 +50 1.25 625 91 0.7 20 0.525 2.05 1.14 A A A A A V V nA MHz kHz % A A V UNITS V V
IN Quiescent Supply Current
IIN
SUPP Quiescent Current
ISUPP
VFBP = 1.5V
SUPN Quiescent Current
ISUPN
VFBN = -0.2V
IN Shutdown Current SUPP Shutdown Current SUPN Shutdown Current SUPL Shutdown Current SUPB Shutdown Current MAIN STEP-UP CONVERTER Main Output Voltage Range FB Regulation Voltage FB Input Bias Current Operating Frequency Oscillator Maximum Duty Cycle LX Switch On-Resistance LX Leakage Current LX Current Limit FB Fault Trip Level VMAIN VFB IFB FOSC
VSHDN = 0, VIN = 5V VSHDN = 0, VSUPP = 13V, MAX1778/MAX1880/MAX1881/MAX1882 VSHDN = 0, VSUPN = 13V, MAX1778/MAX1880/MAX1881/MAX1882 VSHDN = 0, VSUPL = 13V, MAX1778/MAX1881/MAX1883/MAX1884 VSHDN = 0, VSUPB = 13V
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER SUPP Input Supply Range FBP Regulation Voltage FBP Input Bias Current DRVP PCH On-Resistance DRVP NCH On-Resistance FBP Power-Ready Trip Level SUPN Input Supply Range FBN Regulation Voltage FBN Input Bias Current DRVN PCH On-Resistance DRVN NCH On-Resistance FBN Power-Ready Trip Level SUPL Input Supply Range SUPL Undervoltage Lockout SUPL Quiescent Current Dropout Voltage (Note 1) FBL Regulation Voltage LDO Load Regulation LDO Line Regulation FBL Input Bias Current LDO Current Limit VCOM BUFFER SUPB Input Supply Range SUPB Quiescent Current BUFOUT Leakage Current Input Common-Mode Voltage VSUPB ISUPB VCM VSUPB = 13V -10 |VOS| < 10mV 1.2 4.5 13 850 +10 8.8 V A A V IFBL ILDOLIM ISUPL VDROP VFBL VSUPL Rising edge, 50mV hysteresis (typ) ILDO = 100A LDO regulating to 9V, ILDO = 40mA VSUPL = 10V, LDO regulating to 9V, ILDO = 15mA VSUPL = 10V, LDO regulating to 9V, ILDO = 100A to 40mA VSUPL = 4.5V to 15V, FBL = LDOOUT, ILDO = 15mA VFBL = 1.25V VSUPL = 10V, VLDOOUT = 9V, VFBL = 1.2V -1.2 40 1.222 VSUPN VFBN IFBN RPCH(ON) RNCH(ON) VFBN = +50mV VFBN = -50mV Falling edge 20 80 4.5 3.8 165 15 4.3 240 330 1.265 1.2 0.02 +1.2 260 VFBN = 0 SYMBOL VSUPP VFBP IFBP RPCH(ON) RNCH(ON) VFBP = 1.2V VFBP = 1.3V Rising edge 20 1.09 2.7 -50 -50 1.16 13 +50 +50 10 4 VFBP = 1.5V CONDITIONS MIN 2.7 1.2 -50 MAX 13 1.3 +50 10 4 UNITS V V nA k V V mV nA k mV V V A mV V % %/V A mA
POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 ONLY)
NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 ONLY)
LOW DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 ONLY)
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER Input Bias Current Input Offset Current Output Voltage SYMBOL IBIAS IOS VBUFOUT VCM = 5V VCM = 5V IBUFOUT = 0 BUF+ = GND IBUFOUT = 5mA IBUFOUT = 45mA Input Offset Voltage Output Voltage Swing High Output Voltage Swing Low BUF+ Dual Mode Threshold Voltage REFERENCE Reference Voltage Reference Undervoltage Threshold LOGIC SIGNALS SHDN Input Low Voltage SHDN Input High Voltage SHDN Input Current FLTSET Input Voltage Range FLTSET Threshold Voltage FLTSET Input Current RDY Output Low Voltage RDY Output High Leakage Rising edge, 25mV hysteresis (typ) VFLTSET = 1V ISINK = 2mA V RDY = 13V I SHDN 0.74 x VREF 80 2.1 1 0.85 x VREF 170 50 0.5 1 0.9 V V A V mV nA V A VREF -2A < IREF < 50A 1.223 0.9 1.269 1.2 V V VOS VOH VOL VSUPB = 4.5V to 13V VCM = 1.2V to (VSUPB - 1.2V) IBUFOUT = 5mA IBUFOUT = 45mA CONDITIONS MIN -500 -500 4.988 4.97 4.93 -30 -70 9 1 80 170 MAX +500 +500 5.012 5.03 5.07 30 mV 70 V V mV V UNITS nA nA
IBUFOUT = -45mA, VOS = 1V IBUFOUT = +45mA, VOS = 1V Falling edge, 20mV hysteresis (typ)
Note 1: Dropout Voltage is defined as the VSUPL - VLDOOUT, when VSUPL is 100mV below the set value of VLDOOUT. Note 2: Specifications to -40C are guaranteed by design, not production tested.
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Typical Operating Characteristics
(Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.)
MAIN 8V OUTPUT VOLTAGE vs. LOAD CURRENT
MAX1778 toc01
MAIN 8V OUTPUT EFFICIENCY vs. LOAD CURRENT
VIN = 5V 90 EFFICIENCY (%) 80 70 60 50 40 VOUT = 8V RCOMP = 24k CCOMP = 470pF CINTG = 470pF 0 200 400 IOUT (mA) 600 800 VIN = 3.3V VOUT (V)
MAX1778 toc02
MAIN 12V OUTPUT VOLTAGE vs. LOAD CURRENT
MAX1778 toc03
8.12 8.08 8.04 VOUT (V) 8.00 7.96 7.92 7.88 0 200 400 IOUT (mA) 600 CINTG = 470pF RCOMP = 24k CCOMP = 470pF VIN = 5V VIN = 3.3V
100
12.24 12.16 12.08 12.00 VIN = 5V 11.92 11.84 11.76 0 100 200 300 IOUT (mA) 400 500 FIGURE 8 CINTG = 470pF
VIN = 3.3V
800
600
MAIN 12V OUTPUT EFFICIENCY vs. LOAD CURRENT
MAX1778 toc04
STEP UP CONVERTERS SWITCHING FREQUENCY vs. INPUT VOLTAGE
MAX1778 1.15 SWITCHING FREQUENCY (MHz) 1.10 VPOS (V) 1.05 1.00 0.95 0.90 0.85 0.80
MAX1778 toc05
POSITIVE CHARGE-PUMP OUTPUT VOLTAGE vs. LOAD CURRENT
MAX1778 toc06
100 VIN = 5V 90 EFFICIENCY (%) 80 70 60 50 40 0 100 200 300 IOUT (mA) 400 500 FIGURE 8 VOUT = 12V CINTG = 470pF VIN = 3.3V
1.20
20.2 VSUPP = 10V
20.0
19.8 VSUPP = 8V 19.6 VSUPP = 7.5V VSUPP = 7V
19.4
19.2 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 0 5 10 IPOS (mA) 15 20
600
POSITIVE CHARGE-PUMP EFFICIENCY vs. LOAD CURRENT
MAX1778 toc07
MAXIMUM POSITIVE CHARGE-PUMP OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
MAX1778 toc08
NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE vs. LOAD CURRENT
MAX1778 toc09
100 90 80 EFFICIENCY (%) 70 60 50 40 30 0 5 10 INEG (mA) 15 VSUPP = 10V VSUPP = 7V VSUPP = 7.5V VSUPP = 8V
40 35 30 VPOS (V) 25 IPOS = 10mA 20 15
-4.90 -4.92 -4.94 VSUPN = 6V VSUPN = 7V
IPOS = 1mA VNEG (V) -4.96 -4.98 -5.00 -5.02 -5.04 2 4 6 8 VSUPP (V) 10 12 14 0 10 20 INEG (mA) 30 40 VSUPN = 8V
VPOS = 20V 20
10 5
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.)
NEGATIVE CHARGE-PUMP EFFICIENCY vs. LOAD CURRENT
MAX1778 toc10
MAXIMUM NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
MAX1778 toc11
REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT
MAX1778 toc12
100 VNEG = -5V 90 80 EFFICIENCY (%) 70 60 50 40 30 0 10 20 INEG (mA) 30 VSUPN = 6V
-2 -4 -6 VNEG (V) -8 -10 INEG = 10mA
1.27
1.26 VREF (V) VSUPN = 7V
VSUPN = 8V
INEG = 1mA
1.25
1.24 -12 -14 40 2 4 6 8 VSUPN (V) 10 12 14 1.23 0 20 40 60 80 100 IREF (A)
STEP-UP CONVERTER LOAD-TRANSIENT RESPONSE
MAX1778 toc13
STEP-UP CONVERTER LOAD-TRANSIENT RESPONSE WITHOUT INTEGRATOR
MAX1778 toc14
STEP-UP CONVERTER LOAD-TRANSIENT RESPONSE (1s PULSES)
MAX1778 toc15
200mA A 0 8.1V 8.0V 7.9V 1A C 0 B
200mA A 0 8.1V 8.0V 7.9V 1A C 0 B
0.5A A 0 8.0V 7.9V 1A 0.5A C 0 B
40s/div A. IMAIN = 20mA to 200mA, 200mA/div B. VMAIN = 8V, 100mV/div C. INDUCTOR CURRENT, 1A/div CINTG = 1000pF
40s/div A. IMAIN = 20mA to 200mA, 200mA/div B. VMAIN = 8V, 100mV/div C. INDUCTOR CURRENT, 1A/div INTG = REF
4s/div A. IMAIN = 0 to 500mA, 500mA/div B. VMAIN = 8V, 100mV/div C. INDUCTOR CURRENT, 500mA/div
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.)
RIPPLE VOLTAGE WAVEFORMS
MAX1778 toc16
STEP-UP CONVERTER SOFT-START (LIGHT LOAD)
MAX1778 toc17
STEP-UP CONVERTER SOFT-START (HEAVY LOAD)
MAX1778 toc18
2V 8V A A 0 8V -5V B 6V 4V 20V C 0 0.5A C B
2V A 0 8V 6V 4V 1.0A C 0.5A 0 B
1s/div A. VMAIN = 8V, IMAIN = 200mA, 10mV/div B. VNEG = -5V, INEG = 10mA, 20mV/div C. VPOS = 20V, IPOS = 5mA, 20mV/div
1ms/div A. VSHDN = O TO 2V, 2V/div B. VMAIN = 8V, 2V/div C. INDUCTOR CURRENT, 500mA/div RLOAD = 400
1ms/div A. VSHDN = O TO 2V, 2V/div B. VMAIN = 8V, 2V/div C. INDUCTOR CURRENT, 500mA/div RLOAD = 20
POWER-UP SEQUENCE
MAX1778 toc19
POWER-UP SEQUENCE (CIRCUIT OF FIG.10)
4V 2V A 0 20V B C D E 10V 0 0 D -5V 5V 0 1ms/div A. RDY, 2V/div B. POSITIVE CHARGE PUMP, VPOS(SYS) = 20V, 10V/div C. STEP-UP CONVERTER: VMAIN(SYS) = 8V, 10V/div D. NEGATIVE CHARGE PUMP, VNEG = -5V, -5V/div B C
MAX1778 toc20
POWER-UP INTO SHORT-CIRCUIT (CIRCUIT OF FIG. 10)
MAX1778 toc21
2V 0 5V 0 20V 10V 0 -10V 2ms/div A. VSHDN = O TO 2V, 2V/div B. RDY, 5V/div C. POSITIVE CHARGE PUMP = VPOS = 20V, RLOAD = 4k, 10V/div D. STEP-UP CONVERTER: VMAIN = 8V, RLOAD = 40, 10V/div E. NEGATIVE CHARGE PUMP: VNEG = -5V, RLOAD = 500, 10V/div
A
4V 2V 0 5V 0 10V C 100s/div A. RDY, 2V/div B. GATE OF N-CH MOSFET, 5V/div C. STEP-UP CONVERTER, VMAIN(START) = 8V, 5V/div VMAIN(SYS) = GND B A
______________________________________________________________________________________
11
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.)
LDO OUTPUT VOLTAGE vs. LDO INPUT VOLTAGE (INTERNAL LINEAR REGULATOR)
MAX1778 toc22
LDO OUTPUT VOLTAGE vs. LDO OUTPUT CURRENT (INTERNAL LINEAR REGULATOR)
MAX1778 toc23
LDO OUTPUT VOLTAGE vs. TEMPERATURE (INTERNAL LINEAR REGULATOR)
5.08 5.06 5.04 VLDO (V) 5.02 5.00 4.98 4.96 4.94 ILDOOUT = 40mA ILDOOUT = 0
MAX1778 toc24
5.05 ILDOOUT = 0 5.00 4.95 ILDOOUT = 40mA 4.90 4.85 4.80 4.75 4 6 8 VSUPL (V) 10
5.04 5.02 5.00 VLDOOUT (V) 4.98 4.96 4.94 4.92 4.90
5.10
VLDOOUT (V)
4.92 4.90 0.01 0.1 1 ILDOOUT (mA) 10 100 -40 -15 10 35 60 85 TEMPERATURE (C)
12
DROPOUT VOLTAGE vs. LDO LOAD CURRENT (INTERNAL LINEAR REGULATOR)
MAX1778 toc25
LDO SUPPLY CURRENT vs. LDO OUTPUT CURRENT (INTERNAL LINEAR REGULATOR)
VLDOOUT = 5V 3.5 ISUPL - ILDOOUT (mA) 3.0 2.5 2.0 1.5 1.0 0.5
MAX1778 toc26
200 VLDOOUT = 5V 160 VSUPL - VLDOOUT (mV)
4.0
120
80
40
0 0 10 20 ILDOOUT (mA) 30 40
0 0 10 20 ILDOOUT (mA) 30 40
12
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.)
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
MAX1778 toc27
REGION OF STABLE CLDOOUT ESR vs. LOAD CURRENT
CLDOOUT = 1F 10 CLDOOUT ESR ()
MAX1778 toc28
LOAD-TRANSIENT RESPONSE (INTERNAL LINEAR REGULATOR)
MAX1778 toc29
100
100
4OmA 0 A
80
PSRR (dB)
60
1 5.00V 0.1 STABLE REGION 4.96V 0.01 0 10 20 ILDOOUT (mA) 30 40 100s/div A. ILDO = 100A TO 40mA, 40mA/div B. VLDO = 5V, 20mV/div VSUPL = VLDO + 500mV B
40
20
CLDOOUT = 4.7F ILDOOUT = 40mA 1 10 100 1000
0 FREQUENCY (kHz)
LOAD-TRANSIENT RESPONSE NEAR DROPOUT (INTERNAL LINEAR REGULATOR)
MAX1778 toc30
INTERNAL LINEAR-REGULATOR RIPPLE REJECTION
MAX1778 toc31
INTERNAL LINEAR-REGULATOR STARTUP
MAX1778 toc32
4OmA 0 A
5.0V
A
2V 0
A
B 8.0V 5.00V B 1.0A 0.5A 4.94V 100s/div A. ILDO = 100A TO 40mA, 40mA/div B. VLDO = 5V, 20mV/div VIN = VLDO + 100mV 0 C 4V 2V 10s/div A. VLDOOUT = 5V, ILDOOUT = 40mA, 10mV/div B. VMAIN = VSUPL = 8V, 200mV/div C. IMAIN = 0 TO 750mA, 500mA/div 400s/div A. VSHDN = 0 TO 2V, 2V/div B. VLDOOUT = 5V, RLDOOUT = 125, 2V/div C. VMAIN = 8V, RMAIN = 40, 2V/div B 4V 2V 0 C
______________________________________________________________________________________
13
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.)
LINEAR-REGULATOR OUTPUT VOLTAGE vs. INPUT VOLTAGE (EXTERNAL LINEAR REGULATOR)
MAX1778 toc33
LINEAR-REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT (EXTERNAL LINEAR REGULATOR)
FIGURE 7 2.53
MAX1778 toc34
EXTERNAL LINEAR-REGULATOR LOAD-TRANSIENT RESPONSE
MAX1778 toc35
2.55
2.55
250mA 50mA A
2.53
VLDO (V)
VLDO (V)
2.51
ILDO = 0 ILDO = 750mA
2.51 2.55V 2.49 2.50V 2.45V B
2.49
2.47 FIGURE 7 2.45 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5
2.47
2.45 0.1 1 10 ILDO (mA) 100 1000 100s/div A. ILDO = 50mA TO 250mA, 200mA/div B. VLDO = 2.5V, 50mV/div FIGURE 7
EXTERNAL LINEAR-REGULATOR RIPPLE REJECTION
MAX1778 toc36
INPUT OFFSET VOLTAGE DEVIATION vs. COMMON-MODE VOLTAGE
MAX1778 toc37
INPUT OFFSET VOLTAGE DEVIATION vs. BUFFER SUPPLY VOLTAGE
VCM = VSUPB / 2 0.6
MAX1778 toc38
2.5 A 1.5 B VSUPB = 4.5V VOS (mV) 0.5 VSUPB = 13V
1.0
2.5V
VOS (mV)
8.0V 7.8V 1A 0.5A 0
0.2
-0.5
-0.2
C
-1.5
-0.6
-2.5 10s/div A. VLDO = 2.5V, ILDO = 200mA, 10mV/div B. VMAIN = VSUPL = 8V, 200mV/div C. IMAIN = 0 TO 750mA, 500mA/div FIGURE 7 0 2 4 6 8 10 12 14 VCM (V)
-1.0 4 6 8 10 12 14 VSUPB (V)
14
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Quad-Output TFT LCD DC-DC Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.)
INPUT OFFSET VOLTAGE DEVIATION vs. TEMPERATURE
MAX1778 toc39
MAX1778/MAX1880-MAX1885
INPUT OFFSET VOLTAGE DEVIATION vs. TEMPERATURE
MAX1778 toc39
BUFFER INPUT BIAS CURRENT vs. COMMON-MODE VOLTAGE
VSUPB = 13V 8
MAX1778 toc41
1.0 VSUPB = 13V VCM = VSUPB / 2 0.6
1.0 VSUPB = 13V VCM = VSUPB / 2 0.6
10
VOS (mV)
IBIAS (nA)
0.2
VOS (mV)
0.2
6 VSUPB = 4.5V 4
-0.2
-0.2
-0.6
-0.6
2
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 2 4 6 8 10 12 14 VCM (V)
BUFFER INPUT BIAS CURRENT vs. BUFFER SUPPLY VOLTAGE
MAX1778 toc42
BUFFER INPUT BIAS CURRENT vs. TEMPERATURE
MAX1778 toc43
BUFFER SUPPLY CURRENT vs. COMMON-MODE VOLTAGE
VSUPB = 13V 0.46
MAX1778 toc44
10
12 VCM = VSUPB / 2 11 10
0.50
8 IBIAS (nA) IBIAS (nA)
ISUPB (mA)
9 8 7 6 5
0.42
0.38
VSUPB = 4.5V
6
0.34
VCM = VSUPB / 2 4 4 6 8 10 12 14 VSUPB (V) 4 -40 -15 10 35 60 85 TEMPERATURE (C) 0.30 0 2 4 6 8 10 12 14 VCM (V)
BUFFER SUPPLY CURRENT vs. BUFFER SUPPLY VOLTAGE
MAX1778 toc45
NO-LOAD BUFFER SUPPLY CURRENT vs. TEMPERATURE
0.9 0.8 0.7 VSUPB = 13V VCM = VSUPB / 2
MAX1778 toc46
VCOM BUFFER SMALL-SIGNAL RESPONSE
MAX1778 toc47
0.50
1.0
4.05V 4.00V 3.95V A
0.46
ISUPB (mA)
0.42
ISUPB (mA)
0.6 0.5 0.4 0.3
0.38
4.05V 4.00V 3.95V -40 -15 10 35 60 85 4s/div A. VBUF+ = 3.95V TO 4.05V, 50mV/div B. BUFOUT = BUF-, 50mV/div CBUF = 1F, VSUPB = 8V B
0.34 VCM = VSUPB / 2 0.30 4 6 8 10 12 14 VSUPB (V)
0.2 0.1 0 TEMPERATURE (C)
______________________________________________________________________________________
15
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.)
VCOM BUFFER LARGE-SIGNAL RESPONSE
MAX1778 toc48
VCOM BUFFER LOAD-TRANSIENT RESPONSE
MAX1778 toc49
VCOM BUFFER LOAD-TRANSIENT RESPONSE
MAX1778 toc50
4.50V 4.00V 3.50V A
200mA 0 -200mA 4.2V A
500mA 0 -500mA 4.5V B 4.0V 3.5V C 4s/div A. IBUFOUT = 200mA PULSES, 200mA/div B. BUFOUT = BUF-, 200mV/div C. VMAIN = 8V, 50mV/div VSUPB = VMAIN, BUF+ = GND, CBUF = 1F 8.0V C 4s/div A. IBUFOUT = 400mA PULSES, 500mA/div B. BUFOUT = BUF-, 0.5V/div C. VMAIN = 8V, 100mV/div VSUPB = VMAIN, BUF+ = GND, CBUF = 1F B A
4.50V 4.00V 3.50V 10s/div A. VBUF+ = 3.50V TO 4.50V, 0.5V/div B. BUFOUT = BUF-, 0.5V/div CBUF = 1F, VSUPB = 8V B
4.0V 3.8V 8.0V
VCOM BUFFER STARTUP
4V 2V 0 4V 2V 0 8.1V 7.8V 100s/div A. RDY, 2V/div B. BUFOUT = BUF-, CBUF = 1F, 2V/div C. VSUPB = VMAIN = 8V, IMAIN = 20mA, 200mV/div BUF+ = GND C B
MAX1778 toc51
VCOM BUFFER STARTUP
4V
A
MAX1778 toc51
2V 0 4V 2V 0 8.1V 7.8V 100s/div A. RDY, 2V/div B. BUFOUT = BUF-, CBUF = 1F, 2V/div C. VSUPB = VMAIN = 8V, IMAIN = 20mA, 200mV/div BUF+ = GND
A
B
C
16
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Quad-Output TFT LCD DC-DC Converters with Buffer
Pin Description
PIN MAX1778 MAX1881 1 MAX1880 MAX1882 1 MAX1883 MAX1884 1 MAX1885 NAME FUNCTION Main Step-Up Regulator Feedback Input. Regulates to 1.25V nominal. Connect a resistive divider from the output (VMAIN) to FB to analog ground (GND). Main Step-Up Integrator Output. When using the integrator, connect 1000pF to analog ground (GND). To disable the integrator, connect INTG to REF. Main Supply Voltage. The supply voltage powers the control circuitry for all of the regulators and may range from 2.7V to 5.5V. Bypass with a 0.1F capacitor between IN and GND, as close to the pins as possible. VCOM Buffer (Operational Transconductance Amplifier) Positive Feedback Input. Connect to GND to select the internal resistive divider that sets the positive input to half the amplifier's supply voltage (VBUF+ = V SUPB /2). VCOM Buffer (Operational Transconductance Amplifier) Negative Feedback Input VCOM Buffer (Operational Transconductance Amplifier) Supply Voltage VCOM Buffer (Operational Transconductance Amplifier) Output Analog Ground. Connect to power ground (PGND) underneath the IC. Internal Reference Bypass Terminal. Connect a 0.22F ceramic capacitor from REF to analog ground (GND). External load capability up to 50A. Positive Charge-Pump Regulator Feedback Input. Regulates to 1.25V nominal. Connect a resistive divider from the positive charge-pump output (VPOS) to FBP to analog ground (GND). Negative Charge-Pump Regulator Feedback Input. Regulates to 0V nominal. Connect a resistive divider from the negative chargepump output (VNEG) to FBN to the reference (REF). Active-Low Shutdown Control Input. Pull SHDN low to force the controller into shutdown. If unused, connect SHDN to IN for normal operation. A rising edge on SHDN clears the fault latch. Low-Dropout Linear Regulator Input Voltage. Can range from 4.5V to 15V. Bypass with a 1F capacitor to GND (see Capacitor Selection and Regulator Stability). Connect both input pins together externally.
MAX1778/MAX1880-MAX1885
1
FB
2
2
2
2
INTG
3
3
3
3
IN
4
4
4
4
BUF+
5 6 7 8
5 6 7 8
5 6 7 8
5 6 7 8
BUFSUPB BUFOUT GND
9
9
9
9
REF
10
10
-
-
FBP
11
11
-
-
FBN
12
12
10
10
SHDN
13
-
11
-
SUPL
______________________________________________________________________________________
17
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Pin Description (continued)
PIN MAX1778 MAX1881 MAX1880 MAX1882 MAX1883 MAX1884 MAX1885 NAME FUNCTION Linear Regulator Output. Sources up to 40mA. Bypass to GND with a ceramic capacitor determined by: 14 - 12 - LDOOUT
ILDOOUT(MAX) CLDOOUT 0.5ms X VLDOOUT
15
-
13
-
FBL
Voltage Setting Input. Connect a resistive divider from the linear regulator output (VLDOOUT) to FBL to analog ground (GND). Fault Trip-Level Set Input. Connect to a resistive divider between REF and GND to set the main step-up converter's and positive charge pump's fault thresholds between 0.67 x VREF and 0.85 x VREF. Connect to GND for the preset fault threshold (0.9 x VREF). Negative Charge-Pump Driver Supply Voltage. Bypass to power ground (PGND) with a 0.1F capacitor. Negative Charge-Pump Driver Output. Output high level is VSUPN and low level is PGND. Positive Charge-Pump Driver Supply Voltage. Bypass to power ground (PGND) with a 0.1F capacitor. Positive Charge-Pump Driver Output. Output high level is VSUPP and low level is PGND Power Ground. Connect to analog ground (GND) underneath the IC. Main Step-Up Regulator Power MOSFET N-Channel Drain. Place output diode and output capacitor as close to PGND as possible. Must be connected to ground. Active-Low, Open-Drain Output. Indicates all outputs are ready. On-resistance is 125 (typ). No Connection. Not internally connected.
16
16
14
14
FLTSET
17 18 19 20 21 22 23 24 -
17 18 19 20 21 22 23 24 13, 14, 15
- - - - 17 18 19 20 15, 16
- - - - 17 18 19 20 11, 12, 13, 15, 16
SUPN DRVN SUPP DRVP PGND LX TGND RDY N.C.
18
______________________________________________________________________________________
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
L1 6.8H INPUT VIN = 3.3V CIN 4.7F TO LOGIC LDO VLDOOUT = 5V CLDO 4.7F MAIN (8V) R7 150k C2 0.1F FBL RRDY 100k R2 274k R2 49.9k MAIN VMAIN = 8V COUT (2) 4.7F
C1 0.22F
IN SHDN RDY SUPL LDOOUT
LX FB SUPB SUPN SUPP MAX1778 DRVP
R8 49.9k
C4 0.1F C4 0.1F R3 750k
C5 1.0F
DRVN FBN C3 1.0F R5 200k R6 49.9k CREF 0.22F REF INTG FLTSET PGND BUFOUT BUFBUF+ GND TGND CBUF 1.0F FBP R4 49.9k
C7 1.0F POSITIVE VPOS = 20V
NEGATIVE VNEG = -5V
BUFFER OUTPUT VBUFOUT = VSUPB/2
Figure 1. Typical Application Circuit
Detailed Description
The MAX1778/MAX1880-MAX1885 are highly efficient multiple-output power supplies for thin-film transistor (TFT) liquid crystal display (LCD) applications. The devices contain one high-power step-up converter, two low-power charge pumps, an operational transconductance amplifier (VCOM buffer), and a low-dropout linear regulator. The primary step-up converter uses an internal N-channel MOSFET to provide maximum efficiency and to minimize the number of external components. The output voltage of the main step-up converter (VMAIN) can be set from VIN to 13V with external resistors. The dual charge pumps (MAX1778/MAX1880/ MAX1881/MAX1882 only) independently regulate a positive output (VPOS) and a negative output (VNEG). These low-power outputs use external diode and capacitor stages (as many stages as required) to regulate output voltages from -40V to +40V. A unique
control scheme minimizes output ripple as well as capacitor sizes for both charge pumps. A resistor-programmable 40mA linear regulator (MAX1778/MAX1881/MAX1883/MAX1884 only) can provide preregulation or postregulation for any of the supplies. For higher current applications, an external transistor can be added. Additionally, the VCOM buffer provides a high current output that is ideal for driving capacitive loads, such as the backplane of a TFT LCD panel. The positive feedback input features dual mode operation, allowing this input to be connected to an internal 50% resistivedivider between the buffer's supply voltage and ground, or externally adjusted for other voltages. Also included in the MAX1778/MAX1880-MAX1885 is a precision 1.25V reference that sources up to 50A, logic shutdown, soft-start, power-up sequencing, adjustable fault detection, thermal shutdown, and an active-low, open-drain ready output.
______________________________________________________________________________________
19
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Main Step-up Controller
During normal pulse-width modulation (PWM) operation, the MAX1778/MAX1880-MAX1885 main step-up controllers switch at a constant frequency of 500kHz or 1MHz (see Selector Guide), allowing the use of lowprofile inductors and output capacitors. Depending on the input-to-output voltage ratio, the controller regulates the output voltage and controls the power transfer by modulating the duty cycle (D) of each switching cycle: D VMAIN - VIN VMAIN in the feedback voltage-error signal shift the switch-current trip level, consequently modulating the MOSFET duty cycle. Under very light loads, an inherent switchover to pulseskipping takes place (Figure 3). When this occurs, the controller skips most of the oscillator pulses in order to reduce the switching frequency and gate charge losses. When pulse-skipping, the step-up controller initiates a new switching cycle only when the output voltage drops too low. The N-channel MOSFET turns on, allowing the inductor current to ramp up until the multi-input comparator trips. Then, the MOSFET turns off and the diode turns on, forcing the inductor current to ramp down. When the inductor current reaches zero, the diode turns off, so the inductor stops conducting current. This forces the threshold between pulse-skipping and PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation: ILOAD(CROSSOVER) 1 VIN 2 VMAIN
2
On the rising edge of the internal clock, the controller sets a flip-flop when the output voltage is too low, which turns on the N-channel MOSFET (Figure 2). The inductor current ramps up linearly, storing energy in a magnetic field. Once the sum of the feedback voltage error amplifier, slope-compensation, and current-feedback signals trip the multi-input comparator, the MOSFET turns off, the flip-flop resets, and the diode (D1) turns on. This forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and load. The MOSFET remains off for the rest of the clock cycle. Changes
VMAIN - VIN fOSCL
L1
MAX1778 MAX1880 MAX1881 MAX1882 MAX1883 MAX1884 MAX1885
OSC (80% DUTY)
VIN (2.7V TO 5.5V) CIN
LX S
D1
VMAIN (UP TO 13V) COUT
R
Q ILIM
PWM COMPARATOR ILIM COMPARATOR
R1 PGND RCOMP (OPTIONAL) FB CCOMP (OPTIONAL) REF VREF 1.25V INTG GND CREF VMAIN = 1 + R1 R2 VREF = 1.25V R2
gm ERROR AMPLIFIER
( )V
REF
CINTG
Figure 2. Main Step-Up Converter block Diagram 20 ______________________________________________________________________________________
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
The switching waveforms will appear noisy and asynchronous when light loading causes pulse-skipping operation; this is a normal operating condition that improves light-load efficiency.
Dual Charge-Pump Regulator (MAX1778/ MAX1880/MAX1881/MAX1882 Only)
The MAX1778/MAX1880/MAX1881/MAX1882 controllers contain two independent low-power charge pumps (Figure 4). One charge pump inverts the input voltage and provides a regulated negative output voltage. The second charge pump doubles the input voltage and provides a regulated positive output voltage. The controllers contain internal P-channel and N-channel MOSFETs to control the power transfer. The internal MOSFETs switch at a constant frequency (fCHP = fOSC/2). Positive Charge Pump During the first half-cycle, the N-channel MOSFET turns on and charges flying capacitor CX(POS) (Figure 4). This initial charge is controlled by the variable N-channel on-resistance. During the second half-cycle, the Nchannel MOSFET turns off and the P-channel MOSFET turns on, level shifting CX(POS) by VSUPP volts. This connects CX(POS) in parallel with the reservoir capacitor COUT(POS). If the voltage across COUT(POS) plus a diode drop (VPOS + VDIODE) is smaller than the levelshifted flying capacitor voltage (VCX(POS) + VSUPP), charge flows from CX(POS) to COUT(POS) until the diode (D3) turns off.
IPEAK INDUCTOR CURRENT
ILOAD
TIME tON tOFF
Figure 3. Discontinuous-to-Continuous Conduction Crossover Point
VSUPP 2.7V TO 13V
SUPP
MAX1778 MAX1880 MAX1881 MAX1882
SUPN
VSUPN 2.7V TO 13V
OSC D2 CX(POS) CX(NEG) D4
VSUPD
DRVP
DRVN
D3
D5
R3 VPOS COUT(POS)
FBP
FBN
R5 VNEG COUT(NEG)
R4
VREF 1.25V REF
R6
VPOS = 1 + R3 R4 VREF = 1.25V
( )V
REF
GND
PGND
CREF 0.22F
VNEG = - R5 VREF R6 VREF = 1.25V
()
Figure 4. Low-Power Charge Pump Block Diagram ______________________________________________________________________________________ 21
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Negative Charge Pump During the first half-cycle, the P-channel MOSFET turns on, and flying capacitor C X(NEG) charges to VSUPN minus a diode drop (Figure 4). During the second halfcycle, the P-channel MOSFET turns off, and the Nchannel MOSFET turns on, level shifting CX(NEG). This connects CX(NEG) in parallel with reservoir capacitor COUT(NEG). If the voltage across COUT(NEG) minus a diode drop is greater than the voltage across CX(NEG), charge flows from COUT(NEG) to CX(NEG) until the diode (D5) turns off. The amount of charge transferred to the output is controlled by the variable N-channel on-resistance. increases the pass transistor base current, which allows more current to pass to the output and increases the output voltage. However, the linear regulator also includes an output current limit to protect the internal pass transistor against short circuits. The low-dropout linear regulator monitors and controls the pass transistor's base current, limiting the output current to 130mA (typ). In conjunction with the thermal overload protection, this current limit protects the output, allowing it to be shorted to ground for an indefinite period of time without damaging the part.
VCOM Buffer
The MAX1778/MAX1880-MAX1885 include a VCOM buffer, which uses an operational transconductance amplifier (OTA) to provide a current output that is ideal for driving capacitive loads, such as the backplane of a TFT LCD panel. The unity-gain bandwidth of this current-output buffer is: GBW = gm/COUT where gm is the amplifier's transconductance. The bandwidth is inversely proportional to the output capacitor, so large capacitive loads improve stability; however, lower bandwidth decreases the buffer's transient response time. To improve the transient response
Low-Dropout Linear Regulator (MAX1778/ MAX1881/MAX1883/MAX1884 Only)
The MAX1778/MAX1881/MAX1883/MAX1884 contain a low-dropout linear regulator (Figure 5) that uses an internal PNP pass transistor (QP) to supply loads up to 40mA. As illustrated in Figure 5, the 1.25V reference is connected to the error amplifier, which compares this reference with the feedback voltage and amplifies the difference. If the feedback voltage is higher than the reference voltage, the controller lowers the base current of QP, which reduces the amount of current to the output. If the feedback voltage is too low, the device
MAX1778 MAX1881 MAX1883 MAX1884 THERMAL SENSOR
SUPL CSUPL
VSUPL 4.5V TO 15V
CURRENT LIMIT
QP LDOOUT R7 FBL
VLDOOUT 1.25V TO (VSUPL - 0.3V) CLDOOUT
ERROR AMPLIFIER
VREF 1.25V GND
R8 VLDOOUT = 1 + VREF = 1.25V
(
R7 VREF R8
)
Figure 5. Low-Dropout Linear Regulator Block Diagram
22
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
SUPB MAX1778 MAX1880 MAX1881 MAX1882 MAX1883 MAX1884 MAX1885 gm BUFOUT BUFVSUPB 4.5V TO 13V VBUFOUT 1.2V TO (VSUPB - 1.2V) CBUF
R R11 BUF+
R 125mV GND
R12 VBUFOUT =
( R11R12R12 )V +
SUPB
Figure 6. VCOM Buffer Block Diagram
times, the amplifier's transconductance increases as the output current increases (see Typical Operating Characteristics). The VCOM buffer's positive feedback input features dual mode operation. The buffer's output voltage can be internally set by a 50% resistive divider connected to the buffer's supply voltage (SUPB), or the output voltage can be externally adjusted for other voltages.
Shutdown (SHDN)
A logic-low level on SHDN shuts down all of the converters and the reference. When shut down, the supply current drops to 0.1A to maximize battery life, and the reference is pulled to ground. The output capacitance, feedback resistors, and load current determine the rate at which each output voltage will decay. A logic-level high on SHDN power activates the MAX1778/ MAX1880-MAX1885 (see Power-Up Sequencing). Do not leave SHDN floating. If unused, connect SHDN to IN. A logic-level transition on SHDN clears the fault latch.
ready output signal are not affected by the regulation of the linear regulator. While the main step-up converter powers up, the output of the PWM comparator remains low (Figure 2), and the step-up converter charges the output capacitors, limited only by the maximum duty cycle and current-limit comparator. When the step-up converter approaches its nominal regulation value and the PWM comparator's output changes states for the first time, the negative charge pump turns on. When the negative output voltage reaches approximately 90% of its nominal value (VFBN < 110mV), the positive charge pump starts up. Finally, when the positive output voltage reaches 90% of its nominal value (VFBP > 1.125V), the active-low ready signal (RDY) goes low (see Power Ready), and the VCOM buffer powers up. The MAX1883/MAX1884/MAX1885 do not contain the charge pumps, but the power-up sequence still contains the charge pumps' startup logic, which appears as a delay (2 4096/fOSC) between the step-up converter reaching regulation and when the ready signal and VCOM buffer are activated.
Soft-Start
For the main step-up regulator, soft-start allows a gradual increase of the current-limit level during startup to reduce input surge currents. The MAX1778/MAX1880- MAX1885 divide the soft-start period into four phases. During the first phase, the controller limits the current limit to only 0.38A (see Electrical Characteristics), approximately a quarter of the maximum current limit
23
Power-Up Sequencing
Upon power-up or exiting shutdown, the MAX1778/ MAX1880-MAX1885 start a power-up sequence. First, the reference powers up. Then, the main DC-DC stepup converter powers up with soft-start enabled. The linear regulator powers up at the same time as the main step-up converter; however, the power sequence and
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
(ILX(MAX)). If the output does not reach regulation within 1ms, soft-start enters phase II, and the current limit is increased by another 25%. This process is repeated for phase III. The maximum 1.5A (typ) current limit is reached within 3072 clock cycles or when the output reaches regulation, whichever occurs first (see the startup waveforms in the Typical Operating Characteristics). For the charge pumps (MAX1778/MAX1880/ MAX1881/MAX1882 only), soft-start is achieved by controlling the rate of rise of the output voltage. Both charge-pump output voltages are controlled to be in regulation within 4096 clock cycles, irregardless of output capacitance and load, limited only by the charge pump's output impedance. Although the MAX1883/ MAX1884/MAX1885 controllers do not include the charge pumps, the soft-start logic still contains the 4096 clock cycle startup periods for both charge pumps. The reference fault threshold is 1.05V. For the step-up converter and positive charge-pump, the fault trip level is set by FLTSET (see Fault Trip Level). For the negative charge pump, the fault threshold measured at the charge-pump's feedback input (FBN) is 140mV (typ).
Power Ready (RDY)
Power ready is an open-drain output. When the powerup sequence for the main step-up converter and lowpower charge pumps has properly completed, the 14V MOSFET turns on and pulls RDY low with a 125 (typ) on-resistance. If a fault is detected on any of these three outputs, the internal open-drain MOSFET appears as a high impedance. Connect a 100k pullup resistor between RDY and IN for a logic-level output.
Voltage Reference (REF)
The voltage at REF is nominally 1.25V. The reference can source up to 50A with good load regulation (see Typical Operating Characteristics). Connect a 0.22F ceramic bypass capacitor between REF and GND.
Fault Trip Level (FLTSET)
The MAX1778/MAX1880-MAX1885 feature dual mode operation to allow operation with either a preset fault trip level or an adjustable trip level for the step-up converter and positive charge-pump outputs. Connect FLTSET to GND to select the preset 0.9 V REF fault threshold. The fault trip level may also be adjusted by connecting a voltage divider from REF to FLTSET (Figure 8). For greatest accuracy, the total load on the reference (including current through the negative charge-pump feedback resistors) should not exceed 50A so that VREF is guaranteed to be in regulation (see Electrical Characteristics Table). Therefore, select R10 in the 100k to 1M range, and calculate R9 with the following equation: R9 = R10 [(VREF / VFLTSET) - 1] where VREF = 1.25V, and VFLTSET may range from 0.67 x VREF to 0.85 x VREF. FLTSET's input bias current has a maximum value of 50nA. For 1% error, the current through R10 should be at least 100 times the FLTSET input bias current (IFLTSET).
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX1778/MAX1880-MAX1885. When the junction temperature exceeds TJ = +160C, a thermal sensor activates the fault protection, which shuts down the controller, allowing the IC to cool. Once the device cools down by 15C, toggle shutdown (below 0.8V) or cycle the input voltage (below 0.2V) to clear the fault latch and reactivate the controller. Thermal-overload protection protects the controller in the event of fault conditions. For continuous operation, do not exceed the absolute maximum junction-temperature rating of TJ = +150C.
Operating Region and Power Dissipation
The MAX1778/MAX1880-MAX1885s' maximum power dissipation depends on the thermal resistance of the IC package and circuit board, the temperature difference between the die junction and ambient air, and the rate of any airflow. The power dissipated in the device depends on the operating conditions of each regulator and the buffer. The step-up controller dissipates power across the internal N-channel MOSFET as the controller ramps up the inductor current. In continuous conduction, the power dissipated internally can be approximated by:
2 2 I V 1 VIND PSTEP - UP MAIN MAIN + VIN 12 fOSCL x RDS(ON)D
Fault Condition
Once RDY is low, if the output of the main regulator or either low-power charge pump falls below its fault detection threshold, or if the input drops below its undervoltage threshold, then RDY goes high impedance and all outputs shut down; however, the reference remains active. After removing the fault condition, toggle shutdown (below 0.8V) or cycle the input voltage (below 0.2V) to clear the fault latch and reactivate the device.
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Quad-Output TFT LCD DC-DC Converters with Buffer
where IMAIN includes the primary load current and the input supply currents for the charge pumps (see Charge-Pump Input Power and Efficiency Considerations), linear regulator, and VCOM buffer. The linear regulator generates an output voltage by dissipating power across an internal pass transistor, so the power dissipation is simply the load current times the input-to-output voltage differential: PLDO(INT) = ILDO (VSUPL - VLDO ) When driving an external transistor, the internal linear regulator provides the base drive current. Depending on the external transistor's current gain () and the maximum load current, the power dissipated by the internal linear regulator may still be significant: I PLDO(INT) = LDO VSUPL - (VLDO + 0.7V ) = ILDOOUT (VSUPL - VLDOOUT ) PMAX = (TJ(MAX) - TA) / ( JB + BA) where TJ - TA is the temperature difference between the controller's junction and the surrounding air, JB (or JC) is the thermal resistance of the package to the board, and BA is the thermal resistance from the printed circuit board to the surrounding air.
MAX1778/MAX1880-MAX1885
Design Procedure
Main Step-Up Converter
Output Voltage Selection Adjust the output voltage by connecting a voltagedivider from the output (VMAIN) to FB to GND (see Typical Operating Circuit). Select R2 in the 10k to 50k range. Calculate R1 with the following equations: R1 = R2 [(VMAIN / VREF) - 1] where VREF = 1.25V. VMAIN may range from VIN to 13V. Inductor Selection Inductor selection depends upon the minimum required inductance value, saturation rating, series resistance, and size. These factors influence the converter's efficiency, maximum output load capability, transient response time, and output voltage ripple. For most applications, values between 4.7H and 22H work best with the controller's switching frequency (Tables 1 and 2). The inductor value depends on the maximum output load the application must support, input voltage, output voltage, and switching frequency. With high inductor values, the MAX1778/MAX1880-MAX1885 source higher output currents, have less output ripple, and enter continuous conduction operation with lighter loads; however, the circuit's transient response time is slower. On the other hand, low-value inductors respond faster to transients, remain in discontinuous conduction operation, and typically offer smaller physical size for a given series resistance and current rating. The equations provided here include a constant LIR, which is the ratio of the peak-to-peak AC inductor current to the average DC inductor current. For a good compromise between the size of the inductor, power loss, and output voltage ripple, select an LIR of 0.3 to 0.5. The inductance value is then given by:
2 VIN(MIN) VMAIN - VIN(MIN) 1 LMIN = VMAIN IMAIN(MAX)fOSC LIR
[
]
The charge pumps provide regulated output voltages by dissipating power in the low-side N-channel MOSFET, so they could be modeled as linear regulators followed by unregulated charge pumps. Therefore, their power dissipation is similar to a linear regulator:
PNEG = INEG (VSUPN - 2VDIODE )N - VNEG PPOS =
[ IPOS [(VSUPP - 2VDIODE )N +
]
VSUPD - VPOS
]
where N is the number of charge-pump stages, VDIODE is the diodes' forward voltage, and VSUPD is the positive charge-pump diode supply (Figure 4). The VCOM buffer's power dissipation depends on the capacitive load (C LOAD) being driven, the peak-topeak voltage change (VP-P) across the load, and the load's switching rate: PBUF = VP - PCLOADfLOADVSUPB To find the total power dissipated in the device, the power dissipated by each regulator and the buffer must be added together: PTOTAL = PSTEP - UP + PLDO(INT) + PNEG + PPOS + PBUF The maximum allowed power dissipation is 975mW (24pin TSSOP) / 879mW (20-pin TSSOP) or:
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25
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
where is the efficiency, fOSC is the oscillator frequency (see Electrical Characteristics), and IMAIN includes the primary load current and the input supply currents for the charge pumps (see Charge-Pump Input Power and Efficiency Considerations), linear regulator, and VCOM buffer. Considering the typical application circuit, the maximum average DC load current (IMAIN(MAX)) is 300mA with an 8V output. Based on the above equations and assuming 85% efficiency, the inductance value is then chosen to be 4.7H. The inductor's saturation current rating should exceed the peak inductor current throughout the normal operating range. The peak inductor current is then given by: IMAIN(MAX) VMAIN LIR 1 IPEAK = 1 + VIN(MIN) 2 Under fault conditions, the inductor current may reach up to 1.85A (ILIM(MAX)), see Electrical Characteristics). However, the controller's fast current-limit circuitry allows the use of soft-saturation inductors while still protecting the IC. The inductor's DC resistance may significantly affect efficiency due to the power loss in the inductor. The power loss due to the inductor's series resistance (PLR) may be approximated by the following equation: I X VMAIN PLR RL MAIN VIN
2
Output voltage ripple has two components: variations in the charge stored in the output capacitor with each LX pulse, and the voltage drop across the capacitor's equivalent series resistance (ESR) caused by the current into and out of the capacitor: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) VRIPPLE(ESR) IPEAKRESR(COUT) , AND V - VIN IMAIN VRIPPLE(C) MAIN C VMAIN OUT fOSC where IPEAK is the peak inductor current (see Inductor Selection). For ceramic capacitors, the output voltage ripple is typically dominated by VRIPPLE(C). The voltage rating and temperature characteristics of the output capacitor must also be considered. Feedback Compensation For stability, add a pole-zero pair from FB to GND in the form of a compensation resistor (RCOMP) in series with a compensation capacitor (CCOMP) as shown in Figure 2. Select RCOMP to be half the value of R2, the low-side feedback resistor. Integrator Capacitor The MAX1778/MAX1880-MAX1885 contain an internal current integrator that improves the DC load regulation but increases the peak-to-peak transient voltage (see the load-transient waveforms in the Typical Operating Characteristics). For highly accurate DC load regulation, enable the current integrator by connecting a 470pF ( OSC = 1MHz)/1000pF ( OSC = 500kHz) capacitor to INTG. To minimize the peak-to-peak transient voltage at the expense of DC regulation, disable the integrator by connecting INTG to REF. When using the MAX1883/MAX1884/MAX1885, connect a 100k resistor to GND when disabling the integrator. Input Capacitor The input capacitor (CIN) in step-up designs reduces the current peaks drawn from the input supply and reduces noise injection. The value of CIN is largely determined by the source impedance of the input supply. High source impedance requires high input capacitance, particularly as the input voltage falls. Since step-up DC-DC converters act as "constant-power" loads to their input supply, input current rises as input voltage falls. A good starting point is to use the same capacitance value for CIN as for COUT.
where RL is the inductor's series resistance. For best performance, select inductors with resistance less than the internal N-channel MOSFET on-resistance (0.35 typ). Use inductors with a ferrite core or equivalent. To minimize radiated noise in sensitive applications, use a shielded inductor. Output Capacitor Output capacitor selection depends on circuit stability and output voltage ripple. A 10F ceramic capacitor works well in most applications (Tables 1 and 2). Additional feedback compensation is required (see Feedback Compensation) to increase the margin for stability by reducing the bandwidth further. In cases where the output capacitance is sufficiently large, additional feedback compensation will not be necessary.
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Quad-Output TFT LCD DC-DC Converters with Buffer
Rectifier Diode Use a Schottky diode with an average current rating equal to or greater than the peak inductor current, and a voltage rating at least 1.5 times the main output voltage (VMAIN). charge pump's output impedance may be approximated using the following equation: 1 RTX = 2(RPCH(ON) + RNCH(ON) ) + CX fCHP 1 + COUT fCHP where the charge pump's switching frequency (fCHP) is equal to 0.5 x fOSC, the P-channel MOSFET's on-resistance (RPCH(ON)) is 10, and the N-channel MOSFET's on-resistance (R NCH(ON )) is 4 (see Electrical Characteristics). For negative charge pump outputs, the number of required stages may be determined by: VNEG NNEG VSUPN - 1.1(2VDROP + RTXILOAD ) where NNEG is rounded up to the nearest integer.
MAX1778/MAX1880-MAX1885
Charge Pumps (MAX1778/ MAX1880/ MAX1881/MAX1882 Only)
Selecting the Number of Charge-Pump Stages The number of charge-pump stages required to regulate the output voltage depends on the supply voltage, output voltage, load current, switching frequency, the diode's forward voltage drop, and ceramic capacitor values. For positive charge-pump outputs, the number of required stages may be determined by: VPOS - VSUPD NPOS VSUPP - 1.1(2VDIODE + RTXILOAD ) where VSUPD is the positive charge-pump diode supply (Figure 4), VDIODE is the diode's forward voltage drop, and RTX is the charge pump's output impedance. The
Table 1. MAX1778/MAX1880/MAX1883 Component Values (fOSC = 1MHz)
CIRCUIT #1 VIN VMAIN IMAIN(MAX) VNEG INEG VPOS IPOS L IPEAK COUT R1 R2 RCOMP CCOMP 3.3V 9V 100mA -5V 2mA 24V 2mA 2.2H >1A 4.7F 309k 49.9k None None CIRCUIT #2 3.3V 9V 200mA -5V 5mA 24V 5mA 4.7H >1A 10F 309k 49.9k None None CIRCUIT #3 3.3V 9V 200mA -5V 5mA 24V 5mA 4.7H >1A 20F 309k 49.9k 39k* 100pF* CIRCUIT #4 5V 12V 220mA -5V 5mA 24V 5mA 6.8H >1A 10F 429k 49.9k None None CIRCUIT #5 5V 12V 220mA -5V 5mA 24V 5mA 6.8H >1A 20F 429k 49.9k 20k* 200pF*
*RCOMP and CCOMP are connected between the step-up converter's output (VMAIN) and FB.
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Table 2. MAX1881/MAX1882/MAX1884/MAX1885 Component Values (fOSC = 500kHz)
CIRCUIT #6 VIN VMAIN IMAIN(MAX) VNEG INEG VPOS IPOS L IPEAK COUT R1 R2 RCOMP CCOMP 3.3V 9V 100mA -5V 2mA 24V 2mA 4.7H >1A 4.7F 309k 49.9k None None CIRCUIT #7 3.3V 9V 100mA -5V 2mA 24V 2mA 10H >1A 10F 309k 49.9k None None CIRCUIT #8 3.3V 9V 200mA -5V 5mA 24V 5mA 10H >1A 10F 309k 49.9k None None CIRCUIT #9 3.3V 9V 200mA -5V 5mA 24V 5mA 10H >1A 20F 309k 49.9k 20k* 200pF*
*RCOMP and CCOMP are connected between the step-up converter's output (VMAIN) and FB.
Table 3. Component Suppliers
SUPPLIER INDUCTORS Coilcraft Coiltronics Sumida USA Toko CAPACITORS AVX Kemet Sanyo Taiyo Yuden DIODES Central Semiconductor International Rectifier Motorola Nihon Zetex 803-946-0690 408-986-0424 619-661-6835 408-573-4150 803-626-3123 408-986-1442 619-661-1055 408-573-4159 847-639-6400 561-241-7876 847-956-0666 847-297-0070 847-639-1469 561-241-9339 847-956-0702 847-699-1194 PHONE FAX
Charge-Pump Input Power and Efficiency Considerations The charge pumps in the MAX1778/MAX1880/ MAX1881/MAX1882 provide regulated output voltages by controlling the voltage drop across the low-side Nchannel MOSFET, so they can be modeled as linear regulators followed by an unregulated charge pump when determining the input power requirements and efficiency. The charge pump only provides charge to the output capacitor during half the period (50% duty cycle), so the input current is a function of the number of stages and the load current: ISUPP = IPOS (N + 1) for the positive charge pump, and:
516-435-1110 310-322-3331 602-303-5454 847-843-7500 516-543-7100
516-435-1824 310-322-3332 602-994-6430 847-843-2798 516-864-7630
ISUPP = IPOS (N + 1) for the negative charge pump, where N is the number of charge pump stages. The efficiency characteristics of the MAX1778/ MAX1880/MAX1881/MAX1882 regulated charge pumps are similar to a linear regulator. It is dominated by quiescent current at low output currents and by the
28
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Quad-Output TFT LCD DC-DC Converters with Buffer
input voltage at higher output currents (see Typical Operating Characteristics). So the maximum efficiency may be approximated by: POS VPOS VSUPD + VSUPPN
MAX1778/MAX1880-MAX1885
VCXN(NEG) > 1.5(VSUPNN) for the negative charge pump, where N is the stage number in which the flying capacitor appears, and V SUPD is the positive charge pump's diode supply (Figure 4). For example, the two-stage positive charge pump in the typical application circuit (Figure 1) where VSUPP = VSUPD = 8V contains two flying capacitors. The flying capacitor in the first stage (C4) requires a voltage rating over 12V. The flying capacitor in the second stage (C6) requires a voltage rating over 24V. Charge-Pump Output Capacitor Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-topeak transient voltage. With ceramic capacitors, the output voltage ripple is dominated by the capacitance value. Use the following equation to approximate the required capacitor value: COUT ILOAD fCHP VRIPPLE
for the positive charge pump, and: NEG VNEG VSUPNN
for the negative charge pump, where VSUPD is the positive charge pump's diode supply (Figure 4). Output Voltage Selection Adjust the positive output voltage by connecting a voltage divider from the output (VPOS) to FBP to GND (see Typical Operating Circuit). Adjust the negative output voltage by connecting a voltage-divider from the output (VNEG) to FBN to REF. Select R4 and R6 in the 50k to 100k range. Higher resistor values improve efficiency at low output current but increase output voltage error due to the feedback input bias current. For the negative charge pump, higher resistor values also reduce the load on the reference, which should not exceed 50A for greatest accuracy (including current through the FLTSET resistors) to guarantee that VREF remains in regulation (see Electrical Characteristics Table). Calculate the remaining resistors with the following equations: R3 = R4 [(VPOS / VREF) - 1] R5 = R6 |VNEG / VREF| where VREF = 1.25V. VPOS may range from VSUPP to 40V, and VNEG may range from 0V to -40V. Flying Capacitor Increasing the flying capacitor (CX) value increases the output current capability. Above a certain point, increasing the capacitance has a negligible effect because the output current capability becomes dominated by the internal switch resistance and the diode impedance. The flying capacitor's voltage rating must exceed the following: VCXN(POS) > 1.5 VSUPD + VSUPP (N - 1) for the positive charge pump, and:
where f CHP is typically f OSC /2 (see Electrical Characteristics). Charge-Pump Input Capacitor Use a bypass capacitor with a value equal to or greater than the flying capacitor. Place the capacitor as close to the IC as possible. Connect directly to power ground (PGND). Charge-Pump Rectifier Diodes Use Schottky diodes with a current rating equal to or greater than two times the average charge-pump input current, and a voltage rating at least 1.5 times VSUPP for the positive charge pump and VSUPN for the negative charge pump.
Low-Dropout Linear Regulator (MAX1778/ MAX1881/MAX1883/MAX1884 Only)
Output Voltage Selection Adjust the linear-regulator output voltage by connecting a voltage-divider from LDOOUT to FBL to GND (Figure 5). Select R8 in the 5k to 50k range. Calculate R7 with the following equation: R7 = R8 [(VLDOOUT / VFBL) - 1] where VFBL = 1.25V, and VLDOOUT may range from 1.25V to (VSUPL - 300mV). FBL's input bias current is
[
]
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Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
0.8A (max). For less than 0.5% error due to FBL input bias current (IFBL), R8 must be less than 8k. Capacitor Selection and Regulator Stability Capacitors are required at the input and output of the MAX1778/MAX1881/MAX1883/MAX1884 for stable operation over the full temperature range and with load currents up to 40mA. Connect a 1F input bypass capacitor (CSUPL) between SUPL and ground to lower the source impedance of the input supply. Connect a ceramic capacitor between LDOOUT and ground, using the following equation to determine the lowest value required for stable operation: ILDOOUT(MAX) CLDOOUT 0.5ms X VLDOOUT MIN ILOAD(MAX) - 40mA 40mA
For stable operation, place a capacitor (CLDOOUT) and a minimum load resistor (R5) at the output of the internal linear regulator (the base of the external transistor) to set the dominant pole: 1 CLDOOUT 0.5ms VLDO ILOAD(MAX) V + 0.7V x LDO + R5 MIN Since the LDO cannot sink current, a minimum pulldown resistor (R5) is required at the base of the NPN transistor to sink leakage currents and improve the high-to-low load-transient response. Under no-load conditions, leakage currents from the internal pass transistor supply the output capacitor (CLDOOUT), even when the transistor is off. As the leakage currents increase over temperature, charge may build up on C LDOOUT , making the linear regulator's output rise above its set point. Therefore, R5 must sink at least 100A to guarantee proper regulation. Additionally, the minimum load current provided by R5 improves the high-to-low load transients by lowering the impedance seen by CLDOOUT after the transient occurs. Therefore, if large load transients are expected, select R5 so that the minimum load current is 10% of the transistor's maximum base current: R5 = VLDO + 0.7V = 0.1 ILDOOUT(MIN) (V + 0.7V)MIN LDO ILOAD(MAX)
For example, with a 5V linear regulator output voltage and a maximum 40mA load, use at least 4F of output capacitance. Applications that experience high-current load pulses may require more output capacitance. The ESR of the linear regulator's output capacitor (CLDOOUT) affects stability and output noise. Use output capacitors with an ESR of 0.1 or less to ensure stability and optimum transient response. Surfacemount ceramic capacitors are good for this purpose. Place CSUPL and CLDOOUT as close to the linear regulator as possible to minimize the impact of PC board trace inductance. External Pass Transistor For applications where the linear regulator currents exceed 40mA or where the power dissipation in the IC needs to be reduced, an external NPN transistor can be used. In this case, the internal LDO only provides the necessary base drive while the external NPN transistor supports the load, so most of the power dissipation occurs across the external transistor's collector and emitter. Selection of the external NPN transistor is based on three factors: the package's power dissipation, the current gain (), and the collector-to-emitter saturation voltage (VCE(SAT)). First, the maximum power dissipation should not exceed the transistor's package rating: P = (VCOLLECTOR - VLDO ) x ILOAD(MAX) Once the appropriate package type is selected, consider the NPN transistor's current gain. Since the internal LDO cannot source more than 40mA (min), the transistor's current gain must be high enough at the lowest collector-to-emitter voltage to support the maximum output load:
30
Alternatively, output capacitance placed on the external linear regulator's output (the emitter) adds a second pole that could destabilize the regulator. A capacitive-divider from the transistor's base to the feedback input (C2 and C3, Figure 7) circumvents this second pole by adding a pole-zero pair. Furthermore, to minimize excessive overshoot, the capacitive-divider's ratio must be the same as the resistive-divider's ratio. Once the output capacitor is selected, using the following equations to determine the required capacitive-divider values: C2 + C3 CLDO R4 1 + 100 R3 C2 R4 V = = REF C2 + C3 R3 + R4 VLDO
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Quad-Output TFT LCD DC-DC Converters with Buffer
Input-Output (Dropout) Voltage and Startup A linear regulator's minimum input-to-output voltage differential (dropout voltage) determines the lowest useable supply voltage. Because the MAX1778/ MAX1881/MAX1883/MAX1884 use an internal PNP transistor (or external NPN transistor), their dropout voltage is a function of the transistor's collector-to-emitter saturation voltage (see Typical Operating Characteristics). The linear regulator's quiescent current increases when in dropout. The internal linear regulator will try to start up once its supply voltage (VSUPL) exceeds 4V. When the linear regulator powers up, the linear regulator may be in dropout if the linear regulator's output set voltage is higher than its input supply voltage. Therefore, during this brief period, the linear regulator draws additional supply current until the input supply voltage exceeds the output set voltage plus the pass transistor's saturation voltage (VLDO(SET) + VCE(SAT)). voltage-divider from SUPB to BUF+ to GND (Figure 6). Select R12 in the 10k to 100k range. Calculate R11 with the following equation: V R11 = R12 SUPB - 1 VBUF + where VSUPB may range from 4.5V to 13V, and VBUF+ may range from 1.2V to (VSUPB - 1.2V). Connect a minimum 1F ceramic capacitor from BUFOUT to ground.
MAX1778/MAX1880-MAX1885
PC Board Layout and Grounding
Careful PC board layout is extremely important for proper operation. Follow the following guidelines for good PC board layout: 1) Place the main step-up converter output diode and output capacitor less than 0.2in (5mm) from the LX and PGND pins with wide traces and no vias. 2) Separate analog ground and power ground. The ground connections for the step-up converter's and charge pump's input and output capacitors should be connected to the power ground plane. The linear regulator's and VCOM buffer's input and output capacitors should be connected to a separate power-ground path, star-connected to the PGND pin to minimize voltage drops. When using multilayer boards, the top layer should contain the boost
VCOM Buffer (Operational Transconductance Amplifier)
Buffer Output Voltage and Capacitor Selection The positive input (BUF+) features dual mode operation. Connect BUF+ to GND for the preset VSUPB/2 output voltage, set by an internal 50% resistive-divider. Adjust the amplifier's output voltage by connecting a
INPUT VIN = 3.3V
L1 6.8H CIN 4.7F C1 0.22F
IN SHDN
LX FB
R1 274k
MAIN VMAIN = 8V COUT (2) 4.7F
MAX1778 MAX1883 (MAX1881)* (MAX1884)* SUPL LDOOUT INTG REF CREF 0.22F FBL PGND GND
R2 49.9k
CLDOIN 1F
Q1 R5 1.5k CLDOOUT 4.7F C2 0.01F R3 49.9k CLDO 1F LDO VLDO = 2.5V
C3 0.01F
R4 49.9k
Figure 7. External Linear Regulator ______________________________________________________________________________________ 31
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
regulator and charge-pump power ground plane, and the inner layer should contain the analog ground plane and power-ground plane/path for the VCOM buffer and LDO. Connect all three ground planes together at one place near the PGND pin. 3) Locate all feedback resistive-dividers as close to their respective feedback pins as possible. The voltage-divider's center trace should be kept short. Avoid running any feedback trace near the LX switching node or the charge-pump drivers. The resistive-dividers' ground connections should be to analog ground (GND). 4) When using multilayer boards, separate the top signal layer and bottom signal layer with a ground plane between to eliminate capacitive coupling between fast-charging nodes on the top layer and high-impedance nodes on the bottom layer. The fast-charging nodes, such as the LX and chargepump driver nodes, should not have any other traces or ground planes near by. 5) Keep the charge-pump circuitry as close to the IC as possible, using wide traces and avoiding vias when possible. Place 0.1F ceramic bypass capacitors near the charge-pump input pins (SUPP and SUPN) to the PGND pin. 6) To maximize output power and efficiency and minimize output ripple voltage, use extra wide, power ground traces, and solder the IC's power ground pin directly to it. Refer to the MAX1778/MAX1880-MAX1885 evaluation kit for an example of proper board layout.
INPUT VIN = 5V
L1 10H CIN (2) 4.7F RRDY 100k C1 0.22F R1 86.6k COUT (2) 10F
MAIN VMAIN = 12V
IN SHDN RDY SUPL
LX FB
RCOMP 4.7k CCOMP 470pF
TO LOGIC
LDO VLDO = 3.3V C6 1F R8 10k
Q1 CLDOOUT 4.7F R7 16.4k R8 1.5k
LDOOUT
SUPB SUPN SUPP C4 0.1F DRVP
R2 10k
MAX1778
C6 0.01F FBL DRVN C2 0.1F FBN C3 1.0F R5 316k R6 49.9k REF CREF 0.22F INTG PGND
FBP R4 49.9k BUFOUT BUFR3 750k C5 1.0F
POSITIVE VPOS = 20V
C7 0.01F NEGATIVE VNEG = -8V
CBUF 1.0F
BUFFER OUTPUT VBUFOUT = VSUPB/2 R9 30k REF
FLTSET BUF+ GND TGND R10 100k
Figure 8. 5V Input Monitor Application 32 ______________________________________________________________________________________
Quad-Output TFT LCD DC-DC Converters with Buffer
Applications Information
Low-Profile Components
Notebook applications generally require low-profile components, potentially limiting the circuit's performance. For example, low-profile inductors typically have lower saturation ratings and more series resistance, limiting output current and efficiency. Low-profile capacitors have lower voltage ratings for a given capacitance value, so 3.3F low-profile capacitors with voltage ratings greater than 10V were not available at the time of publication. Larger output capacitors with higher voltage ratings allow configurations with output voltages above 10V. Additionally, physically larger inductors with less series resistance and higher saturation ratings provide more output current and higher efficiency.
MAX1778/MAX1880-MAX1885
Input Voltage Above and Below the Output Voltage
Combining the step-up converter and linear regulator as shown in Figure 9 provides output voltage regulation above and below the input voltage. Supplied by the step-up converter, the linear regulator output provides a constant output voltage (VLDO). When the input voltage exceeds the main step-up converter's nominal output voltage, the controller stops switching but the linear regulator maintains the output voltage. When the input voltage drops below the output voltage, the step-up
Desktop Monitors
Monitor applications do not have the same component height restrictions associated with laptops, allowing more flexibility in component selection (Figure 8).
POWER INPUT VBATT = 10V TO 15V
L1 6.8H CIN 4.7F COUT (3) 3.3F
R1 511k IN LX FB R2 49.9k
INPUT VIN = 3.3V TO 5V
C1 0.1F
SHDN RRDY 100k RDY BUFOUT CBUF 1.0F C2 0.1F DRVN BUFMAX1778 SUPB SUPN SUPP FBL
TO LOGIC BUFFER OUTPUT VBUFOUT = VSUPB/2
SUPL LDOOUT C6 0.1F CLDOOUT 3.3F LDO VLDO = 13V CLDO (2) 3.3F Q1
NEGATIVE VNEG = -12V
FBN C3 1.0F R5 475k R6 49.9k REF R9 30k R10 100k FLTSET CINTG 470pF INTG PGND DRVP
R7 470k
C7 0.1F
R9 6.8k
CREF 0.22F
C4 0.1F
R8 49.9k
FBP BUF+ GND TGND R4 49.9k R3 909k C5 1.0F
POSITIVE VPOS = 24V
Figure 9. Input Voltage Above and Below the Output Voltage ______________________________________________________________________________________ 33
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
INPUT VIN = 3.3V L1 6.8H CIN 4.7F C1 0.22F STARTUP MAIN VMAIN(START) = 8V R1 274k COUT (2) 3.3F SYSTEM MAIN VMAIN(SYS) = 8V C8 3.3F
IN SHDN
LX FB
R2 49.9k
C10 0.1F
SUPP MAX1778 DRVP INTG CREF 0.22F R9 30k FLTSET R10 100k REF R3 750k FBP R4 49.9k STARTUP POSITIVE VPOS(START) = 20V SYSTEM POSITIVE VPOS(SYS) = 20V Q2 INPUT VIN = 3.3V C6 0.1F C4 0.1F C5 1.0F C7 1.0F R7 10k
Q3
RDY TGND PGND GND RRDY 5.1k R8 100k
Figure 10. Power-Up Sequencing and Fault Protection;
converter steps up the input voltage so that the linear regulator will not drop out. Therefore, to guarantee that the external pass transistor does not saturate, the stepup converter's output voltage must be set above the linear regulator's output voltage plus the transistor's saturation rating (VMAIN VLDO + VSAT).
Power-Up Sequencing and Fault Protection
The MAX1778/MAX1880-MAX1885's fault protection cannot be activated until the power-up sequence is successfully completed and the power ready output goes low. Therefore, faults on the main output or positive charge-pump output could damage the controller or external components. Additional fault protection may be added as shown in Figure 10. The external MOSFET and PNP transistor isolate the positive outputs during startup. When the controller finishes the power-up sequence, the power-ready output goes low, turning on
the PNP transistor. Any fault on the positive chargepump output will pull down the charge pump's output voltage and trigger the fault protection; otherwise, the MOSFET's gate slow charges. Once the MOSFET turns on, any faults on the main step-up converter's output will pull down the main output voltage and trigger the fault protection.
VCOM Buffer Startup
The VCOM buffer does not include soft-start. Therefore, once the VCOM buffer turns on, it draws high surge currents while charging the output capacitance. In some applications, the buffer's high startup surge current could potentially trip the fault detection circuit, forcing the controller to shut down. In these cases, adding a soft-start resistive divider between SUPB and BUFOUT reduces the startup surge current and voltage drops associated with this load (Figure 11), as shown in
34
______________________________________________________________________________________
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
INPUT VIN = 3.3V L1 6.8H CIN 4.7F C1 0.22F MAIN VMAIN = 8V COUT (2) 4.7F
IN SHDN
LX FB
R1 274k
MAX1778 INTG REF CREF 0.22F BUFBUFOUT BUF+ PGND GND SUPB
R2 49.9k
R3 10k
CSUPB 1.0F BUFFER OUTPUT VBUFOUT = VSUPB/2
R4 10k
CBUF 1.0F
R3 = R4
[( VV
SUPB
BUFOUT
) -1]
Selector Guide
Figure 11. VCOM Buffer Soft-Start;
the Typical Operating Characteristics. Set the resistive divider to precharge BUFOUT, matching the buffer's output set voltage: V R 3 = R4 SUPB - 1 VBUFOUT These resistor values are selected to charge the output capacitor close to the output set voltage before the buffer starts up: 5000 CBUFOUT (R3 || R4) fOSC
PART MAX1778 MAX1880 MAX1881 MAX1882 MAX1883 MAX1884 MAX1885
STEP-UP SWITCHING FREQUENCY (Hz) 1M 1M 500k 500k 1M 500k 500k
DUAL CHARGE PUMPS Yes Yes Yes Yes No No No
LINEAR REGULATOR Yes No Yes No Yes Yes No
______________________________________________________________________________________
35
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Typical Operating Circuit
INPUT IN SHDN TO LOGIC LDO OUTPUT RDY SUPL LDOOUT LX FB MAIN
SUPB SUPN SUPP
FBL
MAX1778 DRVP
DRVN
FBP
POSITIVE
NEGATIVE
FBN
REF
BUFOUT BUFBUF+
BUFFER OUTPUT
INTG PGND
FLTSET GND TGND
36
______________________________________________________________________________________
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Pin Configurations
TOP VIEW
FB 1 INTG 2 IN 3 BUF+ 4 BUF- 5 SUPB 6 BUFOUT 7 GND 8 REF 9 FBP 10 FBN 11 SHDN 12 24 RDY 23 TGND 22 LX 21 PGND FB 1 INTG 2 IN 3 BUF+ 4 BUF- 5 SUPB 6 BUFOUT 7 GND 8 REF 9 FBP 10 FBN 11 SHDN 12 24 RDY 23 TGND 22 LX 21 PGND
MAX1778 MAX1881
20 DRVP 19 SUPP 18 DRVN 17 SUPN 16 FLTSET 15 FBL 14 LDOOUT 13 SUPL
MAX1880 MAX1882
20 DRVP 19 SUPP 18 DRVN 17 SUPN 16 FLTSET 15 N.C. 14 N.C. 13 N.C.
24 TSSOP
24 TSSOP
TOP VIEW
FB 1 INTG 2 IN 3 BUF+ 4 BUF- 5 SUPB 6 BUFOUT 7 GND 8 REF 9 SHDN 10 20 RDY 19 TGND 18 LX 17 PGND FB 1 INTG 2 IN 3 BUF+ 4 BUF- 5 SUPB 6 BUFOUT 7 GND 8 REF 9 SHDN 10 20 RDY 19 TGND 18 LX 17 PGND
MAX1883 MAX1884
16 N.C. 15 N.C. 14 FLTSET 13 FBL 12 LDOOUT 11 SUPL
MAX1885
16 N.C. 15 N.C. 14 FLTSET 13 N.C. 12 N.C. 11 N.C.
20 TSSOP
20 TSSOP
______________________________________________________________________________________
37
Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885
Chip Information
TRANSISTOR COUNT: 3739
Package Information
TSSOP,NO PADS.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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