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19-2555; Rev 1; 12/02
Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply
General Description
The MAX1932 generates a low-noise, high-voltage output to bias avalanche photodiodes (APDs) in optical receivers. Very low output ripple and noise is achieved by a constant-frequency, pulse-width modulated (PWM) boost topology combined with a unique architecture that maintains regulation with an optional RC or LC post filter inside its feedback loop. A precision reference and error amplifier maintain 0.5% output voltage accuracy. The MAX1932 protects expensive APDs against adverse operating conditions while providing optimal bias. Traditional boost converters measure switch current for protection, whereas the MAX1932 integrates accurate high-side current limiting to protect APDs under avalanche conditions. A current-limit flag allows easy calibration of the APD operating point by indicating the precise point of avalanche breakdown. The MAX1932 control scheme prevents output overshoot and undershoot to provide safe APD operation without data loss. The output voltage can be accurately set with either external resistors, an internal 8-bit DAC, an external DAC, or other voltage source. Output span and offset are independently settable with external resistors. This optimizes the utilization of DAC resolution for applications that may require limited output voltage range, such as 4.5V to 15V, 4.5V to 45V, 20V to 60V, or 40V to 90V. o Small Circuit Footprint o Circuit Height < 2mm o 2.7V to 5.5V Input o o o o o o o o 4.5V to 90V Output No Overshoot Accurate High-Side Current Limit Avalanche Indicator Flag
Features
MAX1932
8-Bit SPI-Compatible DAC Compatible with External DAC 0.5% Accurate Output Low Ripple Output (< 1mV) o Small 12-Pin, 4mm 4mm Thin QFN Package
Ordering Information
PART MAX1932ETC TEMP RANGE PIN-PACKAGE -40C to +85C 12 Thin QFN
Applications
Optical Receivers and Modules Fiber Optic Network Equipment Telecom Equipment Laser Range Finders PIN Diode Bias Supply
Typical Application Circuit
INPUT 2.7V TO 5.5V VIN
Pin Configuration
GATE CS VIN
MAX1932
COMP
APD BIAS OUTPUT 4.5V TO 90V
12 SCLK DIN CL 1 2 3 4 CS+
11
10 9 8 7 GND COMP
DAC INPUTS
GATE CS SCLK DIN AVALANCHE INDICATOR FLAG CL GND DACOUT FB CS+ CS-
MAX1932
FB
5 CS-
6 DACOUT
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
ABSOLUTE MAXIMUM RATINGS
VIN to GND...............................................................-0.3V to +6V DIN, SCLK, CS, FB to GND ......................................-0.3V to +6V COMP, DACOUT, GATE, CL to GND ...........-0.3V to (VIN +0.3V) CS+, CS- to GND .................................................-0.3V to +110V Continuous Power Dissipation (TA = +70C) 12-Pin Thin QFN (derate 16.9mW/C above +70C) .1349mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = 0C to +85C, unless otherwise noted.)
PARAMETER GENERAL Input Supply Range VIN Undervoltage Lockout Operating Supply Current VIN Shutdown Supply Current Input Resistance for CS+/CSCurrent-Limit Threshold for CS+/CSCommon-Mode Rejection of Current Threshold Gate-Driver Resistance FB Input Bias Current FB Voltage FB Voltage Temperature Coefficient FB to COMP Transconductance COMP Pulldown Resistance in Shutdown DACOUT to FB Voltage Difference DACOUT Differential Nonlinearity (Note 1) DACOUT Voltage Temperature Coefficient DACOUT Load Regulation Switching Frequency GATE Maximum On-Time fOSC tON TCVDACOUT DAC code = 0F to FF hex, source or sink 50A -1 250 300 3 VFB TCVFB COMP = 1.5V DAC code = 00 hex DAC code = FF hex DAC Code = 01 to FF hex, DAC guaranteed monotonic -3 -1 0.0007 +1 340 50 TA = +25C TA = 0C to +85C CS+ = 3V to 100V Gate high or low, IGATE = 50mA -25 VIN UVLO IIN ISHDN 00 hex loaded to DAC Resistance from either pin to ground 0.5 1.80 Both rise/fall, hysteresis = 100mV 2.7 2.1 0.5 25 1 2.00 0.005 5 10 +25 5.5 2.6 1 65 2.0 2.20 V V mA A M V %/V nA V %/C 200 100 +3 +1 S mV LSB %/C mV kHz s SYMBOL CONDITIONS MIN TYP MAX UNITS
1.24375 1.2500 1.25625 1.24250 1.2500 1.25750 0.0007 110
2
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = 0C to +85C, unless otherwise noted.)
PARAMETER DIGITAL INPUTS (DIN, SCLK, CS) Input Low Voltage Input High Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (CL) Output Low Voltage Output High Voltage SPI TIMING (FIGURE 5) SCLK Clock Frequency SCLK Low Period SCLK High Period Data Hold Time Data Setup Time CS Assertion to SCLK Rising Edge Setup Time CS Deassertion to SCLK Rising Edge Setup Time SCLK Rising Edge to CS Deassertion SCLK Rising Edge to CS Assertion CS High Period fSCLK tCL tCH tDH tDS tCSS0 tCSS1 tCSH1 tCSH0 tCSW 125 125 0 125 200 200 200 200 300 2 MHz ns ns ns ns ns ns ns ns ns ISINK = 1mA ISOURCE = 0.5mA VIN - 0.5 0.1 V V TA = +25C TA = 0C to +85C -1 10 5 1.4 200 +1 0.6 V V mV A nA pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1932
ELECTRICAL CHARACTERISTICS
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER GENERAL Input Supply Range VIN Undervoltage Lockout Operating Supply Current VIN Shutdown Supply Current Input Resistance for CS+/CSCurrent-Limit Threshold for CS+/CSGate-Driver Resistance FB Input Bias Current Gate high or low, IGATE = 50mA -30 VIN UVLO IIN ISHDN 00 hex loaded to DAC Resistance from either pin to ground 0.5 1.80 Both rise/fall, hysteresis = 100mV 2.7 2.1 5.5 2.6 1 65 2 2.20 10 +30 V V mA A M V nA SYMBOL CONDITIONS MIN TYP MAX UNITS
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER FB Voltage FB to COMP Transconductance COMP Pulldown Resistance in Shutdown DACOUT to FB Voltage Difference DACOUT Differential Nonlinearity (Note 1) DACOUT Load Regulation Switching Frequency DIGITAL INPUTS (DIN, SCLK, CS) Input Low Voltage Input High Voltage DIGITAL OUTPUT (CL) Output Low Voltage Output High Voltage SPI TIMING (FIGURE 5) SCLK Clock Frequency SCLK Low Period SCLK High Period Data Hold Time Data Setup Time CS Assertion to SCLK Rising Edge Setup Time CS Deassertion to SCLK Rising Edge Setup Time SCLK Rising Edge to CS Deassertion SCLK Rising Edge to CS Assertion CS High Period fSCLK tCL tCH tDH tDS tCSS0 tCSS1 tCSH1 tCSH0 tCSW 125 125 0 125 200 200 200 200 300 2 MHz ns ns ns ns ns ns ns ns ns ISINK = 1mA ISOURCE = 0.5mA VIN - 0.5 0.1 V V 1.4 0.6 V V fOSC SYMBOL VFB COMP = 1.5V DAC code = 00 hex DAC code = FF hex DAC Code = 01 to FF hex, DAC guaranteed monotonic DAC code = 0F to FF hex, source or sink 50A -4 -1 -1 240 CONDITIONS MIN 1.23875 50 TYP MAX 1.26125 200 100 +4 +1 +1 360 UNITS V S mV LSB mV kHz
Note 1: DACOUT = DAC code x (1.25V/256) + 1.25V/256. Note 2: Specifications to -40C are guaranteed by design and not production tested.
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
Typical Operating Characteristics
(VIN = 5V, Circuit of Figure 2, TA =+25C, unless otherwise noted)
SWITCHING WAVEFORMS
MAX1932 toc01
SWITCHING WAVEFORM WITH LC FILTER
MAX1932 toc02
STARTUP AND SHUTDOWN WAVEFORMS
MAX1932 toc03
VLX 50V/div
VLX 50V/div
IL 0.05A/div VOUT RIPPLE (AC-COUPLED) VOUT = 90V 1s/div
IL
OUTPUT VOLTAGE 0.05A/div INPUT CURRENT 0.002V/div
50V/div
0.002V/div
VOUT RIPPLE (AC-COUPLED) VOUT = 90V, L = 300H, C = 1F, FIGURE 7 1s/div
50mA/div
20ms/div
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX1932 toc04
VFB vs. TEMPERATURE
MAX1932 toc05
OUTPUT VOLTAGE vs. LOAD CURRENT
90 85 OUTPUT VOLTAGE (V) 80 75 70 65 60 55 50 VCC = 5V, INDUCTOR = 100H, R1 = 806 FEEDBACK DIVIDER CURRENT AND CSCURRENT INCLUDED 0 0.5 1.0 1.5 2.0 2.5 3.0 CURRENT LIMIT ACTIVATED
MAX1932 toc06
MAX1932 toc09
92
1.2520 1.2515 1.2510 1.2505 VFB (V)
95
OUTPUT VOLTAGE (V)
91
90
1.2500 1.2495
89
1.2490 1.2485
88 2.5 3.5 4.5 5.5 INPUT VOLTAGE (V)
1.2480 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
LOAD CURRENT (mA)
OUTPUT VOLTAGE STEP-DOWN DUE TO DAC CHANGE
MAX1932 toc07
OUTPUT VOLTAGE STEP-UP DUE TO DAC CHANGE
MAX1932 toc08
OUTPUT VOLTAGE STEP DUE TO DACOUT CHANGE
OFFSET = 62.962V = 88 hex STEP DOWN FROM 80 hex TO 88 hex VOUT AT 64.233V VOUT AT 1V/div 62.692V OFFSET
OFFSET = 62.962V = 88 hex STEP VALUE = 64.233 = 80 hex
20V/div
1V/div DACOUT EXTERNAL SOURCE
0.5V/div
10ms/div
10ms/div
20ms/div
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 NAME SCLK DIN CL CS+ CSDACOUT FB COMP GND GATE VIN CS DAC Serial Clock Input DAC Serial Data Input Current-Limit Indicator Flag. CL = 0 indicates that the part is in current limit. Logic high level = VIN. Current-Limit Plus Sense Input. Connect a resistor from CS+ to CS- in series with the output. The differential threshold is 2V. CS+ has typically 1M resistance to ground. Current-Limit Minus Sense Input. CS- has typically 1M resistance to ground. Internal DAC Output. Generates a control voltage for adjustable output operation. DACOUT can source or sink 50A. Feedback input. Connect to a resistive voltage-divider between the output voltage (VOUT) and FB to set the output voltage. The feedback set point is 1.25V. Compensation Pin. Compensates the DC-DC converter control loop with a series RC to GND. COMP is actively discharged to ground during shutdown or undervoltage conditions. Ground Gate-Driver Output for External N-FET IC Supply Voltage (2.7V to 5.5V). Bypass VIN with a 1F or greater ceramic capacitor. DAC Chip-Select Input FUNCTION
Detailed Description
Fixed Frequency PWM
The MAX1932 uses a constant frequency, PWM, controller architecture. This controller sets the switch ontime and drives an external N-channel MOSFET (see Figure 1). As the load varies, the error amplifier sets the inductor peak current necessary to supply the load and regulate the output voltage.
nal resistors. See the Applications Information section for output control equations.
SPI Interface/Shutdown
Use an SPI-compatible 3-wire serial interface with the MAX1932 to control the DAC output voltage and to shut down the MAX1932. Figures 4 and 5 show timing diagrams for the SPI protocol. The MAX1932 is a write-only device and uses CS along with SCLK and DIN to communicate. The serial port is always operational when the device is powered. To shut down the DC-DC converter portion only, update the DAC registers to 00 hex.
Output Current Limit
The MAX1932 uses an external resistor at CS+ and CSto sense the output current (see Figure 2). The typical current-limit threshold is 2V. CL is designed to help find the optimum APD bias point by going low to indicate when the APD reaches avalanche and that current limit has been activated. To minimize noise, CL only changes state on an internal oscillator edge.
Applications Information
Voltage Feedback Sense Point
Feedback can be taken from in front of, or after, the current-limit sense resistor. The current-limit sense resistor forms a lowpass filter with the output capacitor. Taking feedback after the current-limit sense resistor (see Figure 2), optimizes the output voltage accuracy, but requires overcompensation, which slows down the control loop response. For faster response, the feedback can be taken from in front of the current-sense resistor (see Figure 3). This configuration however, makes the output voltage more sensitive to load variation and degrades output accuracy by an amount equal to the load current times the current-sense resistor value.
Output Control DAC
An internal digital-to-analog converter can be used to control the output voltage of the DC-DC converter (Figure 2). The DAC output is changed through an SPITM serial interface using an 8-bit control byte. On power-up, the DAC defaults to FF hex (1.25V), which corresponds to a minimum boost converter output voltage. Alternately, the output voltage can be set with external resistors, an external DAC, or a voltage source. Output span and offset are independently settable with exterSPI is a trademark of Motorola, Inc. 6
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply
Output and DAC Adjustments Range
Many biasing applications require an adjustable output voltage, which is easily obtained using the MAX1932's DAC output (Figure 2). The DAC output voltage is given by the following equation: 1.25V 1.25V VDACOUT = CODE x + 256 256 On power-up, DACOUT defaults to FF hex or 1.25V, which corresponds to the minimum VOUT output voltage. The voltage generated at DACOUT is coupled to FB through R6. DACOUT can sink only 50A so: 1.25V R6 50A Select the minimum output voltage (VOUTFF), and the maximum output voltage (V OUT01 ) for the desired adjustment range. R5 sets the adjustment span using the following equation: R5 = (VOUTFF - VOUT01) (R6/1.25V) R8 sets the minimum output of the adjustment range with the following equation: R8 = (1.25V R5)/(VOUTFF) where VIN is the input voltage, IOUT(MAX) is the maximum output current delivered, VOUT is the output voltage, and T is the switching period (3.3s), is the estimated power conversion efficiency, and D is the maximum duty cycle: D < (VOUT - VIN)/VOUT up to a maximum of 0.9 Since the L equation factors in efficiency, for inductor calculation purposes, an of 0.5 to 0.75 is usually suitable. For example, with a maximum DC load current of 2.5mA, a 90V output, VIN = 5V, D = 0.9, T = 3.3s, and estimated at 0.75, the above equation yields an L of 111H, so 100H would be a suitable value. The peak inductor current is given by: V xDx T IPK = IN L These are typical calculations. For worst case, refer to the article titled "Choosing the MAX1932 External Indicator, Diode, Current Sense Resistor, and Output Filter Capacitor for Worst Case Conditions" located on the Maxim website in the Application Notes section (visit www.maxim-ic.com/an1805). The inductance value is given by: L=
MAX1932
2IOUT(MAX) x VOUT
(VIN )2 x D2 x T x
Setting the Output Voltage without the DAC
Adjust the output voltage by connecting a voltagedivider from the output (VOUT) to FB (Figure 2 with R6 omitted). Select R8 between 10k to 50k. Calculate R5 with the following equation: VOUT R5 = R8 - 1 1.25V
External Power-Transistor Selection
An N-FET power switch is required for the MAX1932. The N-FET switch should be selected to have adequate onresistance with the MOSFET VGS = VIN(MIN). The breakdown voltage of the N-FET must be greater than VOUT. For higher-current output applications (such as 5mA at 90V), SOT23 high-voltage low-gate-threshold N-FETs may not have adequate current capability. For example, with a 5V input, a 90V, 5mA output requires an inductor peak of 240mA. For such cases it may be necessary to simply parallel two N-FETs to achieve the required current rating. With SOT23 devices this often results in smaller and lower cost than using a larger N-FET device.
Inductor Selection
Optimum inductor selection depends on input voltage, output voltage, maximum output current, switching frequency, and inductor size. Inductors are typically specified by their inductance (L), peak current (IPK), and resistance (LR).
Diode Selection
The output diode should be rated to handle the output voltage and the peak switch current. Make sure that the diode's peak current rating is at least IPK and that its breakdown voltage exceeds VOUT. Fast reverse recovery time (t rr < 10ns) and low junction capacitance
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
(<10pF) are recommended to minimize losses. A smallsignal silicon switching diode is suitable if efficiency is not critical. where REA = 310M, gM = 110S, RLD is the parallel combination of feedback network and the load resistance. K1 = 2 x VOUT - VIN VOUT - VIN
Output Filter Capacitor Selection
The output capacitors of the MAX1932 must have high enough voltage rating to operate with the V OUT required. Output capacitor effective series resistance (ESR) determines the amplitude of the high-frequency ripple seen on the output voltage. In the typical application circuit, a second RC formed by R1 and C3 further reduces ripple.
2 x VIN V (Volts) K2 = FB x x 0.75 (Volts) 2 x VOUT - VIN VOUT RLD x T(second) VOUT - VIN 2 x L (Henries) A properly compensated MAX1932 results in a gain vs. frequency plot that crosses 0dB with a single pole slope (20dB per decade). See Figure 6. Table 1 lists suggested component values for several typical applications.
Input Bypass Capacitor Selection
The input bypass capacitor reduces the peak currents drawn from the voltage source and reduces noise caused by the MAX1932's switching action. The input source impedance determines the size of the capacitor required at the input (VIN). A low ESR capacitor is recommended. A 1F ceramic capacitor is adequate for most applications. Place the bypass capacitor as close as possible to the VIN and GND pins.
Current-Sense Resistor Selection
Current limit is used to set the maximum delivered output current. In the typical application circuit, MAX1932 is designed to current limit at: R1 = 2V ILIMIT
Further Noise Reduction
The current-limit sense resistor is typically used as part of an output lowpass filter to reduce noise and ripple. For further reduction of noise, an LC filter can be added as shown in Figure 7. Output ripple and noise with and without the LC filter are shown in the Typical Operating Characteristics. If a post LC filter is used, it is best to use a coil with fairly large resistance (or a series resistor) so that ringing at the response peak of the LC filter is damped. For a 330H and 1F filter, 22 accomplishes this, but a resistor is not needed if the coil resistance is greater than 15.
Note that ILIMIT must include current drawn by the feedback divider (if sensing feedback after R1) and the input current of CS-.
Stability and Compensation Component Selection
Compensation components, R7 and C4, introduce a pole and a zero necessary to stabilize the MAX1932 (see Figure 6). The dominant pole, POLE1, is formed by the output impedance of the error amplifier (REA) and C4. The R7/C4 zero, ZERO1, is selected to cancel the pole formed by the output filter cap C3 and output load R LD, POLE2. The additional pole of R1/C3, POLE3, should be at least a decade past the crossover frequency to not affect stability: POLE1 (dominant pole) = 1 / (2 REA C4) ZERO1 (integrator zero) = 1 / (2 R7 C4) POLE2 (output load pole) = K1 / (2 RLD (C2 + C3)) POLE3 (output filter pole) = 1 / (2 R1 C3) The DC open-loop gain is given by: AOL = K2 Gm REA
8
Output Accuracy and Feedback Resistor Selection
The MAX1932 features 0.5% feedback accuracy. The total voltage accuracy of a complete APD bias circuit is the sum of the FB set-point accuracy, plus resistor ratio error and temperature coefficient. If absolute accuracy is critical, the best resistor choice is an integrated network with specified ratio tolerance and temperature coefficient. If using discrete resistors in high-accuracy applications, pay close attention to resistor tolerance and temperature coefficients.
Temperature Compensation
APDs exhibit a change in gain as a function of temperature. This gain change can be compensated with an appropriate adjustment in bias voltage. For this reason it may be desirable to vary the MAX1932 output voltage as a function of temperature. This can be done in soft-
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
Table 1. Compensation Components for Typical Circuits (Figure 2)
VIN, VOUT, IOUT(MAX) 5VIN, 40-90VOUT at 2.5mA 5VIN, 20-60VOUT at 2.5mA 5VIN, 20-60VOUT at 5mA 3VIN, 40-90VOUT at 2.5mA 3VIN, 4.5-15VOUT at 2.5mA INDUCTOR L1 (H) 100 150 82 33 220 CSNS C2 (F) 0.047 0.10 0.22 0.047 0.47 RSNS R1 () 806 806 392 806 806 COUT C3 (F) 0.1 0.047 0.10 0.1 0.01 RCOMP R7 (k) 20 15 10 20 7.5 CCOMP C4 (F) 0.22 0.22 0.47 0.22 0.47
ware by the system through the on-chip DAC, but can also be accomplished in hardware using an external thermistor or IC temperature sensor. Figure 8 shows how an NTC thermistor can be connected to make the bias voltage increase with temperature.
Chip Information
TRANSISTOR COUNT: 1592 PROCESS: BICMOS
PC Board Layout and Grounding
Careful PC board layout is important for minimizing ground bounce and noise. In addition, keep all connections to FB as a short as possible. In particular, locate feedback resistors (R5, R6, and R8) as close to FB as possible. Use wide, short traces to interconnect large current paths for N1, D1, L1, C1, C2. Do not share these connections with other signal paths. Refer to the MAX1932 EV kit for a PC board layout example.
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
COMP
REF 1.25V
UVLO
VIN
FB ERROR AMPLIFIER ERROR COMPARATOR
PWM CONTROL AND GATE DRIVER
GATE
RAMP
GND
OSC
987k CS+ CLIM 13k BUFFER 987k CS13k CL
REF
SCLK DIN CS SPI SERIAL INTERFACE 8 8-BIT DAC
DACOUT
Figure 1. Functional Diagram
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
INPUT 2.7V TO 5.5V CL COMP R7 20k C4 0.22F VIN C1 1F L1 100H D1 100V C2 0.047 N1 BSS123 CS SCLK DIN GND DACOUT FB R6 24.9k R5 1M CS+ CSR1 806
MAX1932
GATE
VOUT 40V TO 90V C3 0.1F
R8 32.4k
Figure 2. Typical Operating Circuit
INSTRUCTION EXECUTED VOUT CS
GATE
FB
1 SCLK DIN
8
MAX1932
CS+ CS-
D7
D6
D5
D4
D3
D2
D1
DO
Figure 3. Taking Feedback Ahead of Output Filter
Figure 4. Serial Interface Timing Diagram
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
CS
tCSH0 tCSS0 tCH tCSH1
tCSW
SCLK
tDS tDH
tCL
tCSS1
DIN
Figure 5. Detailed Serial Interface Timing Diagram
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
120
100
90V, 1mA 80 POLE1 ZERO1 POLE2 POLE3 60 0.0023Hz 36Hz 36Hz 4.2kHz 102dB
90V, 2.5mA 0.0023Hz 36Hz 91Hz 4.2kHz 98dB
MAGNITUDE (dB)
AOL
40
36Hz 91Hz 20
0.01
0.1
1.0 FREQUENCY (Hz)
10
100
1k 4.2k
10k
Figure 6. Loop Response
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
VIN
330H VOUT 0.1F GATE 1F
FB
MAX1932
CS+ CS-
Figure 7. Adding a Post LC Filter
VIN
TO CS+ R1
TO CSVOUT
GATE
R5
MAX1932
FB R8
R9
R10 NTC THERMISTOR
Figure 8. Adding an NTC Thermistor for Hardware Temperature Compensation; Output Voltage Increases with Temperature Rise
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
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Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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