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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MC145750
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QPSK Encoder
The MC145750 is a silicon gate HCMOS device designed to encode /4-shift QPSK baseband signals. The device contains two 10-bit DACs for the I/Q signal, Root-Nyquist digital filtering, and burst rising and falling edge processing for digital RF communication equipment. Primary applications for this device are in products that will be used in PHS (384 kbps) and PDC (42 kbps). It will perform up to 800 kbps data rate. It also contains PN511 random pattern generator and timing generator with PLL. * * * * * * * * * * Root-Nyquist Digital Filtering (Coefficient = 0.5) Burst Edge Processing Circuitry (Ramp-Up and -Down) Two 10-Bit DACs for I/Q Output Operating Voltage Range: 2.7 to 5.5 V PN511 Random Pattern Generator Conformance to RCR Standard for PHS, PDC Variable Data Transmission Rate up to 800 kbps (VDD = 5 V) Timing Generator with PLL QPSK Mode, Burst, and Continuous I/Q Signal Output is Performed Companion Device is MRFIC0001
VFU SUFFIX PLASTIC VQFP CASE 932
ORDERING INFORMATION
MC145750VFU VQFP
PIN ASSIGNMENT
NC PB2 NC NC TB0 TB1 TB2 TB3 TB4 TB5 TB6 NC NC PB1 CF PCO PLL ECLK DVDD DVSS DCLK DS/STBY TXD ERST/PDN 37 36 25 24 48 1 13 12 TB7 TNO/TB8 BW/TB9 NC Iout DAref3 DAref2 DAref1 DAref Qout DAVSS DAVDD
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 2 10/95
(c) Motorola, Inc. 1995 MOTOROLA
MODE2 MODE1 MODE0 TEST NC DVSS DV DD NC DRATE QPSK NC DAb NC = NO CONNECTION
MC145750 1
BLOCK DIAGRAM
TEST TB7:0 M2:0 QPSK DRATE DAb DAref DAref3:1
PN PATTERN GENERATOR PNO/TB8 TXD DS/STBY DCLK INTERFACE CIRCUIT
TEST CIRCUIT 10-BIT DAC /4-SHIFT QPSK ENCODER I ROLL-OFF FILTERS Q 10-BIT DAC Qout
Iout
PLL ECLK
TIMING GENERATOR
DPLL
BW/TB9
DVDD
DVSS
ERST/PDN
Cf PC0 PB1 PB2
DAVDD
DAVSS
INPUT/OUTPUT TIMING RELATIONS
DS (INPUT) 1 DCLK (INPUT) 2 3 4 5 6 7 8 9 n-1 n 1 2 3 9 10 11 14 15 16
TXD (INPUT) n BIT BW (OUTPUT)
DON'T CARE
FIRST SYMBOL
LAST SYMBOL
Iout/Qout (OUTPUT)
RAMP-UP (TWO SYMBOL LENGTH)
100% OUTPUT SWING LEVEL
RAMP-DOWN (TWO SYMBOL LENGTH)
MC145750 2
MOTOROLA
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MAXIMUM RATINGS
Parameter Symbol VDD Vin PD Value Unit V V DC Supply Voltage DC Input Voltage - 0.5 to + 7 - 0.5 to VDD + 0.5 500 Power Dissipation mW C Storage Temperature Tstg - 65 to +150
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol VDD Vin TA
Min 2.7 0 - 20
Typ 3.3 -- 25
Max 5.5 VDD 85
Unit V V C
DC Supply Voltage DC Input Voltage Operating Temperature Range
ELECTRICAL CHARACTERISTICS (TA = 25C, TXD = L, Normal Mode)
Parameters DC Supply Current VDD = 3 V Symbol Idd1 DRATE = L DRATE = H DRATE = L DRATE = H DRATE = L DRATE = H DC Supply Current VDD = 5 V Idd2 Idd3 Idd4 Idd5 Idd6 Idd7 Idd1 DRATE = L DRATE = H DRATE = L DRATE = H DRATE = L DRATE = H Idd2 Idd3 Idd4 Idd5 Idd6 Idd7 DS = Continual Input DS = Burst Input* ERST = L DS = L DS = Continual Input DS = Burst Input* Condition ERST = L DS = L Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ** 0.25 5.0 1.5 5.0 1.5 8.0 2.0 0.5 27.0 17.0 30.0 18.0 33.0 18.0 Max 0.5 6.0 1.8 6.0 1.8 10.0 2.6 3.0 33.0 19.0 33.0 20.0 37.0 20.0 mA Unit mA
* 625 s burst/5 ms period (DRATE = L) at DCLK = 384 kHz. 6.6 ms burst/20 ms period (DRATE = H) at DCLK = 42 kHz. ** Typical numbers are not guaranteed.
ANALOG CHARACTERISTICS (TA = 25C)
Parameters Output Swing Level I/Q Out Output Swing Imbalance Output DC Level I/Q Out Output Swing Imbalance Out-of-Band Noise Level VDD = 5 V VDD = 3 V VDD = 5 V VDD Vin 600 kHz 900 kHz DC Output Resistance * DAref1 = H at VDD = 3 V, DAref3 = H at VDD = 5 V ** Typical numbers are not guaranteed. Rout Iout/Qout VDD = 3 V VDD = 5 V Vout Vout DS = L Symbol Vout Condition RL = k, TXD = L Normal Mode Min 500 520 - 0.5 800 780 -- -- -- -- Typ** 550 570 0 820 800 -- - 50 - 55 50 Max 600 620 0.5 840 820 20 -- -- 100 dB dB mV Unit mV p-p
MOTOROLA
MC145750 3
SWITCHING CHARACTERISTICS (TA = 25C)
Parameters Input Voltage High-Level Low-Level Output Voltage High-Level Low-Level Data Set-Up Time Data Hold Time Data Output Propagation Delay I/Q Output Propagation Delay Data Rate VDD = 3 V Symbol VIH VIL VOH VOL tsu th tpd TD TXD, DS, STBY TXD, DS, STBY BW, PNO Iout, Qout DRATE = L DRATE = H VDD = 5 V DRATE = L DRATE = H Clock Input Duty Cycle VCO Oscillation Frequency VDD = 3 V VDD = 5 V * Typical numbers are not guaranteed. DCLK fVCO1 fVCO2 BW, PNO Condition Min VDD x 0.7 -- VDD x 0.9 -- 10 10 -- -- -- -- -- -- 45 -- -- Typ* -- -- -- -- -- -- 1.5 4 -- -- -- -- 50 -- -- Max -- VDD x 0.3 -- VDD x 0.1 -- -- 3 6 450 55 800 100 55 20 32 % MHz kbps s ns Unit V
DS tsu DCLK tsu tsu th th 1/fclk th tsu
TXD tPD BW tD tPD
tD Iout/Qout tPD PNO
Figure 1. Timing Diagram
MC145750 4
MOTOROLA
PIN DESCRIPTIONS
POWER SUPPLY VSS Digital Ground (Pins 6, 44) These are the negative power supply input pins to the digital portion of the device and are connected to ground (0 V). VDD Positive Power Supply Input (Pins 7, 43) These are the positive power supply input pins to the digital portion of the device. Typical operating voltage range is 3.3 V at DAref3 = H, 5.0 V at DAref1 = H. Power should be fed simultaneously with DAVDD pin in order to avoid any possible damage to the device. DAVDD Positive Power Supply Input for DACs (Pin 13) This is the positive power supply input pin to the analog portion of the device. Typical operating voltage range is 2.7 V to 5.5 V. DAVSS Analog Ground for DACs (Pin 14) This is the negative power supply pin to the analog portion of the device and is connected to ground. MODE CONTROL AND TEST MODE0 - MODE2 Normal/Test Mode Select (Pins 1, 2, 3) These pins must be connected to ground for normal operation. For system test, PN pattern generation mode will be performed when MODE0 = H and MODE1, MODE2 = L. PN511 signal is fed to the encoder instead of input data from TXD pin. Data shift timing is the same as the normal operation mode and burst timing indicated by DS pin is still valid for the device. The PN511 signal is monitored at the PNO pin. TEST Test Mode (Pin 4) The device operates normally while this pin is held low. When this signal is high, the device enters into factory test mode. Only one mode is allowed to be enacted by user for PN Mode. DRATE Data-Rate Select (Pin 9) This pin can select high data rate when it is low, such as in PHS applications. QPSK (D)QPSK//4-Shift QPSK Mode Select (Pin 10) The device operates as a /4-QPSK Encoder when this pin is held high. By making this pin low, it functions as non- shift differential QPSK Encoder. All of the functions are the same in both modes.
PN0/TB8 PN511 Test Pattern Output/Test Bus 8 (Pin 23) This is the output data of PN511 test-pattern in normal mode. When the PN pattern generator outputs to this pin, it can be output I/Q pins and data from TXD pin may be ignored. If the DS signal is L, I/Q pins stop but PN data stream may be output. TB0 - TB7 Test Bus (Pins 24, 26 - 32) These pins are used in factory test and should be connected to ground for normal operation. PLL Int/Ext PLL Clock Select (Pin 41) When this pin is connected to ground, the PLL is active and timing will be generated internally. When this pin is connected to VDD, timing should be applied to the ECLK pin. DIGITAL INTERFACE PINS BW/TB9 Burst Window Output/Test Bus 9 (Pin 22) This output indicates when modulated baseband I/Q signals are output from this device. This pin is used as the transmission control signal for saving power for RF. ECLK External Clock Input (Pin 42) When the internal timing generator with PLL is not used in the system, this pin must have 15.36 MHz applied as a system clock for this device. This pin is connected to ground for normal operation. DCLK Data Shift Clock Input (Pin 45) This is the shift clock input for the transmit data input and is typically 384 kHz for the PHS (DRATE Pin = L) and 42 kHz for the PDC (DRATE Pin = H) application. The data input occurs at the rising edge of the DCLK. For burst-type systems such as the TDMA data transmission applications, this signal must be synchronized with the rising/falling edge of the DS pin (Data Slot Timing Input). DS/STBY Data Slot Timing/Standby Input (Pin 46) For burst-type, this input signal indicates when transmit data are valid for the device. Its duration must be equal with the number of input data to the device, and its transition must be aligned with the rising edge of the DCLK signal. When a logic L is applied to this pin, all digital portions except the timing generator are not clocked and the device is in a low power dissipation mode. When a logic H is applied continuously, all input data are encoded as valid data. TXD Transmit Data Input (Pin 47) Data bit streams to be transmitted are input to this pin. The data is valid only when the DS (Pin 46) is asserted (high). Its transition should be synchronized with rising edge of the DCLK (Pin 45).
MOTOROLA
MC145750 5
ERST/PDN External Reset/Power Down Input (Pin 48) When a logic L is applied to this pin, it forces a complete power down. When at start up, VDD goes high, it is recommended that a logic L, then a logic H be applied to this pin to start up and reset all digital portions. ANALOG INTERFACE PINS Qout Filtered Quadrature-Phase Output (Pin 15) This is the modulated quadrature-phase signal output and the amplitude is typically 550 mV p-p at VDD = 3 V in PN test mode. The output dc resistance is approximately 50 . Iout Filtered In-Phase Output (Pin 20) This is the modulated in-phase signal output and amplitude is typically 500 mV p-p at VDD = 3 V in PN test mode. The output dc resistance is approximately 50 . DAC AND PLL SETTING DAb Reference Bias Setting Pin to DACs (Pin 12) A resistor connected to ground from this pin determines the reference current value for internal DACs. This resistor's value is 200 k typically.
DAref Ripple Filter Capacitor (Pin 16) A capacitor connected to ground from this pin acts as a ripple filter for the internal DACs' reference voltage. This capacitor's value is 0.1F, typically. DAref1 - DAref3 Reference Bias Setting to DACs (Pin 17 - 19) These pins determine the reference voltage for internal DACs in conjunction with DAb pin. At 3 V operation, DAref1 pin should be connected to V DD. DAref2 pin should be connected to VDD at 3.3 V. DAref3 pin should be connected to VDD at 5 V. The two other pins for the respective cases must be left open. PB1, PB2 PLL Bias (Pins 35, 38) This pin determines the bias of the PLL. Its recommended values are shown in Table 1 and it depends on operating voltage. Cf Loop Filter Capacitor (Pin 39) Input from Cf pin is fed directly as the internal VCO control signal. PCO Phase Comparator Output (Pin 40) Connect an LPF as loop filter for the PLL. Refer to the application figure for recommended values.
Table 1. Function Table
Pin 3 10 9 17 18 19 41 MODE0 QPSK DRATE DAref1 DAref2 DAref3 PLL L Normal Mode Non-Shift High Speed -- -- -- PLL Operation Mode Power Down H PN Pattern /4-Shift Low Speed VDD = 5 V VDD 3.3 V VDD 3.0 V Ext Clock Mode In case of external clock mode, TX data rate must be set to a frequency of 1/40 when DRATE = L, and must be set to a frequency of 1/320 when DRATE = H. Max data rate is limited by power supply. Digital circuits reset condition will be released by rising edge of this input. To be determined setting high or low speed data rate. These pins should be held high depending on power supply voltage and others should be left open. Remarks These settings are independent of power supply.
48
ERST/PDN
Normal Operation
ROLL-OFF FILTER SERIAL TO PARALLEL CONVERSION Xk Yk Ik
TO DAC
SERIAL DATA IN
DIFFERENTIAL ENCODING
Qk ROLL-OFF FILTER TO DAC
Figure 2. DQPSK Baseband Signal Generation
MC145750 6
MOTOROLA
DEVICE DESCRIPTION
/4-Shift QPSK Encoding RCR standard (STD-28) specifies the basic configuration of this modulation scheme as shown in Figure 2. First, serial data input is converted to Xk/Yk parallel streams. Then its value is compared with one previous symbol Ik/Qk, respectively, whether or not there is a change of polarity. If there is a change, result is coded as 1. This two-bit r (di-bit) is called symbol, hence symbol rate is just half of the data input rate to be modulated. Phase transitions are determined as shown in Figure 3, with respect to four di-bit values of Xk, Yk. (As is shown, there should be at least /4 of phase shift in each symbol timing unlike plain QPSK.) Actual in-phase outputs are fed to a quadrature modulator circuit, and it is recommended that a 2- to 3-order LPF be used, which may be used as a level shifter and dc offset compensation circuitry at the same time. The reference voltage for the DACs is given by connecting either of DAref1:3 to VDD according to the operating voltage used. It is preferable not to have this voltage vary, since I/Q output levels are affected. Timing Generator The PLL is intended in order to generate all required timing signals for the devices. The VCO oscillating at the PN511 pattern rate is utilized when some characteristics are measured. By pulling MODE0 pin high, the device generates this sequence. It is a useful simple measurement for the occupied power bandwidth and the out-of-band power level. The sequence itself can also be monitored at the PNO pin. This circuit is reset by an external reset signal while the low-state of DS is not valid for initializing the generator.
START-UP SEQUENCE To ensure stability and to initialize the internal ROM and encoder, the start-up sequence should be done at power- up. Refer to Figure 4.
Di-Bit Input Xk 0 0 1 1 Yk 0 1 0 1 Phase Shift /4 3/4 - /4 - 3/4
Q 00 01 22.5 I 11 10
Figure 3. Phase Diagram
VDD
90%
> 100 s
REST/PDN 1s
DS
Figure 4. Start-Up Sequence
MOTOROLA
MC145750 7
220 k
36
35
34
33
32 31 TB0 TB1
PB2
30 TB2 TB3 29 28 TB4 27 TB5 26 TB6 25 NC TB7 PNO/TB8 BW/TB9
NC
NC
NC
37 33 k 47 k 1000 p 2.2 k 100 p 33 k 10 0.1 384 kHz BURST TIMING INPUT TX DATA INPUT EXTERNAL RESET INPUT 0.1 38 39 40 41 42 43 44 45
NC PB1 CF PCO PLL ECLK DVDD DVSS MC145750
24 23 22 21 I OUTPUT BURST TIMING OUTPUT
1
NC Iout 20 19 DAref3 DAref2 18 DAref1 17 16 DAref Qout 15 DAVSS 14 13 DAVDD DAb NC 12 0.1
DV DD
DRATE
DVSS
QPSK
TEST
DCLK 46 DS/STBY 47 TXD 48 ERST/PDN M2 M1 M0
Q OUTPUT
NC
NC
0.1
CP
10
2
3
4
5
6
7
8
9
11
10
10 k 0.1 10
5V
Figure 5. DRATE Equals L: 5 V Operation
47 k
36
35
34
33
32
TB1 TB2 30 TB3 29
31
28 TB4
27
PB2
TB0
26 TB6 25 NC TB7 PNO/TB8 BW/TB9
TB5
NC
NC
NC
37 33 k 47 k 1000 p 2.2 k 100 p 33 k 10 0.1 384 kHz BURST TIMING INPUT TX DATA INPUT EXTERNAL RESET INPUT 0.1 38 39 40 41 42 43
NC PB1 CF PCO PLL ECLK MC145750
24 23 22 21 I OUTPUT BURST TIMING OUTPUT
1
DVSS 7 DV DD 8 NC 9 DRATE 10 QPSK 11 NC 12 DAb
TEST
DVDD 44 DV SS 45 DCLK 46 DS/STBY 47 TXD 48 ERST/PDN M2 M1 M0 CP 2 3
NC Iout 20 19 DAref3 DAref2 18 DAref1 17 16 DAref Qout 15 DAVSS 14 13 DAVDD 0.1
Q OUTPUT
NC
0.1
4
5
6
10
220 k
0.1 10
3V
Figure 6. DRATE Equals H: 3 V Operation
MC145750 8
MOTOROLA
MC145750
I/Q OUTPUT
- + R BALANCE CONTROL - R + R R TO MRFIC0001 MODULATOR
LEVEL SHIFT
Figure 7. I/Q Output Interface Circuit 1
MC145750
I/Q OUTPUT
- + R BALANCE CONTROL - R + R R TO MRFIC0001 MODULATOR
LEVEL SHIFT
Figure 8. I/Q Output Interface Circuit 2
+5V - + -5V 100 k MC145750 220 F - + -5V 100 k Qin +5V MODULATION UNIT SMHU-58 (Zin = 50 ) Iin SPECTRUM ANALYZER R3365 IF (240 MHz)
220 F Iout
Qout
MODULATION ACCURACY ANALYZER R3541A
Measurement Equipment: Advantest Spectrum Analyzer R3365 Advantest Modulation Accuracy Analyzer R3541A Rohde & Schwarz Modulation Unit SMHU-58 Conditions: Internal PLL mode, 384 kbps (PHS), TA = 25C
Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of measurement equipment suppliers.
Figure 9. Modulation Accuracy Measurement Schematic
MOTOROLA
MC145750 9
ERR VEC : 0.982% rms 1.5 1.2 0.9 0.6 0.3 Q (t) 0.0 - 0.3 - 0.6 - 0.9 - 1.2 - 1.5 - 1.2 - 0.9 - 0.6 - 0.3 0.0 I (t) 0.3 0.6 0.9 1.2 1.5 Q (t) 1.5 1.2 0.9 0.6 0.3 0.0 - 0.3 - 0.6 - 0.9 - 1.2
ERR VEC : 0.982% rms
- 1.5 - 1.5 - 1.2 - 0.9 - 0.6 - 0.3
0.0 I (t)
0.3
0.6
0.9
1.2 1.5
Figure 10. I-Q Pattern
Figure 11. I-Q Pattern
ERR VEC : 0.982% rms 1.5 1.2 0.9 0.6 0.3 Q (t) 0.0 - 0.3 - 0.6 - 0.9 - 1.2 - 1.5 0.0 0.2 0.4 0.6 0.8 1.0 TIME 1.2 1.4 1.6 1.8 2.0
Figure 12. Q-Eye Pattern
MC145750 10
MOTOROLA
PACKAGE DIMENSIONS
VFU SUFFIX PLASTIC VQFP CASE 932-02
4X
0.200 (0.008) AB T-U Z 9 A1
48 37
A
DETAIL Y
P
1
36
-T- B B1
12 25
-U- V AE V1 AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BASIC 0.050 0.150 0.090 0.200 0.500 0.700 12 _REF 0.090 0.160 0.250 BASIC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.007 0.011 0.053 0.057 0.007 0.009 0.020 BASIC 0.002 0.006 0.004 0.008 0.020 0.028 12 _REF 0.004 0.006 0.010 BASIC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
13
24
-Z- S1 -T-, -U-, -Z- S
4X
DETAIL Y 0.200 (0.008) AC T-U Z
G -AB- -AC- AD
BASE METAL
0.080 (0.003) AC
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
M_
TOP & BOTTOM
0.080 (0.003)
MOTOROLA
EEEC CCC EEEC CCC EEEC CCC EEEC CCC
F D
M
R
GAUGE PLANE
N
J C E
0.250 (0.010)
AC T-U
S
Z
S
SECTION AE-AE
H DETAIL AD
W K X
Q_
MC145750 11
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC145750 12
*MC145750/D*
MC145750/D MOTOROLA

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