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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
PM4388
TOCTL
OCTAL T1 FRAMER
DATASHEET
ISSUE 5: NOVEMBER 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
CONTENTS 1 2 3 4 5 6 7 8 9 FEATURES ............................................................................................... 1 APPLICATIONS ........................................................................................ 3 REFERENCES ......................................................................................... 4 APPLICATION EXAMPLES ...................................................................... 5 BLOCK DIAGRAM.................................................................................... 6 DESCRIPTION ......................................................................................... 7 PIN DIAGRAM .......................................................................................... 8 PIN DESCRIPTION ................................................................................ 10 FUNCTIONAL DESCRIPTION ............................................................... 20 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 FRAMER (FRMR) ........................................................................ 20 FRAMER/SLIP BUFFER RAM (FRAM) ....................................... 20 INBAND LOOPBACK CODE DETECTOR (IBCD) ....................... 21 PERFORMANCE MONITOR COUNTERS (PMON) .................... 21 BIT ORIENTED CODE DETECTOR (RBOC) .............................. 21 RDLC FACILITY DATA LINK RECEIVER..................................... 22 ALARM INTEGRATOR (ALMI) ..................................................... 23 ELASTIC STORE (ELST) ............................................................ 23 SIGNALING EXTRACTOR (SIGX)............................................... 24 RECEIVE PER-DS0 SERIAL CONTROLLER (RPSC) ................ 24 INGRESS INTERFACE (IIF) ........................................................ 25 PATTERN DETECTOR/GENERATOR (PRGD) ............................ 27 BASIC TRANSMITTER (XBAS) ................................................... 28
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 10 11 12
TRANSMIT PER-DS0 SERIAL CONTROLLER (TPSC) .............. 29 SIGNALING ALIGNER (SIGA)..................................................... 29 INBAND LOOPBACK CODE GENERATOR (XIBC)..................... 29 BIT ORIENTED CODE GENERATOR (XBOC) ............................ 29 TDPR FACILITY DATA LINK TRANSMITTER .............................. 30 RECEIVE AND TRANSMIT DIGITAL JITTER ATTENUATOR (RJAT, TJAT)............................................................................................ 31 TIMING OPTIONS (TOPS) .......................................................... 35 EGRESS INTERFACE (EIF) ........................................................ 35 MICROPROCESSOR INTERFACE (MPIF) ................................. 37
REGISTER DESCRIPTION.................................................................... 38 NORMAL MODE REGISTER DESCRIPTION........................................ 42 TEST FEATURES DESCRIPTION ....................................................... 191 12.1 12.2 TEST MODE 0 ........................................................................... 193 JTAG TEST PORT...................................................................... 197
13 14
FUNCTIONAL TIMING DIAGRAMS ..................................................... 200 OPERATIONS....................................................................................... 207 14.1 14.2 14.3 14.4 14.5 CONFIGURING THE TOCTL FROM RESET............................. 207 USING THE INTERNAL FDL TRANSMITTER ........................... 210 USING THE INTERNAL FDL RECEIVER.................................. 214 USING THE PRGD PATTERN GENERATOR/DETECTOR ........ 218 USING THE LOOPBACK MODES............................................. 223 14.5.1 LINE LOOPBACK............................................................ 223 14.5.2 DIAGNOSTIC DIGITAL LOOPBACK ............................... 224
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
14.5.3 PER-DS0 LOOPBACK .................................................... 225 14.6 USING THE PER-DS0 SERIAL CONTROLLERS...................... 226 14.6.1 INITIALIZATION .............................................................. 226 14.6.2 DIRECT ACCESS MODE ............................................... 226 14.6.3 INDIRECT ACCESS MODE ............................................ 227 14.7 USING THE TRANSMIT DIGITAL JITTER ATTENUATOR ......... 228 14.7.1 DEFAULT APPLICATION................................................. 228 14.7.2 DATA BURST APPLICATION .......................................... 228 14.7.3 ELASTIC STORE APPLICATION.................................... 229 14.7.4 ALTERNATE TLCLK REFERENCE APPLICATION......... 229 14.8 14.9 ISOLATING AN INTERRUPT .................................................... 229 USING THE PERFORMANCE MONITOR COUNTER VALUES 230
14.10 JTAG SUPPORT ........................................................................ 232 15 16 17 18 19 20 ABSOLUTE MAXIMUM RATINGS........................................................ 243 D .C. CHARACTERISTICS .................................................................. 244 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ...... 246 TOCTL I/O TIMING CHARACTERISTICS ............................................ 251 ORDERING AND THERMAL INFORMATION ...................................... 263 MECHANICAL INFORMATION............................................................. 264
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
LIST OF REGISTERS REGISTERS 000H, 080H, 100H, 180H, 200H, 280H, 300H, 380H: RECEIVE LINE OPTIONS ...................................................................................... 43 REGISTERS 001H, 081H, 101H, 181H, 201H, 281H, 301H, 381H: INGRESS INTERFACE OPTIONS........................................................................... 46 REGISTERS 002H, 082H, 102H, 182H, 202H, 282H, 302H, 382H: BACKPLANE PARITY CONFIGURATION AND STATUS .............................................. 48 REGISTERS 003H, 083H, 103H, 183H, 203H, 283H, 303H, 383H: RECEIVE INTERFACE CONFIGURATION ............................................................. 50 REGISTERS 004H, 084H, 104H, 184H, 204H, 284H, 304H. 384H: TRANSMIT INTERFACE CONFIGURATION ............................................................. 52 REGISTERS 005H, 085H, 105H, 185H, 205H, 285H, 305H, 385H: EGRESS OPTIONS ............................................................................................... 54 REGISTERS 006H, 086H, 106H, 186H, 206H, 286H, 306H, 386H: TRANSMIT FRAMING AND BYPASS OPTIONS....................................................... 56 REGISTERS 007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H: TRANSMIT TIMING OPTIONS .................................................................................. 58 REGISTERS 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H: INTERRUPT SOURCE #1 ........................................................................................... 66 REGISTERS 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H: INTERRUPT SOURCE #2 ........................................................................................... 67 REGISTERS 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH: MASTER DIAGNOSTICS ....................................................................................... 68 REGISTER 00BH: TOCTL MASTER TEST ....................................................... 70 REGISTER 00CH: TOCTL REVISION/CHIP ID/GLOBAL PMON UPDATE....... 72 REGISTERS 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH: FRAMER RESET.................................................................................................... 73 REGISTER 00EH: INTERRUPT ID ................................................................... 74
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
REGISTERS 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH: PATTERN GENERATOR/DETECTOR POSITIONING/CONTROL .......................... 75 REGISTERS 010H, 090H, 110H, 190H, 210H, 290H, 310H, 390H: RJAT INTERRUPT STATUS ............................................................................. 77 REGISTER 011H, 091H, 111H, 191H, 211H, 291H, 311H, 391H: RJAT REFERENCE CLOCK DIVISOR (N1) CONTROL .................................. 78 REGISTERS 012H, 092H, 112H, 192H, 212H, 292H, 312H, 392H: RJAT OUTPUT CLOCK DIVISOR (N2) CONTROL ......................................... 79 REGISTERS 013H, 093H, 113H, 193H, 213H, 293H, 313H, 393H: RJAT CONFIGURATION .................................................................................. 80 REGISTERS 018H, 098H, 118H, 198H, 218H, 298H, 318H, 398H: TJAT INTERRUPT STATUS ............................................................................. 82 REGISTER 019H, 099H, 119H, 199H, 219H, 299H, 319H, 399H: TJAT REFERENCE CLOCK DIVISOR (N1) CONTROL .................................. 83 REGISTERS 01AH, 09AH, 11AH, 19AH, 21AH, 29AH, 31AH, 39AH: TJAT OUTPUT CLOCK DIVISOR (N2) CONTROL ......................................... 84 REGISTERS 01BH, 09BH, 11BH, 19BH, 21BH, 29BH, 31BH, 39BH: TJAT CONFIGURATION .................................................................................. 85 REGISTERS 01CH, 09CH, 11CH, 19CH, 21CH, 29CH, 31CH, 39CH: ELST CONFIGURATION .................................................................................. 87 REGISTERS 01DH, 09DH, 11DH, 19DH, 21DH, 29DH, 31DH, 39DH: ELST INTERRUPT ENABLE/STATUS .............................................................. 88 REGISTERS 01EH, 09EH, 11EH, 19EH, 21EH, 29EH, 31EH, 39EH: ELST TROUBLE CODE ................................................................................... 89 REGISTERS 020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H: FRMR CONFIGURATION .................................................................................. 90 REGISTERS 021H, 0A1H, 121H, 1A1H, 221H, 2A1H, 321H, 3A1H: FRMR INTERRUPT ENABLE ............................................................................ 92 REGISTERS 022H, 0A2H, 122H, 1A2H, 222H, 2A2H, 322H, 3A2H: FRMR INTERRUPT STATUS ............................................................................. 94
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
REGISTERS 027H, 0A7H, 127H, 1A7H, 227H, 2A7H, 327H, 3A7H: CLOCK MONITOR............................................................................................... 96 REGISTERS 02AH, 0AAH, 12AH, 1AAH, 22AH, 2AAH, 32AH, 3AAH: RBOC ENABLE ................................................................................................. 98 REGISTERS 02BH, 0ABH, 12BH, 1ABH, 22BH, 2ABH, 32BH, 3ABH: RBOC CODE STATUS ....................................................................................... 99 REGISTERS 02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH: ALMI CONFIGURATION ................................................................................ 100 REGISTERS 02DH, 0ADH, 12DH, 1ADH, 22DH, 2ADH, 32DH, 3ADH: ALMI INTERRUPT ENABLE .......................................................................... 101 REGISTERS 02EH, 0AEH, 12EH, 1AEH 22EH, 2AEH, 32EH, 3AEH: ALMI INTERRUPT STATUS ........................................................................... 102 REGISTERS 02FH, 0AFH, 12FH, 1AFH, 22FH, 2AFH, 32FH, 3AFH: ALMI ALARM DETECTION STATUS ............................................................. 103 REGISTERS 030H, 0B0H, 130H, 1B0H, 230H, 2B0H, 330H, 3B0H: TPSC CONFIGURATION ................................................................................ 105 REGISTERS 031H, 0B1H, 131H, 1B1H, 231H, 2B1H, 331H, 3B1H: TPSC P ACCESS STATUS................................................................................. 106 REGISTERS 032H, 0B2H, 132H, 1B2H, 232H, 2B2H, 332H, 3B2H: TPSC CHANNEL INDIRECT ADDRESS/CONTROL ...................................... 107 REGISTERS 033H, 0B3H, 133H, 1B3H, 233H, 2B3H, 333H, 3B3H: TPSC CHANNEL INDIRECT DATA BUFFER .................................................. 108 TPSC INTERNAL REGISTERS 01-18H: EGRESS CONTROL BYTE ............ 110 TPSC INTERNAL REGISTERS 19-30H: IDLE CODE BYTE .......................... 113 TPSC INTERNAL REGISTERS 31-48H: SIGNALING CONTROL BYTE........ 114 REGISTER 034H, 0B4H, 134H, 1B4H, 234H, 2B4H ,334H, 3B4H: TDPR CONFIGURATION ................................................................................ 115 REGISTER 035H, 0B5H, 135H, 1B5H, 235H, 2B5H ,335H, 3B5H: TDPR UPPER TRANSMIT THRESHOLD ....................................................... 117
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
REGISTER 036H, 0B6H, 136H, 1B6H, 236H, 2B6H ,336H, 3B6H: TDPR LOWER INTERRUPT THRESHOLD .................................................... 118 REGISTER 037H, 0B7H, 137H, 1B7H, 237H, 2B7H ,337H, 3B7H: TDPR INTERRUPT ENABLE .......................................................................... 119 REGISTER 038H, 0B8H, 138H, 1B8H, 238H, 2B8H ,338H, 3B8H: TDPR INTERRUPT STATUS /UDR CLEAR..................................................... 121 REGISTER 039H, 0B9H, 139H, 1B9H, 239H, 2B9H ,339H, 3B9H: TDPR TRANSMIT DATA .................................................................................. 123 REGISTERS 03CH, 0BCH, 13CH, 1BCH, 23CH, 2BCH, 33CH, 3BCH: IBCD CONFIGURATION ................................................................................ 124 REGISTERS 03DH, 0BDH, 13DH, 1BDH, 23DH, 2BDH, 33DH, 3BDH: IBCD INTERRUPT ENABLE/STATUS ............................................................ 125 REGISTERS 03EH, 0BEH, 13EH, 1BEH, 23EH, 2BEH, 33EH, 3BEH: IBCD ACTIVATE CODE.................................................................................. 127 REGISTERS 03FH, 0BFH, 13FH, 1BFH, 23FH, 2BFH, 33FH, 3BFH: IBCD DEACTIVATE CODE............................................................................. 128 REGISTERS 040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H: SIGX CONFIGURATION (COSS=0) .............................................................. 129 REGISTERS 040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H: SIGX CONFIGURATION (COSS=1) .............................................................. 131 REGISTERS 041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H: SIGX P ACCESS STATUS (COSS=0) ............................................................... 132 REGISTERS 041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H: SIGX SIGNALING STATE CHANGE CHANNELS 17-24 (COSS=1) .............. 133 REGISTERS 042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H: SIGX CHANNEL INDIRECT ADDRESS/CONTROL (COSS=0) .................... 134 REGISTERS 042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H: SIGX SIGNALING STATE CHANGE CHANNELS 9-16 (COSS=1) ................ 135 REGISTERS 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H: SIGX CHANNEL INDIRECT DATA BUFFER (COSS = 0) .............................. 136
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
REGISTERS 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H: SIGX SIGNALING STATE CHANGE CHANNELS 1-8 (COSS=1) .................. 137 SIGX INTERNAL REGISTERS 20-37H: SIGNALING DATA ............................ 139 SIGX INTERNAL REGISTERS 40-57H: PER-DS0 CONFIGURATION DATA . 141 REGISTERS 044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H: XBAS CONFIGURATION ................................................................................ 142 REGISTERS 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H: XBAS ALARM TRANSMIT .............................................................................. 144 REGISTERS 046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H: XIBC CONTROL ............................................................................................ 145 REGISTERS 047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H: XIBC LOOPBACK CODE............................................................................... 147 REGISTERS 049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H: PMON INTERRUPT ENABLE/STATUS ............................................................ 148 REGISTERS 04A-04FH, 0CA-0CFH, 14A-14FH, 1CA-1CFH, 24A-24FH, 2CA2CFH, 34A-34FH, 3CA-3CFH: LATCHING PERFORMANCE DATA ..... 149 REGISTERS 04AH, 0CAH, 14AH 1CAH, 24AH, 2CAH, 34AH, AND 3CAH: PMON BEE COUNT (LSB)................................................................... 150 REGISTERS 04BH, 0CBH, 14BH 1CBH, 24BH, 2CBH, 34BH, AND 3CBH: PMON BEE COUNT (MSB).................................................................. 151 REGISTERS 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH: PMON FER COUNT (LSB)............................................................................... 152 REGISTERS 04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH: PMON FER COUNT (MSB).............................................................................. 153 REGISTERS 04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH: PMON OOF COUNT ........................................................................................ 154 REGISTERS 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH: PMON COFA COUNT ...................................................................................... 155 REGISTERS 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H: RPSC CONFIGURATION ................................................................................ 156
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
REGISTERS 051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H: RPSC P ACCESS STATUS................................................................................. 157 REGISTERS 052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H: RPSC CHANNEL INDIRECT ADDRESS/CONTROL ...................................... 158 REGISTERS 053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H: RPSC CHANNEL INDIRECT DATA BUFFER .................................................. 159 RPSC INTERNAL REGISTERS 01-18H: INGRESS CONTROL BYTE........... 161 RPSC INTERNAL REGISTERS 19-30H: DATA TRUNK CONDITIONING CODE BYTE .................................................................................................... 163 RPSC INTERNAL REGISTERS 31-48H: SIGNALING TRUNK CONDITIONING BYTE .................................................................................................... 164 REGISTERS 054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H: RDLC CONFIGURATION ................................................................................ 165 REGISTER 055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H: RDLC INTERRUPT CONTROL ....................................................................... 167 REGISTER 056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H: RDLC STATUS ................................................................................................ 168 REGISTER 057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H: RDLC DATA .............................................................................................................. 171 REGISTER 058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H: RDLC PRIMARY ADDRESS MATCH .............................................................. 172 REGISTER 059H, 0D9H, 159H, 1D9H, 259H, 2D9H, 359H, 3D9H: RDLC SECONDARY ADDRESS MATCH........................................................ 173 REGISTERS 05DH, 0DDH, 15DH, 1DDH, 25DH, 2DDH, 35DH, 3DDH: XBOC CODE ................................................................................................... 174 REGISTER 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H: PRGD CONTROL ............................................................................................ 175 REGISTER 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H: PRGD INTERRUPT ENABLE/STATUS ............................................................ 177
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
REGISTER 062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H: PRGD LENGTH ............................................................................................... 179 REGISTER 063H, 0E3H, 163H, 1E3H, 263H, 2E3H, 363H, 3E3H: PRGD TAP .............................................................................................................. 180 REGISTER 064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H: PRGD ERROR INSERTION REGISTER ......................................................... 181 REGISTER 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H: PRGD PATTERN INSERTION #1 .................................................................... 183 REGISTER 069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H: PRGD PATTERN INSERTION #2 .................................................................... 184 REGISTER 06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH: PRGD PATTERN INSERTION #3 .................................................................... 185 REGISTER 06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH: PRGD PATTERN INSERTION #4 .................................................................... 186 REGISTER 06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH: PRGD PATTERN DETECTOR #1 .................................................................... 187 REGISTER 06DH, 0EDH, 16DH, 1EDH, 26DH, 2EDH, 36DH, 3EDH: PRGD PATTERN DETECTOR #2 .................................................................... 188 REGISTER 06EH, 0EEH, 16EH, 1EEH, 26EH, 2EEH, 36EH, 3EEH: PRGD PATTERN DETECTOR #3 .................................................................... 189 REGISTER 06FH, 0EFH, 16FH, 1EFH, 26FH, 2EFH, 36FH, 3EFH: PRGD PATTERN DETECTOR #4 .................................................................... 190 REGISTER 00BH: TOCTL MASTER TEST ..................................................... 192
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
LIST OF FIGURES FIGURE 1 - HIGH DENSITY CHANNELIZED PORT CARD.............................. 5 FIGURE 2 - CLOCK MASTER: FULL DS1....................................................... 25 FIGURE 3 - CLOCK MASTER: NXDS0 ........................................................... 26 FIGURE 4 - CLOCK SLAVE: ICLK REFERENCE............................................ 26 FIGURE 5 - CLOCK SLAVE: EXTERNAL SIGNALING ................................... 27 FIGURE 6 - DJAT JITTER TOLERANCE ......................................................... 33 FIGURE 7 - DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY ... 34 FIGURE 8 - DJAT JITTER TRANSFER............................................................ 34 FIGURE 9 - CLOCK MASTER: FULL DS1....................................................... 35 FIGURE 10- CLOCK MASTER: NXDS0 ........................................................... 36 FIGURE 11- CLOCK SLAVE: EFP ENABLED .................................................. 36 FIGURE 12- CLOCK SLAVE: EXTERNAL SIGNALING.................................... 37 FIGURE 13- TRANSMIT TIMING OPTIONS ..................................................... 65 FIGURE 14- INGRESS INTERFACE CLOCK MASTER: NXDS0 MODE........ 200 FIGURE 15- EGRESS INTERFACE CLOCK MASTER: NXDS0 MODE ......... 200 FIGURE 16- INGRESS INTERFACE CLOCK MASTER : FULL DS1 MODE .. 201 FIGURE 17- EGRESS INTERFACE : 1.544 MHZ CLOCK MASTER: FULL DS1 MODE................................................................................................... 201 FIGURE 18- INGRESS INTERFACE: 1.544MHZ CLOCK SLAVE MODES .... 202 FIGURE 19- EGRESS INTERFACE : 1.544 MHZ CLOCK SLAVE: EFP ENABLED MODE ................................................................................. 202 FIGURE 20- EGRESS INTERFACE : 1.544 MHZ CLOCK SLAVE: EXTERNAL SIGNALING MODE .............................................................................. 203
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
FIGURE 21- INGRESS INTERFACE: 2.048 MHZ CLOCK SLAVE MODE...... 204 FIGURE 22- EGRESS INTERFACE: 2.048 MHZ CLOCK SLAVE: EFP ENABLED MODE................................................................................................... 205 FIGURE 23- EGRESS INTERFACE: 2.048 MHZ CLOCK SLAVE: EXTERNAL SIGNALING MODE .............................................................................. 206 FIGURE 24- TYPICAL DATA FRAME.............................................................. 216 FIGURE 25- EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ......... 217 FIGURE 26- PRGD PATTERN GENERATOR ................................................. 220 FIGURE 27- LINE LOOPBACK....................................................................... 224 FIGURE 28- DIAGNOSTIC DIGITAL LOOPBACK .......................................... 225 FIGURE 29- PER-DS0 LOOPBACK ............................................................... 226 FIGURE 30- BEE COUNT EXPECTED VS BIT ERROR RATE FOR ESF...... 231 FIGURE 31- BOUNDARY SCAN ARCHITECTURE........................................ 232 FIGURE 32- TAP CONTROLLER FINITE STATE MACHINE .......................... 234 FIGURE 33- INPUT OBSERVATION CELL (IN_CELL) ................................... 240 FIGURE 34- OUTPUT CELL (OUT_CELL)..................................................... 241 FIGURE 35- BIDIRECTIONAL CELL (IO_CELL)............................................ 241 FIGURE 36- LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 242 FIGURE 37- MICROPROCESSOR READ ACCESS TIMING ......................... 247 FIGURE 38- MICROPROCESSOR WRITE ACCESS TIMING ....................... 249 FIGURE 39- XCLK=37.056 MHZ INPUT TIMING ........................................... 251 FIGURE 40- EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED MODE................................................................................................... 252 FIGURE 41- EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL SIGNALING MODE .............................................................................. 253
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
FIGURE 42- EGRESS INTERFACE TIMING - CLOCK MASTER: FULL DS1 MODE................................................................................................... 254 FIGURE 43- EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : NXDS0 MODE................................................................................................... 255 FIGURE 44- INGRESS INTERFACE TIMING - CLOCK SLAVE MODES ....... 256 FIGURE 45- INGRESS INTERFACE TIMING - CLOCK MASTER MODES.... 257 FIGURE 46- TRANSMIT LINE INTERFACE TIMING ...................................... 258 FIGURE 47- LINE INTERFACE INPUT TIMING.............................................. 259 FIGURE 48- JTAG PORT INTERFACE TIMING DIAGRAM ............................ 261 FIGURE 49- 128 PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R SUFFIX):............................................................................................... 264 FIGURE 50- 128 PIN CHIP ARRAY BALL GRID ARRAY (N SUFFIX):........... 265
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 - NORMAL MODE REGISTER MEMORY MAP ............................. 38 - TYPICAL TRANSMIT TIMING CONFIGURATIONS ..................... 60 - TPSC INDIRECT MEMORY MAP............................................... 108 - SIGX INDIRECT MEMORY MAP ............................................... 138 - ACCESSING INPUTS IN TEST MODE 0 ................................... 194 - CONTROLLING OUTPUTS IN TEST MODE 0 .......................... 195 - BOUNDARY SCAN REGISTER ................................................. 198 - DEFAULT SETTINGS ................................................................. 207 - ESF FRAME FORMAT ............................................................... 208
TABLE 10 - SF FRAME FORMAT.................................................................. 209 TABLE 11 - PMON POLLING SEQUENCE ................................................... 209 TABLE 12 - PSEUDO RANDOM PATTERN GENERATION (PS BIT = 0)...... 221 TABLE 13 - REPETITIVE PATTERN GENERATION (PS BIT = 1)................. 222 TABLE 14 - BOUNDARY SCAN REGISTER ................................................. 237 TABLE 15 - TOCTL ABSOLUTE MAXIMUM RATINGS ................................. 243 TABLE 16 - TOCTL D.C. CHARACTERISTICS.............................................. 244 TABLE 17 - MICROPROCESSOR READ ACCESS (FIGURE 37) ................ 246 TABLE 18 - MICROPROCESSOR WRITE ACCESS (FIGURE 38) ............... 248 TABLE 19 - XCLK=37.056 MHZ INPUT (FIGURE 39)................................... 251 TABLE 20 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED MODE (FIGURE 40) ............................................................................. 252 TABLE 21 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL SIGNALING (FIGURE 41) .................................................................... 253
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xiv
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
TABLE 22 - EGRESS INTERFACE TIMING - CLOCK MASTER: FULL DS1 FIGURE 42).......................................................................................... 254 TABLE 23 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : NXDS0 MODE (FIGURE 43) ............................................................................. 255 TABLE 24 - INGRESS INTERFACE TIMING - CLOCK SLAVE MODES (FIGURE 44)......................................................................................... 256 TABLE 25 - INGRESS INTERFACE TIMING - CLOCK MASTER MODES (FIGURE 45)......................................................................................... 257 TABLE 26 - TRANSMIT LINE INTERFACE TIMING (FIGURE 46) ................ 258 TABLE 27 - RECEIVE LINE INTERFACE TIMING (FIGURE 47)................... 259 TABLE 28 - JTAG PORT INTERFACE TIMING (FIGURE 48) ........................ 260 TABLE 29 - TOCTL ORDERING INFORMATION .......................................... 263 TABLE 30 - TOCTL THERMAL INFORMATION............................................. 263
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
xv
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
1
FEATURES * * * Integrates eight T1 framers in a single device for terminating duplex DS-1 signals. Supports SF and ESF format DS-1 signals. Supports transfer of PCM data to/from 1.544 MHz system-side devices. Also supports a fractional T1 system interface with independent ingress/egress NxDS0 rates. Supports a 2.048 MHz system-side interface without external clock gapping. Provides jitter attenuation in the receive and transmit directions. Provides per-DS0 line loopback and per link diagnostic and line loopbacks. Provides an integral pattern generator/detector that may be programmed to generate and detect common pseudo-random or repetitive sequences. The programmed sequence may be inserted/detected in the entire DS-1 frame, or on an NxDS0 basis, in both the ingress and egress directions. May be configured to transmit or detect in only the 7 most significant bits of selected channels, in order to support fractional T1 loopback codes in an N x 56kbps fractional T1 setup. Each framer possesses its own independent pattern generator/detector, and each detector counts pattern errors using a 32-bit saturating error counter. Provides robbed bit signaling extraction and insertion on a per-DS0 basis. Provides programmable idle code substitution, data and sign inversion, and digital milliwatt code insertion on a per-DS0 basis. Software compatible with the PM4341A T1XC Single T1 Transceiver and the PM4344 TQUAD Quad T1 Framer. Seamless interface to the PM8313 D3MX single chip M13 multiplex and to the PM4314 QDSX Quad Line Interface. Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring. Low power 3.3V CMOS technology with 5V tolerant inputs. Supports standard 5 signal P1149.1 JTAG boundary scan.
* * *
* * * * * * *
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1
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
*
Available in a 14 mm by 20 mm 128 pin Plastic Quad Flat Pack (PQFP) or an 11mm by 11mm 128 pin Chip Array Ball Grid Array (CABGA) package.
Each one of eight receiver sections: * * * * * * Accepts gapped data streams to support higher rate demultiplexing. Provides Red, Yellow, and AIS alarms integration. Provides programmable in-band loopback code detection. Indicates signaling state change, and 2 superframes of signaling debounce on a per-DS0 basis. Provides an HDLC interface with 128 bytes of buffering for terminating the facility data link. Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line. Provides an optional elastic store which may be used to time the ingress streams to a common clock and frame alignment, or to facilitate per-DS0 loopbacks.
*
Each one of eight transmitter sections: * May be timed to its associated receive clock (loop timing) or may derive its timing from a common egress clock or a common transmit clock; the transmit line clock may be synthesized from an N*8kHz reference. Provides minimum ones density through Bell (bit 7), GTE or "jammed bit 8" zero code suppression on a per-DS0 basis.Provides a 128 byte buffer to allow insertion of the facility data link using the host interface. Supports transmission of the alarm indication signal (AIS) or the Yellow alarm signal in both SF and ESF formats. Provides a digital phase locked loop for generation of a low jitter transmit clock. Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter.
*
* * *
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2
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
2
APPLICATIONS * * * High density Internet T1 interfaces for multiplexers, switches, routers and digital modems. Frame Relay switches and access devices (FRADS) SONET/SDH Add Drop Multiplexers
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3
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
3
REFERENCES 1. American National Standard for Telecommunications - Digital Hierarchy Formats Specification, ANSI T1.107-1995 2. American National Standard for Telecommunications - Digital Hierarchy Layer 1 In-Service Digital Transmission Performance Monitoring, ANSI T1.231-1993 3. American National Standard for Telecommunications - Carrier to Customer Installation - DS-1 Metallic Interface Specification, ANSI T1.403-1995 4. American National Standard for Telecommunications - Integrated Services Digital Network (ISDN) Primary Rate- Customer Installation Metallic Interfaces Layer 1 Specification, ANSI T1.408-1990 5. Bell Communications Research - DS-1 Rate Digital Service Monitoring Unit Functional Specification, TA-TSY-000147, Issue 1, October, 1987. 6. Bell Communications Research - Alarm Indication Signal Requirements and Objectives, TR-TSY-000191 Issue 1, May 1986. 7. Bell Communications Research - Integrated Digital Loop Carrier Generic Requirements, Objectives, and Interface, TR-NWT-000303, Issue 2, December, 1992. 8. Bell Communications Research - Functional Criteria for the DS-1 Interface Connector, TR-TSY-000312, Issue 1, March, 1988. 9. Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, TR-TSY-000499, Issue 5, December, 1993. 10. AT&T - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, TR 54016, September, 1989. 11. AT&T, TR 62411 - Accunet T1.5 - "Service Description and Interface Specification" December, 1990.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
4
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
4
APPLICATION EXAMPLES Figure 1 - High Density Channelized Port Card
#1 of 11
T1 Channelized DS-3 Interface PM8313-RI D3MX PM4388-RI TOCTL PM4388-RI TOCTL PM4388-RI TOCTL PM4388-RI TOCTL
LIU
AND/OR
PM4314-RI QDSX PM4314-RI QDSX Channelized And/Or Unchannelized T1 Interfaces PM4314-RI QDSX PM4314-RI QDSX PM4388-RI TOCTL
Channelized /Unchannelized HDLC Processor(s) Packet Router Core or Packet Switch Core
#5 of 11
PM4388-RI TOCTL
#11 of 11
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5
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
5
BLOCK DIAGRAM
CTCLK* CECLK*
TRANSMITTER
CEFP* ECLK[1:8]/ EFP[1:8]/ ESIG[1:8] ED[1:8] EIF Egress Interface TPSC Per-DS0 Controller XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunk Conditioning I ti TOPS Timing Options TJAT Digital Jitter Attenuator TLCLK[1:8] TLD[1:8]
TDPR HDLC Transmitter PRGD Pattern Generator/ Detector
XIBC XBOC Bit Oriented Inband Loopback Code Code Generator Generator XCLK*
RECEIVER
CICLK* CIFP* ID[1:8] IIF Ingress Interface SIGX Signaling Extractor FRAM Framer/ ELST Elastic Store RAM Elastic Store ELST FRMR Elastic Framer: Store Frame Alignment, Alarm Extraction
ICLK[1:8]/ ISIG[1:8] IFP[1:8]
RPSC Per-DS0 Controller
RJAT Digital Jitter Attenuator
RLCLK[1:8 RLD[1:8]
A[10:0]* RDB* WRB* CSB* ALE* INTB* RSTB*
RBOC Bit Oriented Code Detector MPIF MicroProcessor Interface RDLC HDLC Receiver
ALMI Alarm Integrator PMON Performance Monitor Counters
IBCD Inband Loopback Code Detector
* These signals are shared between all eight framers. D[7:0]*
JTAG Test Access Port
TDO TDI TCLK TMS TRSTB
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6
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
6
DESCRIPTION The PM4388 Octal T1 Framer (TOCTL) is a feature-rich device for use primarily in systems carrying data (frame relay, Point to Point Protocol, or other protocols) over DS-1 facilities. Each of the framers and transmitters is independently software configurable, allowing feature selection without changes to external wiring. On the receive side, each of eight independent framers can be configured to frame to either of the common DS-1 signal formats: (SF, ESF) or to be bypassed (unframed mode). The TOCTL detects and indicates the presence of Yellow and AIS patterns and also integrates Yellow, Red, and AIS alarms. Performance monitoring with accumulation of CRC-6 errors, framing bit errors, out-of-frame events, and changes of frame alignment is provided. The TOCTL also detects the presence of in-band loopback codes, ESF bit oriented codes, and detects and terminates HDLC messages on the ESF data link. The HDLC messages are terminated in a 128 byte FIFO. An elastic store that optionally supports slip buffering and adaptation to backplane timing is provided, as is a signaling extractor that supports signaling debounce, signaling freezing and interrupt on signaling state change on a per-DS0 basis. The TOCTL also supports idle code substitution and detection, digital milliwatt code insertion, data extraction, trunk conditioning, data sign and magnitude inversion, and pattern generation or detection on a per-DS0 basis. On the transmit side, the TOCTL generates framing for SF or ESF DS-1 formats, or framing can be optionally disabled. The TOCTL supports signaling insertion, idle code substitution, data insertion, line loopback, data inversion, zero-code suppression, and pattern generation or detection on a per-DS0 basis. The TOCTL can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. The TOCTL provides a parallel microprocessor interface for controlling the operation of the TOCTL device. Serial PCM interfaces allow 1.544 Mbit/s ingress/egress system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. It should be noted that the TOCTL device operates on unipolar data only: B8ZS substitution and line code violation monitoring, if required, must be processed by the T1 LIU.
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7
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
7
PIN DIAGRAM The TOCTL is packaged in a 128-pin plastic QFP package having a body size of 14mm by 20mm and a pin pitch of 0.5mm.
P IN 128
P IN 103
P IN 1
R LD [1 ] R LC L K [1 ] R LD [2 ] R LC L K [2 ] R LD [3 ] R LC L K [3 ] R LD [4 ] R LC L K [4 ] T L D [1 ] T L C LK [1] T L D [2 ] T L C LK [2] T L D [3 ] T L C LK [3] T L D [4 ] T L C LK [4] B IA S P H A [0 ] P L A [0 ] P H D[0] P L D[0] T L D [5 ] T L C LK [5] T L D [6 ] T L C LK [6] T L D [7 ] T L C LK [7] T L D [8 ] T L C LK [8] P L A [1 ] R LD [5 ] R LC L K [5 ] R LD [6 ] R LC L K [6 ] R LD [7 ] R LC L K [7 ] R LD [8 ] R LC L K [8 ]
P IN 102
Index P in
E FP /E CL K /E SIG [6 ] E D [7 ] E FP /E CL K /E SIG [7 ] E D [8 ] E FP /E CL K /E SIG [8 ] ID [1 ] IC L K /IS IG [1] IF P [1 ] ID [2 ] P L A [4 ] P H A [3 ] IC L K /IS IG [2] IF P [2 ] ID [3 ] IC L K /IS IG [3] IF P [3 ] P L D[2] P H D[2] ID [4 ] IC L K /IS IG [4] IF P [4 ] ID [5 ] IC L K /IS IG [5] IF P [5 ] ID [6 ] IC L K /IS IG [6] IF P [6 ] P L A [3 ] P H A [2 ] ID [7 ] IC L K /IS IG [7] IF P [7 ] ID [8 ] IC L K /IS IG [8] IF P [8 ] R DB W RB CSB
P M 4388 TO C TL Top V iew
P IN 38
P IN 65
P IN 39
P IN 64
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8
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
The TOCTL is also available in a 128 pin Chip Array Ball Grid Array (CABGA) package having a body size of 11mm by 11mm and a ball pitch of 0.8mm.
12
11
10 EFP/ ECLK/ ESIG[4] EFP/ ECLK/ ESIG[6] EFP/ ECLK/ ESIG[8] PHA[3]
9
8
7 EFP/ ECLK/ ESIG[1] ED[1] EFP/ ECLK/ ESIG[3] ED[4]
6
5
4
3
2
1
A
ED[7]
ED[6]
PLA[5]
ED[3] EFP/ ECLK/ ESIG[2] PHA[4] EFP/ ECLK/ ESIG[5]
PHD[3]
CICLK
CTCLK
TCK
RLD[1]
RLD[3]
A
B
ID[1]
ED[8]
ED[5] EFP/ ECLK/ ESIG[7] IFP[1]
XCLK/ VCLK
CIFP
CECLK
TMS
RLD[2]
RLD[4]
B
C
ID[2]
ICLK/ ISIG[1]
PLD[3]
CEFP
TDO
RLCLK[1] RLCLK[3] TLCLK[1]
C
D
ICLK/ ISIG[2] ICLK/ ISIG[3]
IFP[2]
ED[2]
TRSTB
TDI
RLCLK[2]
TLD[1]
TLCLK[2]
D
E
IFP[3]
ID[3]
PLA[4]
RLCLK[4]
TLD[2]
TLCLK[4]
TLD[4]
E
F
ID[4]
PHD[2]
PLD[2]
ID[5]
TLD[3]
TLCLK[3]
PLA[0]
PHA[0]
F
BOTTOM VIEW
G IFP[4] ICLK/ ISIG[4] ICLK/ ISIG[5] ID[6] ICLK/ ISIG[6] ICLK/ ISIG[7] BIAS TLD[5] PLD[0] PHD[0] G
H
IFP[5]
PLA[3]
TLCLK[8] TLCLK[6] TLCLK[5]
TLD[6]
H
J
IFP[6]
ID[7]
IFP[8]
A[9]
A[7]
PHA[1]
D[4]
INTB
RLD[5]
TLD[8]
TLD[7]
TLCLK[7]
J
K
PHA[2]
ID[8]
WRB
A[6]
A[3]
A[0]
D[5]
D[2]
RLCLK[7] RLCLK[6] RLCLK[5]
PLA[1]
K
L
IFP[7]
RDB
A[10]
A[4]
A[1]
ALE
PHD[1]
D[7]
D[0]
RLCLK[8]
RLD[7]
RLD[6]
L
M
ICLK/ ISIG[8]
CSB
A[8]
A[5]
A[2]
PLD[1]
PLA[2]
D[6]
D[3]
D[1]
RSTB
RLD[8]
M
12
11
10
9
8
7
6
5
4
3
2
1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
9
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
8
PIN DESCRIPTION Pin Name RLD[1] RLD[2] RLD[3] RLD[4] RLD[5] RLD[6] RLD[7] RLD[8] Type Input Pin No. -RI -NI 1 A2 3 B2 5 A1 7 B1 31 J4 33 L1 35 L2 37 M1 2 4 6 8 32 34 36 38 C3 D3 C2 E4 K2 K3 K4 L3 Function Receive Line Data (RLD[1:8]). RLD[1:8] contain the receive stream from each of the eight DS-1 line interface units, or from a higher order demultiplex interface. These inputs are sampled on the active edge of the corresponding RLCLK[1:8].
RLCLK[1] Input RLCLK[2] RLCLK[3] RLCLK[4] RLCLK[5] RLCLK[6] RLCLK[7] RLCLK[8]
Receive Line Clocks (RLCLK[1:8]). Each input is an externally recovered 1.544 MHz line clock that samples the RLD[x] inputs on its active edge. RLCLK[x] may be a gapped clock subject to the timing constraints in the AC Timing section of this datasheet.
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10
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin Name ICLK[1] ICLK[2] ICLK[3] ICLK[4] ICLK[5] ICLK[6] ICLK[7] ICLK[8]/
Type Output
Pin No. -RI -NI 96 C11 91 D12 88 E12 83 G11 80 H11 77 G9 72 H9 69 M12
Function Ingress Clocks (ICLK[1:8]). The Ingress Clocks are active when the external signaling interface is disabled. Each ingress clock is a smoothed (jitter attenuated) version of the associated receive line clock (RLCLK[x]). When the Clock Master: NxDS0 mode is active, ICLK[x] is a gapped version of the smoothed RLCLK[x]. When Clock Slave: ICLK Reference mode is active, ICLK[x] may optionally be the smoothed RLCLK[x], or the smoothed RLCLK[x] divided by 193. When Clock Master: Full DS1 mode is active, IFP[x] and ID[x] are updated on the active edge of ICLK[x]. When the Clock Master: NxDS0 mode is active, ID[x] is updated on the active edge of ICLK[x]. Ingress Signaling (ISIG[1:8]). When the Clock Slave: External Signaling mode is enabled, each ISIG[x] contains the extracted signaling bits for each channel in the frame, repeated for the entire superframe. Each channel's signaling bits are valid in bit locations 5,6,7,8 of the channel and are channel-aligned with the ID[x] data stream. ISIG[x] is updated on the active edge of the common ingress clock, CICLK.
ISIG[1] ISIG[2] ISIG[3] ISIG[4] ISIG[5] ISIG[6] ISIG[7] ISIG[8]
IFP[1] IFP[2] IFP[3] IFP[4] IFP[5] IFP[6] IFP[7] IFP[8]
Output
95 90 87 82 79 76 71 68
D9 D11 E11 G12 H12 J12 L12 J10
Ingress Frame Pulse (IFP[1:8]). The IFP[x] outputs are intended as timing references. IFP[x] indicates the frame alignment or the superframe alignment of the ingress stream, ID[x]. When Clock Master: Full DS1 mode is active, IFP[x] is updated on the active edge of the associated ICLK[x]. When Clock Master: NxDS0 mode is active, ICLK[x] is gapped during the pulse on IFP[x]. When the Clock Slave ingress modes are active, IFP[x] is updated on the active edge of CICLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
11
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin Name ID[1] ID[2] ID[3] ID[4] ID[5] ID[6] ID[7] ID[8]
Type Output
Pin No. -RI -NI 97 B12 94 C12 89 E10 84 F12 81 F9 78 G10 73 J11 70 K11
Function Ingress Data (ID[1:8]). Each ID[x] signal contains the recovered data stream which may have been passed through the elastic store. When the Clock Slave ingress modes are active, the ID[x] stream is aligned to the common ingress timing and is updated on the active edge of CICLK. When the Clock Master ingress modes are active, ID[x] is aligned to the receive line timing and is updated on the active edge of the associated ICLK[x].
CICLK
Input
120
A5
Common Ingress Clock (CICLK). CICLK is either a 1.544MHz or 2.048MHz clock with optional gapping for adaptation to non-uniform backplane data streams. CICLK is common to all eight framers. CIFP is sampled on the active edge of CICLK. When the Clock Slave ingress modes are active, ID[x], ISIG[x], and IFP[x] are updated on the active edge of CICLK. Common Ingress Frame Pulse (CIFP). When the elastic store is enabled (Clock Slave mode is active on the ingress side), CIFP is used to frame align the ingress data to the system frame alignment. CIFP is common to all eight framers. When frame alignment is required, a pulse at least 1 CICLK cycle wide must be provided on CIFP a maximum of once every frame (nominally 193 bit times or 256 bit times if the 2.048 MHz rate is selected). If ingress signaling alignment is required, ingress signaling alignment must be enabled, and a pulse at least 1 CICLK cycle wide must be provided on CIFP every 12 or 24 frame times. CIFP is sampled on the active edge of CICLK.
CIFP
Input
119
B5
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12
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin Name ED[1] ED[2] ED[3] ED[4] ED[5] ED[6] ED[7] ED[8] EFP[1] EFP[2] EFP[3] EFP[4] EFP[5] EFP[6] EFP[7] EFP[8]/
Type Input
Pin No. -RI -NI 115 B7 113 D6 111 A8 109 D7 105 B9 103 A11 101 A12 99 B11 114 112 110 106 104 102 100 98 A7 B8 C7 A10 D8 B10 C9 C10
Function Egress Data (ED[1:8]). The egress data streams to be transmitted are input on these pins. When the Clock Master: Full DS1 mode is active, ED[x] is sampled on the rising edge of TLCLK[x]. When the Clock Master: NxDS0 mode is active, ED[x] is sampled on the active edge of ECLK[x]. When the Clock Slave egress modes are active, ED[x] is sampled on the active edge of CECLK. Egress Frame Pulse (EFP[1:8]). When the Clock Master: Full DS1 or Clock Slave: EFP Enabled modes are active, the EFP[1:8] outputs indicate the frame alignment or the superframe alignment of each of the eight framers. When the Clock Master modes are active, EFP[x] is updated by the falling edge of the TLCLK[x]. When the Clock Slave egress modes are active, EFP[x] is updated on the active edge of CECLK. Egress Clock (ECLK[1:8]). When the Clock Master: NxDS0 mode is active, the ECLK[x] output is used to sample the associated egress data (ED[x]). ECLK[x] is a version of TLCLK[x] that is gapped during the framing bit position and optionally for between 1 and 23 DS0 channels in the associated ED[x] stream. ED[x] is sampled on the active edge of the associated ECLK[x]. Egress Signaling (ESIG[1:8]). When the Clock Slave: External Signaling mode is active, the ESIG[8:1] inputs contain the signaling bits for each channel in the transmit data frame, repeated for the entire superframe. Each channel's signaling bits are in bit locations 5,6,7,8 of the channel and are frame-aligned by the common egress frame pulse, CEFP . ESIG[x] is sampled on the active edge of CECLK.
I/O
ECLK[1] ECLK[2] ECLK[3] ECLK[4] ECLK[5] ECLK[6] ECLK[7] ECLK[8] ESIG[1] ESIG[2] ESIG[3] ESIG[4] ESIG[5] ESIG[6] ESIG[7] ESIG[8]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
13
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin Name CTCLK
Type Input
Pin No. -RI -NI 123 A4
Function Common Transmit Clock (CTCLK). This input signal is used to generate the TLCLK[x] clock signals. Depending on the configuration of the TOCTL, CTCLK may be a 12.352 MHz clock (so TLCLK[x] is generated by dividing CTCLK by 8), or a line rate clock (so TLCLK[x] is generated directly from CTCLK, or from CTCLK after jitter attenuation), or a multiple of 8kHz (Nx8khz, where 1*N*256) so long as CTCLK is jitter-free when divided down to 8kHz (in which case TLCLK is derived by the DJAT PLL using CTCLK as a reference). The TOCTL may be configured to ignore the CTCLK input and utilize CECLK or RLCLK[x] instead. RLCLK[x] is automatically substituted for CTCLK if line loopback is enabled.
CECLK
Input
122
B4
Common Egress Clock (CECLK). The common egress clock is used to time the egress interface when Clock Slave mode is enabled in the egress side. CECLK may be a 1.544MHz or 2.048MHz clock with optional gapping for adaptation from non-uniform system clocks. When the Clock Slave: EFP Enabled mode is active, CEFP and ED[x] are sampled on the active edge of CECLK, and EFP[x] is updated on the active edge of CECLK. When the Clock Slave: External Signaling mode is active, CEFP ESIG[x] and , ED[x] are sampled on the active edge of CECLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
14
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin Name CEFP
Type Input
Pin No. -RI -NI 121 C5
Function Common Egress Frame Pulse. CEFP may be used to frame align the framers to the system backplane. If frame alignment only is required, a pulse at least 1 CECLK cycle wide must be provided on CEFP every 193 bit times. If superframe alignment is required, transmit superframe alignment must be enabled, and a pulse at least 1 CECLK cycle wide must be provided on CEFP every 12 or 24 frame times, on the last F-bit of the multiframe. CEFP is sampled on the active edge of CECLK. CEFP has no effect in the Clock Master egress modes Transmit Line Clock (TLCLK[1:8]). The TLD[x] outputs are updated on the active edge of the associated TLCLK[x]. When the Clock Master: Full DS1 mode is active, ED[1:8] is sampled on the active edge of TLCLK[x] and EFP[1:8] is updated on the active edge of TLCLK[x]. TLCLK[x] is a 1.544 MHz clock that is adequately jitter and wander free in absolute terms to permit an acceptable DS-1 signal to be generated. Depending on the configuration of the TOCTL, TLCLK[x] may be derived from CTCLK, CECLK, or RLCLK[x], with or without jitter attenuation. Transmit Line Data (TLD[1:8]). TLD[1:8] contain the transmit stream for each of the eight DS-1 line interface units, or for the higher order multiplex interface. These outputs are updated on the active edge of the corresponding TLCLK[1:8].
TLCLK[1] TLCLK[2] TLCLK[3] TLCLK[4] TLCLK[5] TLCLK[6] TLCLK[7] TLCLK[8]
Output
10 12 14 16 23 25 27 29
C1 D1 F3 E2 H2 H3 J1 H4
TLD[1] TLD[2] TLD[3] TLD[4] TLD[5] TLD[6] TLD[7] TLD[8]
Output
9 11 13 15 22 24 26 28
D2 E3 F4 E1 G3 H1 J2 J3
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
15
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin Name XCLK/
Type Input
Pin No. -RI -NI 117 B6
Function Crystal Clock Input (XCLK). This signal provides timing for many portions of the TOCTL. XCLK is nominally a 37.056 MHz 32ppm, 50% duty cycle clock. Vector Clock (VCLK). The VCLK signal is used during TOCTL production test to verify internal functionality.
VCLK
INTB
Output
40
J5
Active low open-drain Interrupt signal (INTB). This signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source. Active low chip select (CSB). This signal must be low to enable TOCTL register accesses. CSB must go high at least once after a powerup to clear internal test modes. If CSB is not used, then it should be tied to an inverted version of RSTB, in which case, RDB and WRB determine register accesses. Bidirectional data bus (D[7:0]). This bus is used during TOCTL read and write accesses.
CSB
Input
65
M11
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] RDB
I/O
41 42 43 44 45 46 47 48 67
L4 M3 K5 M4 J6 K6 M5 L5 L11
Input
Active low read enable (RDB). This signal is pulsed low to enable a TOCTL register read access. The TOCTL drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are both low.
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16
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin Name WRB
Type Input
Pin No. -RI -NI 66 K10
Function Active low write strobe (WRB). This signal is pulsed low to enable a TOCTL register write access. The D[7:0] bus contents are clocked into the addressed normal mode register on the rising edge of WRB while CSB is low. Address latch enable (ALE). This signal latches the address bus contents, A[10:0], when low, allowing the TOCTL to be interfaced to a multiplexed address/data bus. When ALE is high, the address latches are transparent. ALE has an integral pull-up. Active low reset (RSTB). This signal is set low to asynchronously reset the TOCTL. RSTB is a Schmitt-trigger input with integral pull-up. When resetting the device, RSTB must be asserted for a minimum of 100 ns to ensure that the TOCTL is completely reset. Address bus (A[10:0]). This bus selects specific registers during TOCTL register accesses.
ALE
Input
53
L7
RSTB
Input
39
M2
A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] TCK
Input
54 55 56 57 58 59 60 61 62 63 64 126
K7 L8 M8 K8 L9 M9 K9 J8 M10 J9 L10 A3
Input
Test Clock (TCK).The test clock (TCK) signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. Test Mode Select (TMS). The test mode select (TMS) signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor.
TMS
Input
128
B3
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17
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin Name TDI
Type Input
Pin No. -RI -NI 127 D4
Function Test Input (TDI).The test data input (TDI) signal carries test data into the TOCTL via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor. Test Output (TDO).The test data output (TDO) signal carries test data out of the TOCTL via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is tristated except when scanning of data is in progress. Test Reset (TRSTB).The active low test reset (TRSTB) signal provides an asynchronous TOCTL test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull up resistor. The JTAG TAP controller must be initialized when the TOCTL is powered up. If the JTAG port is not used TRSTB must be connected to the RSTB input or grounded.
TDO
Tristate
124
C4
TRSTB
Input
125
D5
BIAS
Input
17
G4
+5V Bias (BIAS). The BIAS input is used to implement 5V tolerance on the inputs. BIAS must be connected to a well decoupled +5V rail if 5V tolerant inputs are required. If 5V tolerant inputs are not required, BIAS must be connected to a well-decoupled 3.3V DC supply together with the power pins PHA[3:0] and PHD[3:0]. Pad ring power pins (PHA[4:0]). These pins must be connected to a common, well decoupled +3.3V DC supply together with the core power pins PHD3:0] . Core power pins (PHD[3:0]). These pins must be connected to a common, well decoupled +3.3V DC supply together with the pad ring power pins PHA[4:0].
PHA[0] PHA[1] PHA[2] PHA[3] PHA[4] PHD[0] PHD[1] PHD[2] PHD[3]
Power
18 49 74 92 107 20 51 85 116
F1 J7 K12 D10 C8 G1 L6 F11 A6
Power
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18
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin Name PLA[0] PLA[1] PLA[2] PLA[3] PLA[4] PLA[5] PLD[0] PLD[1] PLD[2] PLD[3]
Type Ground
Pin No. -RI -NI 19 F2 30 K1 50 M6 75 H10 93 E9 108 A9 21 52 86 118 G2 M7 F10 C6
Function Pad ring ground pins (PLA[5:0]). These pins must be connected to a common ground together with the core ground pins PLD[3:0].
Ground
Core ground pins (PLD[3:0]). These pins must be connected to a common ground together with the pad ring ground pins PLA[5:0].
Notes on Pin Description: 1. The PLA[5:0] and PLD[3:0] ground pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the device. The PHA[4:0] and PHD[3:0] power pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the device. These power supply connections must all be utilized and must all connect to a common +3.3 V or ground rail, as appropriate. 2. During power-up, and power-down the voltage on the BIAS pin must be kept equal to or greater than the voltage on the PHA[4:0] and PHD[3:0] pins, to avoid damage to the device. 3. Inputs RSTB, TMS, TDI, and ALE have integral pull-up resistors. 4. All outputs have 2 mA drive capability except for the D[7:0] bidirectionals and the TLCLK[8:1], ECLK[8:1], and ICLK[8:1] clock outputs which have 3 mA drive capability. 5. All inputs and bidirectionals present minimum capacitive loading. 6. Certain inputs are described as being sampled by the "active edge" of a particular clock. These inputs may be enabled to be sampled on either the rising edge or the falling edge of that clock, depending on the software configuration of the device.
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19
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
9 9.1
FUNCTIONAL DESCRIPTION Framer (FRMR) The framing function is provided by the FRMR block. This block searches for the framing bit position in the ingress stream. It works in conjunction with the FRAM block to search for the framing bit pattern in the standard superframe (SF), or extended superframe (ESF) framing formats. When searching for frame, the FRMR simultaneously examines each of the 193 (SF) or each of the 772 (ESF) framing bit candidates. The FRAM block is addressed and controlled by the FRMR while frame synchronization is acquired. The time required to acquire frame alignment to an error-free ingress stream, containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0), is dependent upon the framing format. For SF format, the FRMR block will determine frame alignment within 4.4ms 99 times out of 100. For ESF format, the FRMR will determine frame alignment within 15 ms 99 times out of 100. Once the FRMR has found frame, the ingress data is continuously monitored for framing bit errors, bit error events (a framing bit error in SF or a CRC-6 error in ESF), and severely errored framing events. The FRMR also detects out-of-frame, based on a selectable ratio of framing bit errors. The FRMR can also be disabled to allow reception of unframed data. While the FRMR is disabled, control of the FRAM block is relinquished for use as the elastic store.
9.2
Framer/Slip Buffer RAM (FRAM) The Framer/Slip Buffer RAM function is provided by the Framer RAM (FRAM) block. The FRAM is used to store up to 4 frames of data while the FRMR is acquiring frame and up to 2 frames of data during normal operation (i.e. when accessed by Elastic Store). The FRAM is shared between the Elastic Store (ELST) and the FRMR: when frame synchronization is lost, the FRMR takes control of the FRAM and uses it to find frame; when frame synchronization is determined, the FRMR relinquishes control of FRAM to ELST which buffers the incoming PCM data.
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20
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
9.3
Inband Loopback Code Detector (IBCD) The Inband Loopback Code Detection function is provided by the IBCD block. This block detects the presence of either of two programmable INBAND LOOPBACK ACTIVATE and DEACTIVATE code sequences in either framed or unframed data streams. The inband code sequences are expected to be overwritten by the framing bit in framed data streams. Each INBAND LOOPBACK code sequence is defined as the repetition of the programmed code in the ingress stream for at least 5.1 seconds. The code sequence detection and timing is compatible with the specifications defined in T1.403, TA-TSY-000312, and TR-TSY-000303. LOOPBACK ACTIVATE and DEACTIVATE code indication is provided through internal register bits. An interrupt is generated to indicate when either code status has changed. If inband code detection is not desired, the IBCD_IDLE bit may be set in the Receive Line Options register, allowing the IBCD to be used to detect the DS1 idle code in the receive stream. Setting the IBCD_IDLE bit gaps the data to the IBCD block during the frame bit so that the IBCD searches for the programmed pattern in the payload.
9.4
Performance Monitor Counters (PMON) The Performance Monitor Counters function is provided by the PMON block. The block accumulates CRC error events, Frame Synchronization bit error events, out-of-frame events, and Change of Frame Alignment (COFA) events with saturating counters over consecutive intervals as defined by the time between writes of the Revision/Chip ID/Global PMON update register (00CH), or every second via the AUTOUPDATE feature in the Receive Line Options register, or by writing to any of the PMON holding registers. The PMON uses a 12-bit counter for Bit Error Events (CRC-6 failures in ESF or framing bit errors in SF), a 9-bit counter for framing bit errors, a 5-bit counter for OOF events, and a 3-bit counter for Change of Frame Alignment events. When an update is initiated by any means, the PMON in each framer transfers the counter values into holding registers and resets the counters to begin accumulating events for the interval. The counters are reset in such a manner that error events occurring during the reset are not missed. The holding register addresses are contiguous to facilitate polling operations.
9.5
Bit Oriented Code Detector (RBOC) The Bit Oriented Code detection function is provided by the RBOC block. This block detects the presence of 63 of the possible 64 bit oriented codes transmitted in the Facility Data Link channel in ESF framing format, as defined in
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21
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
ANSI T1.403 and in TR-TSY-000194. The 64 code (111111) is similar to the HDLC flag sequence and is used by the RBOC to indicate no valid code received. Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated at least 10 times. The RBOC can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the control register. Valid BOC are indicated through an internal status register. The BOC bits are set to all ones (111111) if no valid code has been detected. An interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones). 9.6 RDLC Facility Data Link Receiver The RDLC is a microprocessor peripheral used to receive HDLC frames on the 4kHz ESF facility data link. The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS). In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching. Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun. The Status Register contains bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes.
th
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22
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
9.7
Alarm Integrator (ALMI) The Alarm Integration function is provided by the ALMI block. This block detects the presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, or ESF formats. The alarm detection and integration is compatible with the specifications defined in ANSI T1.403 and TR-TSY-000191. The ALMI block declares the presence of Yellow alarm when the Yellow pattern has been received for 425 ms ( 50 ms); the Yellow alarm is removed when the Yellow pattern has been absent for 425 ms ( 50 ms). The presence of Red alarm is declared when an out-of-frame condition has been present for 2.55 sec ( 40 ms); the Red alarm is removed when the out-of-frame condition has been absent for 16.6 sec ( 500 ms). The presence of AIS alarm is declared when an out-of-frame condition and all-ones in the PCM data stream have been present for 1.5 sec (100 ms); the AIS alarm is removed when the AIS condition has been absent for 16.8 sec (500 ms). CFA alarm detection algorithms operate in the presence of a 10-3 bit error rate. The ALMI also indicates the presence or absence of the Yellow, Red, and AIS alarm signal conditions over 40 ms, 40 ms, and 60 ms intervals, respectively, allowing an external microprocessor to integrate the alarm conditions via software with any user-specific algorithms. Alarm indication is provided through internal register bits.
9.8
Elastic Store (ELST) The Elastic Store (ELST) synchronizes ingress frames to the common ingress clock and frame pulse (CICLK, CIFP) in the Clock Slave ingress modes. The frame data is buffered in a two frame circular data buffer. Input data is written to the buffer using a write pointer and output data is read from the buffer using a read pointer. The elastic store can be bypassed to eliminate the 2 frame delay. In this configuration (the Clock Master ingress modes), the elastic store is used to synchronize the ingress frames to the transmit line clock (TLCLK[x]) so that perDS0 loopbacks may be enabled. Per-DS0 loopbacks are only available when the elastic store is bypassed, or when CECLK and CICLK are tied together and CEFP and CIFP are tied together, and the CICLKRISE and CECLKFALL register bits are either both logic 1 or both logic 0. CICLKRISE and CECLKFALL are found in registers 3 and 4 of each octant, respectively.
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23
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
When the elastic store is being used, if the average frequency of the incoming data is greater than the average frequency of the backplane clock, the write pointer will catch up to the read pointer and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The subsequent ingress frame is deleted. If the average frequency of the incoming data is less than the average frequency of the backplane clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The previous ingress frame is repeated. A slip operation is always performed on a frame boundary. For payload conditioning, the ELST inserts a programmable idle code into all channels when the FRMR is out of frame synchronization. If the data is required to pass through the TOCTL unchanged during an out-of-frame condition, then the elastic store may be bypassed. 9.9 Signaling Extractor (SIGX) The Signaling Extraction (SIGX) block provides signaling bit extraction from the ingress stream for ESF, and SF framing formats. When the external signaling interface is enabled, the SIGX serializes the bits into a serial stream aligned to the synchronized outgoing data stream. The signaling data stream contains the A,B,C,D bits in the lower 4 channel bit locations (bits 5,6,7,8) in ESF framing format. In SF format, the A and B bits are repeated in locations C and D (i.e. the signaling stream contains the bits ABAB for each channel). The SIGX also provides user control over signaling freezing and provides control over signaling bit fixing and signaling debounce on a per-DS0 basis. The block contains three superframes worth of signal buffering to ensure that there is a greater than 95% probability that the signaling bits are frozen in the correct state for a 50% ones density out-of-frame condition, as specified in TR-TSY-000170 and BELL PUB 43801. With signaling debounce enabled, the per-DS0 signaling state must be in the same state for 2 superframes before appearing on the serial output stream. The SIGX indicates the occurrence of a change of signaling state for each DS0 via an interrupt and by a change of signaling state bit for each DS0. 9.10 Receive Per-DS0 Serial Controller (RPSC) The RPSC allows data and signaling trunk conditioning to be applied on the receive DS-1 stream on a per-DS0 basis. It also allows per-DS0 control of data inversion, the extraction of clock and data on ICLK[x] and ID[x] (when the Clock
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24
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Master: NxDS0 mode is active), and the detection or generation of pseudorandom or repetitive patterns. The RPSC operates on the data after its passage through ELST, so that data and signaling conditioning may overwrite the ELST trouble code. 9.11 Ingress Interface (IIF) The Ingress Interface allows ingress data to be presented to a system using one of four possible modes as selected by the IMODE[1:0] bits in the Ingress Interface Options Register (Register 001H, 081H, 101H, 181H, 201H, 281H, 301H, 381H): Clock Master: Full DS1, Clock Master : NxDS0, Clock Slave : ICLK Reference, or Clock Slave: External Signaling. Figure 2 - Clock Master: Full DS1
FRAM Framer/ Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction
ID[1:8] IFP[1:8] ID[x], IFP[x] Timed to ICLK[x] ICLK[1:8] IIF Ingress Interface
RJAT Digital Jitter Attenuator
RLCLK[1:8] RLD[1:8]
RECEIVER
In Clock Master: Full DS1 mode, the elastic store is bypassed and the ingress clock (ICLK[x]) is a jitter attenuated version of the 1.544 MHz receive line clock (RLCLK[x]). ICLK[x] is pulsed for each bit in the 193 bit frame. The ingress data appears on ID[x] and the ingress frame alignment is indicated by IFP[x]. In this mode, data passes through the TOCTL unchanged during out-of-frame conditions, similar to an offline framer system. When the TOCTL is the clock master in the ingress direction, then the elastic store is used to buffer between the ingress and egress clocks to facilitate per-DS0 loopback.
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25
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 3
- Clock Master: NxDS0
ID[1:8] IFP[1:8] ID[x], IFP[x] Timed to gapped ICLK[x] ICLK[1:8] IIF Ingress Interface
FRAM Framer/ Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction
RJAT Digital Jitter Attenuator
RLCLK[1:8 RLD[1:8]
RECEIVER
In this mode, ICLK[x] is derived from RLCLK[x], and is gapped on a per DS0 basis so that a subset of the 24 channels in the T1 frame is extracted on ID[x]. Channel extraction is controlled by the RPSC block. The framing bit position is always gapped, so the number of ICLK[x] pulses is controllable from 0 to 192 pulses per frame on a per-DS0 basis. In this mode, data passes through the TOCTL unchanged during out-of-frame conditions. The parity functions are not usable in NxDS0 mode. When the TOCTL is the clock master in the ingress direction, then the elastic store is used to buffer between the ingress and egress clocks to facilitate per-DS0 loopback. Figure 4
CICLK CIFP ID[1:8] IFP[1:8] ID[x], IFP[x] Timed to CICLK[x] ICLK[1:8] IIF Ingress Interface
- Clock Slave: ICLK Reference
FRAM Framer/ Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction
ELST Elastic Store
RJAT Digital Jitter Attenuator
RLCLK[1:8] RLD[1:8]
RECEIVER
In this mode, the elastic store is enabled to permit CICLK to specify the ingressside timing. The ingress data on ID[x] is bit aligned to the 1.544 MHz common ingress clock (CICLK) and is frame aligned to the common ingress frame pulse (CIFP). CICLK can be enabled to be a 1.544 MHz clock or a 2.048 MHz clock. ICLK[x] can be enabled to be either a 1.544 MHz jitter attenuated version of
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26
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
RLCLK[x] or an 8 kHz version of RLCLK[x] (by dividing RLCLK[x] by 193). IFP[x] indicates either the frame or superframe alignment on ID[x]. Figure 5 - Clock Slave: External Signaling
CICLK CIFP ID[1:8] IFP[1:8] ID[x], ISIG[x], IFP[x] Timed to CICLK ISIG[1:8] IIF Ingress Interface
ELST Elastic Store
FRAM Framer/ Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction RJAT Digital Jitter Attenuator RLCLK[1:8 RLD[1:8]
RECEIVER
In this mode, the elastic store is enabled to permit CICLK to specify the ingressside timing. The ingress data on ID[x] and signaling ISIG[x] are bit aligned to the 1.544 MHz common ingress clock (CICLK) and are frame aligned to the common ingress frame pulse (CIFP). CICLK can be enabled to be a 1.544 MHz clock or a 2.048 MHz clock. ISIG[x] contains the robbed-bit signaling state (ABCD or ABAB) in the lower four bits of each channel. 9.12 Pattern Detector/Generator (PRGD) The Pattern Generator/Detector (PRGD) block is a software programmable test pattern generator, receiver, and analyzer. Patterns may be generated in either the transmit or receive directions, and detected in the opposite direction. Two types of ITU-T O.151 compliant test patterns are provided : pseudo-random and repetitive. The PRGD can be programmed to generate any pseudo-random pattern with length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can insert single bit errors or a bit error rate between 10-1 to 10-7. The PRGD can be programmed to check for the presence of the generated pseudo-random pattern. The PRGD can perform an auto synchronization to the expected pattern, and generate interrupts on detection and loss of the specified pattern. The PRGD can accumulate the total number of bits received and the total number of bit errors in two saturating 32-bit counters. The counters accumulate over an interval defined by writes to the Revision/Chip ID/Global
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27
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
PMON Update register (register 00CH), by writes to any PRGD accumulation register, or over a one-second interval timed to the receive line clock, via the AUTOUPDATE feature in the Receive Line Options register (000H, 080H, 100H, 180H, 200H, 280H, 300H, 380H). When an accumulation is forced by either method, then the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way that no events are missed. The data is then available in the holding registers until the next accumulation. In addition to the two counters, a record of the 32 bits received immediately prior to the accumulation is available. The PRGD may also be programmed to check for repetitive sequences. When configured to detect a pattern of length N bits, the PRGD will load N bits from the detected stream, and determine whether the received pattern repeats itself every N subsequent bits. Should it fail to find such a pattern, it will continue loading and checking until it finds a repetitive pattern. All the features (error counting, auto-synchronization, etc.) available for pseudo-random sequences are also available for repetitive sequences. Whenever a PRGD accumulation is forced, the PRGD stores a snapshot of the 32 bits received immediately prior to the accumulation. This snapshot may be examined in order to determine the exact nature of the repetitive pattern received by PRGD. 9.13 Basic Transmitter (XBAS) The Basic Transmitter (XBAS) block generates the 1.544 Mbit/s T1 data stream according to SF or ESF frame formats. A internal control stream, generated by the TPSC block, provides per-DS0 control of idle code substitution, data inversion , and zero code suppression. Three types of zero code suppression (GTE, Bell and "jammed bit 8") are supported and selected on a per-DS0 basis to provide minimum ones density control. An internal signaling control stream provides per-DS0 control of robbed bit signaling and selection of the signaling source. All channels can be forced into a trunk conditioning state (idle code substitution and signaling conditioning) by use of the Master Trunk Conditioning bit in the Configuration Register. The transmitter can be disabled for framing via the disable bit in the Transmit Functions Enable register. When transmitting ESF formatted data, the framing bit, datalink bit, or the CRC-6 bit from the egress stream can be by-passed to the output PCM stream. Finally, the transmitter can be by-passed completely to provide an unframed operating mode.
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28
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
9.14
Transmit Per-DS0 Serial Controller (TPSC) The Transmit Per-DS0 Serial Controller allows data and signaling trunk conditioning or idle code to be applied on the transmit DS-1 stream on a per-DS0 basis. It also allows per-DS0 control of zero code suppression, data inversion, DS0 loopback (from the ingress stream), channel insertion, and the detection or generation of pseudo-random or repetitive patterns. The TPSC interfaces directly to the XBAS block and provides serial streams for signaling control, idle code data and egress data control.
9.15
Signaling Aligner (SIGA) When enabled, the Signaling Aligner is positioned in the egress path between the egress interface and XBAS. Its purpose is to ensure that, if the signaling on ESIG[x] is changed in the middle of a superframe, the XBAS completes transmitting the A,B,C, and D bits for the current superframe before switching to the new values. This permits signaling integrity to be preserved independent of the superframe alignment of the XBAS or the signaling data source.
9.16
Inband Loopback Code Generator (XIBC) The Inband Loopback Code Generator function is provided by the XIBC block. This block generates a stream of inband loopback codes (IBC) to be inserted into a T1 data stream. The IBC stream consists of continuous repetitions of a specific code and can be either framed or unframed. When the XIBC is enabled to generate framed IBC, the framing bit overwrites the inband code pattern. The contents of the code and its length are programmable from 3 to 8 bits.
9.17
Bit Oriented Code Generator (XBOC) The Bit Oriented Code Generator function is provided by the XBOC block. This block transmits 63 of the possible 64 bit oriented codes in the Facility Data Link channel in ESF framing format, as defined in ANSI T1.403-1989. The 64th code (111111) is similar to the HDLC Flag sequence and is used in the XBOC to disable transmission of any bit oriented codes. Bit oriented codes are transmitted on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. The transmitted bit oriented codes have priority over any data transmitted on the FDL
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29
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
except for ESF Yellow Alarm. The code to be transmitted is programmed by writing the code register. 9.18 TDPR Facility Data Link Transmitter The Facility Data Link Transmitter (TDPR) provides a serial data link for the 4 kHz ESF facility data link. The TDPR is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRC-CCITT frame check sequence (FCS) may be appended, followed by flags. If the TDPR transmit data FIFO underflows, an abort sequence is automatically transmitted. When enabled, the TDPR continuously transmits the flag sequence (01111110) until data is ready to be transmitted. Data bytes to be transmitted are written into the Transmit Data Register. The TDPR performs a parallel-to-serial conversion of each data byte before transmitting it. The TDPR automatically begins transmission of data once at least one complete packet is written into its FIFO. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the next packet is available for transmission. The TDPR will also force transmission of the FIFO data once the FIFO depth has surpassed the programmable upper limit threshold. Transmission commences regardless of whether or not a packet has been completely written into the FIFO. The user must be careful to avoid overfilling the FIFO. Underruns can only occur if the packet length is greater than the programmed upper limit threshold because, in such a case, transmission will begin before a complete packet is stored in the FIFO. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data. Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO is full, or if the FIFO is overrun. If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences. Abort characters can be continuously transmitted at any time by setting a control bit. During packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit Data register before the previous byte has been
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30
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDRI interrupt. 9.19 Receive and Transmit Digital Jitter Attenuator (RJAT, TJAT) The Digital Jitter Attenuation function is provided by the DJAT blocks. Each framer in the TOCTL contains two separate jitter attenuators, one between the receive line data and the ingress interface (RJAT) and the other between the egress interface and the transmit line data (TJAT). Each DJAT block receives jittered data and stores the stream in a FIFO timed to the associated clock (either RLCLK[x] or CECLK). The jitter attenuated data emerges from the FIFO timed to the jitter attenuated clock. In the RJAT, the jitter attenuated clock (ICLK[x]) is referenced to RLCLK[x]. In the TJAT, the jitter attenuated clock TLCLK[x] may be referenced to either CTCLK, CECLK, or RLCLK[x]. Each jitter attenuator generates its output clock by adaptively dividing the 37.056 MHz XCLK signal according to the phase difference between the jitter attenuated clock and the reference clock. Jitter fluctuations in the phase of the reference clock are attenuated by the phase-locked loop within each DJAT so that the frequency of the jitter attenuated clock is equal to the average frequency of the reference. To best fit the jitter attenuation transfer function recommended by TR 62411, phase fluctuations with a jitter frequency above 6.6 Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies below 6.6 Hz are tracked by the jitter attenuated clock. The jitter attenuated clock (ICLK[x] for the RJAT and TLCLK[x] for the TJAT) is used to read data out of the FIFO. If the FIFO read pointer comes within one bit of the write pointer, DJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data. Jitter Characteristics Each DJAT Block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. It can accommodate up to 28 UIpp of input jitter at jitter frequencies above 6 Hz. For jitter frequencies below 6 Hz, more correctly called wander, the tolerance increases 20 dB per decade. In most applications the each DJAT Block will limit jitter tolerance at lower jitter frequencies only. For high frequency jitter, above 10 kHz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. For low frequency wander, below 10 Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The DJAT blocks meet the stringent low frequency jitter tolerance
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31
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
requirements of AT&T TR 62411 and thus allow compliance with this standard and the other less stringent jitter tolerance standards cited in the references. DJAT exhibits negligible jitter gain for jitter frequencies below 6.6 Hz, and attenuates jitter at frequencies above 6.6 Hz by 20 dB per decade. In most applications the DJAT Blocks will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through DJAT. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the generated residual jitter in cases where incoming jitter is insignificant. This generated residual jitter is directly related to the use of 24X (37.056 MHz) digital phase locked loop for transmit clock generation. DJAT meets the jitter transfer requirements of AT&T TR 62411. The block allows the implied jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met. Jitter Tolerance Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For DJAT, the input jitter tolerance is 29 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 354 Hz. It is 48 UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK divided by 24 and that of the input data clock.
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32
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 6 100 28 10 Jitter Amplitude, UIpp 1.0
- DJAT Jitter Tolerance
29
DJAT minimum tolerance
acceptable
unacceptable
0.2
0.1
0.01
1
4.9 10
100
0.3k
1k
10k
100k
Jitter Frequency, Hz
The accuracy of the XCLK frequency and that of the reference clock used to generate the jitter attenuated clock have an effect on the minimum jitter tolerance. Given that the DJAT PLL reference clock accuracy can be 200 Hz from 1.544 MHz, and that the XCLK input accuracy can be 100 ppm from 37.056 MHz, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK / 24 are shown in Figure 7. An XCLK input accuracy of 100 ppm is only acceptable if an accurate line rate reference is provided. If TJAT is left to free-run without a reference, or referenced to a derivative of XCLK, then XCLK accuracy must be 32 ppm.
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33
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 7
- DJAT Minimum Jitter Tolerance vs. XCLK Accuracy
40 36 35
DJAT Minimum Jitter Tolerance UI pp
34
30
29
Max frequency offset (PLL Ref to XCLK)
25 100 XCLK Accuracy
200 0
250 32
300
354 100
Hz ppm
Jitter Transfer The output jitter for jitter frequencies from 0 to 6.6 Hz is no more than 0.1 dB greater than the input jitter, excluding the 0.042 UI residual jitter. Jitter frequencies above 6.6 Hz are attenuated at a level of 6 dB per octave, as shown in Figure 8 below: Figure 8 0 -10 -20 Jitter Gain (dB) -30 -40 -50
62411 min DJAT response 62411 max 43802 max
- DJAT Jitter Transfer
1 6.6
10
100 1k Jitter Frequency, Hz
10k
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34
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Frequency Range In the non-attenuating mode, that is, when the FIFO is within one UI of overrunning or under running, the tracking range is 1.48 to 1.608 MHz. The guaranteed linear operating range for the jittered input clock is 1.544 MHz 200 Hz with worst case jitter (29 UIpp) and maximum XCLK frequency offset ( 100 ppm). The nominal range is 1.544 MHz 963 Hz with no jitter or XCLK frequency offset. 9.20 Timing Options (TOPS) The Timing Options block provides a means of selecting the source of the internal input clock to the TJAT block, the reference clock for the TJAT digital PLL, and the clock source used to derive the output TLCLK[x] signal. 9.21 Egress Interface (EIF) The Egress Interface allows egress data to be inserted into the transmit line using one of four possible modes, as selected by the EMODE[1:0] bits in the Egress Options Register: Clock Master: Full DS1, Clock Master: NxDS0, Clock Slave: EFP Enabled, and Clock Slave: External Signaling. Figure 9
TLCLK[1:8] CTCLK CECLK
- Clock Master: Full DS1
TRANSMITTER
ED[1:8] EFP[1:8] ED[x], EFP[x] Timed to TLCLK[x] XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunk Conditioning Line Coding RLCLK[1:8] TJAT Digital PLL TLCLK[1:8]
EIF Egress Interface
TLD[1:8]
In this mode, the transmit clock output (TLCLK[x]) "pulls" data from an upstream data source. The frame alignment is indicated to the upstream data source using EFP[x]. TLCLK[x] may be generated by the TJAT PLL, referenced to either CECLK, CTCLK, or RLCLK[x]. TLCLK[x] may also be derived directly from CTCLK or XCLK. The CEFP input is unused in this mode, and has no effect.
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35
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 10
CTCLK CECLK
- Clock Master: NxDS0
TRANSMITTER
RLCLK[1:8] ED[1:8] ECLK[1:8] ED[x] Timed to ECLK[x] EIF Egress Interface XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunki Conditioning I Line Coding TJAT Digital PLL TLCLK[1:8]
TLD[1:8]
This mode is identical to the full DS1 mode except that the frame alignment is not indicated to the upstream device. Instead, ECLK[x] is gapped on a per DS0 basis so that a subset of the 24 channels in the T1 frame is inserted on ED[x]. Channel insertion is controlled by the IDLE_DS0 bits in the TPSC block's Egress Control Bytes. The framing bit position is always gapped, so the number of ECLK[x] pulses is controllable from 0 to 192 pulses per frame on a per-DS0 basis. The parity functions should not be enabled in NxDS0 mode. The CEFP input is unused in this mode, and has no effect. Figure 11
CTCLK
- Clock Slave: EFP Enabled
TRANSMITTER
XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunki Conditioning I Line Coding TJAT Digital PLL TJAT FIFO
ED[1:8] EFP[1:8] CEFP CECLK Inputs Timed to CECLK
EIF Egress Interface
RLCLK[1:8] TLCLK[1:8]
TLD[1:8]
In this mode, the egress interface is clocked by the common egress clock (CECLK). The transmitter is either frame-aligned or superframe-aligned to the common egress frame pulse (CEFP). EFP[x] is configurable to indicate the frame alignment or the superframe alignment of ED[x]. CECLK can be enabled to be a 1.544 MHz clock or a 2.048 MHz clock.
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36
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 12
CTCLK
- Clock Slave: External Signaling
TRANSMITTER
XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunki Conditioning I Line Coding TJAT Digital PLL TJAT FIFO RLCLK[1:8 TLCLK[1:8
ED[1:8] ESIG[1:8] CEFP CECLK Inputs Timed to CECLK
EIF Egress Interface
TLD[1:8]
In this mode, the egress interface is clocked by the common egress clock (CECLK). The transmitter is either frame-aligned or superframe-aligned to the common egress frame pulse (CEFP). The ESIG[x] contain the robbed-bit signaling data to be inserted into TLD[x], with the four least significant bits of each channel on ESIG[x] representing the signaling state (ABCD or ABAB). EFP[x] is not available in this mode. 9.22 Microprocessor Interface (MPIF) The Microprocessor Interface allows the TOCTL to be configured, controlled and monitored via internal registers.
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37
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
10
REGISTER DESCRIPTION Table 1 - Normal Mode Register Memory Map
Address #1 000 001 002 003 004 005 006 007 008 009 00A #2 080 081 082 083 084 085 086 087 088 089 08A #3 100 101 102 103 104 105 106 107 108 109 10A #4 180 181 182 183 184 185 186 187 188 189 18A 00B 00C 00D 08D 10D 18D 20D 28D 30D 38D #5 200 201 202 203 204 205 206 207 208 209 20A #6 280 281 282 283 284 285 286 287 288 289 28A #7 300 301 302 303 304 305 306 307 308 309 30A #8 380 381 382 383 384 385 386 387 388 389 38A Receive Line Options Ingress Interface Options Backplane Parity Configuration and Status Receive Interface Configuration Transmit Interface Configuration Egress Interface Options Transmit Framing and Bypass Options Transmit Timing Options Interrupt Source #1 Interrupt Source #2 Diagnostics Master Test Revision/Chip ID/Global PMON Update Framer Reset Interrupt ID 20F 210 211 212 213 214217 218 219 21A 21B 21C 21D 28F 290 291 292 293 294297 298 299 29A 29B 29C 29D 30F 310 311 312 313 314317 318 319 31A 31B 31C 31D 38F 390 391 392 393 394397 398 399 39A 39B 39C 39D TJAT Interrupt Status TJAT Reference Clock Divisor (N1) Control TJAT Output Clock Divisor (N2) Control TJAT Configuration ELST Configuration ELST Interrupt Enable/Status Pattern Generator/Detector Positioning/Control RJAT Interrupt Status RJAT Reference Clock Divisor (N1) Control RJAT Output Clock Divisor (N2) Control RJAT Configuration Reserved Register
00E 00F 010 011 012 013 014017 018 019 01A 01B 01C 01D 08F 090 091 092 093 094097 098 099 09A 09B 09C 09D 10F 110 111 112 113 114117 118 119 11A 11B 11C 11D 18F 190 191 192 193 194197 198 199 19A 19B 19C 19D
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
01E 01F 020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038
09E 09F 0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8
11E 11F 120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138
19E 19F 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1AA 1AB 1AC 1AD 1AE 1AF 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8
21E 21F 220 221 222 223 224 225 226 227 228 229 22A 22B 22C 22D 22E 22F 230 231 232 233 234 235 236 237 238
29E 29F 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2AA 2AB 2AC 2AD 2AE 2AF 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
31E 31F 320 321 322 323 324 325 326 327 328 329 32A 32B 32C 32D 32E 32F 330 331 332 333 334 335 336 337 338
39E 39F 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 3A9 3AA 3AB 3AC 3AD 3AE 3AF 3B0 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8
ELST Trouble Code ELST Reserved FRMR Configuration FRMR Interrupt Enable FRMR Interrupt Status FRMR Reserved Reserved Reserved Reserved Clock Monitor Reserved Reserved RBOC Enable RBOC Code Status ALMI Configuration ALMI Interrupt Enable ALMI Interrupt Status ALMI Alarm Detection Status TPSC Configuration TPSC P Access Status TPSC Channel Indirect Address/Control TPSC Channel Indirect Data Buffer TDPR Configuration TDPR Upper Transmit Threshold TDPR Lower Transmit Threshold TDPR Interrupt Enable TDPR Interrupt Status/ UDR Clear
039 03A 03B 03C 03D 03E
0B9 0BA 0BB 0BC 0BD 0BE
139 13A 13B 13C 13D 13E
1B9 1BA 1BB 1BC 1BD 1BE
239 23A 23B 23C 23D 23E
2B9 2BA 2BB 2BC 2BD 2BE
339 33A 33B 33C 33D 33E
3B9 3BA 3BB 3BC 3BD 3BE
TDPR Transmit Data TDPR Reserved TDPR Reserved IBCD Configuration IBCD Interrupt Enable/Status IBCD Activate Code
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
03F 040 041
0BF 0C0 0C1
13F 140 141
1BF 1C0 1C1
23F 240 241
2BF 2C0 2C1
33F 340 341
3BF 3C0 3C1
IBCD Deactivate Code SIGX Configuration SIGX P Access Status/ Signaling State Change Channels 17-24
042
0C2
142
1C2
242
2C2
342
3C2
SIGX Channel Indirect Address/Control/ Signaling State Change Channels 9-16
043
0C3
143
1C3
243
2C3
343
3C3
SIGX Channel Indirect Data Buffer/ Signaling State Change Channels 1-8
044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D
0C4 0C5 0C6 0C7 0C8 0C9 0CA 0CB 0CC 0CD 0CE 0CF 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0DA 0DB 0DC 0DD
144 145 146 147 148 149 14A 14B 14C 14D 14E 14F 150 151 152 153 154 155 156 157 158 159 15A 15B 15C 15D
1C4 1C5 1C6 1C7 1C8 1C9 1CA 1CB 1CC 1CD 1CE 1CF 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1DA 1DB 1DC 1DD
244 245 246 247 248 249 24A 24B 24C 24D 24E 24F 250 251 252 253 254 255 256 257 258 259 25A 25B 25C 25D
2C4 2C5 2C6 2C7 2C8 2C9 2CA 2CB 2CC 2CD 2CE 2CF 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 2DA 2DB 2DC 2DD
344 345 346 347 348 349 34A 34B 34C 34D 34E 34F 350 351 352 353 354 355 356 357 358 359 35A 35B 35C 35D
3C4 3C5 3C6 3C7 3C8 3C9 3CA 3CB 3CC 3CD 3CE 3CF 3D0 3D1 3D2 3D3 3D4 3D5 3D6 3D7 3D8 3D9 3DA 3DB 3DC 3DD
XBAS Configuration XBAS Alarm Transmit XIBC Control XIBC Loopback Code PMON Reserved PMON Interrupt Enable/Status PMON BEE Count (LSB) PMON BEE Count (MSB) PMON FER Count (LSB) PMON FER Count (MSB) PMON OOF Count PMON COFA Count RPSC Configuration RPSC P Access Status RPSC Channel Indirect Address/Control RPSC Channel Indirect Data Buffer RDLC Configuration RDLC Interrupt Control RDLC Status RDLC Data RDLC Primary Address Match RDLC Secondary Address Match RDLC Reserved RDLC Reserved XBOC Reserved XBOC Code
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PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
05E 05F 060 061 062 063 064 065067 068 069 06A 06B 06C 06D 06E 06F 07007F
0DE 0DF 0E0 0E1 0E2 0E3 0E4 0E50E7 0E8 0E9 0EA 0EB 0EC 0ED 0EE 0EF 0F00FF
15E 15F 160 161 162 163 164 165167 168 169 16A 16B 16C 16D 16E 16F 17017F
1DE 1DF 1E0 1E1 1E2 1E3 1E4 1E51E7 1E8 1E9 1EA 1EB 1EC 1ED 1EE 1EF 1F01FF
25E 25F 260 261 262 263 264 265267 268 269 26A 26B 26C 26D 26E 26F 27027F
2DE 2DF 2E0 2E1 2E2 2E3 2E4 2E52E7 2E8 2E9 2EA 2EB 2EC 2ED 2EE 2EF 2F02FF
35E 35F 360 361 362 363 364 365367 368 369 36A 36B 36C 36D 36E 36F 37037F
3DE 3DF 3E0 3E1 3E2 3E3 3E4 3E53E7 3E8 3E9 3EA 3EB 3EC 3ED 3EE 3EF 3F03FF
Reserved Reserved PRGD Control PRGD Interrupt Enable/Status PRGD Length PRGD Tap PRGD Error Insertion PRGD Reserved
PRGD Pattern Insertion #1 PRGD Pattern Insertion #2 PRGD Pattern Insertion #3 PRGD Pattern Insertion #4 PRGD Pattern Detector #1 PRGD Pattern Detector #2 PRGD Pattern Detector #3 PRGD Pattern Detector #4 Reserved
400-7FF
Reserved for Test
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41
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
11
NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the TOCTL. Normal mode registers (as opposed to test mode registers) are selected when A[10] is low. Notes on Normal Mode Register Bits: 1. Although the register bit descriptions for the eight framers have been combined, each framer is completely independent of the others. 2. Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read. 3. All configuration bits that can be written into can also be read back. This allows the processor controlling the TOCTL to determine the programming state of the chip. 4. Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. 5. Writing into read-only normal mode register bit locations does not affect TOCTL operation unless otherwise noted.
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42
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 000H, 080H, 100H, 180H, 200H, 280H, 300H, 380H: Receive Line Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function FIFOBYP UNF IBCD_IDLE Reserved AUTOYELLOW AUTORED AUTOOOF AUTOUPDATE Default 0 0 0 0 0 0 0 0
These registers allow software to configure the receive functions of each framer. FIFOBYP: The FIFOBYP bit enables the receive line data to be bypassed around the RJAT FIFO to the ingress outputs. When jitter attenuation is not being used, the RJAT FIFO can be bypassed to reduce the delay through the receiver section by typically 24 bits. When FIFOBYP is set to logic 1, the RJAT FIFO is bypassed. When FIFOBYP is set to logic 0, the receive line data passes through the RJAT FIFO. UNF: The UNF bit allows the framer to operate with unframed DS-1 data. When UNF is set to logic 1, the FRMR is disabled and the recovered data passes through the receiver section of the framer without frame or channel alignment. While UNF is held at logic 1, the Alarm Integrator continues to operate and detects and integrates AIS alarm, the SIGX holds its signaling frozen, and the AUTO_OOF function, if enabled, will consider OOF to be declared. When UNF is set to logic 0, the framer operates normally, searching for frame alignment on the incoming data. IBCD_IDLE: Setting the IBCD_IDLE bit gaps the data to the IBCD block during the framing bit. This allows the IBCD to be used to detect the idle code in the receive
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43
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
DS1 stream. The IBCD must still be programmed to detect the desired pattern, and otherwise operates unchanged. Reserved Reserved for future use. AUTOYELLOW: When the AUTOYELLOW bit is set to logic 1, then whenever ALMI declares a Red alarm in the ingress direction, XBAS will transmit a Yellow alarm in the egress direction. When AUTOYELLOW is set to logic 0, XBAS will only transmit a Yellow alarm when the XYEL bit is set in the XBAS Alarm Transmit Register (reg. 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H). Note that the Red alarm from ALMI is not deasserted on detection of AIS. AUTORED: The AUTORED bit allows global trunk conditioning to be applied to the ingress data stream, ID[x], immediately upon declaration of Red carrier failure alarm. When AUTORED is set to logic 1, the data on ID[x] for each channel is replaced with the data contained in the data trunk conditioning registers within RPSC while Red CFA is declared. When AUTORED is set to logic 0, the ingress data is not automatically conditioned when Red CFA is declared. AUTOOOF: The AUTOOOF bit allows global trunk conditioning to be applied to the ingress data stream, ID[x], immediately upon declaration of out of frame (OOF). When AUTOOOF is set to logic 1, then while OOF is declared, the data on ID[x] for each channel is replaced with the data contained in the data trunk conditioning registers within RPSC. When AUTOOOF is set to logic 0, the ingress data is not automatically conditioned by RPSC when OOF is declared. However, if the ELST is not bypassed, then the ELST trouble code will still be inserted in channel data while OOF is declared. RPSC data and signaling trunk conditioning overwrites the ELST trouble code. AUTOUPDATE When AUTOUPDATE is logic 1, the PMON and PRGD registers in the appropriate framer are automatically updated once every 8000 receive frame periods, i.e. once a second, timed to the receive line. If the INTE bit is set in the PMON Interrupt/Enable register, then the PMON will interrupt the microprocessor as soon as the results are available in the PMON registers. The results will then be available for reading for the next second, until they are overwritten by the next update. The OVR bit in the PMON Interrupt/Enable register indicates such an overwrite by going to logic 1.
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44
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
When AUTOUPDATE is logic 1, the microprocessor can still initiate additional updates by writing to any of the PMON counter registers or to the Revision/Chip ID/Global PMON Update register (register 00CH), but care should be taken not to initiate a second update in a given PMON before the first is completed, which can lead to unpredictable results. Similarly, the XFERE bit in the PRGD Interrupt Enable/Status Register may be set, allowing the PRGD to interrupt the microprocessor when a PRGD update has been completed. PRGD and PMON perform updates in the same number of clock cycles, so only one of the two interrupts need be enabled. The OVR bit in the same register indicates that data has been overwritten without being read. As is the case for the PMON, additional updates of the PRGD may be initiated by the microprocessor via the Revision/Chip ID/Global PMON Update register, and care must be taken to avoid initiating an update while another update is in progress.
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45
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 001H, 081H, 101H, 181H, 201H, 281H, 301H, 381H: Ingress Interface Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function IMODE[1] IMODE[0] ICLKSEL CICLK2M Reserved ISFP ALTIFP IMTKC Default 1 1 0 0 0 0 0 0
These registers allow software to configure the ingress interface format of each framer. IMODE[1:0]: These bits configure the ingress interface as shown below: IMODE[1:0] 00 01 10 11 ICLKSEL: The ICLKSEL bit is active when the Clock Slave: ICLK Reference mode is enabled, and the ICLK[x] pin is used as a timing reference When ICLKSEL is a logic 1, ICLK[x] is a jitter attenuated version of the 1.544 MHz receive line clock, RLCLK[x]. When ICLKSEL is a logic 0, ICLK[x] is an 8 kHz timing reference that is generated by dividing the jitter attenuated version of RLCLK[x] by 193. Mode Clock Master: NxDS0 Clock Master: Full DS1 Clock Slave: ICLK Reference Clock Slave: External Signaling
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46
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
CICLK2M: The CICLK2M bit selects the 2.048 MHz backplane data rate. When CICLK2M is set to logic 1, the clock rate on the CICLK input is expected to be 2.048MHz and the data stream on ID[x] is output as 1 byte of "filler" followed by 3 bytes of channel data, repeated 8 times. When CICLK2M is set to logic 0, the backplane data rate and format is identical to T1 (i.e. 1.544MHz rate with 24 contiguous channel bytes followed by 1 framing bit). The 2.048 MHz backplane function is not available when the Clock Master modes are active, and CICLK2M MUST BE SET TO LOGIC 0 when these modes are enabled. The HSBPSEL bit in the Timing Options Register (007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H) must be set to logic 1 whenever CICLK2M is set to logic 1. Reserved Reserved for future use. ISFP: The ISFP bit selects the output signal seen on IFP[x]. When set to logic 1, the IFP[x] output pulses high during the first framing bit of the 12 frame SF or the 24 frame ESF. When ISFP is set to logic 0, the IFP[x] output pulses high during each framing bit (i.e. every 193 bits). ALTIFP: The ALTIFP bit suppresses every second output pulse on the backplane output IFP[x]. When ALTIFP is set to logic 1, the output signal on IFP[x] pulses every 386 bits, indicating every second framing bit (if the ISFP bit is logic 0); or the output signal on IFP[x] pulses every 24 or 48 frames (if the ISFP bit is logic 1). This latter setting (i.e. both ALTIFP and ISFP set to logic 1) is useful for converting SF formatted data to ESF formatted data between two TOCTL devices. When ALTIFP is set to logic 0, the output signal on IFP[x] pulses in accordance to the ISFP bit setting. IMTKC: The IMTKC bit allows global trunk conditioning to be applied to the received data and signaling streams, ID[x] and ISIG[x]. When IMTKC is set to logic 1, the data on ID[x] for each channel is replaced with the data contained in the data trunk conditioning registers within RPSC; similarly, the signaling data on ISIG[x] for each channel is replaced with the data contained in the signaling trunk conditioning registers. When IMTKC is set to logic 0, the data and signaling signals are modified on a per-DS0 basis in accordance with the control bits contained in the per-DS0 control registers within the RPSC.
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47
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 002H, 082H, 102H, 182H, 202H, 282H, 302H, 382H: Backplane Parity Configuration and Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W Type R/W R/W R R R/W Function EPTYP EPRTYE EDI ESIGI PTY_EXTD Unused IPTYP IPRTYE Default 0 0 X X 0 X 0 0
These registers provide control and status reporting of data integrity checking on the ingress and egress interfaces. A single parity bit in the F-bit position represents parity over the previous frame (including the undefined bit positions). If a 2.048 Mbit/s backplane rate is selected, the parity calculation is performed over all bit positions, including the undefined positions. Signaling parity is similarly calculated over all bit positions. Parity checking and generation is not supported when the NxDS0 mode is active. EPTYP: The egress parity type (EPTYP) bit sets even or odd parity in the egress streams. If EPTYP is a logic zero, then the expected parity value in the F-bit position of ED[x] and ESIG[x] is even, thus it is a one if the number of ones in the previous frame is odd. If EPTYP is a logic one, then the expected parity value in the F-bit position of ED[x] and ESIG[x] is odd, thus it is a one if the number of ones in the previous frame is even. EPRTYE: The EPRTYE bit enables transmit parity interrupts. When set a logic one, parity errors on inputs ED[x] and ESIG[x] are indicated by the EDI and ESIGI bits, respectively, and by the INTB output. When set to logic zero, parity errors are indicated by the EDI and ESIGI status bits but are not indicated on the INTB output.
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48
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
EDI: The EDI bit indicates if a parity error has been detected on the ED[x] input. This bit is cleared when this register is read. Odd or even parity is selected by the EPTYP bit. ESIGI: The ESIGI bit indicates if a parity error has been detected on the ESIG[x] input. This bit is cleared when this register is read. Odd or even parity is selected by the EPTYP bit. This bit is invalid when the external signaling mode is inactive. PTY_EXTD: The Parity Extend bit (PTY_EXTD) causes both ingress and egress parity to be calculated over the previous frame plus the previous parity bit, instead of only the previous frame. The intended use of this bit is when 1.544 MHz ingress/egress interfaces are selected, when the parity is ordinarily calculated over the previous 192 bits. Setting PTY_EXTD causes parity to be calculated over the previous 193 bits, including the previous parity bit, so that odd parity (if chosen) will be calculated over an odd number of bits, and thus may detect either stuck-at-one or stuck-at-zero conditions on the ID[x], ED[x], ISIG[x] and ESIG[x] connections. IPTYP: The ingress parity type (IPTYP) bit sets even or odd parity in the ingress streams. If IPTYP is a logic zero, then the parity value in the F-bit position of ID[x] and ISIG[x] is even, thus it is a one if the number of ones in the previous frame is odd. If IPTYP is a logic one, then the parity value in the F-bit position of ID[x] and ISIG[x] is odd, thus it is a one if the number of ones in the previous frame is even. IPTYP only has effect if IPRTYE is a logic one. IPRTYE: The IPRTYE bit enables ingress parity insertion. When set a logic one, parity is inserted into the F-bit position of the ID[x] and ISIG[x] streams. When set to logic zero, the F-bit passes through transparently.
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49
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 003H, 083H, 103H, 183H, 203H, 283H, 303H, 383H: Receive Interface Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type Function Unused Unused Unused Unused ICLKRISE RLCLKFALL CIFPFALL CICLKRISE Default X X X X 0 0 0 0
These registers select the active clock edges of the receive line and ingress interfaces. ICLKRISE: The ICLKRISE bit enables the ingress interface to be updated on the rising ICLK[x] edge. When ICLKRISE is set to logic 1, ID[x] and IFP[x] are updated on the rising ICLK[x] edge. When ICLKRISE is set to logic 0, ID[x] and IFP[x] are updated on the falling ICLK[x] edge. This register bit has no effect when the Clock Slave ingress modes are enabled. RLCLKFALL: The RLCLKFALL bit enables the receive line interface to be sampled on the falling RLCLK[x] edge. When RLCLKFALL is set to logic 1, RLD[x] is sampled on the falling RLCLK[x] edge. When RLCLKFALL is set to logic 0, RLD[x] is sampled on the rising RLCLK[x] edge. CIFPFALL: The CIFPFALL bit enables the common ingress frame pulse to be sampled on the falling CICLK edge. When CIFPFALL is set to logic 1, CIFP is sampled on the falling CICLK edge. When CIFPFALL is set to logic 0, CIFP is sampled on the rising CICLK edge. This bit must be set to the same value in all eight registers for proper operation.
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50
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
CICLKRISE: The CICLKRISE bit enables the ingress interface to be updated on the rising CICLK edge. When CICLKRISE is set to logic 1, ID[x], ISIG[x] and IFP[x] are updated on the rising CICLK edge. When CICLKRISE is set to logic 0, ID[x], ISIG[x] and IFP[x] are updated on the falling CICLK edge. This register bit has no effect when the Clock Master ingress modes are enabled.
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51
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 004H, 084H, 104H, 184H, 204H, 284H, 304H. 384H: Transmit Interface Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W R/W Function FIFOBYP TAISEN Unused Unused CECLKFALL EFPRISE ECLKFALL TLCLKRISE Default 0 0 X X 0 0 0 0
These registers select the active clock edges of the transmit line and egress interfaces. FIFOBYP: The FIFOBYP bit enables the egress data to be bypassed around the TJAT FIFO to the transmit line outputs. When jitter attenuation is not being used, the TJAT FIFO can be bypassed to reduce the delay through the transmitter section by typically 24 bits. When FIFOBYP is set to logic 1, the TJAT FIFO is bypassed. When FIFOBYP is set to logic 0, the egress data passes through the TJAT FIFO. The TJAT FIFO is always bypassed when the Clock Master egress modes are active, so the FIFOBYP bit should not be set while EMODE[1] is logic 0. TAISEN: The TAISEN bit enables the interface to generate an unframed all-ones AIS alarm on the TLD[x] pin. When TAISEN is set to logic 1, the unipolar TLD[x] output is forced to all-ones. When TAISEN is set to logic 0, the TLD[x] output operates normally. CECLKFALL : The CECLKFALL bit enables the egress interface to be sampled on the falling CECLK edge. When CECLKFALL is set to logic 1, ED[x], ESIG[x] and CEFP are sampled on the falling CECLK edge. When CECLKFALL is set to logic 0,
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52
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
ED[x], ESIG[x] and CEFP are sampled on the rising CECLK edge. This register bit has no effect when the Clock Master egress modes are selected. EFPRISE : The EFPRISE bit enables the egress frame pulse to be updated on the rising CECLK edge. When EFPRISE is set to logic 1, EFP[x] is updated on the rising CECLK edge. When EFPRISE is set to logic 0, EFP[x] is updated on the falling CECLK edge. This register bit is only active when Clock Slave: EFP Enabled mode is selected. ECLKFALL: The ECLKFALL bit enables the egress data to be sampled on the falling ECLK[x] edge. When ECLKFALL is set to logic 1, ED[x] is sampled on the falling ECLK[x] edge. When ECLKFALL is set to logic 0, ED[x] is sampled on the rising ECLK[x] edge. This register bit only active when Clock Master: NxDS0 mode is selected. TLCLKRISE: The TLCLKRISE bit enables the transmit line interface to be updated on the rising TLCLK[x] edge. When TLCLKRISE is set to logic 1, TLD[x] is updated on the rising TLCLK[x] edge. When TLCLKRISE is set to logic 0, TLD[x] is updated on the falling TLCLK[x] edge.
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53
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 005H, 085H, 105H, 185H, 205H, 285H, 305H, 385H: Egress Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W R/W Function EMODE[1] EMODE[0] Unused ABXXEN Unused CECLK2M CESFP ESFP Default 1 1 X 0 X 0 0 0
These registers allow software to configure the egress interface format of each framer. EMODE[1:0]: These bits configure the egress interface as shown below: EMODE[1:0] 00 01 10 11 Mode Clock Master: NxDS0 Clock Master: Full DS1 Clock Slave: EFP Enabled Clock Slave: External Signaling
When EMODE[1:0] = 0X, then the SYNC bit in the TJAT Configuration Register must be set to logic 0. ABXXEN: The ABXXEN bit selects the format of the ESIG[x] transmit signaling input signal. When ABXXEN is set to logic 1, ESIG[x] is expected to contain only the A and B signaling bits in the upper two bit positions of the lower nibble of each channel (i.e. ABXX), with the lower two bit positions being "Don't Cares". When ABXXEN is set to logic 0, ESIG[x] is expected to contain all four signaling bit in the lower nibble of each channel (i.e. ABCD), or it is expected to contain the A and B bits duplicated in the lower nibble (i.e. ABAB).
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54
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
CECLK2M: The CECLK2M bit selects the 2.048 MHz data rate and format of the egress data. When CECLK2M is set to logic 1, the clock rate on the CECLK input is expected to be 2.048 MHz and the data stream on ED[x] and ESIG[x] is expected to be formatted as 1 byte of "filler" followed by 3 bytes of channel data, repeated 8 times. The format is precisely laid out in the Functional Timing Diagrams section. When CECLK2M is set to logic 0, the egress data rate and format is identical to T1 (i.e. 1.544MHz rate with 24 contiguous channel bytes followed by 1 framing bit). When CECLK2M is set to logic 1, then the SYNC bit must be set to logic 0 in the TJAT Configuration register (Registers 01BH, 09BH, 11BH, 19BH, 21BH, 29BH, 31BH, 39BH.) and the HSBPSEL bit in the Timing Options Register (007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H) must be set to logic 1. PLLREF[1:0] should not be set to 01 in the Timing Options Register unless the TJAT divisors are specifically set to divide the 2048 kHz clock down to the line rate. CECLK2M MUST BE SET TO LOGIC 0 WHEN THE CLOCK MASTER MODES ARE SELECTED. CESFP: The CESFP bit selects the type of egress frame alignment signal, CEFP . When CESFP is set to logic 1, a pulse on CEFP indicates the LAST F-bit of the 12 frame SF or the 24 frame ESF (depending on the framing format selected in the XBAS ). When CESFP is set to logic 0, a pulse on CEFP indicates each framing bit. CESFP should be set to logic 1 when the external signaling mode is active to ensure that the egress superframe is aligned to the transmit line superframe. ESFP: The ESFP bit selects the output signal seen on EFP[x]. When set to logic 1, the EFP[x] output pulses high during the first framing bit of the 12 frame SF or the 24 frame ESF. When ESFP is set to logic 0, the EFP[x] output pulses high during each framing bit (i.e. every 193 bits).
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55
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 006H, 086H, 106H, 186H, 206H, 286H, 306H, 386H: Transmit Framing and Bypass Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W Type Function Unused Unused SIGAEN TXSIGA FDIS FBITBYP CRCBYP FDLBYP Default X X 0 0 0 0 0 0
These registers allow software to configure the bypass options of the transmitter. SIGAEN: When set to logic 1, the SIGA is inserted into the signaling bit data path before the XBAS. In this position, it will take a snapshot of the ESIG[x] stream during frame 1 of each superframe, and use those signaling values for the remainder of the superframe. This ensures signaling bit integrity in systems which do not specify or track the superframe alignment of XBAS. When SIGAEN is set to logic 1, the TXSIGA bit should also be set to logic 1. When SIGAEN is set to logic 0, the SIGA is removed from the circuit. TXSIGA: The TXSIGA bit is reserved, and should be set to logic 1 whenever SIGAEN is set to logic 1. FDIS: The FDIS bit allows the framing generation through the XBAS to be disabled and the egress data to pass through the XBAS unchanged. When FDIS is set to logic 1, XBAS is disabled from generating framing. When FDIS is set to logic 0, XBAS is enabled to generate and insert the framing into the transmit data.
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56
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
FBITBYP: The FBITBYP bit allows the frame synchronization bit in the egress stream, ED[x], to bypass the generation through the XBAS and be re-inserted into the appropriate position in the digital output stream. When FBITBYP is set to logic 1, the input frame synchronization bit is re-inserted into the output data stream. When FBITBYP is set to logic 0, the XBAS is allowed to generate the output frame synchronization bits. CRCBYP: The CRCBYP bit allows the framing bit corresponding to the CRC-6 bit position in the egress stream, ED[x], to bypass the generation through the XBAS and be re-inserted into the appropriate position in the digital output stream. When CRCBYP is set to logic 1, the input CRC-6 bit is re-inserted into the output data stream. When CRCBYP is set to logic 0, the XBAS is allowed to generate the output CRC-6 bits. FDLBYP: The FDLBYP bit allows the framing bit corresponding to the facility data link bit position in the egress data stream, ED[x], to bypass the generation through the XBAS and be re-inserted into the appropriate position in the digital output stream. When FDLBYP is set to logic 1, the input FDL bit is reinserted into the output data stream. When FDLBYP is set to logic 0, the XBAS is allowed to generate the output FDL bit.
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57
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H: Transmit Timing Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type R/W Function HSBPSEL Unused Unused OCLKSEL PLLREF1 PLLREF0 CTCLKSEL SMCLKO Default 0 X X 0 0 1 0 0
These registers allow software to configure the options of the transmit timing section. HSBPSEL: The HSBPSEL bit selects the source of the high-speed clock used in the ELST, SIGX, TPSC, and RPSC blocks. This allows the TOCTL to interface to higher rate backplanes (>2.048MHz, externally gapped, or 2.048MHz, internally gapped). Note, however, that the externally gapped instantaneous backplane clock frequency must not exceed 3.0MHz. When HSBPSEL is set to logic 1, the 37.056MHz XCLK input signal is divided by 2 and used as the high-speed clock to these blocks. XCLK must be driven with 37.056MHz. When HSBPSEL is set to logic 0, XCLK input signal is divided by 3 and used as the high-speed clock to these blocks. OCLKSEL: The OCLKSEL bit selects the source of the Transmit Digital Jitter Attenuator FIFO output clock signal. When OCLKSEL is set to logic 1, the TJAT FIFO output clock is driven with the CTCLK input clock, and the SYNC bit must be set to logic 0 in the TJAT Configuration Register (Registers 01BH, 09BH, 11BH, 19BH, 21BH, 29BH, 31BH, 39BH.) When OCLKSEL is set to logic 0, the TJAT FIFO output clock is driven with the internal smooth 1.544MHz clock selected by the CTCLKSEL and SMCLKO bits.
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58
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
PLLREF1, PLLREF0: The PLLREF[1:0] bits select the source of the Transmit Digital Jitter Attenuator phase locked loop reference signal as follows: PLLRE F1 0 PLLREF0 0 Source of PLL Reference Transmit clock used by XBAS when the Clock Slave egress modes are active. (either the 1.544MHz CECLK or the gapped clock derived from the 2.048MHz CECLK as selected by CECLK2M) CECLK input RLCLK[x] input CTCLK input
0 1 1
1 0 1
PLLREF[1:0] = 00 when the Clock Master egress modes are active is a reserved setting, and should not be used. CTCLKSEL,SMCLKO: The CTCLKSEL and SMCLKO bits select the source of the internal smooth 1.544MHz output clock signals. When CTCLKSEL and SMCLKO are set to logic 0, the internal 1.544MHz clock signal is driven by the smooth 1.544MHz clock source generated by TJAT. When CTCLKSEL is set to logic 0 and SMCLKO is set to logic 1, the internal 1.544MHz clock signal is driven by the CTCLK input signal divided by 8. When CTCLKSEL and SMCLKO are set to logic 1, the internal 1.544MHz clock signal is driven by the XCLK input signal divided by 24. The combination of CTCLKSEL set to logic 1 and SMCLKO set to logic 0 should not be used. The following table provides examples of the most common combinations of settings:
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59
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 2
- Typical Transmit Timing Configurations Bit Settings EMODE[1:0] = 11 HSBPSEL OCLKSEL =0 =0 =0 =0 Transmit Line Clock Options When PLLREF[1:0]=0X, TLCLK[x] is a jitterattenuated clock referenced to CECLK. This is the default. When PLLREF[1:0]=10, TLCLK[x] is a jitterattenuated clock referenced to RLCLK[x] When PLLREF[1:0]=11, TLCLK[x] is a jitterattenuated clock referenced to CTCLK[x]
Mode Description Default Setting Clock Slave: External Signaling Egress data timed to CECLK
CTCLKSEL =0
SMCLKO TJAT FIFO decouples the Egress interface CECLK2M (timed to CECLK) from the Transmit Line side (timed to jitter-attenuated TLCLK[x]). The TJAT PLL is used to generate TLCLK[x] from a reference clock. Clock Slave: EFP Enabled Egress data timed to CECLK
EMODE[1:0] = 10 HSBPSEL OCLKSEL =0 =0
When PLLREF[1:0]=0X, TLCLK[x] is a jitterattenuated clock referenced to CECLK. When PLLREF[1:0]=10, TLCLK[x] is a jitterattenuated clock referenced to RLCLK[x] When PLLREF[1:0]=11, TLCLK[x] is a jitterattenuated clock referenced to CTCLK
CTCLKSEL =0 TJAT FIFO decouples SMCLKO =0 the Egress interface (timed to CECLK) from CECLK2M =0 the Transmit Line side (timed to jitter-attenuated TLCLK[x]). The TJAT PLL is used to generate TLCLK[x] from a reference clock.
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60
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Mode Description Clock Slave with 2.048 MHz CECLK. Egress data timed to internally-gapped CECLK. TJAT FIFO decouples the Egress interface (timed to gapped CECLK) from the Transmit Line side (timed to jitter-attenuated TLCLK[x]). The TJAT PLL is used to generate TLCLK[x] from a reference clock.
Bit Settings EMODE[1:0] = 1X HSBPSEL OCLKSEL SMCLKO CECLK2M =1 =0 =0 =1
Transmit Line Clock Options When PLLREF[1:0]=00, TLCLK[x] is a jitterattenuated clock referenced to the internally gapped CECLK. See note 1. When PLLREF[1:0]=01, TLCLK[x] is a jitterattenuated clock referenced to CECLK. See note 2. When PLLREF[1:0]=10, TLCLK[x] is a jitterattenuated clock referenced to RLCLK[x] When PLLREF[1:0]=11, TLCLK[x] is a jitterattenuated clock referenced to CTCLK
CTCLKSEL =0
Clock Slave with Egress data timed to an externally gapped CECLK.
EMODE[1:0] = 1X HSBPSEL OCLKSEL =1 =0
CTCLKSEL =0 TJAT FIFO decouples the Egress interface SMCLKO =0 (timed to CECLK) from CECLK2M =0 the Transmit Line side (timed to jitter-attenuated TLCLK[x]). The TJAT PLL is used to generate TLCLK[x] from a reference clock.
When PLLREF[1:0]=0X, TLCLK[x] is a jitterattenuated clock referenced to CECLK. See note 2. When PLLREF[1:0]=10, TLCLK[x] is a jitterattenuated clock referenced to RLCLK[x] When PLLREF[1:0]=11, TLCLK[x] is a jitterattenuated clock referenced to CTCLK
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61
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Mode Description Clock Slave with Egress data timed to CECLK. CECLK may be a normal, internally gapped, or externally gapped clock as shown in previous examples. TJAT FIFO decouples the Egress interface (timed to CECLK) from the Transmit Line side (timed to TLCLK[x]). The TJAT PLL is unused. The SYNC, CENT, and LIMIT in the TJAT configuration must be set to logic 0. Clock Slave with Egress data timed to 1.544 MHz CECLK.
Bit Settings EMODE[1:0] = 1X HSBPSEL CECLK2M * See note 3 =* =* PLLREF[1:0] =XX
Transmit Line Clock Options When OCLKSEL = 1, TLCLK[x] = CTCLK. When OCLKSEL = 0, SMCLKO = 1, and CTCLKSEL =0, then TLCLK[x] = CTCLK/8. When OCLKSEL = 0, SMCLKO = 1, and CTCLKSEL =1, then TLCLK[x] = XCLK/24.
EMODE[1:0] = 1X HSBPSEL =0
FIFOBYP =1 TJAT FIFO is bypassed, OCLKSEL =X so that TLCLK[x] is directly driven by PLLREF[1:0] =XX CECLK. CTCLKSEL =0 SMCLKO CECLK2M =0 =0
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62
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Mode Description Clock Master: Full DS1 or NxDS0. Egress data is clocked by TLCLK[x], and TJAT FIFO is automatically bypassed. In NxDS0 mode, a gapped version of TLCLK[x] is provided on ECLK[x], which only clocks during the desired channels. The TJAT PLL is used to generate TLCLK[x] from a reference clock. Clock Master: Full DS1 or NxDS0 Egress data is clocked by TLCLK[x], and TJAT FIFO is automatically bypassed. In NxDS0 mode, a gapped version of TLCLK[x] is provided on ECLK[x], which only clocks during the desired channels. The TJAT PLL is unused. Notes:
Bit Settings EMODE[1:0] = 0X HSBPSEL FIFOBYP OCLKSEL SMCLKO CECLK2M =0 =0 =0 =0 =0
Transmit Line Clock Options The setting PLLREF[1:0]=00 is reserved and should not be used. When PLLREF[1:0]=01, TLCLK[x] is a jitterattenuated clock referenced to CECLK. When PLLREF[1:0]=10, TLCLK[x] is a jitterattenuated clock referenced to RLCLK[x] When PLLREF[1:0]=11, TLCLK[x] is a jitterattenuated clock referenced to CTCLK
CTCLKSEL =0
EMODE[1:0] = 0X HSBPSEL FIFOBYP CECLK2M =0 =0 =0
When OCLKSEL = 1, TLCLK[x] = CTCLK. When OCLKSEL = 0, SMCLKO = 1, and CTCLKSEL =0, then TLCLK[x] = CTCLK/8. When OCLKSEL = 0, SMCLKO = 1, and CTCLKSEL =1, then TLCLK[x] = XCLK/24.
PLLREF[1:0] =XX
1. When the internally gapped clock is used as the TJAT PLL reference, the TJAT divisors N1 and N2 should both be set to C0H.
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63
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
2. When an externally gapped clock is used as the TJAT PLL reference, the TJAT divisors N1 and N2 should be set so that the gapping vanishes. If the gapping introduces no 8kHz jitter, then a setting of C0H (representing division by 193) will be acceptable. 3. Whenever CECLK is used and is not a regular 1.544 MHz clock, HSBPSEL must be set to logic 1. If internal gapping of CECLK is desired, CECLK2M must be set as well. Figure 13 illustrates the various bit setting options, with the reset condition highlighted.
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64
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 13
- Transmit Timing Options
1
CECLK2M
0
TJAT FIFO
FIFO input data clock FIFO output data clock
0
FIFOBYP
TLCLK[x]
CECLK
1 0
EMODE[1]
1
2. 048MHz Clock gapper
OCLKSEL
CTCLK
00 01
PLLREF[1:0]
Smooth 1.544MHz
1
0
TJAT PLL
0 1
SMCLKO "Jitter-free" 1.544MHz
RLCLK[x]
10 11
24X reference clock for jitter attenuation
0
/8 XCLK
(37.056MHz)
1
CTCLKSEL
/3
"High-speed" clock for FRMR (=12.352MHz) 0
/2
1
HSBPSEL
"High-speed" clock for ELST, SIGX, TPSC & RPSC (*6x max backplane clockrate)
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65
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H: Interrupt Source #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PMON IBCD FRMR PRGD ELST RDLC RBOC ALMI Default 0 0 0 0 0 0 0 0
These registers allow software to determine the block which produced the interrupt on the INTB output pin. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
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66
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H: Interrupt Source #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R Type Function Unused PRTY TJAT RJAT Unused Unused TDPR SIGX Default X 0 0 0 X X 0 0
These registers allow software to determine the block which produced the interrupt on the INTB output pin. The PRTY bit indicates a pending parity error indication needs servicing in the Backplane Parity Configuration and Status register. Reading these registers does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
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67
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH: Master Diagnostics Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type Function Unused Unused Unused LINELB Reserved DDLB TXMFP TXDIS Default X X X 0 0 0 0 0
These registers allow software to enable the diagnostic mode of each framer. LINELB: The LINELB bit selects the line loopback mode, where the receive line clock and data, RLCLK[x] and RLD[x] (with or without jitter attenuation by the RJAT block) are internally connected to the transmit line interface, TLCLK[x] and TLD[x]. When LINELB is set to logic 1, the line loopback mode is enabled. When LINELB is set to logic 0, the line loopback mode is disabled. DDLB and LINELB are mutually incompatible and should not be simultaneously enabled. DDLB: The DDLB bit selects the diagnostic digital loopback mode, where the transmit line interface, TLCLK[x] and TD[x] are internally connected to the receive line interface, RLCLK[x] and RD[x]. When DDLB is set to logic 1, the diagnostic digital loopback mode is enabled. When DDLB is set to logic 0, the diagnostic digital loopback mode is disabled. DDLB and LINELB are mutually incompatible and should not be simultaneously enabled. TXMFP: The TXMFP bit introduces a mimic framing pattern in the digital output of the basic transmitter by forcing a copy of the current framing bit into bit location 1 of the frame, thereby creating a mimic pattern in the bit position immediately following the correct framing bit. When TXMFP is set to logic 1, the mimic
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68
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
framing pattern is generated. When TXMFP is set to logic 0, no mimic pattern is generated. TXDIS: The TXDIS bit provides a method of suppressing the output of the basic transmitter. When TXDIS is set to logic 1, the digital output of XBAS is disabled by forcing it to logic 0. When TXDIS is set to logic 0, the digital output of XBAS is not suppressed.
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69
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 00BH: TOCTL Master Test Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W W W R/W W R/W Function A_TM[9] A_TM[8] A_TM[7] PMCTST DBCTRL IOTST HIZDATA HIZIO Default X X X X 0 0 0 0
This register is used to select TOCTL test features. All bits, except for PMCTST and A_TM[9:7] are reset to zero by a hardware reset of the TOCTL; a software reset of the TOCTL does not affect the state of the bits in this register. Refer to the Test Features Description section for more information. A_TM[9]: The state of the A_TM[9] bit internally replaces the input address line A[9] when PMCTST is set. This allows for more efficient use of the PMC manufacturing test vectors. A_TM[8]: The state of the A_TM[8] bit internally replaces the input address line A[8] when PMCTST is set. This allows for more efficient use of the PMC manufacturing test vectors. A_TM[7]: The state of the A_TM[7] bit internally replaces the input address line A[7] when PMCTST is set. This allows for more efficient use of the PMC manufacturing test vectors. PMCTST: The PMCTST bit is used to configure the TOCTL for PMC's manufacturing tests. When PMCTST is set to logic 1, the TOCTL microprocessor port becomes the test access port used to run the PMC manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and is cleared by setting CSB to logic 1.
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70
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin. When the DBCTRL bit is set to logic one and either IOTST or PMCTST are logic one, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high (IOTST must be set to logic 1 since CSB high resets PMCTST) causes the TOCTL to drive the data bus and holding the CSB pin low tristates the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. IOTST: The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each block in the TOCTL for board level testing. When IOTST is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequently the device outputs (refer to the "Test Mode 0 Details" in the "Test Features" section). HIZIO,HIZDATA: The HIZIO and HIZDATA bits control the tristate modes of the TOCTL . While the HIZIO bit is a logic 1, all output pins of the TOCTL except the data bus are held in a high-impedance state. The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a highimpedance state which inhibits microprocessor read cycles.
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71
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 00CH: TOCTL Revision/Chip ID/Global PMON Update Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TYPE[2] TYPE[1] TYPE[0] ID[4] ID[3] ID[2] ID[1] ID[0] Default 0 1 0 0 0 0 0 0
The version identification bits, ID[4:0], are set to a fixed value representing the version number of the TOCTL. ID = 0H indicates Revision C. ID = 1H indicates Revision E. The chip identification bits, TYPE[2:0], are set to binary 010 representing the TOCTL. Writing to this register causes all performance monitor and pattern generator/detector counters to be updated simultaneously.
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72
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH: Framer Reset Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W Type Function Unused Unused Unused Unused Unused Unused Unused RESET Default X X X X X X X 0
The RESET bit implements a software reset. If the RESET bit is a logic 1, the individual framer is held in reset. This bit is not self-clearing; therefore, a logic 0 must be written to bring the framer out of reset. Holding the framer in a reset state effectively puts it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus deasserting the software reset.
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73
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 00EH: Interrupt ID Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 Default 0 0 0 0 0 0 0 0
These registers provide interrupt identification. The T1 framer(s) which caused the INTB output to transition low can be identified by reading this register. The INTx bit is high if the xth framer caused the interrupt. A procedure for identifying the source of an interrupt can be found in the Operations section. INT8, INT7, INT6, INT5, INT4, INT3, INT2, INT1: The INTx bit will be high if the xth T1 framer (the T1 framer corresponding to the input pin RLCLK[x]) causes the INTB pin to transition low.
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74
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH: Pattern Generator/Detector Positioning/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type Function Unused Unused Unused Nx56k_GEN Nx56k_DET RXPATGEN UNF_GEN UNF_DET Default X X X 0 0 0 0 0
This register modifies the way in which the PRGD is used by the TPSC and RPSC. More information on using PRGD is available in the Operations section. Nx56k_GEN: The Nx56k_GEN bit is active when the RPSC or TPSC is used to insert PRBS into selected DS0 channels of the transmit or receive stream. When the Nx56kbps generation bit is set to logic 1, the pattern is only inserted in the first 7 bits of the selected DS0 channels, and gapped on the eighth bit. This is particularly useful when using the jammed-bit-8 zero code suppression in the transmit direction, for instance when sending a Nx56kbps fractional T1 loopback sequence. This bit has no effect when UNF_GEN is set to logic 1. Nx56k_DET: The Nx56k_DET bit is active when the RPSC or TPSC is used to detect PRBS in selected DS0 channels of the transmit or receive stream. When the Nx56kbps detection bit is set to logic 1, the pattern generator only looks at the first 7 bits of the selected DS0 channels, and gaps out the eighth bit. This is particularly useful when searching for fractional T1 loopback codes in an Nx56kbps fractional T1 signal. This bit has no effect when UNF_DET is set to logic 1.
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75
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
RXPATGEN: The Receive Pattern Generate (RXPATGEN) bit controls the location of the pattern generator/detector. When RXPATGEN is set to logic 1, the pattern generator is inserted in the receive path and the pattern detector is inserted in the transmit path. DS0 channels from the receive line may be overwritten with generated patterns before appearing on the ingress interface, and DS0 channels from the egress interface may be checked for the generated pattern before appearing on the transmit line. When RXPATGEN is set to logic 0, the pattern detector is inserted in the receive path and the pattern generator is inserted in the transmit path. DS0 channels from the egress interface may be overwritten with generated patterns before appearing on the transmit line, and DS0 channels from the receive line may be checked for the generated pattern before appearing on the ingress interface. UNF_GEN When the Unframed Pattern Generation bit (UNF_GEN) is set to logic 1 while RXPATGEN = 0, then the PRGD will overwrite all 193 bits in every frame in the transmit direction. Unless signaling and/or framing is disabled, the XBAS will still overwrite the signaling bit positions and/or the framing bit position. The UNF_GEN bit overrides any per-DS0 pattern generation specified in the TPSC. UNF_GEN also overrides idle code insertion and data inversion in the transmit direction, just like the TEST bit in the TPSC. UNF_GEN=1 while RXPATGEN=1 is a reserved setting and should not be used. UNF_DET When the Unframed Pattern Detection bit (UNF_DET) is set to logic 1, then the PRGD will search for the pattern in all 193 bits of the egress or receive stream, depending on the setting of RXPATGEN. The UNF_DET bit overrides any per-DS0 pattern detection specified in the TPSC or RPSC.
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76
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 010H, 090H, 110H, 190H, 210H, 290H, 310H, 390H: RJAT Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R Type Function Unused Unused Unused Unused Unused Unused OVRI UNDI Default X X X X X X 0 0
These registers contain the indication of the RJAT FIFO status. OVRI: The OVRI bit is asserted when an attempt is made to write data into the FIFO when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. The OVRI bit is cleared after this register is read. UNDI: The UNDI bit is asserted when an attempt is made to read data from the FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. The UNDI bit is cleared after this register is read.
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77
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 011H, 091H, 111H, 191H, 211H, 291H, 311H, 391H: RJAT Reference Clock Divisor (N1) Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function N1[7] N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0] Default 0 0 1 0 1 1 1 1
These registers define an 8-bit binary number, N1, which is one less than the magnitude of the divisor used to scale down the RJAT PLL reference clock input. The REF divisor magnitude, (N1+1), is the ratio between the frequency of REF input and the frequency applied to the phase discriminator input. Writing to this register will reset the PLL and, if the SYNC bit in the RJAT Configuration register is high, will also reset the FIFO. Upon reset of the TOCTL, the default value of N1 is set to decimal 47 (2FH).
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78
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 012H, 092H, 112H, 192H, 212H, 292H, 312H, 392H: RJAT Output Clock Divisor (N2) Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function N2[7] N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0] Default 0 0 1 0 1 1 1 1
These registers define an 8-bit binary number, N2, which is one less than the magnitude of the divisor used to scale down the RJAT smooth output clock signal. The output clock divisor magnitude, (N2+1), is the ratio between the frequency of the smooth output clock and the frequency applied to the phase discriminator input. Writing to this register will reset the PLL and, if the SYNC bit is high, will also reset the FIFO. Upon reset of the TOCTL, the default value of N2 is set to decimal 47 (2FH).
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79
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 013H, 093H, 113H, 193H, 213H, 293H, 313H, 393H: RJAT Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W Type Function Unused Unused Reserved CENT UNDE OVRE SYNC LIMIT Default X X 1 0 0 0 1 1
These registers control the operation of the RJAT FIFO read and write pointers and controls the generation of interrupt by the FIFO status. Reserved: The Reserved bit should be programmed to logic 1 for future compatibility. CENT: The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI period, then the period will be extended by the number of UI that the EMPTY or FULL alarm persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during EMPTY or FULL alarm conditions. The CENT bit can only be set to logic 1 if the SYNC bit is set to logic 0. OVRE,UNDE: The OVRE and UNDE bits control the generation of an interrupt on the microprocessor INTB pin when a FIFO error event occurs. When OVRE or UNDE is set to logic 1, an overrun event or underrun event, respectively, is allowed to generate an interrupt on the INTB pin. When OVRE or UNDE is set to logic 0, the FIFO error events are disabled from generating an interrupt.
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80
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
SYNC: The SYNC bit enables the PLL to synchronize the phase delay between the FIFO input and output data to the phase delay between reference clock input and smooth output clock at the PLL. For example, if the PLL is operating so that the smooth output clock lags the reference clock by 24 UI, then the synchronization pulses that the PLL sends to the FIFO will force its output data to lag its input data by 24 UI. When SYNC is set to logic 1, then the RJAT divisors (N1 and N2) must be set so that N1+1 is a multiple of 48 decimal, and N2+1 is a multiple of 48 decimal. LIMIT: The LIMIT bit enables the PLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the smooth output clock whenever the FIFO is within one unit interval (UI) of overflowing or underflowing. This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally.
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81
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 018H, 098H, 118H, 198H, 218H, 298H, 318H, 398H: TJAT Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R Type Function Unused Unused Unused Unused Unused Unused OVRI UNDI Default X X X X X X 0 0
These registers contain the indication of the TJAT FIFO status. OVRI: The OVRI bit is asserted when an attempt is made to write data into the FIFO when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. The OVRI bit is cleared after this register is read. UNDI: The UNDI bit is asserted when an attempt is made to read data from the FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. The UNDI bit is cleared after this register is read.
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82
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 019H, 099H, 119H, 199H, 219H, 299H, 319H, 399H: TJAT Reference Clock Divisor (N1) Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function N1[7] N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0] Default 0 0 1 0 1 1 1 1
These registers define an 8-bit binary number, N1, which is one less than the magnitude of the divisor used to scale down the TJAT PLL reference clock input. The REF divisor magnitude, (N1+1), is the ratio between the frequency of REF input and the frequency applied to the phase discriminator input. Writing to this register will reset the PLL and, if the SYNC bit in the TJAT Configuration register is high, will also reset the FIFO. Upon reset of the TOCTL, the default value of N1 is set to decimal 47 (2FH).
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83
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 01AH, 09AH, 11AH, 19AH, 21AH, 29AH, 31AH, 39AH: TJAT Output Clock Divisor (N2) Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function N2[7] N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0] Default 0 0 1 0 1 1 1 1
These registers define an 8-bit binary number, N2, which is one less than the magnitude of the divisor used to scale down the TJAT smooth output clock signal. The output clock divisor magnitude, (N2+1), is the ratio between the frequency of the smooth output clock and the frequency applied to the phase discriminator input. Writing to this register will reset the PLL and, if the SYNC bit is high, will also reset the FIFO. Upon reset of the TOCTL, the default value of N2 is set to decimal 47 (2FH).
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84
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 01BH, 09BH, 11BH, 19BH, 21BH, 29BH, 31BH, 39BH: TJAT Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W Type Function Unused Unused Reserved CENT UNDE OVRE SYNC LIMIT Default X X 1 0 0 0 1 1
These registers control the operation of the TJAT FIFO read and write pointers and controls the generation of interrupt by the FIFO status. Reserved: The Reserved bit should be programmed to logic 1 for future compatibility. CENT: The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI period, then the period will be extended by the number of UI that the EMPTY or FULL alarm persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during EMPTY or FULL alarm conditions. The CENT bit can only be set to logic 1 if the SYNC bit is set to logic 0. OVRE,UNDE: The OVRE and UNDE bits control the generation of an interrupt on the microprocessor INTB pin when a FIFO error event occurs. When OVRE or UNDE is set to logic 1, an overrun event or underrun event, respectively, is allowed to generate an interrupt on the INTB pin. When OVRE or UNDE is set to logic 0, the FIFO error events are disabled from generating an interrupt.
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85
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
SYNC: The SYNC bit enables the PLL to synchronize the phase delay between the FIFO input and output data to the phase delay between reference clock input and smooth output clock at the PLL. For example, if the PLL is operating so that the smooth output clock lags the reference clock by 24 UI, then the synchronization pulses that the PLL sends to the FIFO will force its output data to lag its input data by 24 UI. When using the 2Mbit/s transmit backplane option, the SYNC bit must be set to logic 0. When SYNC is set to logic 1, then the TJAT divisors (N1 and N2) must be set so that N1+1 is a multiple of 48 decimal, and N2+1 is a multiple of 48 decimal. SYNC should only be set to logic 1 when PLLREF[1:0] = 00, the Egress Interface is in a Clock Slave mode, and CECLK2M is logic 0 the Egress Options Register. LIMIT: The LIMIT bit enables the PLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the smooth output clock whenever the FIFO is within one unit interval (UI) of overflowing or underflowing. This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally.
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86
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 01CH, 09CH, 11CH, 19CH, 21CH, 29CH, 31CH, 39CH: ELST Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W Type R/W Function Reserved Unused Unused Unused Unused Unused IR OR Default 0 X X X X X 0 0
These registers control the format of the expected input frame to the ELST and the format of the generated output frame from the ELST. Reserved: The Reserved bit must be programmed to logic 0 for proper operation. IR: The IR bit selects the input frame format. The IR bit must be cleared to logic 0 to properly handle the T1 frame format being input into the ELST. SETTING IR TO LOGIC 1 IS A RESERVED SETTING AND SHOULD NOT BE USED. OR: The OR bit selects the output frame format. The OR bit must be cleared to properly generate the T1 frame format output from the ELST. SETTING OR TO LOGIC 1 IS A RESERVED SETTING AND SHOULD NOT BE USED.
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87
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 01DH, 09DH, 11DH, 19DH, 21DH, 29DH, 31DH, 39DH: ELST Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLIPE: The SLIPE bit position enables generation of an interrupt on the microprocessor INTB pin when a slip event occurs. SLIPI: The SLIPI bit indicates whether a slip event has occurred since the last read of the Enable/Status register. SLIPI is a logic 1 if a slip has occurred; SLIPI is a logic 0 is no slip has occurred. The SLIPI bit is cleared after the register is read. SLIPD: The SLIPD bit indicates the direction of the last slip when SLIPI is a logic 1. If a slip has occurred and the SLIPD bit is a logic 1 then the slip was due to the frame buffer becoming full. If a slip has occurred and the SLIPD bit is a logic 0 then the slip was due to the frame buffer becoming empty. R/W R R Type Function Unused Unused Unused Unused Unused SLIPE SLIPD SLIPI Default X X X X X 0 0 0
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88
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 01EH, 09EH, 11EH, 19EH, 21EH, 29EH, 31EH, 39EH: ELST Trouble Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D7 D6 D5 D4 D3 D2 D1 D0 Default 1 1 1 1 1 1 1 1
These registers allow the Trouble Code, transmitted in place of channel data when the framer is out of frame, to be programmed to any 8-bit value. The code is transmitted from MSB (D7) to LSB (D0). The writing of the trouble code pattern into the register is asynchronous with respect to the clocks within the framer. One channel of trouble code data will always be corrupted if the register is written while the receiver is out of frame.
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89
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H: FRMR Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W Function M2O[1] M2O[0] ESFFA ESF Reserved Reserved Unused Unused Default 0 0 0 0 0 0 X X
These registers select the framing format and the frame loss criteria used by the FRMR. M2O[1:0]: The M2O[1:0] bits select the ratio of errored to total framing bits before declaring out of frame in SF, and ESF framing formats. A logic 00 selects 2 of 4 framing bits in error; a logic 01 selects 2 of 5 bits in error; a logic 10 selects 2 of 6 bits in error. A logic 11 in the M2O[1:0] bits is reserved and should not be used. ESFFA: The ESFFA bit selects one of two framing algorithms for ESF frame search in the presence of mimic framing patterns in the incoming data. A logic 0 selects the ESF algorithm where the FRMR does not declare inframe while more than one framing bit candidate is following the framing pattern in the incoming data. A logic 1 selects the ESF algorithm where a CRC-6 calculation is performed on each framing bit candidate, and is compared against the CRC bits associated with the framing bit candidate to determine the most likely framing bit position. ESF: The ESF bit selects either extended superframe format or standard superframe format. A logic 1 in the ESF bit position selects ESF; a logic 0 selects SF.
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90
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Reserved: The reserved bits must be written with logic 0 for proper operation..
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91
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 021H, 0A1H, 121H, 1A1H, 221H, 2A1H, 321H, 3A1H: FRMR Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused ACCEL COFAE FERE BEEE SFEE MFPE INFRE Default X 0 0 0 0 0 0 0
These registers select which of the MFP COFA, FER, BEE, SFE, or INFR events , generates an interrupt on the microprocessor INTB pin when their state changes or their event condition is detected. ACCEL: The ACCEL bit is used for production test purposes only. THE ACCEL BIT MUST BE PROGRAMMED TO LOGIC 0 FOR NORMAL OPERATION. COFAE: The COFAE bit enables the generation of an interrupt when the frame find circuitry determines that frame alignment has been achieved and that the new alignment differs from the previous alignment. When COFAE is set to logic 1, the declaration of a change of frame alignment is allowed to generate an interrupt. When COFAE is set to logic 0, a change in the frame alignment does not generate an interrupt. FERE: The FERE bit enables the generation of an interrupt when a framing bit error has been detected. When FERE is set to logic 1, the detection of a framing bit error is allowed to generate an interrupt. When FERE is set to logic 0, any error in the framing bits does not generate an interrupt.
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92
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
BEEE: The BEEE bit enables the generation of an interrupt when a bit error event has been detected. A bit error event is defined as a framing bit errors for SF formatted data, and a CRC-6 error for ESF formatted data. When BEEE is set to logic 1, the detection of a bit error event is allowed to generate an interrupt. When BEEE is set to logic 0, bit error events are disabled from generating an interrupt. SFEE: The SFEE bit enables the generation of an interrupt when a severely errored framing event has been detected. A severely errored framing event is defined as 2 or more framing bit errors during the current superframe for SF or ESF formatted data. When SFEE is set to logic 1, the detection of a severely errored framing event is allowed to generate an interrupt. When SFEE is set to logic 0, severely errored framing events are disabled from generating an interrupt. MFPE: The MFPE bit enables the generation of an interrupt when the frame find circuitry detects the presence of framing bit mimics. The occurrence of a mimic is defined as more than one framing bit candidate following the frame alignment pattern. When MFPE is set to logic 1, the assertion or deassertion of the detection of a mimic is allowed to generate an interrupt. When MFPE is set to logic 0, the detection of a mimic framing pattern is disabled from generating an interrupt. INFRE: The INFRE bit enables the generation of an interrupt when the frame find circuitry determines that frame alignment has been achieved and that the framer is now "inframe". When INFRE is set to logic 1, the assertion or deassertion of the "inframe" state is allowed to generate an interrupt. When INFRE is set to logic 0, a change in the "inframe" state is disabled from generating an interrupt.
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93
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 022H, 0A2H, 122H, 1A2H, 222H, 2A2H, 322H, 3A2H: FRMR Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function COFAI FERI BEEI SFEI MFPI INFRI MFP INFR Default 0 0 0 0 0 0 0 0
These registers indicate whether a change of frame alignment, a framing bit error, a bit error event, or a severely errored framing event generated an interrupt. These registers also indicate whether a mimic framing pattern was detected or whether there was a change in the "inframe" state of the frame circuitry. COFAI,FERI,BEEI,SFEI: A logic 1 in the status bit positions COFAI, FERI, BEEI, and SFEI indicate that the occurrence of the corresponding event generated an interrupt; a logic 0 in the status bit positions COFAI, FERI, BEEI, and SFEI indicate that the corresponding event did not generate an interrupt. MFPI: A logic 1 in the MFPI status bit position indicates that the assertion or deassertion of the mimic detection indication has generated an interrupt; a logic 0 in the MFPI bit position indicates that no change in the state of the mimic detection indication occurred. INFRI: A logic 1 in the INFRI status bit position indicates that a change in the "inframe" state of the frame alignment circuitry generated an interrupt; a logic 0 in the INFRI status bit position indicates that no state change occurred.
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94
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
MFP ,INFR: The bit position MFP and INFR indicate the current state of the mimic detection and of the frame alignment circuitry. The interrupt and the status bit positions (COFAI, FERI, BEEI, SFEI, MFPI, and INFRI) are cleared to logic 0 when this register is read.
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95
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 027H, 0A7H, 127H, 1A7H, 227H, 2A7H, 327H, 3A7H: Clock Monitor Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R Type Function Unused Unused Unused XCLKA CECLKA CTCLKA CICLKA RLCLKA Default X X X 0 0 0 0 0
These registers provide activity monitoring on TOCTL clocks. When a monitored clock signal makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point, all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. These registers should be read at periodic intervals to detect clock failures. XCLKA: The XCLK active bit monitors for low to high transitions on the XCLK input. XCLKA is set high on a rising edge of XCLK, and is set low when this register is read. RLCLKA: The RLCLK active bit monitors for low to high transitions on the RLCLK[x] input. RLCLKA is set high on a rising edge of RLCLK[x], and is set low when this register is read. CICLKA: The CICLK active bit monitors for low to high transitions on the CICLK input. CICLKA is set high on a rising edge of CICLK, and is set low when this register is read.
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96
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
CTCLKA: The CTCLK active bit monitors for low to high transitions on the CTCLK input. CTCLKA is set high on a rising edge of CTCLK, and is set low when this register is read. CECLKA: The CECLK active bit monitors for low to high transitions on the CECLK input. CECLKA is set high on a rising edge of CECLK, and is set low when this register is read.
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97
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 02AH, 0AAH, 12AH, 1AAH, 22AH, 2AAH, 32AH, 3AAH: RBOC Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type Function Unused Unused Unused Unused Unused IDLE AVC BOCE Default X X X X X 0 0 0
These registers select the validation criteria to be used in determining a valid bit oriented code (BOC) and enables generation of an interrupt on a change in code status. IDLE: The IDLE bit position enables or disables the generation of an interrupt when there is a transition from a validated BOC to idle code. A logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation. AVC: The AVC bit position selects the validation criteria used in determining a valid BOC. A logic 1 in the AVC bit position selects the "alternate" validation criterion of 4 out of 5 matching BOCs; a logic 0 selects the 8 out of 10 matching BOC criterion. BOCE: The BOCE bit position enables or disables the generation of an interrupt on the microprocessor INTB pin when a valid BOC is detected. A logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation.
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98
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 02BH, 0ABH, 12BH, 1ABH, 22BH, 2ABH, 32BH, 3ABH: RBOC Code Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function IDLEI BOCI BOC[5] BOC[4] BOC[3] BOC[2] BOC[1] BOC[0] Default 0 0 1 1 1 1 1 1
These registers indicate the current state value of the BOC[5:0] bits and indicates whether an interrupt was generated by a change in the code value. IDLEI: The IDLEI bit position indicates whether an interrupt was generated by the detection of the transition from a valid BOC to idle code. A logic 1 in the IDLEI bit position indicates that a transition from a valid BOC to idle code has generated an interrupt; a logic 0 in the IDLEI bit position indicates that no transition from a valid BOC to idle code has been detected. IDLEI is cleared to logic 0 when the register is read. BOCI: The BOCI bit position indicates whether an interrupt was generated by the detection of a valid BOC. A logic 1 in the BOCI bit position indicates that a validated BOC code has generated an interrupt; a logic 0 in the BOCI bit position indicates that no BOC has been detected. BOCI is cleared to logic 0 when the register is read. BOC[5:0] BOC[5:0] contain the validated 6-bit BOC. BOC[5] corresponds to the MSB of the code; BOC[0] corresponds to the LSB. An all-ones setting indicates that no valid BOC has been received.
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99
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH: ALMI Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type Function Unused Unused Unused ESF Reserved Reserved Unused Unused Default X X X 0 0 0 X X
These registers allow selection of the framing format to allow operation of the CFA detection algorithms. ESF: The ESF bit selects either extended superframe format or standard superframe format. A logic 1 in the ESF bit position selects ESF; a logic 0 bit selects SF. Reserved: The reserved bits must be written with logic 0 for proper operation..
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100
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 02DH, 0ADH, 12DH, 1ADH, 22DH, 2ADH, 32DH, 3ADH: ALMI Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type Function Unused Unused Unused FASTD ACCEL YELE REDE AISE Default X X X 0 0 0 0 0
These registers select which of the three CFA's can generate an interrupt when their logic state changes and enables the "fast" deassertion mode of operation. FASTD: The FASTD bit enables the "fast" deassertion of Red and AIS alarms. When FASTD is set to a logic 1, deassertion of Red alarm occurs within 120 ms of going in frame. Deassertion of AIS alarm occurs within 180 ms of either detecting a 60 ms interval containing 127 or more zeros, or going in frame. When FASTD is set to a logic 0, Red and AIS alarm deassertion times remain as defined in the ALMI description. ACCEL: The ACCEL bit is used for production test purposes only. THE ACCEL BIT MUST BE PROGRAMMED TO LOGIC 0 FOR NORMAL OPERATION. YELE,REDE,AISE: A logic 1 in the enable bit positions (YELE, REDE, AISE) enables a state change in the corresponding CFA to generate an interrupt; a logic 0 in the enable bit positions disables any state changes to generate an interrupt. The enable bits are independent; any combination of Yellow, Red, and AIS CFA's can be enabled to generate an interrupt.
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101
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 02EH, 0AEH, 12EH, 1AEH 22EH, 2AEH, 32EH, 3AEH: ALMI Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R Type Function Unused Unused YELI REDI AISI YEL RED AIS Default X X 0 0 0 0 0 0
These registers indicate which of the three CFA's generated an interrupt when their logic state changed in bit positions 5 through 3; and indicate the current state of each CFA in bit positions 2 through 0. A logic 1 in the status positions (YELI, REDI, AISI) indicate that a state change in the corresponding CFA has generated an interrupt; a logic 0 in the status positions indicates that no state change has occurred. Both the status bit positions (bits 5 through 3) and the interrupt generated because of the change in CFA state are cleared to logic 0 when this register is read.
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102
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 02FH, 0AFH, 12FH, 1AFH, 22FH, 2AFH, 32FH, 3AFH: ALMI Alarm Detection Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R Type Function Unused Unused Unused Unused Unused REDD YELD AISD Default X X X X X X X X
These registers indicate the presence or absence of one or more OOF occurrences within the last 40 ms; the presence or absence of the Yellow ALARM signal over the last 40 ms; and indicate the presence or absence of the AIS ALARM signal over the last 60 ms. REDD: When REDD is a logic 1, one or more out of frame events have occurred during the last 40 ms interval. When REDD is a logic 0, no out of frame events have occurred within the last 40 ms interval. YELD: When YELD is logic 1, a valid Yellow signal was present during the last 40 ms interval. When YELD is logic 0, the Yellow signal was absent during the last 40 ms interval. For each framing format, a valid Yellow signal is deemed to be present if: * * AISD: When AISD is logic 1, a valid AIS signal was present during the last 60 ms interval. When AISD is logic 0, the AIS signal was absent during the last 60 bit 2 of each channel is not logic 0 for 16 or fewer times during the 40 ms interval for SF framing format; the 16-bit Yellow bit oriented code is received error-free 8 or more times during the interval for ESF framing format;
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103
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
ms interval. A valid AIS signal is deemed to be present during a 60 ms interval if the out of frame condition has persisted for the entire interval and the received PCM data stream is not logic 0 for 126 or fewer times.
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104
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 030H, 0B0H, 130H, 1B0H, 230H, 2B0H, 330H, 3B0H: TPSC Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W Type Function Unused Unused Unused Unused Unused Unused IND PCCE Default X X X X X X 0 0
These registers allow selection of the microprocessor read access type and output enable control for the Transmit Per-DS0 Serial Controller. The per-DS0 Serial Controller allows per-DS0 data and signaling trunk alignment, idle code, zero code suppression, data inversion, DS0 loopback from the ingress stream, channel insertion, and the detection or generation of pseudo-random or repetitive patterns. More information on using the TPSC can be found in the Operations section. IND: The IND bit controls the microprocessor access type: either indirect or direct. The IND bit must be set to logic 1 for proper operation. When the TOCTL is reset, the IND bit is set low, disabling the indirect access mode. PCCE: The PCCE bit enables the per-DS0 functions. When the PCCE bit is set to a logic 1, each channel's Egress Control byte, IDLE Code byte, and SIGNALING Control byte are enabled. When the PCCE bit is set to logic 0, the per-DS0 functions are disabled.
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105
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 031H, 0B1H, 131H, 1B1H, 231H, 2B1H, 331H, 3B1H: TPSC P Access Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R Function BUSY Unused Unused Unused Unused Unused Unused Unused Default 0 X X X X X X X
The BUSY bit in the Status register is high while a P access request is in progress. The BUSY bit goes low timed to an internal high-speed clock rising edge after the access has been completed. During normal operation, the Status Register should be polled until the BUSY bit goes low before another P access request is initiated. A P access request is typically completed within 640 ns.
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106
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 032H, 0B2H, 132H, 1B2H, 232H, 2B2H, 332H, 3B2H: TPSC Channel Indirect Address/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function R/WB A6 A5 A4 A3 A2 A1 A0 Default 0 0 0 0 0 0 0 0
These registers allow the P to access the internal TPSC registers addressed by the A[6:0] bits and perform the operation specified by the R/WB bit. Writing to this register with a valid address and R/WB bit initiates an internal P access request cycle. The R/WB bit selects the operation to be performed on the addressed register: when R/WB is set to a logic 1, a read from the internal TPSC register is requested; when R/WB is set to a logic 0, a write to the internal TPSC register is requested.
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107
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 033H, 0B3H, 133H, 1B3H, 233H, 2B3H, 333H, 3B3H: TPSC Channel Indirect Data Buffer Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D7 D6 D5 D4 D3 D2 D1 D0 Default 0 0 0 0 0 0 0 0
These registers contain either the data to be written into the internal TPSC registers when a write request is initiated or the data read from the internal TPSC registers when a read request has completed. During normal operation, if data is to be written to the internal registers, the byte to be written must be written into this Data register before the target register's address and R/WB=0 is written into the Address/Control register, initiating the access. If data is to be read from the internal registers, only the target register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data byte. The internal TPSC registers control the per-DS0 functions on the egress data, provide the per-DS0 transmit idle code, and provide the per-DS0 transmit signaling control and the alternate signaling bits. The functions are allocated within the registers as follows: Table 3 01H 02H
* *
- TPSC Indirect Memory Map Egress Control byte for Channel 1 Egress Control byte for Channel 2
* *
17H 18H
Egress Control byte for Channel 23 Egress Control byte for Channel 24
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108
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
19H 1AH
* *
IDLE Code byte for Channel 1 IDLE Code byte for Channel 2
* *
2FH 30H 31H 32H
* *
IDLE Code byte for Channel 23 IDLE Code byte for Channel 24 SIGNALING Control byte for Channel 1 SIGNALING Control byte for Channel 2
* *
47H 48H
SIGNALING Control byte for Channel 23 SIGNALING Control byte for Channel 24
The bits within each control byte are allocated as follows:
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109
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
TPSC Internal Registers 01-18H: Egress Control byte Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INVERT: When the INVERT bit is set to a logic 1, data from the ED[x] input is inverted for the duration of that channel. SIGNINV: When the SIGNINV bit is set to a logic 1, the most significant bit from the ED[x] input is inverted for that channel. The INVERT and SIGNINV can be used to produce the following types of inversions: INVERT 0 1 0 1 SIGNINV 0 0 1 1 Effect on PCM Channel Data PCM Channel data is unchanged All 8 bits of the PCM channel data are inverted Only the MSB of the PCM channel data is inverted (SIGN bit inversion) All bits EXCEPT the MSB of the PCM channel data is inverted (Magnitude inversion) Type R/W R/W R/W R/W R/W R/W R/W R/W Function INVERT IDLE_DS0 DMW SIGNINV TEST LOOP ZCS0 ZCS1 Default
IDLE_DS0: When the IDLE_DS0 bit is set to a logic 1, data from the IDLE Code Byte replaces the ED[x] input data for the duration of that channel.
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110
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
When the NxDS0 mode is active, IDLE_DS0 also controls the generation of ECLK[x]. When IDLE_DS0 is a logic 0, data is inserted from the egress interface during that channel, and eight clock pulses are generated on ECLK[x]. When IDLE_DS0 is a logic 1, an IDLE code byte is inserted, and ECLK[x] is suppressed for the duration of that channel. DMW: When the DMW bit is set to a logic 1, the digital milliwatt pattern replaces the ED[x] input data for the duration of that channel. TEST: When the TEST bit is set to a logic 1, channel data from the ED[x] input is either overwritten with a test pattern from the PRGD block or is routed to the PRGD block and compared against an expected test pattern. The RXPATGEN bit in the Pattern Generator/Detector Positioning/Control register determines whether the egress data is overwritten or compared as shown in the following table: TEST 0 1 1 RXPATGEN Description X 1 0 Channel data is not included in test pattern Channel data is routed to PRGD and compared against expected test pattern Channel data is overwritten with PRGD test pattern
All the channels that are routed to the PRGD are concatenated and treated as a continuous stream in which pseudorandom or repetitive sequences are searched for. Similarly, all channels set to be overwritten with PRGD test pattern data are treated such that if the channels are subsequently extracted and concatenated, the PRBS or repetitive sequence appears in the concatenated stream. Pattern generation/detection can be enabled to work on only the first 7 bits of a channel (for Nx56 kbps fractional T1) using the Nx56k_DET and Nx56k_GEN bits in the Pattern Generator/Detector Positioning/Control register (Reg. 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH). THe PRGD can also be enabled to work on the entire DS1, including framing bits, using the UNF_GEN and UNF_DET bits in the Pattern Generator/Detector Positioning/Control register. LOOP: The LOOP bit enables the DS0 loopback. When the LOOP bit is set to a logic 1, egress data is overwritten with the corresponding channel data from the
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111
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
receive line. When the Clock Master ingress modes are enabled, the elastic store is used to align the receive line data to the egress frame. When the Clock Slave ingress modes are enabled, however, the elastic store is unavailable to facilitate per-DS0 loopacks, and loopback functionality is provided only when the Egress Interfaces is also in a Clock Slave mode, and ingress and egress clocks and frame alignment are identical (CICLK=CECLK, CIFP=CEFP). Data inversion, idle, loopback and test pattern insertion/checking are performed independent of the transmit framing format. DS0 loopback takes precedence over digital milliwatt pattern insertion. Next in priority is test pattern insertion, which, in turn, takes precedence over idle code insertion. Data inversion has the lowest priority. When test pattern checking is enabled, the egress data is compared before DS0 loopback, digital milliwatt pattern insertion, idle code insertion or data inversion is performed. None of this prioritizing has any effect on the gapping of ECLK in NxDS0 mode. That is, if both DS0 loopback and idle code insertion are enabled for a given channel while in NxDS0 mode, the DS0 will be looped-back, will not be overwritten with idle code, and ECLK will be gapped out for the duration of the channel. Similarly, none of the prioritizing has any effect on the generation of test patterns from the PRGD, only on the insertion of that pattern. Thus, if both DMW and TEST are set for a given DS0, and RXPATGEN = 0, then the test pattern from the PRGD will be overwritten with the digital milliwatt code. This same rule also applies to test patterns inserted via the UNF_GEN bit in the Pattern Generator/Detector Positioning/Control register. ZCS0,ZCS1: The ZCS0 and ZCS1 bits select the zero code suppression used as follows. With the exception of the "Jammed bit 8" setting, the ZCS[1:0] bits are logically ORed with the ZCS[1:0] bits in the XBAS Configuration register: ZCS0 0 0 1 ZCS1 0 1 0 Description No Zero Code Suppression "Jammed bit 8" - Every bit 8 is forced to a one. This may be used for 56kbit/s data service. GTE Zero Code Suppression (Bit 8 of an all zero channel byte is replaced by a one, except in signaling frames where bit 7 is forced to a one.) Bell Zero Code Suppression (Bit 7 of an all zero channel byte is replaced by a one.)
1
1
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112
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
TPSC Internal Registers 19-30H: IDLE Code byte Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function IDLE7 IDLE6 IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0 Default
The contents of the IDLE Code byte register is substituted for the channel data on ED[x] when the IDLE_DS0 bit in the Egress Control byte is set to a logic 1. The IDLE Code is transmitted from MSB (IDLE7) to LSB (IDLE0).
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113
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
TPSC Internal Registers 31-48H: SIGNALING Control byte Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W R/W Function SIGC0 SIGC1 Unused Unused A' B' C' D' Default
Signaling insertion is controlled by the SIGC[1:0] bits. The source of the signaling bits is determined by SIGC0: when SIGC0 is set to a logic 1, signaling data is taken from the A', B', C', and D' bits; when SIGC0 is set to logic 0, signaling data is taken from the A,B,C, and D bit locations on the ESIG[x] input. Signaling insertion is controlled by SIGC1: when SIGC1 is set to a logic 1, insertion of signaling bits is enabled; when SIGC1 is set to logic 0, the insertion of signaling bits is disabled. For SF format, the C' and D' or C and D bits from Signaling Control byte or ESIG[x], respectively, are inserted into the A and B signaling bit positions of every second superframe that is transmitted. It is assumed that C=A and D=B.
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114
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 034H, 0B4H, 134H, 1B4H, 234H, 2B4H ,334H, 3B4H: TDPR Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W R/W R/W Function FLGSHARE FIFOCLR Reserved Unused EOM ABT CRC EN Default 1 0 0 X 0 0 1 0
Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register and reads of the TDPR Interrupt Status/UDR Clear register should not occur at rates greater than 1/8th that of XCLK. EN: The EN bit enables the TDPR functions. When EN is set to logic 1, the TDPR is enabled and flag sequences are sent until data is written into the TDPR Transmit Data register. When the EN bit is set to logic 0, the TDPR is disabled and an all 1's Idle sequence is transmitted on the datalink. CRC: The CRC enable bit controls the generation of the CCITT_CRC frame check sequence (FCS). Setting the CRC bit to logic 1 enables the CCITT-CRC generator and appends the 16-bit FCS to the end of each message. When the CRC bit is set to logic 0, the FCS is not appended to the end of the message. The CRC type used is the CCITT-CRC with generator polynomial x16 + x12 + x5 + 1. The high order bit of the FCS word is transmitted first. ABT: The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC abort code. Setting the ABT bit to a logic 1 causes the 01111111 code (the 0 is transmitted first) to be transmitted after the current byte from the Transmit Data register is transmitted. The FIFO is then reset. All data in the FIFO will
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115
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
be lost. Aborts are continuously sent and the FIFO is held in reset until this bit is reset to a logic 0. At least one Abort sequence will be sent when the ABT bit transitions from logic 0 to logic 1. EOM: The EOM bit indicates that the last byte of data written in the Transmit Data register is the end of the present data packet. If the CRC bit is set then the 16-bit FCS word is appended to the last data byte transmitted and a continuous stream of flags is generated. The EOM bit is cleared upon a write to the TDPR Transmit Data register (039H, 0B9H, 139H, 1B9H, 239H, 2B9H, 339H, 3B9H). Reserved: This bit should be programmed to logic 0 for proper operation. FIFOCLR: The FIFOCLR bit resets the TDPR FIFO. When set to logic 1, FIFOCLR will cause the TDPR FIFO to be cleared. FLGSHARE: The FLGSHARE bit configures the TDPR to share the opening and closing flags between successive frames. If FLGSHARE is logic 1, then the opening and closing flags between successive frames are shared. If FLGSHARE is logic 0, then separate closing and opening flags are inserted between successive frames.
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116
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 035H, 0B5H, 135H, 1B5H, 235H, 2B5H ,335H, 3B5H: TDPR Upper Transmit Threshold Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UTHR[6:0]: The UTHR[6:0] bits define the TDPR FIFO fill level which will automatically cause the bytes stored in the TDPR FIFO to be transmitted. Once the fill level exceeds the UTHR[6:0] value, transmission will begin. Transmission will not stop until the last complete packet is transmitted and the TDPR FIFO fill level is below UTHR[6:0] + 1. The value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both values are equal to 00H. R/W R/W R/W R/W R/W R/W R/W Type Function Unused UTHR[6] UTHR[5] UTHR[4] UTHR[3] UTHR[2] UTHR[1] UTHR[0] Default X 1 0 0 0 0 0 0
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117
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 036H, 0B6H, 136H, 1B6H, 236H, 2B6H ,336H, 3B6H: TDPR Lower Interrupt Threshold Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LINT[6:0]: The LINT[6:0] bits define the TDPR FIFO fill level which causes an internal interrupt (LFILLI) to be generated. Once the TDPR FIFO level decrements to empty or to a value less than LINT[6:0], the LFILLI and BLFILL bits will be set to logic 1. LFILLI will cause an interrupt on INTB if LFILLE is set to logic 1. The value of LINT[6:0] must always be less than the value of UTHR[6:0] unless both values are equal to 00H. R/W R/W R/W R/W R/W R/W R/W Type Function Unused LINT[6] LINT[5] LINT[4] LINT[3] LINT[2] LINT[1] LINT[0] Default X 0 0 0 0 1 1 1
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118
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 037H, 0B7H, 137H, 1B7H, 237H, 2B7H ,337H, 3B7H: TDPR Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LFILLE: The LFILLE enables a transition to logic 1 on LFILLI to generate an interrupt on INTB. If LFILLE is a logic 1, a transition to logic 1 on LFILLI will generate an interrupt on INTB. If LFILLE is a logic 0, a transition to logic 1 on LFILLI will not generate an interrupt on INTB. UDRE: The UDRE enables a transition to logic 1 on UDRI to generate an interrupt on INTB. If UDRE is a logic 1, a transition to logic 1 on UDRI will generate an interrupt on INTB. If UDRE is a logic 0, a transition to logic 1 on UDRI will not generate an interrupt on INTB. OVRE: The OVRE enables a transition to logic 1 on OVRI to generate an interrupt on INTB. If OVRE is a logic 1, a transition to logic 1 on OVRI will generate an interrupt on INTB. If OVRE is a logic 0, a transition to logic 1 on OVRI will not generate an interrupt on INTB. FULLE: The FULLE enables a transition to logic 1 on FULLI to generate an interrupt on INTB. If FULLE is a logic 1, a transition to logic 1 on FULLI will generate an interrupt on INTB. If FULLE is a logic 0, a transition to logic 1 on FULLI will not generate an interrupt on INTB. R/W R/W R/W R/W R/W Type Function Unused Unused Unused Reserved FULLE OVRE UDRE LFILLE Default X X X 0 0 0 0 0
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119
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Reserved: This bit should be set to logic 0 for proper operation.
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120
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 038H, 0B8H, 138H, 1B8H, 238H, 2B8H ,338H, 3B8H: TDPR Interrupt Status /UDR Clear Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R Type Function Unused FULL BLFILL Reserved FULLI OVRI UDRI LFILLI Default X X X X X X X X
Writing to this register will clear the underrun condition if it has occurred. Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register and reads of the TDPR Interrupt Status/UDR Clear register should not occur at rates greater than 1/8th that of XCLK. LFILLI: The LFILLI bit will transition to logic 1 when the TDPR FIFO level transitions to empty or falls below the value of LINT[6:0] programmed in the TDPR Lower Interrupt Threshold register. LFILLI will assert INTB if it is a logic 1 if LFILLE is programmed to logic 1. LFILLI is cleared when this register is read. UDRI: The UDRI bit will transition to 1 when the TDPR FIFO underruns. That is, the TDPR was in the process of transmitting a packet when it ran out of data to transmit. UDRI will assert INTB if it is a logic 1 if UDRE is programmed to logic 1. UDRI is cleared when this register is read. OVRI: The OVRI bit will transition to 1 when the TDPR FIFO overruns. That is, the TDPR FIFO was already full when another data byte was written to the TDPR Transmit Data register. OVRI will assert INTB if it is a logic 1 if OVRE is programmed to logic 1. OVRI is cleared when this register is read.
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121
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
FULLI: The FULLI bit will transition to logic 1 when the TDPR FIFO is full. FULLI will assert INTB if it is a logic 1 if FULLE is programmed to logic 1. FULLI is cleared when this register is read. Reserved: This bit is not used in TOCTL applications, and should be set to logic 0 for proper operation. BLFILL: The BLFILL bit is set to logic 1 if the current FIFO fill level is below the LINT[7:0] level or is empty. FULL: The FULL bit reflects the current condition of the TDPR FIFO. If FULL is a logic 1, the TDPR FIFO already contains 128-bytes of data and can accept no more.
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122
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 039H, 0B9H, 139H, 1B9H, 239H, 2B9H ,339H, 3B9H: TDPR Transmit Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function TD[7] TD[6] TD[5] TD[4] TD[3] TD[2] TD[1] TD[0] Default X X X X X X X X
Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register and reads of the TDPR Interrupt Status/UDR Clear register should not occur at rates greater than 1/8th that of XCLK. TD[7:0]: The TD[7:0] bits contain the data to be transmitted on the data link. Data written to this register is serialized and transmitted (TD[0] is transmitted first).
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123
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 03CH, 0BCH, 13CH, 1BCH, 23CH, 2BCH, 33CH, 3BCH: IBCD Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W Function Reserved Unused Unused Unused DSEL1 DSEL0 ASEL1 ASEL0 Default 0 X X X 0 0 0 0
These registers provide the selection of the Activate and De-activate loopback code lengths (from 3 bits to 8 bits) as follows: DEACTIVATE Code DSEL1 0 0 1 1 *Note: 3 and 4 bit code sequences can be accommodated by configuring the IBCD for 6 or 8 bits and by programming two repetitions of the code sequence. The Reserved bit must be programmed to logic 0 for normal operation. DSEL0 0 1 0 1 ACTIVATE Code ASEL1 0 0 1 1 ASEL0 0 1 0 1 5 bits 6 (or 3*) bits 7 bits 8 (or 4*) bits CODE LENGTH
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124
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 03DH, 0BDH, 13DH, 1BDH, 23DH, 2BDH, 33DH, 3BDH: IBCD Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R/W R/W R R R R Function LBACP LBDCP LBAE LBDE LBAI LBDI LBA LBD Default 0 0 0 0 0 0 0 0
LBACP ,LBDCP: The LBACP and LBDCP bits indicate when the corresponding loopback code is present during a 39.8 ms interval. LBAE: The LBAE bit enables the assertion or deassertion of the inband Loopback Activate (LBA) detect indication to generate an interrupt on the microprocessor INTB pin. When LBAE is set to logic 1, any change in the state of the LBA detect indication generates an interrupt. When LBAE is set to logic 0, no interrupt is generated by changes in the LBA detect state. LBDE: The LBDE bit enables the assertion or deassertion of the inband Loopback Deactivate (LBD) detect indication to generate an interrupt on the microprocessor INTB pin. When LBDE is set to logic 1, any change in the state of the LBD detect indication generates an interrupt. When LBDE is set to logic 0, no interrupt is generated by changes in the LBD detect state. LBAI,LBDI: The LBAI and LBDI bits indicate which of the two expected loopback codes generated the interrupt when their state changed. A logic 1 in these bit positions indicate that a state change in that code has generated an interrupt; a logic 0 in these bit positions indicate that no state change has occurred.
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125
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
LBA,LBD: The LBA and LBD bits indicate the current state of the corresponding loopback code detect indication. A logic 1 in these bit positions indicate the presence of that code has been detected; a logic 0 in these bit positions indicate the absence of that code.
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126
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 03EH, 0BEH, 13EH, 1BEH, 23EH, 2BEH, 33EH, 3BEH: IBCD Activate Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1 ACT0 Default 0 0 0 0 0 0 0 0
This 8 bit register selects the Activate code sequence that is to be detected. If the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8 bit register. For example, if code sequence is a repeating 00001, then the first 8 bits of two repetitions (0000100001) is programmed into the register, i.e.00001000. Note that bit ACT7 corresponds to the first code bit received.
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127
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 03FH, 0BFH, 13FH, 1BFH, 23FH, 2BFH, 33FH, 3BFH: IBCD Deactivate Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function DACT7 DACT6 DACT5 DACT4 DACT3 DACT2 DACT1 DACT0 Default 0 0 0 0 0 0 0 0
This 8 bit register selects the Deactivate code sequence that is to be detected. If the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8 bit register. For example, if code sequence is a repeating 001, then the first 8 bits of three repetitions (001001001) is programmed into the register, i.e.00100100. Note that bit DACT7 corresponds to the first code bit received.
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128
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H: SIGX Configuration (COSS=0) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function Reserved COSS SIGE Reserved Reserved ESF IND PCCE Default 0 0 0 0 0 0 0 0
These registers allow selection of the framing format, the microprocessor access type, and allows enabling of the per-DS0 configuration registers. The bits in this register are valid when the COSS bit is a logic 0. The reserved bits must be set to logic 0 for correct operation. SIGE: The SIGE bit enables a change of signaling state in any of the 24 channels to generate an interrupt on the INTB pin. When SIGE is set to logic 1, a change of signaling state in any channel generates an interrupt. When SIGE is set to logic 0, the interrupt is disabled. COSS: The COSS bit allows the channels to be polled to determine in which channel(s) the signaling state has changed. When COSS is a logic 1, the SIGX register space is configured to allow the change of signaling state event bits to be read. When COSS is a logic 0, the SIGX register space is configured to allow indirect access to the configuration and signaling data registers for each of the 24 channels. ESF: The ESF bit selects either extended superframe format standard superframe formats. A logic 1 in the ESF bit position selects ESF; a logic 0 bit selects SF.
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129
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
IND: The IND bit controls the microprocessor access type: either indirect or direct. The IND bit must be set to logic 1 for proper operation. When the TOCTL is reset, the IND bit is set low, disabling the indirect access mode. PCCE: The PCCE bit enables the per-DS0 functions. When the PCCE bit is set to a logic 1, bit fixing and signaling debouncing are performed on a per-DS0 basis. When the PCCE bit is logic 0, the per-DS0 functions are disabled.
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130
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H: SIGX Configuration (COSS=1) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COSS: The COSS bit allows the channels to be polled to determine in which channel(s) the signaling state has changed. When COSS is a logic 1, the SIGX register space is configured to allow the change of signaling state event bits to be read. When COSS is a logic 0, the SIGX register space is configured to allow indirect access to the configuration and signaling data registers for each of the 24 channels. R/W Type Function Unused COSS Unused Unused Unused Unused Unused Unused Default X 0 X X X X X X
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131
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H: SIGX P Access Status (COSS=0) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R Function BUSY Unused Unused Unused Unused Unused Unused Unused Default 0 X X X X X X X
The BUSY bit in the Status register is high while a P access request is in progress. The BUSY bit goes low timed to an internal high-speed clock rising edge after the access has been completed. During normal operation, the Status Register should be polled until the BUSY bit goes low before another P access request is initiated. A P access request is typically completed within 640 ns. The bits in this register are valid when the COSS bit is a logic 0.
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132
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H: SIGX Signaling State Change Channels 17-24 (COSS=1) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function COSS[24] COSS[23] COSS[22] COSS[21] COSS[20] COSS[19] COSS[18] COSS[17] Default X X X X X X X X
The bits in this register are valid when the COSS bit is a logic 1. COSS[24:17]: The COSS[24:17] bits indicate a signaling state change in channels 17 - 24. A logic 1 in a bit position indicates a change of signaling state in the corresponding channel since the last time this register was read; a logic 0 in a bit position indicates that no signaling state change has occurred. These bits are cleared when this register is read.
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133
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H: SIGX Channel Indirect Address/Control (COSS=0) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function R/WB A6 A5 A4 A3 A2 A1 A0 Default 0 0 0 0 0 0 0 0
These registers allow the P to access to internal SIGX registers addressed by the A[6:0] bits and perform the operation specified by the R/WB bit. Writing to one of these registers with a valid address and R/WB bit initiates an internal P access request cycle. The R/WB bit selects the operation to be performed on the addressed register: when R/WB is set to a logic 1, a read from the internal SIGX register is requested, when R/WB is set to a logic 0, an write to the internal SIGX register is requested. The bits in this register are valid when the COSS bit is a logic 0.
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134
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H: SIGX Signaling State Change Channels 9-16 (COSS=1) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function COSS[16] COSS[15] COSS[14] COSS[13] COSS[12] COSS[11] COSS[10] COSS[9] Default X X X X X X X X
The bits in this register are valid when the COSS bit is a logic 1. COSS[16:9]: The COSS[16:9] bits indicate a signaling state change in channels 9 - 16. A logic 1 in a bit position indicates a change of signaling state in the corresponding channel since the last time this register was read; a logic 0 in a bit position indicates that no signaling state change has occurred. These bits are cleared when this register is read.
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135
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H: SIGX Channel Indirect Data Buffer (COSS = 0) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D7 D6 D5 D4 D3 D2 D1 D0 Default X X X X 0 0 0 0
These registers contain either the data to be written into the internal SIGX registers when a write request is initiated or the data read from the internal SIGX registers when a read request has completed. During normal operation, if data is to be written to the internal registers, the byte to be written must be written into this Data register before the target register's address and R/WB=0 is written into the Address/Control register, initiating the access. If data is to be read from the internal registers, only the target register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data bits.
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136
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H: SIGX Signaling State Change Channels 1-8 (COSS=1) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function COSS[8] COSS[7] COSS[6] COSS[5] COSS[4] COSS[3] COSS[2] COSS[1] Default X X X X X X X X
The bits in this register are valid when the COSS bit is a logic 1. COSS[8:1]: The COSS[8:1] bits indicate a signaling state change in channels 1 - 8. A logic 1 in a bit position indicates a change of signaling state in the corresponding channel since the last time this register was read; a logic 0 in a bit position indicates that no signaling state change has occurred. These bits are cleared when this register is read. The internal registers of the SIGX control the per-DS0 functions on the ingress signaling data and allow the P to read the channel's current signaling state. The address bit A6 selects whether a channel's configuration data register is to be accessed (A6=1) or whether a channel's signaling data register is to be accessed. The channel registers are allocated within the SIGX as follows:
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137
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 4 20H 21H * * 36H 37H 38-3FH 40H 41H 42H * * 56H 57H 58-5FH
- SIGX Indirect Memory Map Channel 1 Signaling Data Channel 2 Signaling Data * * Channel 23 Signaling Data Channel 24 Signaling Data Ignored Channel 1 Per-DS0 Configuration Data Channel 2 Per-DS0 Configuration Data Channel 3 Per-DS0 Configuration Data * * Channel 23 Per-DS0 Configuration Data Channel 24 Per-DS0 Configuration Data Ignored
The bits within each channel register byte are allocated as follows:
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138
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
SIGX Internal Registers 20-37H: Signaling Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type Function Unused Unused Unused Unused A B C D
When the Signaling Data registers are read, the byte returned contains the 4 signaling bits in the 4 least significant bit positions. If SF framing format is selected then C=A and D=B. The bits read correspond to the signaling state extracted from the third to last superframe received. When reading the extracted signaling data for a channel with signaling state debounce enabled, the signaling data returned is the debounced version, meaning that the signaling state value for that channel must have been the same for two consecutive superframes before it was allowed to propagate through the signaling buffers and be visible in the signaling data registers. If the state was not the same, the current state (accessible via these registers) is not changed.
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139
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Signaling data is not available for one full signaling multi-frame after the COSS[x] indication is available. If the signaling data is needed in the same signaling multiframe that the COSS indication is available, the following registers can be read.
TimeSlot
SIGX Address 10H 11H 1EH 1FH
Bit Mask F0H F0H F0H
Timeslot
SIGX Address 10H 11H 16H 17H Reserved
Bit Mask 0FH 0FH 0FH 0FH
1 2 15 16
17 18 23 24
F0H
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140
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
SIGX Internal Registers 40-57H: Per-DS0 Configuration Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIX: The FIX bit controls whether the signaling bit (the least significant bit of the DS0 channel on ID[x] during each signaling frame) is fixed to the polarity specified by the POL bit. A logic 1 in the FIX position enables bit fixing; a logic 0 in the FIX position disables bit fixing. Note that the RPSC functions (inversion, digital milliwatt code insertion, trunk conditioning, and PRBS detection or insertion) take place after bit fixing. POL: The POL bit selects the logic level the signaling bit is fixed to when bit fixing is enabled. When POL is a logic 1, the signaling is fixed to logic 1. When POL is a logic 0, the signaling is fixed to logic 0. DEB: The DEB bit controls whether a channel's signaling bits are to be debounced. Debouncing requires that the signaling bits be in the same state for two successive superframes before the signaling bits are changed to that state. Type R/W R/W R/W R/W R/W R/W R/W R/W Function Unused Unused Unused Unused Unused FIX POL DEB
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141
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H: XBAS Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MTRK: The MTRK bit forces trunk conditioning, idle code substitution and signaling conditioning, on all channels when MTRK is a logic 1. This has the same effect as setting the IDLE_DS0 bit in the Egress Control byte and the SIG0 bit in the Signaling Control byte for all channels, except that the ECLK[x] output is unaffected in NxDS0 mode. Signalling conditioning only occurs if SIGC[1] is logic 1 in the TPSC Internal Signaling Control register for the channel in question. ESF: The ESF bit selects either Extended Superframe format or standard superframe format. A logic 1 selects ESF, a logic 0 selects SF. ZCS[1:0]: The ZCS[1:0] bits select the Zero Code Suppression format to be used. These bits are logically ORed with the ZCS[1:0] bits in the TPSC per-DS0 Egress Control byte. The bits are encoded as follows: ZCS1 0 ZCS0 0 Zero Code Suppression Format None Type R/W R/W R/W R/W R/W R/W R/W R/W Function MTRK Reserved Reserved ESF Reserved Reserved ZCS1 ZCS0 Default 0 0 0 0 0 0 0 0
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142
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
ZCS1 0
ZCS0 1
Zero Code Suppression Format GTE Zero Code Suppression (Bit 8 of an all zero channel byte is replaced by a one, except in signaling frames where bit 7 is forced to a one.) Reserved (do not use) Bell Zero Code Suppression (Bit 7 of an all zero channel byte is replaced by a one.)
1 1
0 1
Reserved: The reserved bits must be set to logic 0 for correct operation.
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143
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H: XBAS Alarm Transmit Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W Type Function Unused Unused Unused Unused Unused Unused XYEL Reserved Default X X X X X X 0 0
These registers control the transmission of Yellow alarm. XYEL: The XYEL bit enables the XBAS to generate a Yellow alarm in the appropriate framing format. When XYEL is set to logic 1, framer is enabled to set bit 2 of each channel to logic 0 for SF format, or the framer is enabled to transmit repetitions of 1111111100000000 (the Yellow Alarm BOC) on the FDL for ESF format. When XYEL is set to logic 0, XBAS is disabled from generating the Yellow alarm.
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144
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H: XIBC Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN: The EN bit controls whether the Inband Code is transmitted or not. A logic 1 in the EN bit position enables transmission of inband codes; a logic 0 in the EN bit position disables inband code transmission. UF: The UF bit controls whether the code is transmitted framed or unframed. A logic 1 in the UF bit position selects unframed inband code transmission; a logic 0 in the UF bit position selects framed inband code transmission. Note: the UF register bit controls the XBAS directly and is not qualified by the EN bit. When UF is set to logic 1, the XBAS is disabled and no framing is inserted regardless of the setting of EN. The UF bit should only be written to logic 1 when the EN bit is set, and should be cleared to logic 0 when the EN bit is cleared. R/W R/W Type R/W R/W Function EN UF Unused Unused Unused Unused CL1 CL0 Default 0 0 X X X X 0 0
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145
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
CL1, CL0: The bit positions CL[1:0] (bits 1 & 0) of this register indicate the length of the inband loopback code sequence, as follows: CL1 0 0 1 1 CL0 0 1 0 1 Code Length 5 6 7 8
Codes of 3 or 4 bits in length may be accommodated by treating them as half of a double-sized code (i.e. a 3-bit code would use the 6-bit code length setting).
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146
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H: XIBC Loopback Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 Default X X X X X X X X
These registers contain the inband loopback code pattern to be transmitted. The code is transmitted most significant bit (IBC7) first, followed by IBC6 and so on. The code, regardless of the length, must be aligned with the MSB always in the IBC7 position (e.g., a 5-bit code would occupy the IBC7 through IBC2 bit positions). To transmit a 3-bit or a 4-bit code pattern, the pattern must be paired to form a double-sized code (i.e., the 3-bit code '011' would be written as the 6bit code '011011'). When the TOCTL is reset, the contents of this register are not affected.
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147
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H: PMON Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R R Type Function Unused Unused Unused Unused Unused INTE XFER OVR Default X X X X X 0 0 0
These registers contain status information indicating when counter data has been transferred into the holding registers and indicating whether the holding registers have been overrun. INTE: The INTE bit controls the generation of a microprocessor interrupt when the transfer clock has caused the counter values to be stored in the holding registers. A logic 1 bit in the INTE position enables the generation of an interrupt ; a logic 0 bit in the INTE position disables the generation of an interrupt. If the AUTOUPDATE bit is set in the Receive Line Options register, then INTE should be set, causing the XFER interrupt to occur every second, indicating that the PMON registers have been updated. XFER: The XFER bit indicates that a transfer of counter data has occurred. A logic 1 in this bit position indicates that a latch request, initiated by writing to one of the counter register locations, by writing to the Revision/Chip ID/Global PMON Update register (address 00CH) or via the AUTOUPDATE function, was received and a transfer of the counter values has occurred. A logic 0 indicates that no transfer has occurred. The XFER bit is cleared (acknowledged) by reading this register.
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148
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
OVR: The OVR bit is the overrun status of the holding registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFER being logic 1) has not been acknowledged before the next transfer clock has been issued and that the contents of the holding registers have been overwritten. A logic 0 indicates that no overrun has occurred. The OVR bit is cleared by reading this register. Registers 04A-04FH, 0CA-0CFH, 14A-14FH, 1CA-1CFH, 24A-24FH, 2CA2CFH, 34A-34FH, 3CA-3CFH: Latching Performance Data The Performance Data registers for a single framer are updated as a group by writing to any of the PMON count registers. A write to one (and only one) of these locations loads performance data located in the PMON into the internal holding registers. Alternately, the Performance Data registers for all eight framers are updated by writing to the Revision/Chip ID/Global PMON Update register (address 00CH). A third update option is to set the AUTOUPDATE bit in the Receive Line Options register, which causes the PMON to be updated automatically every second (or, more precisely, every 8000 frames). The data contained in the holding registers can then be subsequently read by microprocessor accesses into the PMON count register address space. The latching of count data, and subsequent resetting of the counters, is synchronized to the internal event timing so that no events are missed. The PMON is loaded with new performance data within 3.5 receive line clock, RLCLK[x], periods of the latch performance data register write. With nominal line rates, the PMON registers should not be polled until 2.3 sec have elapsed from the "latch performance data" register write. When the TOCTL is reset, the contents of the PMON count registers are unknown until the first latching of performance data is performed.
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149
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 04AH, 0CAH, 14AH 1CAH, 24AH, 2CAH, 34AH, AND 3CAH: PMON BEE Count (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function BEE7 BEE6 BEE5 BEE4 BEE3 BEE2 BEE1 BEE0 Default X X X X X X X X
These registers contain the lower eight bits of the 12-bit Bit Error event counter. A Bit Error event is defined as a CRC-6 error in ESF format, or a framing bit error in SF format.
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150
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 04BH, 0CBH, 14BH 1CBH, 24BH, 2CBH, 34BH, AND 3CBH: PMON BEE Count (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type Function Unused Unused Unused Unused BEE11 BEE10 BEE9 BEE8 Default X X X X X X X X
These registers contain the upper four bits of the 12-bit Bit Error event counter. A Bit Error event is defined as a CRC-6 error in ESF format, or a framing bit error in SF format.
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151
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH: PMON FER Count (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function FER7 FER6 FER5 FER4 FER3 FER2 FER1 FER0 Default X X X X X X X X
These registers contain the lower eight bits of the 9-bit Framing Bit Error event counter.
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152
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH: PMON FER Count (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Type Function Unused Unused Unused Unused Unused Unused Unused FER8 Default X X X X X X X X
These registers contain the upper bit of the 9-bit Framing Bit Error event counter.
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153
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH: PMON OOF Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R Type Function Unused Unused Unused OOF4 OOF3 OOF2 OOF1 OOF0 Default X X X X X X X X
These registers contain the value of the 5 bit Out Of Frame event counter.
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154
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH: PMON COFA Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R Type Function Unused Unused Unused Unused Unused COFA2 COFA1 COFA0 Default X X X X X X X X
These registers contain the value of the 3 bit counter accumulating Change of Frame Alignment events.
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155
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H: RPSC Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W Type Function Unused Unused Unused Unused Unused Unused IND PCCE Default X X X X X X 0 0
These registers allow selection of the microprocessor read access type and output enable control for the Receive Per-DS0 Serial Controller. The RPSC allows data and signaling trunk conditioning to be applied on the receive DS-1 stream on a per-DS0 basis. It also allows per-DS0 control of data inversion, data extraction (when the NxDS0 interface is enabled), and the detection or generation of pseudo-random or repetitive patterns. More information on using the RPSC is available in the Operations section IND: The IND bit controls the microprocessor access type: either indirect or direct. The IND bit must be set to logic 1 for proper operation. When the TOCTL is reset, the IND bit is set low, disabling the indirect access mode. PCCE: The PCCE bit enables the per-DS0 functions. When the PCCE bit is set to a logic 1, the Data Trunk Conditioning Code byte is enabled to modify the ingress data stream, ID[x], under direction of each channel's Ingress Control byte. When the PCCE bit is set to logic 0, the per-DS0 functions are disabled. The RPSC per-channel functions overwrite the data after the ELST, and thus overwrite the ELST trouble code when the framer is OOF.
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156
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H: RPSC P Access Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R Function BUSY Unused Unused Unused Unused Unused Unused Unused Default 0 X X X X X X X
The BUSY bit in the Status register is high while a P access request is in progress. The BUSY bit goes low timed to an internal high-speed clock rising edge after the access has been completed. During normal operation, the Status Register should be polled until the BUSY bit goes low before another P access request is initiated. A P access request is typically completed within 640 ns.
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157
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H: RPSC Channel Indirect Address/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function R/WB A6 A5 A4 A3 A2 A1 A0 Default 0 0 0 0 0 0 0 0
These registers allow the P to access the internal RPSC registers addressed by the A[6:0] bits and perform the operation specified by the R/WB bit. Writing to this register with a valid address and R/WB bit initiates an internal P access request cycle. The R/WB bit selects the operation to be performed on the addressed register: when R/WB is set to a logic 1, a read from the internal RPSC register is requested; when R/WB is set to a logic 0, a write to the internal RPSC register is requested.
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158
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H: RPSC Channel Indirect Data Buffer Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D7 D6 D5 D4 D3 D2 D1 D0 Default 0 0 0 0 0 0 0 0
These registers contain either the data to be written into the internal RPSC registers when a write request is initiated or the data read from the internal RPSC registers when a read request has completed. During normal operation, if data is to be written to the internal registers, the byte to be written must be written into this Data register before the target register's address and R/WB=0 is written into the Address/Control register, initiating the access. If data is to be read from the internal registers, only the target register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data byte. The internal RPSC registers control the per-DS0 functions on the ingress data, and provide the per-DS0 data trunk conditioning code. The functions are allocated within the registers as follows:
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159
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
01H 02H
* *
Ingress Control byte for Channel 1 Ingress Control byte for Channel 2
* *
17H 18H 19H 1AH
* *
Ingress Control byte for Channel 23 Ingress Control byte for Channel 24 Data Trunk Conditioning byte for Channel 1 Data Trunk Conditioning byte for Channel 2
* *
2FH 30H 31H 32H
* *
Data Trunk Conditioning byte for Channel 23 Data Trunk Conditioning byte for Channel 24 Signaling Trunk Conditioning byte for Channel 1 Signaling Trunk Conditioning byte for Channel 2
* *
47H 48H
Signaling Trunk Conditioning byte for Channel 23 Signaling Trunk Conditioning byte for Channel 24
The bits within each control byte are allocated as follows:
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160
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
RPSC Internal Registers 01-18H: Ingress Control byte Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INVERT: When the INVERT bit is set to a logic 1, data output on the ID[x] pin is the bit inverse of the received data for the duration of that channel. SIGNINV: When the SIGNINV bit is set to logic 1, the most significant bit of the data output on the ID[x] pin in the inverse of the received data most significant bit for that channel. INVERT 0 1 0 1 SIGNINV 0 0 1 1 Effect on PCM Channel Data PCM Channel data is unchanged All 8 bits of the PCM channel data are inverted Only the MSB of the PCM channel data is inverted (SIGN bit inversion) All bits EXCEPT the MSB of the PCM channel data is inverted (Magnitude inversion) Type R/W R/W R/W R/W R/W R/W Function INVERT DTRKC DMW SIGNINV TEST EXTRACT Unused Unused Default
DTRKC: When the DTRKC bit is set to a logic 1, data from the Data Trunk Conditioning Code Byte replaces the receive data for the duration of that channel.
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161
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
DMW: When the DMW bit is set to a logic 1, the digital milliwatt pattern replaces the ID[x] output data for the duration of that channel. TEST: When the TEST bit is set to a logic 1, receive data is either overwritten with a test pattern from the PRGD block or is routed to the PRGD block and compared against an expected test pattern. The RXPATGEN bit in the Pattern Generator/Detector Positioning/Control register determines whether the receive data is overwritten or compared as shown in the following table: TEST 0 1 1 RXPATGEN Description X 0 1 Channel data is not included in test pattern Channel data is routed to PRGD and compared against expected test pattern Channel data is overwritten with PRGD test pattern
Pattern generation/detection can be enabled to work on only the first 7 bits of a channel (for Nx56 kbps fractional T1) using the Nx56k_DET and Nx56k_GEN bits in the Pattern Generator/Detector Positioning/Control register (Reg. 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH). The PRGD can also be enabled to detect patterns in the entire DS1, including framing bits, using the UNF_DET bit in the Pattern Generator/Detector Positioning/Control register. More information on using the PRGD is available in the Operations section. EXTRACT: When the NxDS0 mode is active, EXTRACT controls the generation of ICLK[x]. When EXTRACT is a logic 1, channel data is extracted to the ingress interface and eight clock pulses are generated on ICLK[x]. When EXTRACT is a logic 0, ICLK[x] is suppressed for the duration of that channel. Data inversion, data trunk conditioning, digital milliwatt pattern insertion, and test pattern insertion are performed independent of the received framing format. Digital milliwatt pattern insertion has the highest priority. Data trunk conditioning takes precedence over the test pattern insertion which, in turn, takes precedence over data inversion. When test pattern checking is enabled, the receive data is compared before data trunk conditioning or data inversion is performed.
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162
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
RPSC Internal Registers 19-30H: Data Trunk Conditioning Code byte Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function DTRK7 DTRK6 DTRK5 DTRK4 DTRK3 DTRK2 DTRK1 DTRK0
The contents of the Data Trunk Conditioning Code byte register is substituted for the channel data on ID[x] when the DTRKC bit in the Ingress Control Byte is set to a logic 1. The Data Trunk Conditioning Code is transmitted from MSB (DTRK7) to LSB (DTRK0).
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163
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
RPSC Internal Registers 31-48H: Signaling Trunk Conditioning byte Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W Function STRKC Unused Unused Unused A' B' C' D' Default
The contents of the Signaling Trunk Conditioning Code byte register is substituted for the channel signaling data on ISIG[x] when the STRKC bit is set to a logic 1. The Signaling Trunk Conditioning Code is placed in least significant nibble of the channel byte.
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164
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H: RDLC Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type Function Unused Unused Unused Reserved MEN MM TR EN Default X X X 0 0 0 0 0
The RDLC is a microprocessor peripheral used to receive HDLC frames on the 4kHz ESF facility data link. More information on using the RDLC can be found in the Operations section. EN: The EN bit controls the overall operation of the RDLC. When EN is set to logic 1, RDLC is enabled; when set to logic 0, RDLC is disabled. TR: Setting the terminate reception (TR) bit to logic 1 forces the RDLC to immediately terminate the reception of the current data frame, empty the RDLC FIFO buffer, clear the interrupts, and begin searching for a new flag sequence. The RDLC handles a terminate reception event in the same manner as it would the toggling of the EN bit from logic 1 to logic 0 and back to logic 1. Thus, the RDLC state machine will begin searching for flags. An interrupt will be generated when the first flag is detected. The TR bit will reset itself to logic 0 after the register write operation is completed and a rising and falling edge occurs on the internal datalink clock input. If the RDLC Configuration Register is read after this time, the TR bit value returned will be logic 0. MEN: Setting the Match Enable (MEN) bit to logic 1 enables the detection and storage in the RDLC FIFO of only those packets whose first data byte
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165
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
matches either of the bytes written to the Primary or Secondary Match Address Registers, or the universal all ones address. When the MEN bit is logic 0, all packets received are written into the RDLC FIFO. MM: Setting the Match Mask (MM) bit to logic 1 ignores the PA[1:0] bits of the Primary Address Match Register, the SA[1:0] bits of the Secondary Address Match Register, and the two least significant bits of the universal all ones address when performing the address comparison. Reserved: This register bit should be set to logic 0 for proper operation.
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166
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H: RDLC Interrupt Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTC [6:0]: The INTC[6:0] bits control the assertion of FIFO fill level set point interrupts. Whenever the number of bytes in the RDLC FIFO exceeds the value of INTC[6:0], INTR is set to logic 1 and, if INTE is set, an interrupt will be generated. This interrupt persists until the RDLC FIFO becomes empty. A value of 0 in INTC[6:0] is interpreted as decimal 128. INTE: The Interrupt Enable bit (INTE) must set to logic 1 to allow the internal interrupt status to be propagated to the INTB output. When the INTE bit is logic 0 the RDLC will not assert INTB. The contents of the Interrupt Control Register should only be changed when the EN bit in the RDLC Configuration Register is logic 0. This prevents any erroneous interrupt generation. Type R/W R/W R/W R/W R/W R/W R/W R/W Function INTE INTC[6] INTC[5] INTC[4] INTC[3] INTC[2] INTC[1] INTC[0] Default 0 0 0 0 0 0 0 0
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167
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H: RDLC Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function FE OVR COLS PKIN PBS[2] PBS[1] PBS[0] INTR Default X X X X X X X X
The RDLC Status and Data registers should not be accessed at a rate greater than 1/15 of the XCLK rate. INTR: The interrupt (INTR) bit reflects the status of the internal RDLC interrupt. If the INTE bit in the RDLC Interrupt Control Register is set to logic 1, a RDLC interrupt (INTR is a logic 1) will cause INTB to be asserted low. The INTR register bit will be set to logic 1 when one of the following conditions occurs: 1. the number of bytes specified in the RDLC Interrupt Control register have been received on the data link and written into the FIFO 2. RDLC FIFO buffer overrun has been detected 3. the last byte of a packet has been written into the RDLC FIFO 4. the last byte of an aborted packet has been written into the RDLC FIFO 5. transition of receiving all ones to receiving flags has been detected. If INTR is logic 1 due to condition 1, then INTR will be cleared at the start of the next Data Register read that results in an empty FIFO buffer. This is independent of the FIFO buffer fill level for which the interrupt is programmed. If INTR is logic 1 due to conditions 2,3,4, or 5 then INTR is cleared by a read of this register. INTR may always be forced low by setting the EN bit low in the RDLC Configuration register, disabling the RDLC, or by setting the TR bit high in the
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168
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
RDLC Configuration register, forcing RDLC to terminate reception of the current packet and empty the FIFO. PBS[2:0]: The packet byte status (PBS[2:0]) bits indicate the status of the data last read from the FIFO as indicated in the following table: PBS[2:0] 000 001 Data Status The data byte read from the FIFO is not special. The data byte read from the FIFO is the dummy byte that was written into the FIFO when the first HDLC flag sequence (01111110) was detected. This indicates that the data link became active. The data byte read from the FIFO is the dummy byte that was written into the FIFO when the HDLC abort sequence (01111111) was detected. This indicates that the data link became inactive. Unused. The data byte read from the FIFO is the last byte of a normally terminated packet with no CRC error and the packet received had an integer number of bytes. The data byte read from the FIFO must be discarded because there was a noninteger number of bytes in the packet. The data byte read from the FIFO is the last byte of a normally terminated packet with a CRC error. The packet was received in error. The data byte read from the FIFO is the last byte of a normally terminated packet with a CRC error and a non-integer number of bytes. The packet was received in error.
010
011 100
101
110
111
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169
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
PKIN: The Packet In (PKIN) bit is logic 1 when the last byte of a non-aborted packet is written into the FIFO. The PKIN bit is cleared to logic 0 after the RDLC Status Register is read. COLS: The Change of Link Status (COLS) bit is set to logic 1 if the RDLC has detected the HDLC flag sequence (01111110) or HDLC abort sequence (01111111) in the data. This indicates that there has been a change in the data link status. The COLS bit is cleared to logic 0 by reading this register or by clearing the EN bit in the RDLC Configuration Register. For each change in link status, a byte is written into the FIFO. If the COLS bit is found to be logic 1 then the RDLC FIFO must be read until empty. The status of the data link is determined by the PBS[2:0] bits associated with the data read from the RDLC FIFO. OVR: The overrun (OVR) bit is set to logic 1 when data is written over unread data in the RDLC FIFO buffer. This bit is not reset to logic 0 until after the Status Register is read. While the OVR bit is logic 1, the RDLC and RDLC FIFO buffer are held in the reset state, causing the COLS and PKIN bits to be reset to logic 0. FE: The FIFO buffer empty (FE) bit is set to logic 1 when the last RDLC FIFO buffer entry is read. The FE bit goes to logic 0 when the FIFO is loaded with new data.
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170
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H: RDLC Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] Default X X X X X X X X
The RDLC Status and Data registers should not be accessed at a rate greater than 1/15 of the XCLK rate. RD[7:0]: RD[7:0] contains the received data link information. RD[0] corresponds to the first received bit of the data link message. This register reads from the RDLC 128-byte FIFO buffer. If data is available, the FE bit in the RDLC Status Register is logic 0. When an overrun is detected, an interrupt is generated and the FIFO buffer is held cleared until the RDLC Status Register is read.
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171
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H: RDLC Primary Address Match Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA[7:0]: The first byte received after a flag character is compared against the contents of this register. If a match occurs, the packet data, including the matching first byte, is written into the FIFO. PA[0] corresponds to the first received bit of the data link message. The MM bit in the Configuration Register is used mask off PA[1:0] during the address comparison. Type R/W R/W R/W R/W R/W R/W R/W R/W Function PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] Default 1 1 1 1 1 1 1 1
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172
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 059H, 0D9H, 159H, 1D9H, 259H, 2D9H, 359H, 3D9H: RDLC Secondary Address Match Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SA[7:0]: The first byte received after a flag character is compared against the contents of this register. If a match occurs, the packet data, including the matching first byte, is written into the FIFO. SA[0] corresponds to the first received bit data link message. The MM bit in the Configuration Register is used mask off SA[1:0] during the address comparison. Type R/W R/W R/W R/W R/W R/W R/W R/W Function SA[7] SA[6] SA[5] SA[4] SA[3] SA[2] SA[1] SA[0] Default 1 1 1 1 1 1 1 1
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173
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Registers 05DH, 0DDH, 15DH, 1DDH, 25DH, 2DDH, 35DH, 3DDH: XBOC Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W Type Function Unused Unused BC[5] BC[4] BC[3] BC[2] BC[1] BC[0] Default X X 1 1 1 1 1 1
These registers enables the XBOC to generate a bit oriented code and selects the 6-bit code to be transmitted. When this register is written with any 6-bit code other than 111111, that code will be transmitted repeatedly in the ESF Facility Data Link with the format 111111110[BC0][BC1][BC2][BC3][BC4][BC5]0, overwriting any HDLC packets currently being transmitted. When the register is written with 111111, the XBOC is disabled.
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174
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H: PRGD Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PDR[1] PDR[0] QRSS PS TINV RINV AUTOSYNC MANSYNC Default 0 0 0 0 0 0 1 0
The PRGD provides test pattern generation, detection, and monitoring. More information on using PRGD can be found in the Operations section. PDR[1:0]: The PDR[1:0] bits select the contents of the four pattern detector registers (at addresses 6CH to 6FH in each octant) to be any one of the pattern receive registers, the error count holding registers, or the bit count holding registers. The selection is shown in the following table: PDR[1:0] 00, 01 10 11 PDR#1 PDR#2 PDR#3 Pattern Receive Error Count Bit Count PDR#4 Pattern Receive (MSB) Error Count (MSB) Bit Count (MSB)
Pattern Receive Pattern (LSB) Receive Error Count (LSB) Bit Count (LSB) Error Count Bit Count
QRSS: The QRSS bit enables the zero suppression feature required when generating the QRSS sequence. When QRSS is a logic 1, a one is forced in the TDAT stream when the following 14 bit positions are all zeros. When QRSS is a logic 0, the zero suppression feature is disabled.
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175
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
PS: The PS bit selects the pattern type. When PS is a logic 1, a repetitive pattern is generated/detected. When PS is a logic 0, a pseudo-random pattern is generated/detected. The PS Bit must be programmed to the desired setting before programming any other PRGD registers, otherwise the transmitted pattern may be corrupted. Any time the setting of the PS bit is changed, the PRGD Pattern Insertion Registers should be reprogrammed. TINV: The TINV bit controls the logical inversion of the generated data stream. When TINV is a logic 1, the data is inverted. When TINV is a logic 0, the data is not inverted RINV: The RINV bit controls the logical inversion of the receive data stream before processing. When RINV is a logic 1, the received data is inverted before being processed by the pattern detector. When RINV is a logic 0, the received data is not inverted AUTOSYNC: The AUTOSYNC bit enables the automatic resynchronization of the pattern detector. When AUTOSYNC is logic 1, then the PRGD will search in the receive data stream until it finds 48 consecutive bits in which the pattern is present and error-free. The PRGD will then declare SYNCV = 1. Thereafter, the PRGD will automatically initiate a resynchronization when 10 or more bit errors are detected in a fixed 48 bit window. When AUTOSYNC is a logic 0, then the PRGD will search in the data stream in the same way. However, once SYNCV=1 has been declared, resynchronization will only be initiated by a 0 to 1 transition on MANSYNC. SYNCV will still be asserted and deasserted in the usual way, but the PRGD will not initiate a search for the new pattern alignment. MANSYNC: The MANSYNC bit is used to manually initiate a resynchronization of the pattern detector. A low to high transition on MANSYNC initiates the resynchronization.
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176
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H: PRGD Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SYNCE: The SYNCE bit enables the generation of an interrupt when the pattern detector changes synchronization state. When SYNCE is set to logic 1, the interrupt is enabled. BEE: The BEE bit enables the generation of an interrupt when a bit error is detected in the receive data. Bit errors are not flagged unless the pattern detector is synchronized. When BEE is set to logic 1, the interrupt is enabled. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the receive pattern registers, the bit counter holding registers, and the error counter holding registers. When XFERE is set to logic 1, the interrupt is enabled. PMON and PRGD transfer values in the same number of clock cycles, so as long as both are being updated at once, only one interrupt need be used. SYNCV: The SYNCV bit indicates the synchronization state of the pattern detector. When SYNCV is a logic 1 the pattern detector is synchronized (the pattern detector has observed at least 48 consecutive error free bit periods). When Type R/W R/W R/W R R R R R Function SYNCE BEE XFERE SYNCV SYNCI BEI XFERI OVR Default 0 0 0 X X X X X
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177
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
SYNCV is a logic 0, the pattern detector is out of sync (the pattern detector has detected 10 or more bit errors in a fixed 48 bit window). SYNCI: The SYNCI bit indicates that the detector has changed synchronization state since the last time this register was read. If SYNCI is logic 1, then the pattern detector has gained or lost synchronization at least once. SYNCI is set to logic 0 when this register is read. BEI: The BEI bit indicates that one or more bit errors have been detected since the last time this register was read. When BEI is set to logic 1, at least one bit error has been detected. Bit errors are not flagged unless the pattern detector is synchronized. BEI is set to logic 0 when this register is read. XFERI: The XFERI bit indicates that a transfer of pattern detector data has occurred. A logic 1 in this bit position indicates that the pattern receive registers, the bit counter holding registers and the error counter holding registers have been updated. This update is initiated by writing to one of the pattern detector register locations, or by writing to the Revision/Chip ID/Global PMON Update register (00CH), or via the AUTOUPDATE feature in the Receive Line Options Register (000H, 080H, 100H, 180H, 200H, 280H, 300H, 480H). XFERI is set to logic 0 when this register is read. OVR: The OVR bit is the overrun status of the pattern detector registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFERI being logic 1) has not been acknowledged before the next accumulation interval has occurred and that the contents of the pattern receive registers, the bit counter holding registers and the error counter holding registers have been overwritten. OVR is set to logic 0 when this register is read.
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178
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H: PRGD Length Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PL[4:0]: PL[4:0] determine the length of the generated pseudo random or repetitive pattern. The pattern length is equal to the value of PL[4:0] + 1. R/W R/W R/W R/W R/W Type Function Unused Unused Unused PL[4] PL[3] PL[2] PL[1] PL[0] Default X X X 0 0 0 0 0
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179
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 063H, 0E3H, 163H, 1E3H, 263H, 2E3H, 363H, 3E3H: PRGD Tap Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PT[4:0]: PT[4:0] determine the feedback tap position of the generated pseudo random pattern. The feedback tap position is equal to the value of PT[4:0] + 1. R/W R/W R/W R/W R/W Type Function Unused Unused Unused PT[4] PT[3] PT[2] PT[1] PT[0] Default X X X 0 0 0 0 0
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180
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H: PRGD Error Insertion Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EVENT: A low to high transition on the EVENT bit causes a single bit error to be inserted in the generated pattern. This bit must be cleared and set again for a subsequent error to be inserted. EIR[2:0]: The EIR[2:0] bits control the insertion of a programmable bit error rate as indicated in the following table: EIR[2:0] 000 001 010 011 100 101 110 111 Generated Bit Error Rate No errors inserted 10-1 10-2 10-3 10-4 10-5 10-6 10-7 R/W R/W R/W R/W Type Function Unused Unused Unused Unused EVENT EIR[2] EIR[1] EIR[0] Default X X X X 0 0 0 0
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181
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
In order to prevent single error insertion from interfering with error rate generation, writes to EIR[2:0] do not take effect immediately. Instead, they take effect when the next generated bit error occurs. When using very low error rates and using PRGD in only a few channels, this delay can be significant, since a 10-7 error rate at 64kbps is one error every 156 seconds.
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182
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H: PRGD Pattern Insertion #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PI[7] PI[6] PI[5] PI[4] PI[3] PI[2] PI[1] PI[0] Default 0 0 0 0 0 0 0 0
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183
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H: PRGD Pattern Insertion #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PI[15] PI[14] PI[13] PI[12] PI[11] PI[10] PI[9] PI[8] Default 0 0 0 0 0 0 0 0
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184
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH: PRGD Pattern Insertion #3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PI[23] PI[22] PI[21] PI[20] PI[19] PI[18] PI[17] PI[16] Default 0 0 0 0 0 0 0 0
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185
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH: PRGD Pattern Insertion #4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PI[31:0]: PI[31:0] contain the data that is loaded in the pattern generator each time a new pattern (pseudo random or repetitive) is to be generated. When a pseudo random pattern is to be generated, PI[31:0] should be set to FFFFFFFFH. The data is loaded each time pattern insertion register #4 is written. Pattern insertion registers #1 - #3 should be loaded with the desired data before pattern register #4 is written. When a repetitive pattern is transmitted, PI[31] is transmitted first, followed by the remaining bits in sequence down to PI[0]. Subsequently, PI [pattern_length-1] down to PI[0] will be repetitively transmitted, where pattern_length is the decimal value stored in the PRGD length register. Type R/W R/W R/W R/W R/W R/W R/W R/W Function PI[31] PI[30] PI[29] PI[28] PI[27] PI[26] PI[25] PI[24] Default 0 0 0 0 0 0 0 0
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186
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH: PRGD Pattern Detector #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0] Default 0 0 0 0 0 0 0 0
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187
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 06DH, 0EDH, 16DH, 1EDH, 26DH, 2EDH, 36DH, 3EDH: PRGD Pattern Detector #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PD[15] PD[14] PD[13] PD[12] PD[11] PD[10] PD[9] PD[8] Default 0 0 0 0 0 0 0 0
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188
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 06EH, 0EEH, 16EH, 1EEH, 26EH, 2EEH, 36EH, 3EEH: PRGD Pattern Detector #3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PD[23] PD[22] PD[21] PD[20] PD[19] PD[18] PD[17] PD[16] Default 0 0 0 0 0 0 0 0
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189
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 06FH, 0EFH, 16FH, 1EFH, 26FH, 2EFH, 36FH, 3EFH: PRGD Pattern Detector #4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PD[31:0]: Reading PD[31:0] returns the contents of the pattern detector data register selected by the PDR[1:0] bits in the control register. All three detector data registers are updated during an accumulation interval. When PDR[1:0] is set to 00 or 01, reading PD[31:0] returns the contents of pattern receive register. The 32 bits received immediately before the last accumulation interval are present on PD[31:0]. PD[0] contains the bit received immediately prior to the last accumulation. The pattern receive register is particularly useful for identifying received repetitive patterns. When PDR[1:0] is set to 10, reading PD[31:0] returns the contents of the error counter holding register. The value in this register represents the number of bit errors that were accumulated during the last accumulation interval, up to a maximum (saturation) of 2 32-1. Note that bit errors are not accumulated while the pattern detector is out of sync. When PDR[1:0] is set to 11, reading PD[31:0] returns the contents of the bit counter holding register. The value in this register represents the total number of bits that were received during the last accumulation interval, up to a maximum (saturation) of 232-1. Writing to any of these registers causes them to be updated, and the internal counters reset. The XFERI bit in PRGD Enable/Status register will go high once the update is complete, and an interrupt will be generated if enabled. Type R R R R R R R R Function PD[31] PD[30] PD[29] PD[28] PD[27] PD[26] PD[25] PD[24] Default 0 0 0 0 0 0 0 0
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190
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
12
TEST FEATURES DESCRIPTION Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the TOCTL. Test mode registers (as opposed to normal mode registers) are mapped into addresses 400H-7FFH. Test mode registers may also be used for board testing. When all of the constituent Telecom System Blocks within the TOCTL are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "Test Mode 0" for details). Notes on Test Mode Register Bits: 1. Writing values into unused register bits has no effect. Reading unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2. Writeable test mode register bits are not initialized upon reset unless otherwise noted.
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191
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Register 00BH: TOCTL Master Test Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W W W R/W W R/W Function A_TM[9] A_TM[8] A_TM[7] PMCTST DBCTRL IOTST HIZDATA HIZIO Default X X X X 0 0 0 0
This register is used to select TOCTL test features. All bits, except for PMCTST and A_TM[9:7] are reset to zero by a hardware reset of the TOCTL; a software reset of the TOCTL does not affect the state of the bits in this register. Refer to the Test Features Description section for more information. A_TM[9]: The state of the A_TM[9] bit internally replaces the input address line A[9] when PMCTST is set. This allows for more efficient use of the PMC manufacturing test vectors. A_TM[8]: The state of the A_TM[8] bit internally replaces the input address line A[8] when PMCTST is set. This allows for more efficient use of the PMC manufacturing test vectors. A_TM[7]: The state of the A_TM[7] bit internally replaces the input address line A[7] when PMCTST is set. This allows for more efficient use of the PMC manufacturing test vectors. PMCTST: The PMCTST bit is used to configure the TOCTL for PMC's manufacturing tests. When PMCTST is set to logic 1, the TOCTL microprocessor port becomes the test access port used to run the PMC manufacturing test
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192
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and is cleared by setting CSB to logic 1. DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin. When the DBCTRL bit is set to logic 1, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the TOCTL to drive the data bus and holding the CSB pin low tristates the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. IOTST: The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each block in the TOCTL for board level testing. When IOTST is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequently the device outputs (refer to the "Test Mode 0 Details" in the "Test Features" section). HIZIO,HIZDATA: The HIZIO and HIZDATA bits control the tristate modes of the TOCTL . While the HIZIO bit is a logic 1, all output pins of the TOCTL except the data bus are held in a high-impedance state. The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a highimpedance state which inhibits microprocessor read cycles. 12.1 Test Mode 0 In test mode 0, the TOCTL allows the logic levels on the device inputs to be read through the microprocessor interface, and allows the device outputs to be forced to either logic level through the microprocessor interface. To enable test mode 0, the IOTST bit in the Master Test Register is set to logic 1 and the following addresses must be written with 00H: 411H, 419H, 41DH, 421H, 42BH, 42DH, 431H, 435H, 43DH, 441H, 445H, 449H, 451H, 455H, 45DH, and 461H. Repeat these writes to 491H, 499H, ... , 4E1H, then 511H .. 561H, and so on until all 8 octants have been set up. Reading the following address locations returns the values for the indicated inputs :
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193
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 5
Addr 410H 418H 41CH 444H 490H 498H 49CH 4C4H 510H 518H 51CH 544H 590H 598H 59CH 5C4H 610H 618H 61CH 644H 690H 698H 69CH 6C4H 710H 718H 71CH 744H 790H 798H 79CH 7C4H Bit 7
- Accessing Inputs in Test Mode 0
Bit 6 Bit 5 Bit 4 Bit 3 XCLK XCLK CIFP CECLK CICLK CEFP ESIG[1] XCLK XCLK CIFP CECLK CICLK CEFP ESIG[2] XCLK XCLK CIFP CECLK CICLK CEFP ESIG[3] XCLK XCLK CIFP CECLK CICLK CEFP ESIG[4] XCLK XCLK CIFP CECLK CICLK CEFP ESIG[5] XCLK XCLK CIFP CECLK CICLK CEFP ESIG[6] XCLK XCLK CIFP CECLK CICLK CEFP ESIG[7] XCLK XCLK CIFP CECLK CICLK CEFP ESIG[8] ED[8] RLCLK[8] CTCLK ED[7] RLD[8] RLCLK[7] CTCLK ED[6] RLD[7] RLCLK[6] CTCLK ED[5] RLD[6] RLCLK[5] CTCLK ED[4] RLD[5] RLCLK[4] CTCLK ED[3] RLD[4] RLCLK[3] CTCLK ED[2] RLD[3] RLCLK[2] CTCLK ED[1] RLD[2] Bit 2 RLCLK[1] CTCLK Bit 1 Bit 0 RLD[1]
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194
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Writing the following address locations forces the outputs to the value in the corresponding bit position: Table 6
Addr 418H 41CH 440H 498H 49CH 4C0H 518H 51CH 540H 598H 59CH 5C0H 618H 61CH 640H 698H 69CH 6C0H 718H 71CH 740H 798H 79CH 7C0H INT1 INT1 ID[8]2 INT1 INT1 ID[7]2 TLCLK[8] IFP[8] ISIG[8] INT1 INT1 ID[6]2 TLCLK[7] IFP[7] ISIG[7] TLD[8] INT1 INT1 ID[5]2 TLCLK[6] IFP[6] ISIG[6] TLD[7] INT1 INT1 ID[4]2 TLCLK[5] IFP[5] ISIG[5] TLD[6] INT1 INT1 ID[3]2 TLCLK[4] IFP[4] ISIG[4] TLD[5] INT1 INT1 ID[2]2 TLCLK[3] IFP[3] ISIG[3] TLD[4] Bit 7 INT1 INT1 ID[1]2 TLCLK[2] IFP[2] ISIG[2] TLD[3]
- Controlling Outputs in Test Mode 0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TLCLK[1] IFP[1] ISIG[1] TLD[2] Bit 1 Bit 0 TLD[1]
Notes: 1. Writing a logic 1 to any of the block interrupt signals asserts the INTB output low. In order to force INT high-impedance, registers 410 .. 461 in each octant must initially be cleared.
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195
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
2. In order for bit 2 of this register to control ID[x], bit 3 of this register must be written logic 0. The bidirectional pins ESIG[x]/ECLK[x]/EFP[x] are inputs while IOTST is set.
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196
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
12.2
JTAG Test Port The TOCTL JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP device input logic levels can be read, device outputs can be , forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section. Instruction Register Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111
Identification Register Length - 32 bits Version number - 1H for Rev. E, 0H for Rev. C. Part Number - 4388H Manufacturer's identification code - 0CDH Device identification - 143880CDH for Rev. E ( 043880CDH for Rev. C.)
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197
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 7
- Boundary Scan Register
Length - 120 bits Pin/ Enable HIZ 2,3 RLD1 RLCLK1 RLD2 RLCLK2 RLD3 RLCLK3 RLD4 RLCLK4 TLD1 TLCLK1 TLD2 TLCLK2 TLD3 TLCLK3 TLD4 TLCLK4 TLD5 TLCLK5 TLD6 TLCLK6 TLD7 TLCLK7 TLD8 Scan Register Bit 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 Pin/ Enable Scan Register Bit D3 D3_OEB 1 D4 D4_OEB 1 D5 D5_OEB 1 D6 D6_OEB 1 D7 D7_OEB 1 ALE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CSB WRB 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 Pin/ Enable Scan Register Bit 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
ISIG3 ID3 IFP2 ISIG2 ID2 IFP1 ISIG1 ID1 ESIG8 ESIG_OEB81 ED8 ESIG7 ESIG_OEB71 ED7 ESIG6 ESIG_OEB61 ED6 ESIG5 ESIG_OEB51 ED5 ESIG4 ESIG_OEB41 ED4 ESIG3
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198
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Pin/ Enable TLCLK8 RLD5 RLCLK5 RLD6 RLCLK6 RLD7 RLCLK7 RLD8 RLCLK8 RSTB INTB D0 D0_OEB 1 D1 D1_OEB 1 D2 D2_OEB 1 Notes:
Scan Register Bit 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
Pin/ Enable Scan Register Bit RDB IFP8 ISIG8 ID8 IFP7 ISIG7 ID7 IFP6 ISIG6 ID5 IFP5 ISIG5 ID5 IFP4 ISIG4 ID4 IFP3 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
Pin/ Enable
Scan Register Bit 14 13 12 11 10 9
1
ESIG_OEB31 ED3 ESIG2 ESIG_OEB21 ED2 ESIG1 ESIG_OEB1 ED1 XCLK CIFP CICLK CEFP CECLK CTCLK
8 7 6 5 4 3 2 1
1. All OEB signals will set the corresponding bidirectional signal to an output when set low. 2. When set high, TLD[8:1], TLCLK[8:1], ID[8:1], ISIG[8:1], IFP[8:1], and INTB will be set to high impedance. 3. HIZ is the first bit in the boundary scan chain.
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199
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
13
FUNCTIONAL TIMING DIAGRAMS Figure 14
IFP[x] ID[x] ICLK[x] Don't Care 123456 78 12345 678
- Ingress Interface Clock Master: NxDS0 Mode
The Ingress Interface Options register is programmed to select NxDS0 mode. The RPSC ingress control bytes are programmed to extract the desired channels. In this example, the ingress control bytes for channels 2 and 24 are configured to extract these channels. ICLK[x] is gapped so that it is only active for those channels with the associated EXTRACT bit set. If either ISFP or ALTIFP is set, then IFP[x] will pulse only during the appropriate frames. When the ICLKRISE register bit is set, then ID[x] is updated on the rising edge of ICLK[x] and the functional timing is described by Figure 14 with ICLK inverted. Figure 15 - Egress Interface Clock Master: NxDS0 Mode
Channel 24 Channel 1
ED[x] ECLK[x]
Don't Care
12 345 678
12 345 678
The Egress Interface Options register is programmed to select NxDS0 mode. The TPSC egress control bytes are programmed to insert the desired channels. In this example, the egress control bytes for channels 1 and 24 are configured to insert these channels. ECLK[x] is gapped so that it is only active for those channels with the associated IDLE_DS0 bit cleared (logic 0). The remaining channels (with IDLE_DS0 set) contain the per-DS0 idle code as defined in the associated Idle Code byte. When the ECLKFALL bit is set to logic 1, then ED[x] is sampled on the falling edge of ECLK, and the functional timing is described by Figure 15 with the ECLK signal inverted.
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200
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 16
IC L K [x] IF P [x] ID [x]
- Ingress Interface Clock Master : Full DS1 Mode
123456 78F1234567812345678
12345678F12345678
C h anne l 24 C h anne l 1 F-bit or P arity
C h an ne l 2
C h anne l 24 C h an ne l 1 F-bit or P arity
The Ingress Interface Options register is programmed to select the Clock Master: Full DS1 mode. IFP[x] is set high for one ICLK[x] period every frame. If ISFP=1, IFP[x] pulses on the superframe frame boundaries (i.e. once every 12 or 24 frame periods). If ALTRFP=1, IFP[x] pulses on every second indication of either the frame or the superframe boundary. Figure 17
TLCLK[x] EFP[x] ED[x]
1 2 3 4 5 6 7 8F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 12 345678F12345678
- Egress Interface : 1.544 MHz Clock Master: Full DS1 Mode
Channel 24 Channel 1 F-bit or Parity
Channel 2
Channel 24 Channel 1 F-bit or Parity
The Egress Interface is configured for the Clock Master: Full DS1 mode by writing 01 binary to EMODE[1:0] in the Egress Options register. ED[x] is clocked in on the rising edge of the TLCLK[x] output. Frame alignment is indicated to an upstream source by EFP[x], which may be configured to indicate frame or superframe alignment via the ESFP bit in the Egress Options Register.
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201
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 18
CICLK CIFP ID[x] ISIG[x]
- Ingress Interface: 1.544MHz Clock Slave Modes
1 2 3 4 5 6 7 8F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 A BCD A BCD A BCD
12 3 45 67 8F1 2 3 45 6 78 A BC D A BCD
Channel 24 Channel 1 F-bit or Parity
Channel 2
Channel 24 Channel 1 F-bit or Parity
The Ingress Interface is programmed for Clock Slave mode by setting the IMODE[1:0] bits to 10 (ICLK Reference) or 11 (external signaling) in the Ingress Interface Options register. ID[x] is timed to the active edge of CICLK, and is frame-aligned to CIFP; CIFP need not be provided every frame. ID[x] and ISIG[x] may be configured to carry a parity bit during the first bit of each frame. In External Signaling Mode, ISIG[x] is active and is aligned as shown. In ICLK Reference mode, ICLK[x] is active in place of ISIG[x]; ICLK is either a jitterattenuated line-rate clock referenced to RLCLK, or an 8 kHz clock generated by dividing the smoothed RLCLK by 193. Figure 19
CE CLK CE FP E D[x] E FP [x] C hannel 24 C hannel 1 F -bit or P arity C hannel 2 C hannel 24 C hannel 1 F -bit or P arity
12 34 5 6 7 8F12 3 45 6 7 8 1 2 34 56 78 12 345678F12345678
- Egress Interface : 1.544 MHz Clock Slave: EFP Enabled mode
The Egress Interface is configured for the Clock Slave: EFP Enabled mode by writing 10 binary to EMODE[1:0] in the Egress Options register. ED[x] is clocked in on the active edge of CECLK. In the illustrated case, the CESFP bit is written to logic 1 in the Egress Options Register, so that CEFP must pulse once every 12 or 24 frames (for SF and ESF, respectively) on the last frame bit of the multiframe. If parity checking is enabled, a parity bit should be inserted on ED[x] in the first bit of each frame. The EFP[x] output will pulse high to mark the F-bit of each frame in order to indicate frame alignment to an upstream device; EFP may be configured to mark superframe alignment instead via the ESFP bit in the Egress Options Register.
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202
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 20 mode
CECLK CEFP ED[x] ESIG[x]
- Egress Interface : 1.544 MHz Clock Slave: External Signaling
1 2 3 4 5 6 7 8F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 A BCD A BCD A BCD
12 3 45 67 8F1 2 3 45 6 78 A BC D A BCD
Channel 24 Channel 1 F-bit or Parity
Channel 2
Channel 24 Channel 1 F-bit or Parity
The Egress Interface is configured for the Clock slave: External Signaling Mode by writing 11 binary to EMODE[1:0] in the Egress Options register. ED[x] is clocked in on the active edge of CECLK. Frame alignment is specified by pulses on CEFP ESIG[x] should carry the signaling bits for each channel in bits 5,6,7 . and 8; the signaling bits will be inserted into the data stream by the transmitter. If the ABXXEN bit is set to logic 1 in the Egress Options register, then the A and B bits will be internally forced onto the C and D positions. If parity checking is enabled, a parity bit should be inserted on ED[x] and ESIG[x] in the first bit of each frame. The parity operates on all bits in the ED[x] and ESIG[x] streams, including the unused bits on ESIG. ABXXEN has no effect on ESIG[x] parity.
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203
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 21
- Ingress Interface: 2.048 MHz Clock Slave Mode
CICLK CIFP ID[x] ISIG[x]
F
Don't Care
1 2 3 4 5 67 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ABCD ABCD ABCD
Don't Care
1 2 34 5 6 7 8 AB C D
Don't Care
Don't Care
F-Bit or Parity
Channel 1
Channel 2
Channel 3
"filler"
Channel 4
CICLK CIFP ID[x] ISIG[x]
Ch24 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch23 Ch 24 Ch1
The Ingress Interface is programmed for Clock Slave mode by stetting the IMODE[1:0] bits to 10 (ICLK Reference) or 11 (external signaling) in the Ingress Interface Options register. The 2.048 MHz internally-gapped clock mode is selected by setting the CICLK2M bit to logic 1 in the Ingress Interface Options. ID[x] is timed to the active edge of CICLK, and is frame-aligned to CIFP; CIFP need not be provided every frame. ID[x] and ISIG[x] may be configured to carry a parity bit during the first bit of each frame. In External Signaling Mode, ISIG[x] is active and is aligned as shown. In ICLK Reference mode, ICLK[x] is active in place of ISIG[x]; ICLK is either a jitter-attenuated line-rate clock referenced to RLCLK, or an 8 kHz clock generated by dividing RLCLK by 193. The values of the filler bits will depend on the exact configuration of the TOCTL, and they will be included in the parity calculation
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204
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 22
- Egress Interface: 2.048 MHz Clock Slave: EFP Enabled Mode
CECLK CEFP ED[x] EFP[x]
F
Don't Care
1 2 3 4 5 67 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Don't Care
1 2 34 5 6 7 8
F-Bit or Parity
Channel 1 Frame 1
Channel 2 Frame 1
Channel 3 Frame 1
"filler"
Channel 4 Frame 1
CECLK CEFP ED[x] EFP[x]]
Ch24 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch23 Ch24 Ch1
The Egress Interface is configured for the Clock Slave: EFP Enabled Mode by writing 10 binary to EMODE[1:0] in the Egress Options register. The 2.048 MHz internally gapped clock mode is selected by writing CECLK2M to logic 1 in the Egress Options Register. In the illustrated case, CEFP is configured for superframe alignment by writing CESFP to logic 1 in the Egress Options Register, so that the CEFP input must pulse once every 12 or 24 frames (for SF and ESF, respectively) on the last F-bit of the multiframe to specify superframe alignment, instead of once every frame to specify frame alignment. If parity checking is enabled, a parity bit should be inserted on ED[x] in the first bit of each frame. The EFP[x] output will pulse high to mark the F-bit of each frame in order to indicate frame alignment to an upstream device; EFP may be configured to mark superframe alignment instead. The values of the don't-care bits are not important, except that they will be used in the backplane parity check if it is enabled.
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205
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 23 Mode
- Egress Interface: 2.048 MHz Clock Slave: External Signaling
CECLK CEFP ED[x] ESIG[x]
F
Don't Care
1 2 3 4 5 67 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ABCD ABCD ABCD
Don't Care
1 2 34 5 6 7 8 AB CD
Don't Care
Don't Care
F-Bit or Parity
Channel 1
Channel 2
Channel 3
"filler"
Channel 4
CECLK CEFP ED[x] ESIG[x]
Ch24 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch23 Ch24 Ch1
The Egress Interface is configured for the 2.048 MHz Clock Slave: External Signaling Mode by writing 11 binary to EMODE[1:0] in the Egress Options register. The 2.048 MHz internally gapped clock mode is selected by writing CECLK2M to logic 1 in the Egress Options register. In the illustrated case, CEFP specifies frame alignment and is required to pulse high for one cycle every frame. ESIG[x] should carry the signaling bits for each channel in bits 5,6,7 and 8; the signaling bits will be inserted into the data stream by the transmitter. If the ABXXEN bit is set to logic 1 in the Egress Options register, then the A and B bits will be repeated in the C and D positions. If parity checking is enabled, a parity bit should be inserted on ED[x] and ESIG[x] in the first bit of each frame. The values of the don't-care bits are not important, except that they will be used in the backplane parity check if it is enabled.
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206
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
14 14.1
OPERATIONS Configuring the TOCTL from Reset After a system reset (either via the RSTB pin or via the RESET register bit), the TOCTL will default to the following settings: Table 8 Setting Framing Format DS-1 interface - Default Settings Receiver Section SF * RLD[x] inputs NRZ data sampled on rising RLCLK[x] edge. * Clock Slave: External Signaling Mode * ID[x], ISIG[x] updated on falling CICLK edge * Elastic Store enabled, CIFP indicates frame alignment Data Link Options * internal RDLC disabled * Signaling alignment disabled * Automatic trunk conditioning disabled * PRGD configured to monitor test patterns Timing Options Not applicable Transmitter Section SF * TLD[x] outputs NRZ data updated on falling TLCLK[x] edge * Clock Slave: External Signaling Mode * ED[x] and ESIG[x] sampled on rising CECLK edge * CEFP indicates frame alignment * internal TDPR disabled * PRGD configured to insert test patterns * F, CRC, FDL bit bypass disabled * Digital jitter attenuation enabled, with TLCLK[x] referenced to CECLK * All diagnostic modes disabled
Ingress/Egress Interfaces
Diagnostics
* All diagnostic modes disabled
In the following tables the "Addr Offset" is the address relative to 000H, 080H, 100H, 180H, 200H, 280H, 300H, or 380H depending on which framer is being configured.
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207
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
To configure the TOCTL for ESF framing format, after a reset, the following registers should be written with the indicated values:
Table 9 Action
- ESF Frame Format Addr Offset 44H 20H Data 10H 10H or 50H or 90H Effect Select ESF transmitter Select ESF, 2 of 4 OOF threshold Select ESF, 2 of 5 OOF threshold Select ESF, 2 of 6 OOF threshold Enable 8 out of 10 validation Enable 4 out of 5 validation Select ESF Enable Inband Code detection Program Loopback Activate Code pattern Program Loopback Deactivate Code pattern Select ESF
Write XBAS Configuration Register Write FRMR Configuration Register
Write RBOC Enable Register
2AH
00H or 02H
Write ALMI Configuration Register Write IBCD Configuration Register Write IBCD Activate Code Register Write IBCD Deactivate Code Register Write SIGX Configuration Register
2CH 3CH 3EH 3FH 40H
10H 00H 08H 44H 04H
To configure the TOCTL for SF framing format, after a reset, the following registers should be written with the indicated values:
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208
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 10 Action
- SF Frame Format Addr Offset 44H 20H Data 00H 00H or 40H or 80H Effect Enable for SF in transmitter Select SF, 2 of 4 OOF threshold Select SF, 2 of 5 OOF threshold Select SF, 2 of 6 OOF threshold Select SF Enable Inband Code detection Program Loopback Activate Code pattern Program Loopback Deactivate Code pattern Select SF
Write XBAS Configuration Register Write FRMR Configuration Register
Write ALMI Configuration Register Write IBCD Configuration Register Write IBCD Activate Code Register Write IBCD Deactivate Code Register Write SIGX Configuration Register
2CH 3CH 3EH 3FH 40H
00H 00H 08H 44H 00H
To access the Performance Monitor Registers, the following polling sequence should be used: Table 11 Action Write PMON BEE Count (LSB) Register (To transfer the PMON registers for all eight framers, write the Revision/Chip ID/Global PMON Update register.) Read BEE Count (LSB) Register - PMON Polling Sequence Addr Offset 4CH Data 00H Effect Latch performance data into PMON registers
4AH
Read least significant byte of bit error event count
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209
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Action Read BEE Count (MSB) Register Read FER Count (LSB) Register Read FER Count (MSB) Register Read OOF Count Register Read COFA Count Register
Addr Offset 4BH 4CH
Data
Effect Read most significant byte of bit error event count Read least significant byte of Framing bit error event count Read most significant byte of Framing bit error event count Read out-of-frame event count Read change of frame alignment event count
4DH
4EH 4FH
14.2
Using the Internal FDL Transmitter The access rate to the TDPR registers is limited by the rate of the high-speed system clock (XCLK). The TDPR registers should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no faster than 1/8 that of the 37.056 MHz XCLK. This time is used by the high-speed system clock to sample the event, write the FIFO, and update the FIFO status. Upon reset of the TOCTL, the TDPR should be disabled by setting the EN bit in the TDPR Configuration Register to logic 0 (default value).An HDLC all-ones Idle signal will be sent while in this state. The TDPR should then be enabled by setting EN to logic 1. The FIFOCLR bit should be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit. To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS generation is desired, the CRC bit should be set to logic 1. If the block is to be used in interrupt driven mode, then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and LFILLE bits in the TDPR Interrupt Enable register to logic 1. The TDPR operating parameters in the TDPR Upper Transmit Threshold and TDPR Lower Interrupt Threshold registers should be set to the desired values. The TDPR Upper Transmit Threshold sets the value at which the TDPR automatically begins the transmission of HDLC packets, even if no complete packets are in the FIFO. Transmission will continue until the current packet is transmitted and the number of bytes in the TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all complete HDLC
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packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is set to logic 1, continuous flags will be sent. The TDPR can be used in a polled or interrupt driven mode for the transfer of data. In the polled mode the processor controlling the TDPR must periodically read the TDPR Interrupt Status register to determine when to write to the TDPR Transmit Data register. In the interrupt driven mode, the processor controlling the TDPR uses the INTB output, the TOCTL Interrupt ID register, and the TOCTL Interrupt Source registers to identify TDPR interrupts which determine when writes can or must be done to the TDPR Transmit Data register. Interrupt Driven Mode: The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 1 so an interrupt on INTB is generated upon detection of a FIFO full state, a FIFO depth below the lower limit threshold, a FIFO overrun, or a FIFO underrun. The following procedure should be followed to transmit HDLC packets: 1. Wait for data to be transmitted. Once data is available to be transmitted, then go to step 2. 2. Write the data byte to the TDPR Transmit Data register. 3. If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 4. If there are more bytes in the packet to be sent, then go to step 2. While performing steps 1 to 4, the processor should monitor for interrupts generated by the TDPR. When an interrupt is detected, the TDPR Interrupt Routine detailed in the following text should be followed immediately. The TDPR will force transmission of the packet information when the FIFO depth exceeds the threshold programmed with the UTHR[6:0] bits in the TDPR Upper Transmit Threshold register. Transmission will not stop until the last byte of all complete packets is transmitted and the FIFO depth is at or below the threshold
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limit. The user should watch the FULLI and LFILLI interrupts to prevent overruns and underruns. TDPR Interrupt Routine: Upon assertion of INTB, the source of the interrupt must first be identified by reading the Interrupt ID register and Interrupt Source registers. Once the source of the interrupt has been identified as TDPR, then the following procedure should be carried out: 1. Read the TDPR Interrupt Status register. 2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. When the UDRI bit transitions to logic 1, one Abort sequence and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To reenable the TDPR FIFO and to clear the underrun, the TDPR Interrupt Status/UDR Clear register should be written with any value. 3. If OVRI=1, then the FIFO has overflowed. The packet which the last byte written into the FIFO belongs to has been corrupted and must be retransmitted. Other packets in the FIFO are not affected. Either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. The next write to the TDPR Transmit Data register should contain the first byte of the next packet to be transmitted. If the FIFO overflows on the packet currently being transmitted (packet is greater than 128 bytes long), the OVRI bit is set, an Abort signal is scheduled to be transmitted, the FIFO is emptied, and then flags are continuously sent until there is data to be transmitted. The FIFO is held in reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte of the next packet to be transmitted. 4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can be written. When in this state, either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state earlier, but has since emptied out some of its data bytes and now has space available in its FIFO for more data.
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5. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. If there is more data to transmit, then it should be written to the TDPR Transmit Data register before an underrun occurs. If there is no more data to transmit, then an EOM should be set at the end of the last packet byte. Flags will then be transmitted once the last packet has been transmitted. If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lowerthreshold state earlier, but has since been refilled to a level above the lowerthreshold level. Polling Mode: The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a periodic polling procedure. The following procedure should be followed to transmit HDLC packets: 1. Wait until data is available to be transmitted, then go to step 2. 2. Read the TDPR Interrupt Status register. 3. If FULL=1, then the TDPR FIFO is full and no further bytes can be written. Continue polling the TDPR Interrupt Status register until either FULL=0 or BLFILL=1. Then, go to either step 4 or 5 depending on implementation preference. 4. If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. Write the data into the TDPR Transmit Data register. Go to step 6. 5. If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be written. Write the data into the TDPR Transmit Data register. Go to step 6. 6. If more data bytes are to be transmitted in the packet, then go to step 2. 7. If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1.
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14.3
Using the Internal FDL Receiver The RDLC requires 15 XCLK cycles to process the results of accesses to the RDLC Status and RDLC Data registers. Thus, accesses to these registers should not occur at a rate greater than 1/15 of the 37.056 MHz XCLK. On power up of the system, the RDLC should be disabled by setting the EN bit in the Configuration Register to logic 0 (default state). The RDLC Interrupt Control register should then be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt will be generated. If the INTE bit is not set to logic 1, the RDLC Status register must be continuously polled to check the interrupt status (INTR) bit. After the RDLC Interrupt Control register has been written, the RDLC can be enabled at any time by setting the EN bit in the RDLC Configuration register to logic 1. When the RDLC is enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags. When the first flag is found, an interrupt will be generated, and a dummy byte will be written into the FIFO buffer. This is done to provide alignment of link up status with the data read from the FIFO. When an abort character is received, another dummy byte and link down status is written into the FIFO. This is done to provide alignment of link down status with the data read from the FIFO. It is up to the controlling processor to check the COLS bit in the RDLC Status register for a change in the link status. If the COLS bit is set to logic 1, the FIFO must be emptied to determine the current link status. The first flag and abort status encoded in the PBS bits is used to set and clear a Link Active software flag. When the last byte of a properly terminated packet is received, an interrupt is generated. While the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the external processor to empty the bytes remaining in the FIFO or to just increment a number-of-packets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC Status register is read, the PKIN bit is cleared to logic 0 . If the RDLC Status register is read immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the CRC and non-integer byte status can be checked by reading the PBS[1:0] bits. When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to remove this source of interrupt. The RDLC can be used in a polled or interrupt driven mode for the transfer of frame data. In the polled mode, the processor controlling the RDLC must periodically read the RDLC Status register to determine when to read the RDLC Data register. In the interrupt driven mode, the processor controlling the RDLC
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must identify the interrupt source to determine when to read the RDLC Data register. When the RDLC is identified as the interrupt source, the RDLC should be serviced as follows: 1. RDLC Status register read. The INTR bit should be logic 1 if the RDLC is the interrupt source. 2. If OVR = 1, then discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 3. If COLS = 1, then set the EMPTY FIFO software flag. 4. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. 5. Read the RDLC Data register. 6. Read the RDLC Status register. 7. If OVR = 1, then discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 8. If COLS = 1, then set the EMPTY FIFO software flag. 9. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. 10. Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is to be done with the FIFO data. 10.1) If PBS[2:0] = 001, discard data byte read in step 5 and set the LINK ACTIVE software flag. 10.2) If PBS[2:0] = 010, discard the data byte read in step 5 and clear the LINK ACTIVE software flag. 10.3) If PBS[2:0] = 1XX, store the last byte of the packet, decrement the PACKET COUNT, and check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the packet.
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10.4) If PBS[2:0] = 000, store the packet data. 11. If FE = 0 and INTR = 1 or FE = 0 and EMPTY FIFO = 1, go to step 5 else clear the EMPTY FIFO software flag and leave this interrupt service routine to wait for the next interrupt. The link state is typically a local software variable. The link state is inactive if the RDLC is receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. The link state is active if the RDLC is receiving flags or data. If the RDLC data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt. Figure 24 - Typical Data Frame 7
1
BIT: 8
0
6
1
5
1
4
1
3
1
2
1
1
0
FLAG
Address (high) (low)
CONTROL
data bytes received and transferred to the FIFO Buffer
Frame Check Sequence 0 1 1 1 1 1 1 0
FLAG
Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match.
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PM4388 TOCTL
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Figure 25
- Example Multi-Packet Operational Sequence
DATA INT FE LA
FF F D D D D F D D D D D D D D DD A FF F F DD D D FF 1 2 3 45 6 7
F A D INT FE LA
- flag sequence (01111110) - abort sequence (01111111) - packet data bytes - active high interrupt output - internal FIFO empty status - state of the LINK ACTIVE software flag
Figure 25 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link relative the input data sequence. The cause of each interrupt and the processing required at each point is described in the following paragraphs. At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte is written in the FIFO, FE goes low, and an interrupt goes high. When the interrupt is detected by the processor it reads the dummy byte, the FIFO becomes empty, and the interrupt is removed. The LINK ACTIVE (LA) software flag is set to logic 1. At points 2 and 6 the last byte of a packet is detected and interrupt goes high. When the interrupt is detected by the processor, it reads the data and status registers until the FIFO becomes empty. The interrupt is removed as soon as the RDLC Status register is read since the FIFO fill level of 8 bytes has not been exceeded. It is possible to store many packets in the FIFO and empty the FIFO when the FIFO fill level is exceeded. In either case the processor should use this interrupt to count the number of packets written into the FIFO. The packet count or a software time-out can be used as a signal to empty the FIFO.
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At point 3 the FIFO fill level of 8 bytes is exceeded and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. At points 4 or 7 an abort character is detected, a dummy byte is written into the FIFO, and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. The LINK ACTIVE software flag is cleared. 14.4 Using the PRGD Pattern Generator/Detector The pattern generator/detector block provides a valuable diagnostic tool, capable of generating and detecting an enormous variety of pseudo-random and repetitive patterns. Controlling the PRGD is accomplished by programming four register sets: the Pattern Generator/Detector Positioning/Control Register (00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH), the TPSC Internal Registers 0118H, the RPSC Internal Registers 01-18H, and the PRGD registers. Using PRGD to test T1 link integrity For example, suppose it is desired to monitor the error rate on a T1 link without taking the entire T1 offline. A subset of channels should be chosen (say channels 1,3,5 and 7) to carry PRBS instead of data. The TPSC Egress Control Bytes for channels 1,3,5 and 7 must have their TEST bits set to logic 1, and PCCE must be set in the TPSC Configuration register to enable the per-DS0 functions. Register 00F should be written to its default of all-zeroes. The PRGD should be configured to generate the desired PRBS sequence. The selected channels will then be treated as a single, concatenated data stream in which the selected PRBS will appear. If the device at the far end of the line can be set to loop back at least the selected channels, then the PRGD can be used to monitor the return error rate. The RPSC Ingress Control Bytes for channels 1,3,5, and 7 must have their TEST bits set to logic 1, and the PCCE bit set in the RPSC Configuration register to enable the per-DS0 functions. The PRGD will then synchronize to the returning pattern, and begin counting errors. To determine the BER, an periodic accumulation of the PRGD detection registers may be forced by writing to one of the PRGD Pattern Detector registers, by writing to the Revision/Chip ID/Global PMON Update register (00CH), or via the AUTOUPDATE feature. The bit error count, bits received count, and previous 32 bits received are then available via the Pattern Detector registers. In this scenario, any desired combination of channels may be selected. If it is desired to insert the test pattern in the entire T1, including the framing bits, then UNF_GEN must be set in the Pattern Generator/Detector Positioning/Control
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Register, and framing bit insertion must be disabled by setting FDIS to logic 1 in the Transmit Framing and Bypass Options Register. To detect such an unframed sequence, UNF_DET must also be set. Using PRGD to test backplane integrity If, instead, it is desired to test the backplane side of the system, RXPATGEN may be set to logic 1 in the Pattern Generator/Detector Positioning/Control Register. This will cause the pattern to replace the data received in the selected channels of RLD[x], and will cause the PRGD to search for the desired PRBS on the ED[x] stream. Inserting PRBS in the 7 MSB of each channel In cases where the least-significant bit of the channel may be overwritten by signaling, excess zeroes suppression, SIGX signaling bit fixing, or other factors, the Nx56k_GEN and/or Nx56k_DET bits may be set in the Pattern Generator/Detector Positioning/Control Register. This will cause the PRGD to only insert patterns into, or detect patterns in, the seven most-significant bits of selected channels. This feature is particularly useful when generating or monitoring for fractional T1 loopback codes when handling Nx56kbps fractional T1. Generating and detecting repetitive patterns When a repetitive pattern (such as 1-in-8) is to be generated or detected, the PS bit must be set to logic 1. The pattern length register must be set to (N-1), where N is the length of the desired repetitive pattern. Several examples of programming for common repetitive sequences are given below in the Common Test Patterns section. For pattern generation, the desired pattern must be written into the PRGD Pattern Insertion registers. The repetitive pattern will then be continuously generated. The generated pattern will be inserted in data stream formed from the selected channels, but the phase of the pattern cannot be guaranteed. For pattern detection, the PRGD will determine if a repetitive pattern of the length specified in the pattern length register exists in the selected channels. It does so by loading the first N bits from the selected channels, and then monitoring to see if the pattern loaded repeats itself error free for the subsequent 48 bit periods. It will repeat this process until it finds a repetitive pattern of length N, at which point it begins counting errors (and possibly re-synchronizing) in the same way as for pseudo-random sequences. Note that the PRGD does NOT
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look for the pattern loaded into the Pattern Insertion registers, but rather automatically detects any repetitive pattern of the specified length. The precise pattern detected can be determined by initiating a PRGD update, setting PDR[1:0] = 00 in the PRGD Control register, and reading the Pattern Detector registers (which will then contain the 32 bits detected immediately prior to the strobe). Using PRGD with ELST Enabled If the elastic store is enabled (Ingress interface is in a Clock Slave mode) then the PRGD will operate on the data output from the ELST. This has two effects: first, when the framer is out-of-frame, the ELST Trouble Code overwrites the received data, and so patterns cannot be detected in the receive direction until the FRMR finds frame. If patterns must be detected while the FRMR is out-offrame, then the UNF bit must be set in the Receive Line options Register (Reg. 00H in each octant), disabling the FRMR from finding frame but allowing the data to pass through ELST untouched. The second effect is that if slips occur in the ELST, then the PRGD will be forced to re-synchronize to the incoming pattern. Note that the default ELST trouble code, which is all-ones, is a repetitive pattern of every length, so the PRGD will synchronize to it automatically if repetitive patterns are being detected. The pattern generator can be configured to generate pseudo random patterns or repetitive patterns as shown in the Figure 26 below: Figure 26 - PRGD Pattern Generator
LENGTH PS TAP
1
2
3
32
O UT P UT
The pattern generator consists of a 32 bit shift register and a single XOR gate. The XOR gate output is fed into the first stage of the shift register. The XOR gate inputs are determined by values written to the length register (PL[4:0]) and the tap register (PT[4:0]), when the PS bit is low. When PS is high, the pattern
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detector functions as a recirculating shift register, with length determined by PL[4:0]. Common Test Patterns The PRGD can be configured to monitor the standardized pseudo random and repetitive patterns described in ITU-T O.151. The register configurations required to generate these patterns and others are indicated in the two tables below: Table 12 - Pseudo Random Pattern Generation (PS bit = 0) PL 02 03 04 05 06 06 06 08 09 0A 0E 10 11 13 13 14 PT 00 00 01 04 00 03 03 04 02 08 0D 02 06 02 10 01 PI#1 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF PI#2 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF PI#3 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF PI#4 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF TINV 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 RINV 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0
Pattern Type 23 -1 24 -1 25-1 26 -1 27 -1 27 -1 (Fractional T1 LB Activate) 27 -1 (Fractional T1 LB Deactivate) 29 -1 (O.153) 210 -1 211 -1 (O.152, O.153) 215 -1 (O.151) 217 -1 218 -1 220 -1 (O.153) 220 -1 (O.151 QRSS bit=1) 221 -1
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Pattern Type 222 -1 223 -1 (O.151) 225 -1 228 -1 229 -1 231 -1 Table 13
PL 15 16 18 1B 1C 1E
PT 00 11 02 02 01 02
PI#1 FF FF FF FF FF FF
PI#2 FF FF FF FF FF FF
PI#3 FF FF FF FF FF FF
PI#4 FF FF FF FF FF FF
TINV 0 1 0 0 0 0
RINV 0 1 0 0 0 0
- Repetitive Pattern Generation (PS bit = 1) PL 00 00 01 03 17 0F 07 03 04 02 PT 00 00 00 00 00 00 00 00 00 00 PI#1 FF FE FE FC 22 01 01 F1 F0 FC PI#2 FF FF FF FF 00 00 FF FF FF FF PI#3 FF FF FF FF 20 FF FF FF FF FF PI#4 FF FF FF FF FF FF FF FF FF FF TINV 0 0 0 0 0 0 0 0 0 0 RINV 0 0 0 0 0 0 0 0 0 0
Pattern Type All ones All zeros Alternating ones/zeros Double alternating ones/zeros 3 in 24 1 in 16 1 in 8 1 in 4 Inband loopback activate Inband loopback deactivate
Notes for the Pseudo Random and Repetitive Pattern Generation Tables: 1. The PS bit and the QRSS bit are contained in the PRGD Control register 2. PL = Pattern Length Register 3. PT = Pattern Tap Register 4. PI#1 = Pattern Insertion #1 Register
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5. PI#2 = Pattern Insertion #2 Register 6. PI#3 = Pattern Insertion #3 Register 7. PI#4 = Pattern Insertion #4 Register 8. The TINV bit and the RINV bit are contained in the control register 14.5 Using the Loopback Modes The TOCTL provides three loopback modes to aid in network and system diagnostics. Line loopback can be initiated at any time via the P interface, but is usually initiated once an inband loopback activate code is detected. The system Diagnostic Digital loopback can be initiated at any time by the system via the P interface to check the path of system data through the framer. The payload can also be looped-back on a per-DS0 basis to allow network testing without taking an entire DS1 off-line. 14.5.1 Line Loopback When LINE loopback (LINELB) is initiated by writing 10H to the Master Diagnostics Register (00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, and 38AH), the appropriate T1 framer in the TOCTL is configured to internally connect the jitter-attenuated clock and data from the RJAT to the transmit line clock and data, TLD[x] and TLCLK[x]. The RJAT may be bypassed if desired. Conceptually, the data flow through a single T1 framer in this loopback condition is illustrated in Figure 27:
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Figure 27
CTCLK*
- Line Loopback
TRANSMITTER
XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunki Conditioning I Line Coding TOPS Timing Options TJAT Digital Jitter Attenuator TLCLK[1:8] TLD[1:8]
ED[1:8] ECLK[1:8]/EFP[1:8]/ESIG[1:8] CEFP* CECLK*
EIF Egress Interface
CICLK* CIFP* ID[1:8] ICLK[1:8]/ISIG[1:8 ] IFP[1:8]
ELST Elastic Store
FRAM Framer/ Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction
Li ne L oopback
IIF Ingress Interface
RJAT Digital Jitter Attenuator
RLCLK[1:8] RLD[1:8]
RECEIVER
14.5.2 Diagnostic Digital Loopback When Diagnostic Digital loopback (DDLB) is initiated by writing 04H to the Master Diagnostics Register (00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, and 38AH), the appropriate T1 framer in the TOCTL is configured to internally connect its line clock and data (TLD[x] and TLCLK[x]) to the receive line clock and data (RLD[x] and RLCLK[x]) The data flow through a single T1 framer in this loopback condition is illustrated in Figure 28:
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Figure 28
CTCLK*
- Diagnostic Digital Loopback
TRANSMITTER
XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunki Conditioning I Line Coding TOPS Timing Options TJAT Digital Jitter Attenuator TLCLK[1:8] TLD[1:8]
ED[1:8] ECLK[1:8]/EFP[1:8]/ESIG[1:8] CEFP* CECLK*
EIF Egress Interface
Di agn ost i c Loopb ack
CICLK* CIFP* ID[1:8] ICLK[1:8]/ISIG[1:8 ] IFP[1:8] FRAM Framer/ Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction RJAT Digital Jitter Attenuator RLCLK[1:8] RLD[1:8]
ELST Elastic Store
IIF Ingress Interface
RECEIVER
14.5.3 Per-DS0 Loopback The T1 payload may be looped-back on a per-DS0 basis through the use of the TPSC. If all DS0s are looped-back, the result is very similar to Payload Loopback on the PM4344 TQUAD. In order for per-DS0 loopback to operate correctly, the Ingress Interface must be in Clock Master mode, or else CIFP and CICLK must be connected to CEFP and CECLK, respectively. The LOOP bit must be set to logic 1 in the TPSC Internal Registers for each DS0 desired to be looped back, and the PCCE bit must be set to logic 1 in the TPSC Configuration register. When all these configurations have been made, the ingress DS0 channels selected will overwrite their corresponding egress DS0 channels; the remaining egress DS0 channels will pass through intact. Note that because the egress and ingress streams will not be superframe aligned, that any robbed-bit signaling in the ingress stream may not fall in the correct frame once loopedback, and that egress robbed-bit signaling will overwrite the looped-back channel data if signaling insertion is enabled. The data flow in per-DS0 loopback is illustrated in Figure 29:
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Figure 29
CTCLK*
- Per-DS0 Loopback
TRANSMITTER
XBAS BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunki Conditioning I Line Coding TOPS Timing Options TJAT Digital Jitter Attenuator TLCLK[1:8] TLD[1:8]
ED[1:8] ECLK[1:8]/EFP[1:8]/ESIG[1:8] CEFP* CECLK*
EIF Egress Interface TPSC Per-DS0 Serial Controller
MUX
Per - DS0 Loopback
FRAM Framer/ Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction RJAT Digital Jitter Attenuator RLCLK[1:8] RLD[1:8]
ELST Elastic Store ID[1:8] ICLK[1:8]/ISIG[1:8 ] IFP[1:8]
IIF Ingress Interface
RECEIVER
14.6
Using the Per-DS0 Serial Controllers
14.6.1 Initialization Before the TPSC (RPSC) block can be used, a proper initialization of the internal registers must be performed to eliminate erroneous control data from being produced on the block outputs. The output control streams should be disabled by setting the PCCE bit in the TPSC (RPSC) Configuration Register (registers 030H, 0B0H, 130H, 1B0H, 230H, 2B0H, 330H, 3B0H for TPSC; 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H for RPSC) to logic 0. Then, all 72 locations of the TPSC (RPSC) must be filled with valid data. Finally, the output streams can be enabled by setting the PCCE bit in the TPSC (RPSC) Configuration Register to logic 1. 14.6.2 Direct Access Mode Direct access mode to the TPSC or RPSC is not used in the TOCTL. However, direct access mode is selected by default whenever the TOCTL is reset. The IND
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bit within the TPSC and RPSC Configuration Registers must be set to logic 1 after a reset is applied. 14.6.3 Indirect Access Mode Indirect access mode is selected by setting the IND bit in the TPSC or RPSC Configuration Register to logic 1. When using the indirect access mode, the status of the BUSY indication bit should be polled to determine the status of the microprocessor access: when the BUSY bit is logic 1, the TPSC or RPSC is processing an access request; when the BUSY bit is logic 0, the TPSC or RPSC has completed the request. The indirect write programming sequence for the TPSC (RPSC) is as follows: 1. Check that the BUSY bit in the TPSC (RPSC) P Access Status Register is logic 0. 2. Write the channel data to the TPSC (RPSC) Channel Indirect Data Buffer register. 3. Write RWB=0 and the channel address to the TPSC (RPSC) Channel Indirect Address/Control Register. 4. Poll the BUSY bit until it goes to logic 0. The BUSY bit will go to logic 1 immediately after step 3 and remain at logic 1 until the request is complete. 5. If there is more data to be written, go back to step 1. The indirect read programming sequence for the TPSC (RPSC) is as follows: 1. Check that the BUSY bit in the TPSC (RPSC) P Access Status Register is logic 0. 2. Write RWB=1 and the channel address to the TPSC (RPSC) Channel Indirect Address/Control Register. 3. Poll the BUSY bit, waiting until it goes to a logic 0. The BUSY bit will go to logic 1 immediately after step 2 and remain at logic 1 until the request is complete. 4. Read the requested channel data from the TPSC (RPSC) Channel Indirect Data Buffer register. 5. If there is more data to be read, go back to step 1.
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14.7
Using the Transmit Digital Jitter Attenuator In using TJAT, it is important to choose the appropriate divisors for the phase comparison between the selected reference clock and the generated smooth TLCLK[x[.
14.7.1 Default Application Upon reset, the TOCTL default condition provides jitter attenuation with TLCLK[x] referenced to the common egress clock, CECLK. The TJAT SYNC bit is also logic 1 by default. TJAT is configured to divide its input clock rate, CECLK, and its output clock rate, TLCLK[x], both by 48, which is the maximum length of the FIFO. These divided down clock rates are then used by the phase comparator to update the TJAT DPLL. The phase delay between CECLK and TLCLK[x] is synchronized to the physical data delay through the FIFO. For example, if the phase delay between BTCLK[x] and TCLKO[x] is 12UI, the FIFO will be forced to lag its output data 12 bits from its input data. The default mode works well with the common egress clock running at 1.544MHz. 14.7.2 Data Burst Application In applications where the 2.048MHz transmit backplane rate (or a higher backplane rate with external gapping) is used, a few factors must be considered to adequately filter the resultant TLCLK[x] into a smooth 1.544MHz clock. The magnitude of the phase shifts in the incoming bursty data are too large to be properly attenuated by the PLL alone. However, the magnitudes, and the frequency components of these phase shifts are known, and are most often multiples of 8 kHz. When using the 2.048MHz transmit backplane rate, the input clock to TJAT is a gapped version of the 2.048MHz CECLK. The phase shifts of the input clock with respect to the generated TLCLKx] in this case are large, but when viewed over a longer period, such as a frame, there is little net phase shift. Therefore, by choosing the divisors appropriately, the large phase shifts can be filtered out, leaving a stable reference for the DPLL to lock onto. In this application, the N1 and N2 divisors should be changed to C0H (i.e. divisors of 193). Consequently, the frequency of the clock inputs to the phase discriminator in the PLL is 8 kHz. The TJAT SYNC option must be disabled, since the divisor magnitude of 193 is not an integer multiple of the FIFO length, 48.
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The self-centering circuitry of the FIFO should be enabled by setting the CENT register bit. This sets up the FIFO read pointer to be at least 4 UI away from the end of the FIFO registers, and then disengages. Should variations in the frequency of input clock or the output clock cause the read pointer to drift to within one unit interval of FIFO overflow or underflow, the pointer will be incrementally pushed away by the LIMIT control without any loss of data. With SYNC disabled, CENT and LIMIT enabled, the maximum tolerable phase difference between the bursty input clock and the smooth TLCLK[x] is 40UI. Phase wander between the two clock signals is compensated for by the LIMIT control. 14.7.3 Elastic Store Application In multiplex applications where the jitter attenuation is not required, the TJAT FIFO can be used to provide an elastic store function. For example, in an M12 application, the data is written into the FIFO at 1.544MHz and the data is read out of the FIFO with a gapped DS2 rate clock applied on CTCLK. In this configuration, the Timing Options OCLKSEL bit should be programmed to 1, and the CTCLKSEL bit should be programmed to 1. Also, the TJAT SYNC and LIMIT bits should be disabled and the CENT bit enabled. This provides the maximum phase difference between the input clock and the gapped output clock of 40UI. The maximum jitter and wander between the two clocks is 8UIp-p. 14.7.4 Alternate TLCLK Reference Application In applications where TLCLK[x] is referenced to an Nx8 kHz clock source applied on CTCLK, TJAT can be configured by programming the output clock divisor, N2, to C0H and the input clock divisor, N1, to the value (N-1). The resultant input clocks to the phase comparator are both 8kHz. The TJAT SYNC and LIMIT bits should be disabled in this configuration. 14.8 Isolating an Interrupt When the INTB pin goes low, the following procedure may be used to isolate the interrupt source. 1. Read the Interrupt ID register (Register 00EH). The bit corresponding to any framer that has an outstanding interrupt will be logic 1. 2. Read the Interrupt Source Registers (Registers 008H and 009H for each framer) for the framer that caused the interrupt. For instance, if framer 5 caused the interrupt, then registers 288H and 289H would be read. The bit
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corresponding to any block with an outstanding interrupt will be set to logic 1 in these registers. 3. Read the register(s) containing the interrupt status bits of the interrupting block in order to determine the event causing the interrupt. A typical block interrupt has two related bits: an enable bit (EVENTE for instance) and an interrupt status bit (EVENTI for instance). EVENTI will go to logic 1 when the triggering event occurs, and goes low when the register containing it is read; the setting of EVENTE has no effect on the value of EVENTI. However, a chip interrupt will only be caused if EVENTE is logic 1 and EVENTI is logic 1. Thus, both the interrupt status bit(s) and their respective enables may need to be read in order to determine which event caused an interrupt. Specific interrupt setups may differ from this model, however. 14.9 Using the Performance Monitor Counter Values All PMON event counters are of sufficient length so that the probability of counter saturation over a one second interval is very small. For ESF frame format, the FER and BEE error counts are incapable of saturating over a one second interval unless the FRMR is locked in-frame, and even then the likelihood is negligible for BER much less than 10-1. For SF format, the BEE and FER counts are identical, but the FER counter is smaller and should be ignored. The BEE count is incapable of saturating unless the FRMR is locked in-frame, and even then the likelihood of saturating in one second at a 5x10-1 bit error ratio is less than 2% in SF format; at 10-1 or lower BER the odds of saturation are zero for all practical purposes. The relationship between BER and the odds of the OOF and COFA counters saturating is complicated, but at a 10-3 BER the probability is less than 0.001% in either format. In ESF mode, the BEE count (which counts CRC-6 errors) is effective at bit error rates below 10-3. The bit error rate can be calculated from the one-second PMON BEE count by the following equation: 24 log1 - 8000 BEE 24 * 193 Bit Error Rate = 1 - 10 The following graph illustrates the expected BEE Count for a range of Bit Error Ratios.
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Figure 30
- BEE Count Expected vs Bit Error Rate for ESF
350 300 250 200 150 100 50 0 1.00E-06 1.00E-05 1.00E-04 Bit Error Rate 1.00E-03 1.00E-02
The ESF FER count accumulates framing-pattern errors. There are 2000 framing pattern bits in a second, so the bit error ratio is equal to approximately FER/2000. However, as the bit error rate rises above 5x10-3, the chance of losing frame at least once a second becomes significant. Because the PMON does not count errors during out-of-frame conditions, this will make the FER count slightly optimistic. Each reframing event will be recorded by the OOF counter, and there is a 99% probability that any given OOF event lasts for less than 15ms. The SF BEE count also accumulates framing-pattern errors, for which there are 8000 opportunities in a second. Thus, the bit error ratio is equal to approximately BEE/8000. However, as the bit error rate rises above 2x10-3, OOF events begin to occur infrequently. Because the PMON does not count errors during out-offrame conditions, this will make the BEE count slightly optimistic. Each reframing event, however, will be recorded by the OOF counter, and there is a 99% probability that any given OOF event lasts for less than 4.4ms.
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14.10 JTAG Support The TOCTL supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown in Figure 31. Figure 31 - Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register
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and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input TDI to primary output TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output TDO. In addition, patterns can be shifted in on primary input TDI and forced onto all digital outputs. TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary TMS. The finite state machine is shown in Figure 32.
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Figure 32
- TAP Controller Finite State Machine
TRSTB=0
Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 0 1 Exit1-IR 0 Pause-IR 1 0 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP
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controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle The run test/idle state is used to execute tests. Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
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Update-IR The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. Boundary Scan Instructions The following is an description of the standard instructions. Each instruction selects an serial test data register path between input TDI and output TDO. BYPASS The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
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IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out TDO using the Shift-DR state. Boundary Scan Register The boundary scan register is made up of 120 boundary scan cells, divided into input observation (in_cell), output (out_cell), and bidirectional (io_cell) cells. These cells are detailed in the pages which follow. The first 32 cells (120 down to 89) form the ID code register, and carry the code 043880CD. The remaining cells also have values which may be captured during the idcode instruction and shifted out if desired; these are included in brackets for reference. The cells are arranged as follows: Table 14
Pin/ Enable Bit HIZ2,3 RLD1 RLCLK1 RLD2 RLCLK2 RLD3 RLCLK3 RLD4 RLCLK4 TLD1 TLCLK1 120 119 118 117 116 115 114 113 112 111 110 OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL 0 0 0 1/04 0 1 0 0 0 0 1 IFP8 ISIG8 ID8 IFP7 ISIG7 ID7 IFP6 ISIG6 ID6 IFP5 ISIG5 54 53 52 51 50 49 48 47 46 45 44 OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
- Boundary Scan Register
Register Cell Type I.D Bit. Pin/ Enable Register Bit Cell Type I.D. Bit
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Pin/ Enable
Register Bit
Cell Type
I.D Bit.
Pin/ Enable
Register Bit
Cell Type
I.D. Bit
TLD2 TLCLK2 TLD3 TLCLK3 TLD4 TLCLK4 TLD5 TLCLK5 TLD6 TLCLK6 TLD7 TLCLK7 TLD8 TLCLK8 RLD5 RLCLK5 RLD6 RLCLK6 RLD7 RLCLK7 RLD8 RLCLK8 RSTB INTB D0 D0_OEB 1 D1 D1_OEB 1 D2 D2_OEB 1 D3 D3_OEB 1
109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL
1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
ID5 IFP4 ISIG4 ID4 IFP3 ISIG3 ID3 IFP2 ISIG2 ID2 IFP1 ISIG1 ID1 ESIG8 ESIG_OEB8 1 ED8 ESIG7 ESIG_OEB7 1 ED7 ESIG6 ESIG_OEB6 1 ED6 ESIG5 ESIG_OEB5 1 ED5 ESIG4 ESIG_OEB4 1 ED4 ESIG3 ESIG_OEB3 1 ED3 ESIG2
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IN_CELL IO_CELL OUT_CELL IN_CELL IO_CELL OUT_CELL IN_CELL IO_CELL OUT_CELL IN_CELL IO_CELL OUT_CELL IN_CELL IO_CELL OUT_CELL IN_CELL IO_CELL
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (1) (0) (0) (1) (0) (0) (1) (0) (0) (1) (0) (0) (1) (0) (0) (1) (0)
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Pin/ Enable
Register Bit
Cell Type
I.D Bit.
Pin/ Enable
Register Bit
Cell Type
I.D. Bit
D4 D4_OEB 1 D5 D5_OEB 1 D6 D6_OEB 1 D7 D7_OEB 1 ALE A[10:0] CSB WRB RDB
77 76 75 74 73 72 71 70 69 68:58 57 56 55
IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (1) (1) (1)
ESIG_OEB2 1 ED2 ESIG1 ESIG_OEB1 1 ED1 XCLK CIFP CICLK CEFP CECLK CTCLK
11 10 9 8 7 6 5 4 3 2 1
OUT_CELL IN_CELL IO_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
(0) (1) (0) (0) (1) (1) (1) (1) (1) (1) (1)
Notes: 1. All OEB signals will set the corresponding bidirectional signal to an output when set low. 2. When set high, TLD[8:1], TLCLK[8:1], ID[8:1], ISIG[8:1], IFP[8:1], and INTB will be set to high impedance. 3. HIZ is the first bit in the boundary scan chain. 4. Bits 120:117 represent the revision identification code. "0000" indicates revision C. "0001" indicates revision E.
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Figure 33
IDCODE
- Input Observation Cell (IN_CELL)
Scan Chain Out
Input Pad
G1 G2 SHIFT-DR
INPUT to internal logic
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
In this diagram and those that follow, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the centre of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the table above.
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Figure 34
- Output Cell (OUT_CELL)
S can Chain Out
EXT EST OUT PUT or Enable from s ys t em logic IDCODE S HI F T - DR
G 1 1 G 1 G 2 1 1 1 1 2 2 MUX 2 2 1
OUT PUT or Enable
MUX
D C
D C
I.D. code bit CL OCK -DR UPDAT E- DR
S can Chain In
Figure 35
- Bidirectional Cell (IO_CELL)
Scan Chain Out INPUT to internal logic
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin
G1 1 G1 G2 12 1 2 MUX 12 12 1
MUX
OUTPUT to pin
D C
D C
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
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Figure 36
- Layout of Output Enable and Bidirectional Cells Scan Chain Out
OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
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15
ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal operating conditions. Table 15 - TOCTL Absolute Maximum Ratings -55C to +125C -65C to +150C -0.3V to 4.6V VDD - 0.3V to 5.5V -0.3V to BIAS + 0.3V 1000 V 100 mA 20 mA +230 C +150 C
Ambient Temperature under Bias Storage Temperature Voltage on VDD with Respect to GND Voltage on BIAS with respect to GND Voltage on Any Pin Static Discharge Voltage Latchup current on any pin Maximum DC current on any pin Maximum Lead Temperature Maximum Junction Temperature
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16
D .C. CHARACTERISTICS TA= -40 to +85C, VDD=3.3V 10%, VDD BIAS 5.5V Table 16 Symbol PHA, PHD BIAS IBIAS VIL VIH VOL - TOCTL D.C. Characteristics Parameter Power Supply 5V Tolerant Bias Current into 5V Bias Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage Output or Bidirectional High Voltage Reset Input High Voltage Reset Input Low Voltage Reset Input Hysteresis Voltage Input Low Current1,3 -100 0.5 2.4 0 2.0 0.25 Min 2.97 VDD Typ 3.3 5.0 6.0 0.8
BIAS
Max 3.63 5.5
Units Volts Volts A Volts Volts Volts
Conditions
VBIAS = 5.5V Guaranteed Input LOW Voltage Guaranteed Input HIGH Voltage VDD = min, IOL = -3 mA for high drive outputs4 and -2 mA for others3 VDD = min, IOL = 3 mA for high drive outputs4 and 2 mA for others3
0.4
VOH
Volts
VT+ VTVTH
2.0 0.8
Volts Volts Volts
IILPU
-60
-10
A
VIL = GND
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244
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Symbol IIL IIH IDDOP
Parameter Input Low Current2,3 Input High Current2,3 Operating Current Input Capacitance Output Capacitance Bi-directional Capacitance
Min -10 -10
Typ 0 0 80
Max +10 +10 150
Units A A mA
Conditions VIL = GND VIH = VBIAS VDD = 3.63 V, Outputs Unloaded, XCLK = 37.056 MHz Excluding Package -RI Package 2pF Typ. -NI Package 1pF Typ. Excluding Package -RI Package 2pF Typ. -NI Package 1pF Typ. Excluding Package -RI Package 2pF Typ. -NI Package 1pF Typ.
CIN
5
pF
COUT
5
pF
CIO
5
pF
Notes on D.C. Characteristics: 1. Input pin or bidirectional pin with internal pull-up resistors. 2. Input pin or bidirectional pin without internal pull-up resistors 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. D[7:0], TLCLK[1:8], ISIG/ICLK[1:8], ESIG/ECLK/EFP[1:8].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
245
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
17
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS TA= -40 to +85C, VDD=3.3V 10% Table 17 Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH - Microprocessor Read Access (Figure 37) Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tristate Valid Read Negated to INTB high Min 10 5 10 10 20 0 5 80 20 50 Max Units ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
246
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 37
- Microprocessor Read Access Timing tSAR
A[9:0] tS ALR
Valid
Address
tHAR tHALR
tV L ALE tS LR (CSB+RDB)
tHLR
tZ INTH INTB
tPRD D[7:0]
tZ RD
Valid Data
Notes on Microprocessor Read Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 50 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
247
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
4. Microprocessor Interface timing applies to normal mode register accesses only. 5. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 6. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 7. In non-multiplexed address/data bus architectures ALE can be held high; parameters tSALR, tHALR, tVL, and tSLR, tHLR are not applicable. 8. Parameter tHAR is not applicable when address latching is used. Table 18 Symbol tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR - Microprocessor Write Access (Figure 38) Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width Min 10 10 10 10 20 0 5 5 5 40 Max Units ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
248
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 38
- Microprocessor Write Access Timing
A[9:0] tS ALW tV L ALE tSAW (CSB+WRB)
Valid Address
tH ALW tS LW tHLW
tVWR
tH AW
tS DW D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. Microprocessor Interface timing applies to normal mode register accesses only. 3. In non-multiplexed address/data bus architectures, ALE can be held high, parameters tSALW, tHALW, tVL, and tSLW, tHLW are not applicable. 4. Parameters tHAW and tSAW are not applicable if address latching is used. 5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
249
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
250
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
18
TOCTL I/O TIMING CHARACTERISTICS TA= -40 to +85C, VDD=3.3V 10% Table 19 Symbol tLXCLK tHXCLK tXCLK Figure 39 - XCLK=37.056 MHz Input (Figure 39) Description XCLK Low Pulse Width4 XCLK High Pulse Width4 XCLK Period (typically 1/37.056 MHz 32 ppm)5 - XCLK=37.056 MHz Input Timing Min 10 10 20 Max Units ns ns ns
t H XCLK
XCLK
t L XCLK
t XCLK
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
251
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 20 - Egress Interface Timing - Clock Slave: EFP Enabled Mode (Figure 40) Symbol Description Common Egress Clock Frequency1,2(Typically 1.544 MHz 130 ppm or 2.048 MHz 130 ppm) t1CECLK t0CECLK tSCECLK tHCECLK tPEFP1 Common Egress High Pulse Width4 Common Egress Low Pulse Width4 CECLK to Input Set-up Time7,9 CECLK to Input Hold Time8,9 CECLK to EFP[x] Propagation delay9,10,11 Min 1.5 Max 2.1 Units MHz
167 167 20 20 20
ns ns ns ns ns
Figure 40
- Egress Interface Timing - Clock Slave: EFP Enabled Mode CEFP ED[x]
Valid tS CECLK tHCECLK t0 CECLK
CECLK
t1 CECLK
EFP[x] tP EFP1
Valid
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
252
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 21 - Egress Interface Timing - Clock Slave: External Signaling (Figure 41) Symbol Description Common Egress Clock Frequency1,2(Typically 1.544 MHz 130 ppm or 2.048 MHz 130 ppm) t1CECLK t0CECLK tSCECLK tHCECLK Figure 41 Mode Common Egress High Pulse Width4 Common Egress Low Pulse Width4 CECLK to Input Set-up Time7,9 CECLK to Input Hold Time8,9 Min 1.5 Max 2.1 Units MHz
167 167 20 20
ns ns ns ns
- Egress Interface Timing - Clock Slave: External Signaling
CEFP ED[x] ESIG[x]
Valid tS CECLK tHCECLK t0 CECLK
CECLK
t1 CECLK
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
253
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 22 Symbol tSTLCLK tHTLCLK tPEFP2
- Egress Interface Timing - Clock Master: Full DS1 Figure 42) Description TLCLK[x] to ED[x] Set-up Time7 TLCLK[x] to ED[x] Hold Time8 TLCLK[x]to EFP[x] Propagation delay10,11 Min 20 20 -20 20 Max Units ns ns ns
Figure 42
- Egress Interface Timing - Clock Master: Full DS1 Mode
ED[x]
Valid tS TLCLK tHTLCLK
TLCLK[x]
EFP[x] tP EFP2
Valid
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
254
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 23 - Egress Interface Input Timing - Clock Master : NxDS0 Mode (Figure 43) Symbol tSECLK tHECLK Figure 43 Description ECLK[x] to ED[x] Set-up Time7,9 ECLK[x] to ED[x] Hold Time8,9 Min 20 20 Max Units ns ns
- Egress Interface Input Timing - Clock Master : NxDS0 Mode
ED[x]
Valid tS ECLK tHECLK
ECLK[x]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
255
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 24 Symbol
- Ingress Interface Timing - Clock Slave Modes (Figure 44) Description Common Ingress Clock Frequency1,2 (Typically 1.544 MHz 130 ppm or 2.048 MHz 130 ppm) Min 1.5 Max 2.1 Units MHz
t1CICLK t0CICLK tSCICLK tHCICLK tPCICLK
Common Ingress High Pulse Width4 Common Ingress Low Pulse Width4 CICLK to CIFP Set-up Time7,9 CICLK to CIFP Hold Time8,9 CICLK to Ingress Output Prop. Delay9,10,11
167 167 20 20 20
ns ns ns ns ns
Figure 44
- Ingress Interface Timing - Clock Slave Modes
CIFP
Valid tS CICLK tHCICLK t0 CICLK
CICLK ID[x] ISIG[x] IFP[x]
t1 CICLK
Valid tP CICLK
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
256
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 25 Symbol tPICLK
- Ingress Interface Timing - Clock Master Modes (Figure 45) Description ICLK[x] to Ingress Output Prop. Delay9,10,11 Min 20 Max 20 Units ns
Figure 45
- Ingress Interface Timing - Clock Master Modes ICLK[x]
ID[x] IFP[x] tP ICLK
Valid
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
257
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 26 Symbol
- Transmit Line Interface Timing (Figure 46) Description CTCLK Frequency (when used for TJAT REF), typically 1.544 MHz 130 ppm2,6 Min Max 1.545 Units MHz
tHCTCLK tLCTCLK tPTLCLK
CTCLK High Duration4 (when used for TJAT REF) CTCLK Low Duration4 (when used for TJAT REF) TLCLK[x] to TLD[x] Output Prop. Delay9,10,11 - Transmit Line Interface Timing
160 160 -20 20
ns ns ns
Figure 46
t H CTCLK
CTCLK
t L CTCLK
TLCLK[x]
t CTCLK
TLD[x]] tP TLCLK
Valid
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258
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 27 Symbol
- Receive Line Interface Timing (Figure 47) Description RLCLK[x] Frequency, typically 1.544 MHz 130 ppm2,6 Min Max 1.545 180 180 20 20 Units MHz ns ns ns ns
tHIRLCLK tLORLCLK tSRLCLK tHRLCLK Figure 47
RLCLK[x] High Duration4 RLCLK[x] Low Duration4 RLCLK[x] to RLD[x] Set-up Time7,9 RLCLK[x] to RLD[x] Hold Time8,9 - Line Interface Input Timing
t HI RLCLK
RLCLK[x]
t LO RLCLK
t RLCLK
RLD[x]
Valid tS RLCLK tHRLCLK
RLCLK[x]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
259
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Table 28 Symbol tTCK tDTCK tSTMS tHTMS tSTDI tHTDI tPTDO
- JTAG Port Interface Timing (Figure 48) Description TCK Frequency TCK Duty Cycle4 TMS Set-up time to TCK7 TMS Hold time to TCK8 TDI Set-up time to TCK7 TDI Hold time to TCK8 TCK Low to TDO Valid10,11 40 50 50 50 50 2 50 Min Max 1 60 Units MHz % ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
260
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 48
- JTAG Port Interface Timing Diagram
TCK tSTMS TMS tSTDI TDI tH TDI tHTMS
TCK tP TDO TDO
Notes on AC Timing: 1. CECLK and CICLK can be gapped and/or jittered clock signals subject to the minimum high and low times shown. These specifications correspond to nominal XCLK input frequencies. 2. Guaranteed by design for nominal XCLK input frequency (37.056 MHz 100 ppm). 3. CTCLK can be a jittered clock signal subject to the minimum high and low times shown. These specifications correspond to nominal XCLK input frequency of 37.056 MHz 100 ppm.
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261
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
4. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse width is measured from the 1.4 Volt points of the fall and rise ramps. 5. XCLK frequency must be 24x the line rate 32 ppm when TJAT is freerunning or referenced to a derivative of XCLK. XCLK may be 100 ppm if an accurate reference is provided to TJAT. XCLK frequency may be as high as 50 MHz only if the line rate is increased to 1/24 of XCLK, or if both RJAT and TJAT are bypassed. 6. CTCLK[x] can be a jittered clock signal subject to the minimum high and low durations tHCTCLK, tLCTCLK. These durations correspond to nominal XCLK input frequency. 7. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 8. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 9. Setup, hold, and propagation delay specifications are shown relative to the default active clock edge, but are equally valid when the opposite edge is selected as the active edge. 10. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 11. Output propagation delays are measured with a 50 pF load on all outputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
262
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
19
ORDERING AND THERMAL INFORMATION Table 29 PART NO. PM4388-RI PM4388-NI Table 30 PART NO. PM4388-RI PM4388-NI - TOCTL Ordering Information DESCRIPTION 128 Plastic Quad Flat Pack (PQFP) 128 Chip Array Ball Grid Array (CABGA) - TOCTL Thermal Information AMBIENT TEMPERATURE -40C to 85C -40C to 85C Theta Ja 47 C/W 50 C/W Theta Jc 14 C/W
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263
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
20
MECHANICAL INFORMATION Figure 49 - 128 Pin Copper Leadframe Plastic Quad Flat Pack (R Suffix):
E E1
128
A
1
Pin 1 Designator
e
D
D1
8-12 DEG
8-12 DEG
A2
SEE DETAIL A
0-10 DEG. STANDOFF
NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSIONS SHOWN ARE NOMINAL WITH TOLERANCES AS INDICATED. 3) FOOT LENGTH "L" IS MEASURED AT GAGE PLANE, 0.25 ABOVE SEATING PLANE.
A
.25
A1
SEATING PLANE C 0-7 DEG L b C
0.13-0.23
LEAD COPLANARITY ccc C
DETAIL A
PACKAGE TYPE: 128 PIN METRIC RECTANGULAR PLASTIC QUAD FLATPACK-MQFP BODY SIZE: 14 x 20 x 2.7 MM Dim. Min. Nom. Max. 3.40 0.53 A 2.82 A1 0.25 A2 2.57 2.70 2.87 D 22.95 23.20 23.45 D1 19.90 20.00 20.10 E 16.95 17.20 17.45 E1 13.90 14.00 14.10 L 0.73 0.88 1.03 0.50 e b 0.17 0.22 0.27 0.10 ccc
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
264
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
Figure 50
- 128 Pin Chip Array Ball Grid Array (N Suffix):
A1 BALL CORNER
0.20
-A-
D
-B-
12 11 10 9 8 7 6 5 4 3 2 1 D1 A B C D E F E1 G H J K L M
S e
A1 BALL CORNER
A1 BALL I.D. INK MA RK
S
E
A2
A
-Cb
0.10
SEA TING PLA NE
.15 A C A S B S .08 A C
A1
NOTES: 1) A LL DIMENSIONS IN MILLIMETER.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
265
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
266
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
267
PM4388 TOCTL
DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998 PMC-Sierra, Inc. PM-960840 (R5) ref PMC-960646 (R7) Issue date: October 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

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