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HA-5221
TM
Data Sheet
April 2000
File Number
2915.5
100MHz, Low Noise, Precision Operational Amplifier
The HA-5221 is a single high performance dielectrically isolated, op amp, featuring precision DC characteristics while providing excellent AC characteristics. Designed for audio, video, and other demanding applications, noise (3.4nV/Hz at 1kHz), total harmonic distortion (<0.005%), and DC errors are kept to a minimum. The precision performance is shown by low offset voltage (0.3mV), low bias currents (40nA), low offset currents (15nA), and high open loop gain (128dB). The combination of these excellent DC characteristics with the fast settling time (0.4s) makes the HA-5221 ideally suited for precision signal conditioning. The unique design of the HA-5221 gives it outstanding AC characteristics not normally associated with precision op amps, high unity gain bandwidth (35MHz) and high slew rate (25V/s). Other key specifications include high CMRR (95dB) and high PSRR (100dB). The combination of these specifications will allow the HA-5221 to be used in RF signal conditioning as well as video amplifiers. For MIL-STD-883C compliant product and Ceramic LCC packaging, consult the HA-5221/883C data sheet. (Intersil AnswerFAX (321-724-7800) Document #3716.)
Features
* Gain Bandwidth Product. . . . . . . . . . . . . . . . . . . . 100MHz * Unity Gain Bandwidth. . . . . . . . . . . . . . . . . . . . . . . 35MHz * Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V/s * Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 0.3mV * High Open Loop Gain. . . . . . . . . . . . . . . . . . . . . . . 128dB * Low Noise Voltage at 1kHz. . . . . . . . . . . . . . . . 3.4nV/Hz * High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 56mA * Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Applications
* Precision Test Systems * Active Filtering * Small Signal Video * Accurate Signal Processing * RF Signal Conditioning
Pinout
HA-5221 (CERDIP, SOIC) TOP VIEW
Ordering Information
-BAL 1 8 +BAL 7 V+ + 6 OUT 5 NC
PART NUMBER (BRAND) HA7-5221-5 HA9P5221-5 (H52215)
TEMP. RANGE (oC) 0 to 75 0 to 75
PACKAGE 8 Ld CERDIP 8 Ld SOIC
PKG. NO. F8.3A M8.15
-IN
2
+IN 3 V4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
HA-5221
Absolute Maximum Ratings
Supply Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . 35V Differential Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . 5V Output Current Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 135 50 SOIC Package . . . . . . . . . . . . . . . . . . . 157 N/A Maximum Junction Temperature (Hermetic Package) . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range HA-5221-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Input is protected by back-to-back zener diodes. See applications section. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS Input Offset Voltage
VSUPPLY = 15V, Unless Otherwise Specified TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS
25 Full
12 -
0.30 0.35 0.5 40 70 15 30 400 70 0.25 6.2 3.6 3.4 4.7 1.8 0.97 <0.005
0.75 1.5 100 200 100 150 750 1500 10 6 4.0 8.0 2.8 1.8 -
mV mV V/oC nA nA nA nA V V V k VP-P nV/Hz nV/Hz nV/Hz pA/Hz pA/Hz pA/Hz %
Average Offset Voltage Drift Input Bias Current
Full 25 Full
Input Offset Current
25 Full
Input Offset Voltage Match
25 Full
Common Mode Range Differential Input Resistance Input Noise Voltage f = 0.1Hz to 10Hz
25 25 25 25 25 25 25 25 25 25
Input Noise Voltage Density (Notes 3, 11) f = 10Hz f = 100Hz f = 1000Hz Input Noise Current Density (Notes 3, 11) f = 10Hz f = 100Hz f = 1000Hz THD+N TRANSFER CHARACTERISTICS Large Signal Voltage Gain Note 5 Note 4
25 Full
106 100 86 -
128 120 95 35
-
dB dB dB MHz
CMRR Unity Gain Bandwidth
VCM = 10V -3dB
Full 25
2
HA-5221
Electrical Specifications
PARAMETER Gain Bandwidth Product Minimum Stable Gain OUTPUT CHARACTERISTICS Output Voltage Swing RL = 333 RL = 1k RL = 1k Output Current Output Resistance Full Power Bandwidth TRANSIENT RESPONSE (Note 11) Slew Rate Rise Time Overshoot Settling Time (Notes 9, 10) Notes 7, 11 Notes 8, 11 Notes 8, 11 0.1% 0.01% POWER SUPPLY PSRR Supply Current NOTES: 3. Refer to typical performance curve in data sheet. 4. AVCL = 10, fO = 1kHz, VO = 5VRMS, RL = 600, 10Hz to 100kHz, minimum resolution of test equipment is 0.005%. 5. VOUT = 0 to 10V, RL = 1k, CL = 50pF. Slew Rate 6. Full Power Bandwidth is calculated by: FPBW = -------------------------- , V PEAK = 10V . 2V PEAK 7. VOUT = 2.5V, RL = 1k, CL = 50pF. 8. VOUT = 100mV, RL = 1k, CL = 50pF. 9. Settling time is specified for a 10V step and AV = -1. 10. See Test Circuits. 11. Guaranteed by characterization. VS = 10V to 20V Full Full 86 100 8 11 dB mA Full Full Full 25 25 15 25 13 28 0.4 1.5 20 50 V/s ns % s s Note 6 VOUT = 10V Full 25 Full Full 25 25 10 12 11.5 30 239 12.5 12.1 56 10 398 V V V mA kHz VSUPPLY = 15V, Unless Otherwise Specified (Continued) TEST CONDITIONS 1kHz to 400kHz TEMP. (oC) 25 Full MIN 1 TYP 100 MAX UNITS MHz V/V
Test Circuits and Waveforms
VIN +
-
VOUT 1k 50pF
FIGURE 1. TRANSIENT RESPONSE TEST CIRCUIT
3
HA-5221 Test Circuits and Waveforms
(Continued)
2.5V 0V
100mV VIN 0V
-100mV -2.5V
2.5V
100mV VOUT 0V
0V -100mV -2.5V
VOUT = 2.5V Vertical Scale = 2V/Div., Horizontal Scale = 200ns/Div. FIGURE 2. LARGE SIGNAL RESPONSE
VOUT = 100mV Vertical Scale = 100mV/Div., Horizontal Scale = 200ns/Div. FIGURE 3. SMALL SIGNAL RESPONSE
VSETTLE
5K
5K 2K 2K
VIN
+
VOUT
NOTES: 12. AV = -1. 13. Feedback and summing resistors must be matched (0.1%). 14. HP5082-2810 clipping diodes recommended. 15. Tektronix P6201 FET probe used at settling point. FIGURE 4. SETTLING TIME TEST CIRCUIT
Application Information
Operation at Various Supply Voltages
The HA-5221 operates over a wide range of supply voltages with little variation in performance. The supplies may be varied from 5V to 15V. See typical performance curves for variations in supply current, slew rate and output voltage swing.
+15V
7 2 3
RP 1 8 + 4
6
Offset Adjustment
The following diagram shows the offset voltage adjustment configuration for the HA-5221. By moving the potentiometer wiper towards pin 8 (+BAL), the op amps output voltage will increase; towards pin 1 (-BAL) decreases the output voltage. A 20k trim pot will allow an offset voltage adjustment of about 10mV.
-15V
Capacitive Loading Considerations
When driving capacitive loads >80pF, a small resistor, 50 to 100, should be connected in series with the output and inside the feedback loop.
4
HA-5221
Saturation Recovery
When an op amp is over driven, output devices can saturate and sometimes take a long time to recover. By clamping the input, output saturation can be avoided. If output saturation can not be avoided, the maximum recovery time when overdriven into the positive rail is 10.6s. When driven into the negative rail the maximum recovery time is 3.8s.
VIN RLIMIT 2 6 RLIMIT 3 + VOUT
PC Board Layout Guidelines
When designing with the HA-5221, good high frequency (RF) techniques should be used when building a PC board. Use of ground plane is recommended. Power supply decoupling is very important. A 0.01F to 0.1F high quality ceramic capacitor at each power supply pin with a 2.2F to 10F tantalum close by will provide excellent decoupling. Chip capacitors produce the best results due to ease of placement next to the op amp and basically no lead inductance. If leaded capacitors are used, the leads should be kept as short as possible to minimize lead inductance.
Input Protection
The HA-5221 has built in back-to-back protection diodes which limit the maximum allowable differential input voltage to approximately 5V. If the HA-5221 is used in circuits where the maximum differential voltage may be exceeded, then current limiting resistors must be used. The input current should be limited to a maximum of 10mA.
Typical Performance Curves
RL = 1K, CL = 50pF 120
VS = 15V, TA = 25oC
12 9 GAIN (dB) 6 GAIN PHASE MARGIN (DEGREES) 3 0 -3 -6 PHASE 180 135 90 45 10K 100K 1M FREQUENCY (Hz) 10M 0 100M AV = +1, RL = 1K, CL = 50pF
100 GAIN (dB) 60 40 20 0 PHASE 180 135 90 45 0 1K 10K 100K 1M 10M 100M PHASE MARGIN (DEGREES) 80 GAIN
FREQUENCY (Hz)
FIGURE 5. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 6. CLOSED LOOP GAIN vs FREQUENCY
6 3 0
AV = -1, RL = 1K, CL = 50pF
CLOSED LOOP GAIN (dB)
GAIN (dB)
9
80 60 40 20 0 AV = -10 AV = -100 180 135 90 AV = -1000 45 0 10K 100K 1M FREQUENCY (Hz) 10M 100M AV = -1000 AV = -100 AV = -10 PHASE MARGIN (DEGREES) RL = 1K, CL = 50pF
GAIN PHASE MARGIN (DEGREES)
PHASE
180 135 90 45 0
10K
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 7. CLOSED LOOP GAIN vs FREQUENCY
FIGURE 8. VARIOUS CLOSED LOOP GAINS vs FREQUENCY
5
HA-5221 Typical Performance Curves
120 100 CMRR (dB) 80 PSRR (dB) 60 40 20 0 AV = +1, RL = 1K 100 80 60 40 20 0 +PSRR -PSRR
VS = 15V, TA = 25oC (Continued)
AV = +1, RL = 1K
10K
100K
1M FREQUENCY (Hz)
10M
100M
10K
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 9. CMRR vs FREQUENCY
FIGURE 10. PSRR vs FREQUENCY
20 18 OPEN LOOP GAIN (V/V) 16 OFFSET VOLTAGE (V) -40 -20 0 20 40 60 80 100 120 RL = 1K
300 250 200 150 100 50 0 -50 -100 -60
14 12 10 8 6 4 2 0 -60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 11. OPEN LOOP GAIN vs TEMPERATURE
FIGURE 12. OFFSET VOLTAGE vs TEMPERATURE (4 REPRESENTATIVE UNITS)
14 PEAK OUTPUT VOLTAGE (V) 13.5 13 12.5 12 11.5 11 10.5 10 -40 -20 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) TEMPERATURE (oC) RL = 600
160 BIAS CURRENT (nA) 140 120 100 80 60 40 20 0 -20 -40 -60
FIGURE 13. BIAS CURRENT vs TEMPERATURE (4 REPRESENTATIVE UNITS)
FIGURE 14. OUTPUT VOLTAGE SWING vs TEMPERATURE
6
HA-5221 Typical Performance Curves
SLEW RATE (NORMALIZED TO 1 AT 25oC) 1.1 AV = +1, RL = 1K, CL = 50pF OFFSET VOLTAGE CHANGE (V) 1.05 60 50 40 30 20 10 0 -40 -20 0 20 40 60 80 100 120 0 1 2 3 4 5 TEMPERATURE (oC) TIME AFTER POWER UP (MINUTES)
VS = 15V, TA = 25oC (Continued)
70
1.0 0.95 0.9 0.85 0.8 -60
FIGURE 15. SLEW RATE vs TEMPERATURE
FIGURE 16. OFFSET VOLTAGE WARM-UP DRIFT (CERDIP PACKAGES)
8.5
36 34 32 SLEW RATE (V/s) 30 28 26 24 22 20 18 16 14 12 10 5 7 9 11 13 15 17 5
AV = +1, RL = 2K, CL = 50pF +SLEW RATE
SUPPLY CURRENT (mA)
8.25
8
-SLEW RATE
7.75
7.5 SUPPLY VOLTAGE (V)
7
9
11
13
15
17
SUPPLY VOLTAGE (V)
FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 18. SLEW RATE vs SUPPLY VOLTAGE
20 PEAK OUTPUT VOLTAGE SWING (V) RL = 600 16 15 VOLTAGE NOISE (nV/Hz) 14 12 10 8 6 4 2 0 5 7 9 11 13 SUPPLY VOLTAGE (V) 15 17 1 10 100 FREQUENCY (Hz) 1K VOLTAGE NOISE 24 CURRENT NOISE (pA/Hz) 21 18 15 12 9 6
10
5
CURRENT NOISE 3 0 10K
0
FIGURE 19. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE
FIGURE 20. NOISE CHARACTERISTICS
7
HA-5221 Typical Performance Curves
100 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -60
VS = 15V, TA = 25oC (Continued)
115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 -60
OFFSET CURRENT (nA)
CMRR AND PSRR (dB)
+PSRR -PSRR
CMRR
-40
-20
0
20 40 60 TEMPERATURE (oC)
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (oC)
FIGURE 21. OFFSET CURRENT vs TEMPERATURE (4 REPRESENTATIVE UNITS)
FIGURE 22. CMRR AND PSRR vs TEMPERATURE
45 PHASE MARGIN 40 BANDWIDTH (MHz) 35 BANDWIDTH 30 AV = +1, RL = 1K
120 100 80 60 40
130
PHASE MARGIN (DEGREE)
OUTPUT CURRENT (mA)
110
90
25 20 15 1 10 100 1000 LOAD CAPACITANCE (pF)
70
20 0
50 0 1 2 3 4 5 TIME AFTER SHORT CIRCUIT (MINUTES)
FIGURE 23. BANDWIDTH AND PHASE MARGIN vs LOAD CAPACITANCE
FIGURE 24. SHORT CIRCUIT OUTPUT CURRENT vs TIME
Vertical Scale = 1mV/Div.; Horizontal Scale = 1s/Div. AV = +25,000; EN = 0.168VP-P RTI FIGURE 25. 0.1Hz TO 10Hz NOISE
Vertical Scale = 10mV/Div.; Horizontal Scale = 1s/Div. AV = +25,000; EN = 1.5VP-P RTI FIGURE 26. 0.1Hz TO 1MHz
8
HA-5221 Typical Performance Curves
18 16 PEAK OUTPUT VOLTAGE (V) 14 12 10 8 6 4 2 VS = 5 100K 1M 10M VS = 10 VS = 15 VS = 18
VS = 15V, TA = 25oC (Continued)
18 16 PEAK OUTPUT VOLTAGE (V) 14 12 10 8 6 4 2 0 10 100 1K 10K VS = 5 VS = 10
AV = +1, RL = 1K, CL = 15pF, THD 0.01%
AV = +1, THD 0.01%, f = 1kHz
VS = 18 VS = 15
0 10K
FREQUENCY (Hz)
LOAD RESISTANCE ()
FIGURE 27. OUTPUT VOLTAGE SWING vs FREQUENCY
FIGURE 28. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
10 9.5 SUPPLY CURRENT (mA) 9 8.5 8 7.5 7 6.5 6 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC)
FIGURE 29. SUPPLY CURRENT vs TEMPERATURE
9
HA-5221 Die Characteristics
DIE DIMENSIONS: 72 mils x 94 mils 1840m x 2400m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: 62 PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5221
V+IN -IN
-BAL
+BAL
OUT
V+
10
HA-5221 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH
aaa bbb ccc M N
11
HA-5221 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
L
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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