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| CALIFORNIA MICRO DEVICES PAC DN002 Applications Parallel printer port protection ESD protection for sensitive electronic equipment Drop-in replacement for PDN 002 17 CHANNEL ESD PROTECTION ARRAY Features 17-channel ESD protection 8kV contact discharge ESD protection per IEC 61000-4-2 15kV ESD protection (HBM) Low loading capacitance, 5.5pF typ. 20-pin SOIC or QSOP package Product Description The PAC DN002 is a diode array designed to provide 17 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (VP) or negative (VN) supply. The PAC DN002 will protect against ESD pulses up to 15KV Human Body Model. This device is particularly well-suited to provide additional ESD protection for parallel printer ports. It exhibits low loading capacitance for all signal lines. ABSOLUTE MAXIMUM RATINGS SCHEMATIC CONFIGURATION Diode Forward DC Current (Note 1) 20mA Storage Temperature -65C to 150C Operating Temperature Range -20C to 85C DC Voltage at any Channel Input VN-0.5V to VP+0.5V Note 1: Only one diode conducting at a time. STANDARD SPECIFICATIONS STANDARD SPECIFICATIMiNS O n. Parameter Paraatieter upply Voltage (V - V ) m ng S Min. Oper P N Opppaying rSentp(lV VoVage (V P2 .0 V, T = 25C Su er l t Cu r up y P - lt N) = 1 - V N) SuodeyFCuwent (V Ptage, I== 200 V, ,TT =55C 0.65 V Di ppl or rrard Vol - V N) F 1 2 . mA =2 2 C 0.65 V D iode Forward Voltage, I F = 20mA, T = 25C ESD Protection ESD Protection Voltage at any Channel Input Voltage at any Channel Input Human Body Model, Method 3015 (See Note 2, 3) 15KV Human Body Model, Method 3015 (See Note 2, 3) 15KV 8KV Contact Discharge per IEC 1000-4-2 (See Note 4) 8KV Contact D ischarge per IEC 1000-4-2 (See Note 4) Channel Clamp Voltage under ESD test conditions Channel Clamp Voltage under ESD test conditions specified above, T = 25C (Notes 2,3,4) specified above, T = 25C (Notes 2,3,4) Positive transients Positive transients 00 Negative transients 00 Negative transients Channel Leakage Current, T = 25C Channel Leakage Current, T = 25C Channel Input Capacitance (Measured @ 1 MHz) VP = 12V, VN = 0V, V IN = 6 V (See Note 4) Package Power Rating Note 2: Note 3: Note 4: Typ. Typ. Max. M .0 . 12axV 10 .A 1 2 0V 100V 1. A 1.0 V 0.1 A 0.1 A 5.5pF V P + 13.0 V V P + 13.0 V V N - 13.0 V V N - 13.0 V 1.0 A 1.0 A 12pF 1.00W From I/O pins to VP or VN only. VP bypassed to VN with 0.2 F ceramic capacitor. Human Body Model per MIL-STD-883, Method 3015, C Discharge=100pF, RDischarge=1.5K, VP=12V, VN=GND. This parameter is guaranteed by characterization. (c)1999 California Micro Devices Corp. All rights reserved. P/Active and PAC are trademarks of California Micro Devices. 11/99 C0270498D 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1 CALIFORNIA MICRO DEVICES Input Capacitance vs. Input Voltage 12 11 PAC DN002 Input Capacitance (pF) 10 9 8 7 6 5 4 3 2 0 2 4 6 8 10 12 Input Voltage (V) Typical variation of CIN with VIN (VP = 12V, VN = 0V, 0.1F chip capacitor between VP & VN) STANDARD PART ORDE RING INFORMATION Package Ordering Part Number Style Part Marking SOIC QSOP PACD N002S PACD N002Q Pins 20 20 When placing an order please specify desired shipping: Tubes or Tape & Reel. Application Information See also California Micro Devices Application note AP209, Design Considerations for ESD protection. In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the power supply is represented by L1. The voltage VZ on the line being protected is: VZ = Forward voltage drop of D1 + L1 x d(Iesd)/dt + VSupply where Iesd is the ESD current pulse, and VSupply is the positive supply voltage. Figure 1 An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(Iesd)/dt can be approximated by Iesd/t, or 30/(1x10-9). So just 10nH of series inductance (L1) will lead to a 300V increment in VZ! (c) 1999 California Micro Devices Corp. All rights reserved. 2 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 11/99 CALIFORNIA MICRO DEVICES PAC DN002 Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a much higher output impedance to fast transient current spikes. In the VZ equation above, the VSupply term, in reality, is given by (VDC + Iesd x Rout), where VDC and Rout are the nominal supply DC output voltage and effective output impedance of the power supply respectively. As an example, a Rout of 1 ohm would result in a 10V increment in VZ for a peak Iesd of 10A. To mitigate these effects, a high frequency bypass capacitor should be connected between the VP pin of the ESD Protection Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with minimal change in VP. Typically a value in the 0.1 F to 0.2 F range is adequate for IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray series inductance. (c)1999 California Micro Devices Corp. All rights reserved. 11/99 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 3 |
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