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INTEGRATED CIRCUITS
DATA SHEET
TDA8315T Integrated NTSC decoder and sync processor
Preliminary specification File under Integrated Circuits, IC02 September 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
FEATURES * CVBS or Y/C input * Integrated chrominance trap and bandpass filters (automatically calibrated) * Integrated luminance delay line * Alignment-free NTSC colour decoder * Horizontal PLL with an alignment-free horizontal oscillator * Vertical count-down circuit * Low dissipation (320 mW) * Small amount of peripheral components compared with competition ICs. QUICK REFERENCE DATA SYMBOL VP IP Input voltages V13(p-p) V15(p-p) Output signals VO(b-w) V21(p-p) V20(p-p) V2 V7 V10 Control voltages Vcontrol control voltages for Saturation and Hue 0 - 5 luminance output voltage (blank-to-white value) -U output voltage (peak-to-peak value) -V output voltage (peak-to-peak value) horizontal sync pulse vertical sync pulse back porch clamping pulse - - - - - - 1.65 1.5 1.5 4 4 4 - - - - - - CVBS/Y input voltage (peak-to-peak value) chrominance input voltage (peak-to-peak value) - - 1 0.3 - - supply current PARAMETER supply voltage (pins 11 and 12) - MIN. 7.2 TYP. 8.0 40 - GENERAL DESCRIPTION
TDA8315T
The TDA8315T is an alignment-free NTSC decoder/sync processor. The device can be used for normal television applications and for Picture-in-Picture (PIP) applications. The input signal can be either CVBS or Y/C and at the outputs the following signals are available: Luminance signal Colour difference signals (U and V) Horizontal and vertical synchronization pulses Back porch clamping pulse (burst-key pulse). The supply voltage for the IC is 8 V. It is available in a 24-pin SO package.
MAX. 8.8 V
UNIT mA
V V
V V V V V V
V
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8315T SO24 DESCRIPTION plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT137-1
September 1994
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DEC DIG DEC BG V P1 V P2 GND1 GND2 9 5 11 12 3 23 COINCIDENCE DETECTOR VERTICAL SYNC SEPARATOR SYNC SEPARATOR CHROMINANCE TRAP CVBS CHROMA CVBS/Y switch 13 15 CVBS/Y SWITCH CHROMINANCE BANDPASS reference 21 NTSC DECODER MATRIX U/V-SIGNALS 18 17 8 SATURATION CONTROL 16
MBE015
BLOCK DIAGRAM
Philips Semiconductors
Integrated NTSC decoder and sync processor
PH1LF
4 PHASE DETECTOR OSCILLATOR PLUS CONTROL PULSE SHAPER 2
HOUT
10
CLAMP VOUT
H/V DIVIDER
7
FILTER TUNING
LUMINANCE DELAY LINE
AMPLIFIER
19
Y
DEC FT
handbook, full pagewidth
3
U V
20
TDA8315T
14 22 24
SSC HUE PLL XTAL
DEM SW
SAT
Preliminary specification
TDA8315T
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
PINNING SYMBOL TEST1(1) HOUT GND1 PH1LF DECBG TEST2(1) VOUT DEMSW DECDIG CLAMP VP1 VP2 CVBS/Y DECFT CHROMA SAT SCS HUE Y -V -U PLL GND2 XTAL Note 1. In the application the test pins must be connected to ground. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 test pin 1 horizontal output pulse ground 1 (0 V) phase 1 loop filter bandgap decoupling test pin 2 vertical output pulse demodulation angle switch decoupling digital supply back porch clamping pulse supply voltage 1 (+8 V) supply voltage 2 (+8 V) CVBS/Y input decoupling filter tuning chrominance and switch input saturation control input sub-carrier signal output hue control input Y output -V output -U output PLL colour filter ground 2 (0 V) 3.58 MHz crystal connection
handbook, halfpage
TDA8315T
DESCRIPTION
TEST1 HOUT GND1 PH1LF BG DEC TEST2 VOUT DEM SW DEC DIG
1 2 3 4 5 6 TDA8315T 7 8 9
24 XTAL 23 GND2 22 PLL 21 20 19 Y 18 HUE 17 SCS 16 SAT 15 CHROMA 14 DEC FT 13 CVBS/Y
MBE016
U V
CLAMP 10 V P1 11 V P2 12
Fig.2 Pin configuration.
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
FUNCTIONAL DESCRIPTION CVBS or Y/C input The TDA8315T has a video input which can be switched to CVBS (with internal chrominance bandpass and trap filters) and to Y/C (without chrominance bandpass and trap filters). The switching between CVBS and Y/C is achieved by the DC level of the CHROMA input (pin 15). Integrated video filters The circuit contains a chrominance bandpass and trap circuit. The filters are realised by gyrator circuits that are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. The chrominance trap can be switched off by the DC level of the CHROMA input. The luminance delay line is also realised by gyrator circuits. Colour decoder The colour decoder contains an alignment-free crystal oscillator, a colour killer circuit and colour difference demodulators. The gain of the two colour difference signal demodulators is identical and the phase angle of the reference carrier signals is 90. This phase shift is achieved internally. It is possible to switch the demodulator angle to 110 by an internal matrix circuit. The switching is obtained externally via pin 8. Synchronization circuit
TDA8315T
The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed level. The sync pulses are then fed to the slicing stage (separator) which operates at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence detector is used to detect whether the line oscillator is synchronized. The PLL has a very high static steepness, this ensures that the phase of the picture is independent of the line frequency. The line oscillator operates at twice the line frequency. The oscillator network is internal. Because of the spread of internal components an automatic adjustment circuit has been added to the IC. The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in a free-running frequency which deviates less than 2% from the typical value. The horizontal output pulse is derived from the horizontal oscillator via a pulse shaper. The pulse width of the output pulse is 5.4 s, the front edge of this pulse coincides with the front edge of the sync pulse at the input. The vertical output pulse is generated by a count-down circuit. The pulse width is approximately 380 s. Both the horizontal and vertical pulses will always be available at the outputs even when no input signal is available.
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL VP Tstg Tamb Tsld Tj supply voltage storage temperature operating ambient temperature soldering temperature for 5 s maximum operating junction temperature PARAMETER - -25 -25 - - MIN. 9.0 +150 +70 260 125
TDA8315T
MAX. V C C C C
UNIT
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 65 UNIT K/W
CHARACTERISTICS VP = 8 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VP IP Ptot supply voltage (pins 11 and 12) supply current (pins 11 and 12) total power dissipation 7.2 - - 8.0 40 320 8.8 - - V mA mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
CVBS or Y/C input CVBS/Y INPUT (PIN 13) V13(p-p) I13 V15(p-p) V15(p-p) RI CI V15 V15 CVBS/Y input voltage (peak-to-peak value) notes 1 and 2 CVBS/Y input current - - notes 2 and 3 note 2 - 1 - note 4 - 3 - 1 4 1.4 - - - - 5 5 1 V A V V k pF V V
COMBINED CHROMINANCE AND SWITCH INPUT (PIN 15) chrominance input voltage (peak-to-peak value) input signal amplitude before clipping occurs (peak-to-peak value) chrominance input resistance chrominance input capacitance DC input voltage for Y/C operation DC input voltage for CVBS operation 0.3 - 15 - 4 -
Chrominance filters and luminance delay line CHROMINANCE TRAP CIRCUIT ftrap B SR trap frequency luminance signal bandwidth colour subcarrier rejection note 2 - - 20 3.58 2.7 - - - - MHz MHz dB
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
SYMBOL PARAMETER CONDITIONS - - note 2 note 2 - 8 - - - notes 2 and 5 - MIN. TYP.
TDA8315T
MAX. - - - - - - - -
UNIT
CHROMINANCE BANDPASS CIRCUIT fc QBP Y DELAY LINE td B delay time bandwidth of internal delay line 390 - 2.27 350 2.85 56 ns MHz centre frequency bandpass quality factor 3.58 3 MHz
Y OUTPUT SIGNAL (PIN19) V19(p-p) ZO V19 S/N output signal amplitude (peak-to-peak value) output impedance top sync level signal-to-noise ratio note 1 V V dB
Colour decoder CHROMINANCE AMPLIFIER ACCcr V THRon HYSoff ACC control range change in amplitude of the output signals over the ACC range threshold colour killer ON hysteresis colour killer OFF strong input signal noisy input signal ACL CIRCUIT chrominance burst ratio at which the ACL starts to operate REFERENCE PART 2.3 - 2.7 note 2 S/N 40 dB - - +3 +1 - - dB dB note 6 24 - tbf - - -31 - 2 tbf dB dB dB
Phase-locked loop; note 7 (filter connected to pin 22)
fCR catching range phase shift for a 400 Hz deviation of the oscillator frequency note 7 300 - 500 - - 2 Hz deg
Oscillator (pin 24)
TCosc fosc RI CI HUEcr SATcr temperature coefficient of fosc fosc deviation with respect to VP input resistance input capacitance note 2 note 2; VP = 8 V10% note 4 note 4 - - - - 35 52 2.0 - 1.5 - 45 - 2.5 250 - 10 - - Hz/K Hz k pF
HUE CONTROL INPUT (PIN 18) hue control range see also Fig.3 deg
SATURATION CONTROL INPUT (PIN 16) saturation control range see also Fig.4 dB
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
SYMBOL PARAMETER CONDITIONS -3 dB; note 8 note 2 note 2 - - - 0.9 85 105 note 9 note 9 - - - - - VP - 1 - - - MIN. TYP.
TDA8315T
MAX. - - 0.1 1.1 95 115 - - 500 - 1 - - - -
UNIT
DEMODULATOR OUTPUTS (PINS 20 AND 21) B VO/T VO/VP G bandwidth of demodulators change of output signal amplitude with temperature change of output signal amplitude with supply voltage gain ratio of demodulator G(-U)/G(-V) demodulator angle pin 8 LOW pin 8 HIGH V21(p-p) V20(p-p) ZO VO V8 V8 V17(p-p) ZO VO -U output signal amplitude at nominal saturation (peak-to-peak value) -V output signal amplitude at nominal saturation (peak-to-peak value) output impedance (-U)/(-V) output DC output voltage 90 110 1.5 1.5 - 3 - - 300 250 1.6 deg deg V V V 650 0.1 - 1.0 kHz %/K dB
DEMODULATION ANGLE SWITCH INPUT (PIN 8) input voltage for 90 angle input voltage for 110 angle V V
SUBCARRIER OUTPUT SIGNAL (PIN 17) output signal amplitude (peak-to-peak value) output impedance DC output voltage mV V
Horizontal and vertical synchronization circuits SYNC VIDEO INPUT (PIN 13) V13 SL sync pulse amplitude slicing level note 4 note 10 50 - 22 300 50 - - - - mV % s
VERTICAL SYNC tW width of the vertical sync pulse without sync note 11 instability
HORIZONTAL OSCILLATOR ffr ffr fosc/VP fosc/T free-running frequency spread on free running frequency frequency variation with respect to the supply voltage frequency variation with temperature VP = 8 V10%; note 2 note 2 - - - - 15734 - 0.2 - - 2 0.5 tbf Hz % % Hz/K
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
SYMBOL PARAMETER CONDITIONS - note 2 0.6 - MIN. TYP. 0.9 0.9 20
TDA8315T
MAX. 1.2 - -
UNIT
HORIZONTAL PLL; NOTE 12 (FILTER CONNECTED TO PIN 4) fHR fCR S/N holding range PLL catching range PLL signal-to-noise ratio of the video input signal at which the time constant is switched hysteresis at the switching point kHz kHz dB
HYS
- IO = 2 mA IO = 2 mA 2.4 - - - note 13 - -
3
- - 0.6 2 2 - -
dB
HORIZONTAL OUTPUT (PIN 2) VOH VOL IO(sink) IO(source) tW td HIGH level output voltage LOW level output voltage output sink current output source current pulse width delay time between positive edge of the horizontal output pulse and start of the horizontal sync pulse at the input 4.0 0.3 - - 5.4 0 V V mA mA s s
BACK PORCH CLAMPING OUTPUT (PIN 10) VOH VOL IO(sink) IO(source) tW td HIGH level output voltage LOW level output voltage output sink current output source current pulse width delay time between start of clamping pulse and start of the start sync pulse IO = 2 mA IO = 2 mA 2.4 - - - 3.2 5.2 4.0 0.3 - - 3.4 5.4 - 0.6 2 2 3.6 5.6 V V mA mA s s
VERTICAL OUTPUT (PIN 7); NOTE 14 ffr flock free-running frequency locking range divider value not locked locking range (lines/frame) VOH VOL IO(sink) IO(source) tW td HIGH level output voltage LOW level output voltage output sink current output source current pulse width (6 line periods) delay time between start of the vertical sync pulse at the input and the positive edge of the output pulse IO = 2 mA IO = 2 mA - 54.6 - 488 2.4 - - - - - 60 - 525 - 4.0 0.3 - - 380 37.5 - 64.5 - 576 - 0.6 2 2 - - V V mA mA s s Hz Hz
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
Notes to the characteristics 1. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
TDA8315T
2. This parameter is not tested during production and is guaranteed by the design and qualified by matrix batches which are made in the pilot production period. 3. Burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mV (p-p). 4. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 5. The signal-to-noise ratio is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). 6. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)) the dynamic range of the ACC is +6 and -18 dB. 7. All frequency variations are referenced to 3.58 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520. If the spurious response of the crystal is lower than -3 dB with respect to the fundamental frequency for a damping resistance of 1.5 k, oscillation at the fundamental frequency is guaranteed. The catching and detuning range are measured for nominal crystal parameters. These are: a) load resonance frequency f0 (CL = 20 pF) = 3.579545 MHz b) motional capacitance CM = 14.5 fF c) parallel capacitance C0 = 4.5 pF. The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. The free-running frequency of the oscillator can be checked by pulling the saturation control pin to the positive supply rail. In that condition the colour killer is not active so that the frequency offset is visible on the screen. 8. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter. The bandwidth of the demodulator low-pass filter is approximately 1 MHz. 9. Output signal amplitude for a standard colour bar signal with 75% saturation and a demodulation angle of 90. For a demodulation angle of 110 the -V signal amplitude will decrease to 1.2 V (p-p) and the -U signal amplitude remains unchanged. The nominal saturation is specified as maximum -6 dB. 10. Slicing level independent of sync pulse amplitude. The slicing level of the vertical sync separator is 70% (slicing level in direction of black level) during strong signal reception (no noise detected in the incoming signal) and 30% during weak signal reception. 11. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 s. 12. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time constant is switched to `slow' when excessive noise is present in the signal. In the `fast' mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. To prevent the horizontal synchronization being disturbed by anti-copy guard signals such as Macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately 12 s. during weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 s so that the effect of the noise is reduced to a minimum. The output current of the phase detector in the two modes is shown in Table 1.
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
TDA8315T
13. The horizontal output pulses are obtained from the horizontal oscillator by a pulse shaper. The width of the output pulse is approximately 5.4 s and the rising edge of the pulse symmetrically coincides with the start of the sync pulse at the input. 14. The vertical output pulses are generated by a divider circuit. The vertical output pulse has a delay of 37.5 s with respect to the start of the vertical sync pulse at the input. This is caused by the clock frequency of the divider being twice the horizontal frequency. This divider circuit has 2 modes of operation: Search mode (large window). This mode is switched on when the circuit is not synchronized or, when a non-standard signal is received (the number of lines per frame outside the range is between 261 and 264). In the search mode the divider can be triggered between line 244 and line 288 (approximately 54 to 64.5 Hz). Standard mode (narrow window). This mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the output pulse is generated at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. When no input signal is available the divider generates output pulses with a timing of 262.5 lines (standard 60 Hz signal). Table 1 Output current of phase detector. CURRENT PHASE DETECTOR DURING Weak signal and synchronized Strong signal and synchronized Not synchronized Note 1. Vertical retrace. QUALITY SPECIFICATION Quality level in accordance with SNW-FQ-611-part E. SYMBOL ESD PARAMETER protection circuit specification (note 1) RANGE A(2) >2000 100 1500 Notes 1. All pins are protected against ESD by means of internal clamping diodes. 2. Range A is for Human body model. 3. Range B is for machine model. Latch up All pins meet the specification: Itrigger 100 mA or 1.5 VDDmax Itrigger -100 mA or -0.5 VDDmax. RANGE B(3) >200 200 0 V pF UNIT SCAN (A) 30 180 180 VERTICAL RETRACE (A) 30 270 270 GATED YES/NO YES (5.7 s) YES (12 s)(1) NO
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
TDA8315T
MBE018
handbook, halfpage 40
handbook, halfpage
MBE017
200
(deg)
(%)
20
150
0
100
20
50
40
0
0
1
2
3
4
(V)
5
0
1
2
3
4
(V)
5
Fig.3 Hue control curve
Fig.4 Saturation control curve.
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
PACKAGE OUTLINE
TDA8315T
handbook, full pagewidth
15.6 15.2
7.6 7.4
A
S 0.9 (4x) 0.4
0.1 S
10.65 10.00
24
13 2.45 2.25 1.1 1.0 0.3 0.1 0.32 0.23 2.65 2.35
pin 1 index 1 12 detail A 1.1 0.5 0 to 8o
MBC235 - 1
1.27
0.49 0.36
0.25 M (24x)
Dimensions in mm.
Fig.5 Plastic small outline package; 24 leads; large body (SO24, SOT137-1).
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
SOLDERING Plastic small-outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C.
TDA8315T
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
September 1994
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Philips Semiconductors
Preliminary specification
Integrated NTSC decoder and sync processor
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8315T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
September 1994
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Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)14163160/4163333, Fax. (01)14163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors LTD., 276 Bath road, Hayes, MIDDLESEX UB3 5BX, Tel. (081)73050000, Fax. (081)7548421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD34 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
533061/1500/01/pp16 Document order number: Date of release: September 1994 9397 739 00011
Philips Semiconductors

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