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INTEGRATED CIRCUITS
DATA SHEET
TDA8764 10-bit high-speed low-power ADC with internal reference regulator
Preliminary specification 1999 Jan 12
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
FEATURES * 10-bit resolution (binary or gray code) * Sampling rate up to 40 MHz (/4 version) Sampling rate up to 80 MHz (/8 version) * DC sampling allowed * One clock cycle conversion only * High signal-to-noise ratio over a large analog input frequency range (9.5 effective bits at 5 MHz; full-scale input at fclk = 40 MHz) * No missing codes guaranteed * In-Range (IR) CMOS output * TTL and CMOS levels compatible digital inputs * 2.7 to 3.6 V CMOS digital outputs * Low-level AC clock input signal allowed * Internal reference voltage regulator * Power dissipation only 250 mW (typical for /4 version) Power dissipation only 375 mW (typical for /8 version) * Low analog input capacitance, no buffer amplifier required * No sample-and-hold circuit required. ORDERING INFORMATION TYPE NUMBER TDA8764TS/4 TDA8764TS/8 TDA8764HL/4 TDA8764HL/8 LQFP32 PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm VERSION SOT341-1 SOT401-1 APPLICATIONS
TDA8764
High-speed analog-to-digital conversion for: * Video data digitizing * Radar pulse analysis * Transient signal analysis * High energy physics research * modulators * Medical imaging. GENERAL DESCRIPTION The TDA8764 is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary or gray coded digital words at a maximum sampling rate of 40 MHz (/4 version) and 80 MHz (/8 version). All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed. The device includes an internal voltage reference regulator.
SAMPLING FREQUENCY (MHz) 40 80 40 80
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA PARAMETER analog supply voltage digital supply voltage output stages supply voltage analog supply current TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 ICCD digital supply current TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 ICCO output stages supply current TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 INL integral non-linearity TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 DNL differential non-linearity TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 fclk(max) maximum clock frequency TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 Ptot total power dissipation TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 fclk = 40 MHz; ramp input fclk = 80 MHz; ramp input - - 250 375 40 80 - - - - fclk = 40 MHz; ramp input fclk = 80 MHz; ramp input - - 0.25 0.25 fclk = 40 MHz; ramp input fclk = 80 MHz; ramp input - - 0.8 0.8 fclk = 40 MHz; ramp input fclk = 80 MHz; ramp input - - 0 0 - - 25 30 - - 25 45 CONDITIONS MIN. 4.75 4.75 2.7 TYP. 5.0 5.0 3.3
TDA8764
MAX. 5.25 5.25 3.6 tbf tbf tbf tbf tbf tbf tbf tbf tbf tbf
UNIT V V V mA mA mA mA mA mA LSB LSB LSB LSB MHz MHz mW mW
tbf tbf
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
BLOCK DIAGRAM
TDA8764
handbook, full pagewidth
VCCA 3 (7)
DEC 5 (10)
CLK 1 (5)
VCCD2
OE
GRAY
11 (17) 10 15 (21) (16) 2 (6)
REFERENCE VOLTAGE REGULATOR VRT 9 (15)
CLOCK DRIVER
TC
25 (31) 24 (30) 23 (29) analog VI 8 (14) voltage input VRM 7 (13) ANALOG-TO-DIGITAL CONVERTER RLAD LATCHES CMOS OUTPUTS 22 (28) 21 (27) 20 (26) 19 (25) 18 (24) 17 (23) 16 (22) VRB 6 (12) CMOS OUTPUT 13 (19)
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB
data outputs
LSB
VCCO 26 (2) 28 (4) 4 (8) AGND 12 (18) DGND2 digital ground 14 (20) OGND output ground 27 (3) DGND1 digital ground
FCE099
TDA8764
IN-RANGE LATCH
IR output VCCD1
analog ground
The pin numbers given in parenthesis refer to the LQFP32 package.
Fig.1 Block diagram.
1999 Jan 12
4
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
PINNING PINS SYMBOL SSOP28 CLK TC VCCA AGND DEC VRB VRM VI VRT OE VCCD2 DGND2 VCCO OGND GRAY D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 IR DGND1 VCCD1 n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 - LQFP32 5 6 7 8 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 2 3 4 clock input twos complement input (input active LOW) analog supply voltage (+5 V) analog ground decoupling input reference voltage BOTTOM input reference voltage MIDDLE input analog input voltage reference voltage TOP input output enable input (input active LOW) digital supply voltage 2 (+5 V) digital ground 2 supply voltage for output stages (2.7 to 3.6 V) output ground gray code input (input active HIGH) data output; bit 0 (LSB) data output; bit 1 data output; bit 2 data output; bit 3 data output; bit 4 data output; bit 5 data output; bit 6 data output; bit 7 data output; bit 8 data output; bit 9 (MSB) in-range data output digital ground 1 digital supply voltage 1 (+5 V) DESCRIPTION
TDA8764
1, 9, 11 and 32 not connected
1999 Jan 12
5
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
TDA8764
handbook, halfpage
CLK 1 TC 2 VCCA 3 AGND 4 DEC 5 VRB 6 VRM 7 VI 8 VRT 9 OE 10 VCCD2 11 DGND2 12 VCCO 13 OGND 14
FCE100
28 VCCD1 27 DGND1 26 IR 25 D9 24 D8 23 D7 22 D6
TDA8764TS
21 D5 20 D4 19 D3 18 D2 17 D1 16 D0 15 GRAY
Fig.2 Pin configuration (SSOP28).
32 n.c.
26 D4
31 D9
27 D5
30 D8
handbook, full pagewidth
25 D3
28 D6
29 D7
n.c. IR DGND1 VCCD1 CLK TC VCCA AGND
1 2 3 4
24 D2 23 D1 22 D0 21 GRAY
TDA8764HL
5 6 7 8 20 OGND 19 VCCO 18 DGND2 17 VCCD2
DEC 10
n.c. 11
VRB 12
VRM 13
VI 14
VRT 15
OE 16
9
FCE125
Fig.3 Pin configuration (LQFP32).
1999 Jan 12
n.c.
6
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage output stages supply voltage supply voltage difference VCCA - VCCD VCCA - VCCO VCCD - VCCO VI Vi(sw)(p-p) IO Tstg Tamb Tj Note input voltage output current storage temperature operating ambient temperature junction temperature referenced to AGND AC input voltage for switching (peak-to-peak value) referenced to DGND -1.0 -1.0 -1.0 -0.3 - - -55 -40 - CONDITIONS note 1 note 1 note 1 MIN. -0.3 -0.3 -0.3
TDA8764
MAX. +7.0 +7.0 +7.0 +1.0 +4.0 +4.0 +7.0 VCCD 10 +150 +85 150 V V V V V V V V
UNIT
mA C C C
1. The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 V and +7.0 V provided that the supply voltage differences VCC are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) SSOP28 LQFP32 PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 110 90 K/W K/W VALUE UNIT
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
TDA8764
CHARACTERISTICS The characteristics given refer to the SSOP28 package. VCCA = V3 to V4 = 4.75 to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 to 5.25 V; VCCO = V13 to V14 = 2.7 to 3.6 V; AGND and DGND shorted together; Tamb = 0 to 70 C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 10 pF and Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VCCA VCCD1 VCCD2 VCCO VCC analog supply voltage digital supply voltage 1 digital supply voltage 2 output stages supply voltage supply voltage difference VCCA - VCCD VCCA - VCCO VCCD - VCCO ICCA analog supply current TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 ICCD digital supply current TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 ICCO output stages supply current TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 Inputs CLOCK INPUT; CLK (REFERENCED TO DGND); note 1 VIL VIH IIL IIH Ci VIL VIH IIL IIH LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance VCLK = 0.8 V VCLK = 2 V 0 2 -1 - - 0 2 VIL = 0.8 V VIH = 2 V -1 - - - 0 2 2 - - - - 0.8 VCCD +1 10 - 0.8 VCCD - 1 V V A A pF fclk = 40 MHz; ramp input fclk = 80 MHz; ramp input - - 0 0 tbf tbf mA mA - - 25 30 tbf tbf mA mA - - 25 45 tbf tbf mA mA -0.20 -0.20 -0.20 - - - +0.20 +2.55 +2.55 V V V 4.75 4.75 4.75 2.7 5.0 5.0 5.0 3.3 5.25 5.25 5.25 3.6 V V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
INPUTS OE, TC AND GRAY (REFERENCED TO DGND); see Tables 3 and 4 LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current V V A A
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8764
MAX.
UNIT
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) IIL LOW-level input current TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 IIH HIGH-level input current TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 Yi input admittance TDA8764TS/4; TDA8764HL/4 input resistance input capacitance input admittance TDA8764TS/8; TDA8764HL/8 input resistance input capacitance fi = 5 MHz; note 2 - 3 45 5 - 7 k pF VI = VRT VI = VRT fi = 5 MHz; note 2 - 3 70 5 - 7 k pF - - 45 85 - - A A VI = VRB VI = VRB - - 0 0 - - A A
Reference voltages for the resistor ladder using the internal voltage regulator; see Table 1 VRB VRT Vdiff(ref) TCVdiff Voffset(B) Voffset(T) VI(p-p) Outputs DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND) VOL LOW-level output voltage TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 VOH HIGH-level output voltage TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 IOZ output current in 3-state mode IOH = -1 mA IOH = -2 mA 0.5 V < Vo < VCCO VCCO - 0.5 - VCCO - 0.5 - -20 - VCCO VCCO +20 V V A IOL = 1 mA IOL = 2 mA 0 0 - - 0.5 0.5 V V reference voltage BOTTOM reference voltage TOP differential reference voltage VRT - VRB temperature coefficient of differential reference voltage offset voltage BOTTOM offset voltage TOP analog input voltage (peak-to-peak value) note 3 note 3 note 4 tbf tbf tbf - - - tbf 1.3 3.7 2.4 tbf 161 161 2.08 tbf tbf tbf - - - tbf V V V mV/K mV mV V
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8764
MAX.
UNIT
Switching characteristics CLOCK INPUT; CLK; see Fig.5; note 1 fclk(max) maximum clock frequency TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 tCPH clock pulse width HIGH TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 tCPL clock pulse width LOW TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 Analog signal processing LINEARITY INL integral non-linearity TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 DNL differential non-linearity TDA8764TS/4; TDA8764HL/4 TDA8764TS/8; TDA8764HL/8 Eoffset EG offset error gain error (from device to device) using internal reference voltage fclk = 40 MHz; ramp input fclk = 80 MHz; ramp input middle code note 5 - - - - 0.25 0.25 1 tbf tbf tbf - - LSB LSB LSB % fclk = 40 MHz; ramp input fclk = 80 MHz; ramp input - - 0.8 0.8 tbf tbf LSB LSB 7 5 - - - - ns ns 7 5 - - - - ns ns 40 80 - - - - MHz MHz
BANDWIDTH (fclk = 40 MHZ)/4 VERSION; B analog bandwidth full-scale sine wave; note 6 75% full-scale sine wave; note 6 small signal at mid-scale; VI = 10 LSB at code 512; note 6 tstLH tstHL analog input settling time LOW-to-HIGH analog input settling time HIGH-to-LOW full-scale square wave; see Fig.7 and note 7 full-scale square wave; see Fig.7 and note 7 - - - 20 30 350 - - - MHz MHz MHz
- -
tbf tbf
tbf tbf
ns ns
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
SYMBOL PARAMETER CONDITIONS - - - MIN. TYP.
TDA8764
MAX. - - -
UNIT
BANDWIDTH (fclk = 80 MHZ) /8 VERSION; B analog bandwidth full-scale sine wave; note 6 75% full-scale sine wave; note 6 small signal at mid-scale; Vi = 10 LSB at code 512; note 6 tstLH tstHL analog input settling time LOW-to-HIGH analog input settling time HIGH-to-LOW full-scale square wave; see Fig.7 and note 7 full-scale square wave; see Fig.7 and note 7 40 60 700 MHz MHz MHz
- -
tbf tbf
tbf tbf
ns ns
HARMONICS (fclk = 40 MHZ) /4 VERSION; Hall(FS) harmonics (full-scale); all components second harmonics third harmonics SFDR THD spurious free dynamic range total harmonic distortion fi = 5 MHz fi = 5 MHz fi = 5 MHz - - fi = 5 MHz fi = 5 MHz without harmonics; fi = 5 MHz fclk = 40 MHz; /4 version fclk = 80 MHz; /8 version EFFECTIVE BITS; note 8 EB effective bits TDA8764TS/4; TDA8764HL/4 fclk = 40 MHz fi = 5 MHz fi = 7.5 MHz fi = 10 MHz fi = 20 MHz effective bits TDA8764TS/8; TDA8764HL/8 fclk = 80 MHz fi = 5 MHz fi = 10 MHz fi = 20 MHz fi = 40 MHz 1999 Jan 12 11 tbf tbf tbf tbf 9.5 tbf tbf tbf tbf tbf tbf tbf bits bits bits bits tbf tbf tbf tbf 9.5 9.2 9.0 tbf tbf tbf tbf tbf bits bits bits bits tbf tbf 58 58 - - dB dB - - -71 -87 tbf -70 tbf tbf - - dBc dBc dBc dB fi = 5 MHz - - - - -70 -90 tbf -70 tbf tbf - - dBc dBc dBc dB
HARMONICS (fclk = 80 MHZ)/8 VERSION; Hall(FS) harmonics (full-scale); all components second harmonics third harmonics SFDR THD spurious free dynamic range total harmonic distortion
SIGNAL-TO-NOISE RATIO; note 8 SNR(FS) signal-to-noise ratio (full-scale)
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
SYMBOL TWO-TONE; note 9 TTID two-tone intermodulation distortion fclk = 40 MHz fclk = 80 MHz BIT ERROR RATE BER bit error rate fi = 5 MHz; Vi = 16 LSB at code 512 fclk = 40 MHz fclk = 80 MHz Timing (fclk = 40 MHz; CL = 10 pF) /4 version; see Fig.5 and note 10 tds th td CL SR sampling delay time output hold time output delay time digital output load capacitance slew rate VCCO = 2.7 V; CL = 10 pF VCCO = 2.7 V VCCO = 3.3 V - 5 tbf tbf - - - 4 VCCO = 2.7 V VCCO = 3.3 V CL SR digital output load capacitance slew rate VCCO = 2.7 V; CL = 10 pF tbf tbf - - - - - - - - - - - - 12 11 - - - - 8 7 - - - - 10-13 10-13 - - tbf tbf PARAMETER CONDITIONS MIN. TYP.
TDA8764
MAX. - -
UNIT
dB dB
- -
times/ sample times/ sample
2 - tbf tbf 10 tbf
ns ns ns ns pF V/s
Timing (fclk = 80 MHz; CL = 10 pF) /8 version; see Fig.5 and note 10 tds th td sampling delay time output hold time output delay time 2 - tbf tbf 10 tbf ns ns ns ns pF V/s
3-state output delay times (fclk = 40 MHz) /4 version; see Fig.6 tdZH tdZL tdHZ tdLZ enable HIGH enable LOW disable HIGH disable LOW tbf tbf tbf tbf tbf tbf tbf tbf ns ns ns ns
3-state output delay times (fclk = 80 MHz) /8 version; see Fig.6 tdZH tdZL tdHZ tdLZ enable HIGH enable LOW disable HIGH disable LOW tbf tbf tbf tbf tbf tbf tbf tbf ns ns ns ns
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
Notes
TDA8764
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 1 2. The input admittance is V i = ---- + Cijw Ri 3. Analog input voltages producing code 0 up to and including code 1023: a) Voffset(B) (offset voltage BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 C. b) Voffset(T) (offset voltage TOP) is the difference between reference voltage TOP (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 C. 4. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.4. V RT - V RB a) The current flowing into the resistor ladder is I L = ----------------------------------------- and the full-scale input range at the converter, R OB + R L + R OT RL to cover code 0 to code 1023, is V I = R L x I L = ----------------------------------------- x ( V RT - V RB ) = 0.866 x ( V RT - V RB ) R OB + R L + R OT b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio RL ----------------------------------------- will be kept reasonably constant from device to device. Consequently variation of the output R OB + R L + R OT codes at a given input voltage depends mainly on the difference VRT - VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 5. ( V 1023 - V 0 ) - V i ( p - p ) E G = ----------------------------------------------------------- x 100 Vi ( p - p)
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, nor any significant attenuation are observed in the reconstructed signal. 7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. 8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = EB x 6.02 + 1.76 dB. 9. Intermodulation measured relative to either tone with analog input frequencies of 5 and 5.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. 10. Output data acquisition: the output data is available after the maximum delay time of td(max). For the 80 MHz version it is recommended to have the lowest possible output load.
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
TDA8764
handbook, halfpage
VRT ROT RL VRM RLAD IL code 0 ROB VRB
MGD281
code 1023
Fig.4 Explanation of note 4.
Table 1 STEP U/F 0 1 ... ... 1022 1023 O/F Table 2 STEP U/F 0 1 ... ... 1022 1023 O/F
Output coding and input voltage (typical values; referenced to AGND); binary and gray codes BINARY OUTPUT BITS Vi(p-p) tbf IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 ... ... 1 1 0 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 1 ... ... 0 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 0 0 0 0 0 0 ... ... 0 0 0 0 0 0 ... ... 0 0 0 0 0 0 ... ... 0 0 0 0 0 0 ... ... 0 0 0 0 0 0 ... ... 0 0 0 0 0 0 ... ... 0 0 0 0 0 0 ... ... 0 0 0 0 0 1 ... ... 1 0 0 GRAY OUTPUT BITS
Output coding and input voltage (typical values; referenced to AGND); binary and twos complement codes BINARY OUTPUT BITS Vi(p-p) tbf IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 ... ... 1 1 0 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 1 ... ... 0 1 1 1 1 1 ... ... 0 0 0 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 0 ... ... 1 1 1 0 0 1 ... ... 0 1 1 TWO'S COMPLEMENT OUTPUT BITS
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
Table 3 TC X 0 1 Table 4 Mode selection OE 1 0 0 Mode selection OE 1 0 0 active; binary active; gray D9 TO D0 high impedance high impedance active active IR D9 TO D0 high impedance active; two complement active; binary high impedance active active IR
TDA8764
GRAY X 0 1
handbook, full pagewidth
t CPL t CPH VCCO CLK 50% 0V sample N sample N + 1 sample N + 2
Vl
t ds DATA D0 to D9 DATA N-2 DATA N-1 td
th VCCO DATA N DATA N+1
MBG916
50% 0V
Fig.5 Timing diagram.
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
TDA8764
V handbook, full pagewidthCCD OE 50%
tdHZ HIGH output data 90% tdLZ HIGH output data LOW 10% 50% tdZL
tdZH
50% LOW
TEST VCCD 3.3 k S1 tdLZ tdZL tdHZ 15 pF OE fOE = 100 kHz. tdZH
S1 VCCD VCCD DGND DGND
FCE101
TDA8764
Fig.6 Timing diagram and test conditions of 3-state output delay time.
t STLH code 1023 VI code 0 2 ns 50%
t STHL
50%
2 ns
CLK
50%
50%
MBE566
0.5 ns
0.5 ns
Fig.7 Analog input settling time diagram.
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
INTERNAL PIN CONFIGURATIONS
TDA8764
handbook, halfpage
handbook, halfpage
VCCO
V CCA
D9 to D0 IR
VI
OGND
MBG915
AGND
MGC040 - 1
Fig.8 CMOS data and in range outputs.
Fig.9 Analog inputs.
DEC
handbook, halfpage
VCCA
handbook, halfpage
VCCO VRT OE TC GRAY VRM VRB RLAD REGULATOR
OGND
FCE102
AGND
MBE558 - 1
Fig.10 OE, GRAY and TC inputs.
Fig.11 VRB, VRM and VRT.
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
TDA8764
handbook, halfpage
VCCD
CLK
1.5 V
DGND
FCE103
Fig.12 CLK input.
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
APPLICATION INFORMATION
TDA8764
handbook, full pagewidth
CLK TC VCCA 100 nF
(2)
1 2 3 4 5 6 7
28 27 26 25 24 23 22
VCCD1 DGND1 IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GRAY
(2)
100 nF
AGND DEC
4.7 nF AGND 1 nF AGND 1 nF AGND 1 nF
VRB(1) VRM(1) VI VRT(1) OE
TDA8764TS
8 9 10 11 12 13 14 21 20 19 18 17 16 15
FCE104
AGND V CCD2 100 nF
(2)
DGND2 VCCO 100 nF
(2)
OGND
The analog and digital supplies should be separated and well decoupled. An application note is available which describes the design and the realization of a demonstration board that uses TDA8764HL in an application environment. (1) VRB, VRM and VRT are decoupled to AGND. (2) Decoupling capacitor for supplies; it must be placed close to the device.
Fig.13 Application diagram (SSOP28).
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
TDA8764
handbook, full pagewidth
n.c. n.c. IR DGND1 100 nF(2) VCCD1 CLK TC VCCA 100 nF(2) AGND 32 1 2 3 4
D9 31
D8 30
D7 29
D6 28
D5 27
D4 26
D3 25 24 23 22 21 D2 D1 D0 GRAY OGND VCCO DGND2 VCCD2 100 nF(2) 100 nF(2)
TDA8764HL
5 6 7 8 9 n.c. 4.7 nF AGND 10 DEC 11 n.c. 1 nF(1) 12 VRB 13 VRM 1 nF(1) 14 VI 15 VRT 1 nF(1) AGND 16 OE 20 19 18 17
AGND AGND
FCE126
The analog and digital supplies should be separated and well decoupled. An application note is available which describes the design and the realization of a demonstration board that uses TDA8764HL in an application environment. (1) VRB, VRM and VRT are decoupled to AGND. (2) Decoupling capacitor for supplies; it must be placed close to the device.
Fig.14 Application diagram (LQFP32).
1999 Jan 12
20
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
PACKAGE OUTLINES SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
TDA8764
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150AH EIAJ EUROPEAN PROJECTION A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
ISSUE DATE 93-09-08 95-02-04
1999 Jan 12
21
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm
TDA8764
SOT401-1
c y X
24 25
17 16 ZE
A
e E HE wM bp 32 1 8 9 L detail X Lp A A2 A1 pin 1 index (A 3)
e bp D HD
ZD wM B
vM A
vM B
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.15 0.05 A2 1.5 1.3 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 5.1 4.9 E (1) 5.1 4.9 e 0.5 HD 7.15 6.85 HE 7.15 6.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT401-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-19 97-08-04
1999 Jan 12
22
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TDA8764
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable
TDA8764
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 Jan 12
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Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
NOTES
TDA8764
1999 Jan 12
25
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
NOTES
TDA8764
1999 Jan 12
26
Philips Semiconductors
Preliminary specification
10-bit high-speed low-power ADC with internal reference regulator
NOTES
TDA8764
1999 Jan 12
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
295002/750/01/pp28
Date of release: 1999 Jan 12
Document order number:
9397 750 04632

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