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| DATA SHEET PD754202, 754202(A) 4-BIT SINGLE-CHIP MICROCONTROLLERS MOS INTEGRATED CIRCUIT The PD754202 is a member of the 75XL Series of 4-bit single-chip microcontrollers that enable data processing equivalent to that of an 8-bit microcontroller. It features expanded CPU functions compared to the 75X Series and enables high-speed, low-voltage operation at 1.8 V, making it suitable for battery-driven applications. The PD754202(A) is a higher-reliability product compared to the PD754202. Detailed function descriptions, etc., are provided in the following user's manual. Be sure to read it when designing. PD754202 User's Manual: U11132E FEATURES * * * Key return reset function for keyless entry Low-voltage operation: VDD = 1.8 to 6.0 V On-chip memory * Program memory (ROM): 2048 x 8 bits * Data memory (RAM) : 128 x 4 bits * Variable instruction execution time useful for high-speed operation and power save * 0.95, 1.91, 3.81, 15.3 s (at 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (at 6.0-MHz operation) * Compact package (20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)) APPLICATIONS Automotive electronics such as keyless entry units The PD754202 and PD754202(A) have different quality grades. Unless otherwise specified, descriptions in this data sheet apply to the PD754202. The information in this document is subject to change without notice. Document No. U12181EJ1V0DS00 (1st edition) Date Published May 1997 N Printed in Japan (c) 1997 PD754202, 754202(A) ORDERING INFORMATION Package 20-pin plastic SOP (300 mil, 1.27-mm pitch) 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) 20-pin plastic SOP (300 mil, 1.27-mm pitch) 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Quality Grade Standard Standard Special Special Part Number PD754202GS-xxx-BA5 PD754202GS-xxx-GJG PD754202GS(A)-xxx-BA5 PD754202GS(A)-xxx-GJG Remark xxx indicates the ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Differences between PD754202 and PD754202(A) Part Number Item Quality grade Standard Special PD754202 PD754202(A) 2 PD754202, 754202(A) FUNCTION LIST Parameter Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (system clock: at 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (system clock: at 6.0-MHz operation) 2048 x 8 bits 128 x 4 bits * 4-bit manipulation: 8 x 4 banks * 8-bit manipulation: 4 x 4 banks 4 9 13 4 channels * 8-bit timer counter: 3 channels (Usable as 16-bit timer counter) * Basic interval timer/watchdog timer: 1 channel 16 bits External: 1, Internal: 4 External: 1 (key return reset function provided) Ceramic/crystal oscillation circuit STOP/HALT mode TA = -40 to +85 C VDD = 1.8 to 6.0 V * 20-pin plastic SOP (300 mil, 1.27-mm pitch) * 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Mask option-specifiable on-chip pull-up resistor Software-specifiable on-chip pull-up resistor connection On-chip memory ROM RAM General-purpose register I/O port CMOS input CMOS input/output Total Timer Bit sequential buffer (BSB) Vectored interrupt Test input System clock oscillation circuit Standby function Operating ambient temperature Supply voltage Package 3 PD754202, 754202(A) CONTENTS 1. PIN CONFIGURATION (Top View) .................................................................................................... 6 2. BLOCK DIAGRAM ............................................................................................................................... 7 3. PIN 3.1 3.2 3.3 3.4 FUNCTION .................................................................................................................................... 8 Port Pins ...................................................................................................................................... 8 Non-port Pins .............................................................................................................................. 9 Pin Input/Output Circuits ......................................................................................................... 10 Recommended Connection of Unused Pins .......................................................................... 11 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ....................................... 12 4.1 Differences between Mk I Mode and Mk II Mode .................................................................... 12 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 13 5. MEMORY CONFIGURATION ............................................................................................................14 6. PERIPHERAL HARDWARE FUNCTION ......................................................................................... 17 6.1 Digital I/O Port ........................................................................................................................... 17 6.2 Clock Generator ........................................................................................................................17 6.3 Basic Interval Timer/Watchdog Timer ..................................................................................... 19 6.4 Timer Counter ........................................................................................................................... 20 6.5 Bit Sequential Buffer ................................................................................................................24 7. INTERRUPT FUNCTION AND TEST FUNCTION ........................................................................... 25 8. STANDBY FUNCTION .......................................................................................................................27 9. RESET FUNCTION ............................................................................................................................28 9.1 Configuration and Operation Status of Reset Function ........................................................ 28 9.2 Watchdog Flag (WDF), Key Return Flag (KRF) ...................................................................... 32 10. MASK OPTION ..................................................................................................................................34 11. INSTRUCTION SETS ......................................................................................................................... 35 12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 44 13. CHARACTERISTIC CURVES (REFERENCE VALUES) ................................................................ 53 14. PACKAGE DRAWINGS ......................................................................................................................55 15. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 57 4 PD754202, 754202(A) APPENDIX A. PD754202, 75F4264 FUNCTION LIST ..................................................................... 58 APPENDIX B. DEVELOPMENT TOOLS ..............................................................................................59 APPENDIX C. RELATED DOCUMENTS ..............................................................................................62 5 PD754202, 754202(A) 1. PIN CONFIGURATION (Top View) * 20-pin plastic SOP (300 mil, 1.27-mm pitch) PD754202GS-xxx-BA5 PD754202GS(A)-xxx-BA5 * 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) PD754202GS-xxx-GJG PD754202GS(A)-xxx-GJG RESET X1 X2 VSS IC VDD P60 P61/INT0 P62 P63 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 KRREN P80 P30/PTO0 P31/PTO1 P32/PTO2 P33 P70/KR4 P71/KR5 P72/KR6 P73/KR7 IC: Internally Connected (Connect directly to VDD) Pin Identification IC INT0 KR4 to KR7 KRREN P30 to P33 P60 to P63 P70 to P73 P80 PTO0 to PTO2 RESET VDD VSS X1, X2 : : : : : : : : : : : : : Internally Connected External Vectored Interrupt Key Return 4 to 7 Key Return Reset Enable Port 3 Port 6 Port 7 Port 8 Programmable Timer Output 0 to 2 Reset Positive Power Supply Ground System Clock (Ceramic/Crystal) 6 PD754202, 754202(A) 2. BLOCK DIAGRAM BASIC INTERVAL TIMER/WATCHDOG TIMER SP (8) INTBT RESET ALU PTO0/P30 8-BIT TIMER COUNTER#0 INTT0 TOUT PROGRAM COUNTER INTT1 8-BIT TIMER COUNTER#1 BANK PORT7 4 P70-P73 CY PORT6 4 P60-P63 PORT3 4 P30-P33 SBS PTO1/P31 GENERAL REG. CASCADED 16-BIT TIMER COUNTER PTO2/P32 8-BIT TIMER COUNTER#2 PROGRAM MEMORY (ROM) 2048x8 BITS DATA MEMORY (RAM) 128x4 BITS PORT8 1 P80 INTT2 INT0/P61 DECODE AND CONTROL BIT SEQ. BUFFER (16) KRREN INTERRUPT CONTROL 4 KR4/P70KR7/P73 fX/2N CPU CLOCK CLOCK SYSTEM CLOCK STAND BY CONTROL DIVIDER GENERATOR X1 X2 IC V DD VSS RESET 7 PD754202, 754202(A) 3. PIN FUNCTION 3.1 Port Pins Alternate Function PTO0 PTO1 PTO2 - Input/Output - INT0 - - Input KR4 KR5 KR6 KR7 Input/Output - 1-bit input/output port (PORT8). On-chip pull-up resistor can be specified by software. - Input F -A 8-bit I/O - I/O Circuit TypeNote E-B Pin Name P30 P31 P32 P33 P60 P61 P62 P63 P70 P71 P72 P73 P80 Input/Output Input/Output Function Programmable 4-bit input/output port (PORT3). This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by software in 4-bit units. Programmable 4-bit input/output port (PORT6). This port can be specified input/output bit-wise. On-chip pull-up resistor can be specified by software in 4-bit units. Noise eliminator can be selected on P61/ INT0. 4-bit input port (PORT7). On-chip pull-up resistor can be specified bit-wise (mask option). After Reset Input - Input F -A - Input B -A Note Circled characters indicate Schmitt trigger input. 8 PD754202, 754202(A) 3.2 Non-port Pins Alternate Function P30 P31 P32 Input P61 Edge detection vectored interrupt input (detected edge is selectable) Noise eliminator selectable Noise eliminator/ asynchronous selectable Input F -A I/O Circuit TypeNote E-B Pin Name PTO0 PTO1 PTO2 INT0 Input/Output Output Function Timer counter output After Reset Input KR4 to KR7 KRREN Input Input P70 to P73 - Falling edge detection testable input Key return reset enable. When KRREN = high level in STOP mode, reset signal is generated at falling edge of KRn. System clock oscillation crystal/ceramic connection pin. If using an external clock, input to X1 and reverse input to X2. Input Input B -A B X1 X2 Input - - - - RESET Input - System reset input (low-level active). Pull-up resistor can be incorporated on-chip (mask option). - B -A IC VDD VSS - - - - - - Internally connected. Connect directly to VDD. Positive power supply Ground potential - - - - - - Note Circled characters indicate Schmitt trigger input. 9 PD754202, 754202(A) 3.3 Pin Input/Output Circuits The PD754202 pin input/output circuits are shown schematically. TYPE A TYPE D VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT CMOS standard input buffer TYPE B Push-pull output that can be placed in output high-impedance (both P-ch and N-ch off). TYPE E-B VDD P.U.R. P.U.R. enable data Type D output disable P-ch IN IN/OUT Schmitt trigger input with hysteresis characteristics Type A P.U.R. : Pull-Up Resistor TYPE B-A TYPE F-A VDD P.U.R. VDD P.U.R. (Mask Option) data IN output disable Type D P.U.R. enable P-ch IN/OUT P.U.R. : Pull-Up Resistor Type B P.U.R. : Pull-Up Resistor 10 PD754202, 754202(A) 3.4 Recommended Connection of Unused Pins Table 3-1. List of Recommended Connection of Unused Pins Pin P30/PTO0 P31/PTO1 P32/PTO2 P33 P60 P61/INT0 P62 P63 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 Input state : Independently connect to VSS or VDD via a resistor. Output state: Leave open. KRREN When this pin is connected to VDD, internal reset signal is generated at the falling edge of the KRn pin in the STOP mode. When this pin is connected to VSS, internal reset signal is not generated even if the falling edge of KRn pin is detected in the STOP mode. Connect directly to VDD. Connect to VDD. Recommended Connecting Method Input state : Independently connect to VSS or VDD via a resistor. Output state: Leave open. IC 11 PD754202, 754202(A) 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Differences between Mk I Mode and Mk II Mode The PD754202 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the stack bank select register (SBS). * Mk I mode : * Mk II mode: Instructions are compatible with the 75X Series. Can be used in the 75XL CPU with a ROM capacity of up to 16 Kbytes. Incompatible with 75X Series. Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I mode Number of stack bytes for subroutine instructions BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction Not available Available 2 bytes 3 bytes Mk II mode 3 machine cycles 2 machine cycles 4 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes. The number of stack bytes (usable area) during execution of subroutine call instructions increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected. However, when the CALL !addr and CALL !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility, the Mk I mode should be used. 12 PD754202, 754202(A) 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using the Mk II mode, it must be initialized to 0000B. Figure 4-1. Stack Bank Select Register Format Address F84H 3 SBS3 2 1 0 SBS0 Symbol SBS SBS2 SBS1 Stack area specification 0 0 Memory bank 0 Other than above setting prohibited 0 0 must be set in the bit 2 position. Mode switching specification 0 1 Mk II mode Mk I mode Caution Because SBS.3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS.3 to "0" to select the Mk II mode. 13 PD754202, 754202(A) 5. MEMORY CONFIGURATION Program Memory (ROM): 2048 x 8 bits (0000H-07FFH) * Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. * Addresses 0002H to 000DH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt service can start from any address. * Addresses 0020H to 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the number of program steps. * * Data Memory (RAM) * Data area: 128 words x 4 bits (000H-07FH) * Peripheral hardware area: 128 words x 4 bits (F80H-FFFH) 14 PD754202, 754202(A) Figure 5-1. Program Memory Map Address 7 6 5 0 4 0 3 0 0 Internal reset start address (high-order 3 bits) Internal reset start address (low-order 8 bits) 0 0 0 INTBT start address INTBT start address 0 0 0 INT0 start address INT0 start address (high-order 3 bits) (low-order 8 bits) (high-order 3 bits) (low-order 8 bits) 0000H MBE RBE 0001H 0002H MBE RBE 0003H 0004H MBE RBE 0005H 0006H 0007H 0008H 0009H 000AH MBE RBE 000BH 000CH MBE RBE 000DH CALLF !faddr instruction entry address 0 0 0 INTT0 start address INTT0 start address (high-order 3 bits) (low-order 8 bits) Branch address of BR !addr BRCB !caddr BR BCDE BR BCXA BRA !addr1Note CALL !addr CALLA !addr1Note instructions 0 0 0 INTT1/INTT2 start address (high-order 3 bits) INTT1/INTT2 start address (low-order 8 bits) GETI branch/call address 0020H GETI instruction reference table 007FH 0080H BR $addr instruction relative branch address (-15 to -1, +2 to +16) 07FFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be made to an address with only the low-order 8 bits of the PC changed by means of a BR PCDE or BR PCXA instruction. 15 PD754202, 754202(A) Figure 5-2. Data Memory Map Data memory 000H General-purpose register area 01FH 020H Data area static RAM (128 x 4) Stack area 128 x 4 (96 x 4) 07FH 080H 0FFH Not incorporated (32 x 4) Memory bank 0 F80H Peripheral hardware area 128 x 4 15 FFFH 16 PD754202, 754202(A) 6. PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Port The following two types of I/O ports are provided. * CMOS Input (PORT7) Total : 4 9 13 Table 6-1. Types and Features of Digital Ports Port Name PORT3 Function 4-bit I/O Operation and Features Can be set to input or output mode bit-wise. Remarks Also used for PTO0 to PTO2 pins. Also used for INT0 pin. 4-bit input 4-bit input only port On-chip pull-up resistor can be specified by mask option bit-wise. Can be set to input or output mode bit-wise. Also used for KR4 to KR7 pins. * CMOS Input/Output (PORT3, 6, 8) : PORT6 PORT7 PORT8 1-bit I/O - 6.2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware. Its configuration is shown in Figure 6-1. The operation of the clock generator is set with the processor clock control register (PCC). The instruction execution time can be changed as follows. * 0.95, 1.91, 3.81, 15.3 s (system clock operating at 4.19 MHz) * 0.67, 1.33, 2.67, 10.7 s (system clock operating at 6.0 MHz) 17 PD754202, 754202(A) Figure 6-1. Clock Generator Block Diagram * Basic interval timer (BT) * Timer counter * INT0 noise eliminator X1 System clock oscillator 1/1 to 1/4096 fX 1/2 1/41/16 Divider X2 Oscillation stops Selector Divider 1/4 * CPU * INT0 noise eliminator Internal bus PCC PCC0 PCC1 4 PCC2 HALTNote PCC3 STOPNote PCC2, PCC3 clear STOP F/F Q S R R Q HALT F/F S Wait release signal from BT Reset signal Standby release signal from interrupt control circuit Note Instruction execution fX: System clock frequency = CPU clock PCC: Processor Clock Control Register One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. Remarks 1. 2. 3. 4. 18 PD754202, 754202(A) 6.3 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program and reset the CPU (c) Selects and counts the wait time when the standby mode is released (d) Reads the contents of counting Figure 6-2. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator fX/25 fX/27 MPX fX/29 fX/212 3 BT Clear Clear Basic interval timer (8-bit frequency divider) Set BT interrupt request flag Vectored interrupt IRQBT request signal Wait release signal when standby is released. Internal reset signal WDTM SET1Note 1 BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 8 Internal bus Note Instruction execution 19 PD754202, 754202(A) 6.4 Timer Counter The PD754202 incorporates three timer counters. Its configuration is shown in Figures 6-3, 6-4, and 6-5. The timer counter functions are shown below. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) Count value read function The timer counter can operate in the following four modes as set by the mode register. Table 6-2. Mode List Mode Channel Channel 0 Channel 1 Channel 2 TM11 0 x x x x 0 1 0 TM10 0 0 0 0 TM21 0 0 1 1 TM20 0 1 0 1 8-bit timer counter mode PWM pulse generator mode 16-bit timer counter mode Carrier generator mode Remark : Available x: Not available 20 Figure 6-3. Timer Counter (Channel 0) Block Diagram Internal bus 8 SET1Note TM0 - TM06 TM05 TM04 TM03 TM02 0 0 8 8 TMOD0 Modulo register (8) 8 Match Comparator (8) TOUT F/F Reset T0 MPX CP Count register (8) Clear INTT0 IRQT0 set signal TOE0 T0 enable flag PORT3.0 P30 output latch PMGA bit 0 Port 3 input/output mode P30/PTO0 Output buffer 8 fx/24 From clock generator fx/2 6 fx/28 fx/210 Timer operation start RESET IRQT0 clear signal Note Instruction execution PD754202, 754202(A) Caution Always set bits 0 and 1 to 0 when setting data to TM0. 21 22 8 - Figure 6-4. Timer Counter (Channel 1) Block Diagram Internal bus SET1Note TM1 TM16 TM15TM14TM13TM12TM11TM10 TOE1 8 TMOD1 T1 enable flag PORT3.1 P31 output latch PMGA bit 1 Port 3 input/output mode Decoder Modulo register (8) 8 Comparator (8) Match TOUT F/F Reset T1 P31/PTO1 Output buffer Timer counter (channel 2) output fx/25 fx/26 From clock fx/28 generator fx/210 fx/212 8 Count register (8) Clear MPX CP RESET Timer operation start 16-bit timer counter mode IRQT1 clear signal Selector Timer counter (channel 2) match signal (When 16-bit timer counter mode) Timer counter (channel 2) reload signal INTT1 IRQT1 set signal PD754202, 754202(A) Timer counter (channel 2) comparator (When 16-bit timer counter mode) Note Instruction execution Figure 6-5. Timer Counter (Channel 2) Block Diagram Internal bus 8 - SET1 Note TM2 8 TMODH 8 8 MPX (8) 8 TMOD2 0 - - 8 - TC2 TOE2 REMCNRZB NRZ Reload TM26 TM25 TM24 TM23 TM22 TM21 TM20 High-level period setting modulo register (8) Modulo register (8) PORT3.2 PMGA bit 2 P32 Port 3 input/output output mode latch Selector Decoder 8 Comparator (8) fx fx/2 From clock fx/24 generator fx/26 fx/28 fx/210 8 T2 MPX CP Count register (8) Clear P32/PTO2 Output buffer Selector Match TOUT F/F Reset Overflow Carrier generator mode Timer counter (channel 1) clock input 16-bit timer counter mode Timer operation start INTT2 IRQT2 set signal IRQT2 clear signal RESET Timer counter (channel 1) clear signal (When 16-bit timer counter mode) Timer counter (channel 1) match signal Timer counter (channel 1) match signal (When carrier generator mode) (When 16-bit timer counter mode) PD754202, 754202(A) Note Instruction execution Caution Always set bit 7 to 0 when setting data to TC2. 23 PD754202, 754202(A) 6.5 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise. Figure 6-6. Bit Sequential Buffer Format Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0 BSB3 BSB2 BSB1 BSB0 L register L = FH L = CH L = BH L = 8H L = 7H DECS L L = 4H L = 3H L = 0H INCS L Remarks 1. 2. In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification. 24 PD754202, 754202(A) 7. INTERRUPT FUNCTION AND TEST FUNCTION The PD754202 is provided with five types of interrupt sources and one test source to enable a variety of applications. The interrupt control circuit of the PD754202 has the following functions. (1) Interrupt function * Vectored interrupt function for hardware control, enabling/disabling the interrupt acknowledgement by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). * Can set any interrupt start address. * Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). * Test function of interrupt request flag (IRQxxx). An interrupt generated can be checked by software. * Release the standby mode. The interrupt to be released can be selected by the interrupt enable flag. (2) Test function * Test request flag (IRQ2) generation can be checked by software. * Release the standby mode. The test source to be released can be selected by the test enable flag. 25 Selector 26 2 IM2 4 IM0 INTBT INT0/P61 Note1 Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus Interrupt enable flag (IExxx) IME IPS IST1 IST0 Decoder VRQn IRQBT IRQ0 IRQT0 IRQT1 IRQT2 IRQ2 Priority control circuit Vector table address generator Edge detector INTT0 INTT1 INTT2 KR4/P70 KR7/P73 Falling edge detectorNote 2 Key return reset circuit PD754202, 754202(A) IM2 Standby release signal Notes 1. 2. Noise eliminator (Standby release is disabled when noise eliminator is selected.) The INT2 pin is not available. Interrupt request flag (IRQ2) is set at the KRn pin falling edge when IM20 = 1 and IM21 = 0. PD754202, 754202(A) 8. STANDBY FUNCTION In order to reduce power dissipation while a program is in standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD754202. Table 8-1. Operation Status in Standby Mode Item Set instruction Operation status Clock generator Mode STOP mode STOP instruction Operation stops. HALT mode HALT instruction Only the CPU clock halts (oscillation continues). Operable BT mode : The IRQBT is set in the reference time interval. WT mode: Reset signal generation by BT overflow. Operable. Basic interval timer/ watchdog timer Operation stops. Timer counter External interrupt Operation stops. The INT0 is not operableNote. The INT2 is operable at the falling edge of KRn. CPU Release signal Operation stops. * Reset signal * Interrupt request signal sent from interrupt enabled hardware * System reset signal (key return reset) generated by KRn falling edge when KRREN pin = 1. * Reset signal * Interrupt request signal sent from interrupt enabled hardware Note Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 27 PD754202, 754202(A) 9. RESET FUNCTION 9.1 Configuration and Operation Status of Reset Function There are three kinds of reset input: the external reset signal (RESET), the reset signal sent from the basic interval/watchdog timer, and the reset signal generated by a falling edge signal from KRn in the STOP mode. When any of these reset signals is input, an internal reset signal is generated. The configuration is shown in Figure 9-1. Figure 9-1. Configuration of Reset Function VDD Mask option RESET Internal reset signal Watchdog timer overflow S R Instruction KRREN S R QR S VDD Instruction STOP mode One-shot pulse generator Q WDF Q KRF Interrupt Falling edge detector Mask option P70/KR4 P71/KR5 P72/KR6 P73/KR7 Internal bus 28 PD754202, 754202(A) The RESET signal generation initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation WaitNote RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Operation mode Note The following 2 time modes can be specified with mask option. 2 17/fx (21.8 ms: at 6.0-MHz operation, 31.3 ms: at 4.19-MHz operation) 2 15/fx (5.46 ms: at 6.0-MHz operation, 7.81 ms: at 4.19-MHz operation) 29 PD754202, 754202(A) Table 9-1. Hardware Status After Reset (1/3) RESET signal generation in the standby mode Sets the low-order 3 bits of program memory's address 0000H to the PC10-PC8 and the contents of address 0001H to the PC7-PC0. Held 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH RESET signal generation in operation Sets the low-order 3 bits of program memory's address 0000H to the PC10-PC8 and the contents of address 0001H to the PC7-PC0. Undefined 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH Hardware Program counter (PC) PSW Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval timer/watchdog timer Timer counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer counter (T1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer counter (T2) Counter (T2) Modulo register (TMOD2) High-level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB 0 0, 0 0, 0, 0 0 0, 0 0, 0, 0 30 PD754202, 754202(A) Table 9-1. Hardware Status After Reset (2/3) RESET signal generation in the standby mode 0 Reset (0) 0 0 0 0, 0 Off Cleared (0) 0 0 Held RESET signal generation in operation 0 Reset (0) 0 0 0 0, 0 Off Cleared (0) 0 0 Undefined Hardware Clock generator Interrupt function Processor clock control register (PCC) Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt master enable flag (IME) Interrupt priority selection register (IPS) INT0, 2 mode registers (IM0, IM2) Digital port Output buffer Output latch I/O mode registers (PMGA, PMGC) Pull-up resistor setting register (POGA, POGB) Bit sequential buffer (BSB0-BSB3) Table 9-1. Hardware Status After Reset (3/3) RESET signal generation by key return reset Hold the previous status 1 RESET signal generation in the standby mode 0 0 RESET signal generation by WDT during operation 1 Hold the previous status RESET signal generation during operation 0 0 Hardware Watchdog flag (WDF) Key return flag (KRF) 31 PD754202, 754202(A) 9.2 Watchdog Flag (WDF), Key Return Flag (KRF) The WDF is set by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by the KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal is generated. As the WDF and KRF are cleared only by external signal or instruction execution, if once these flags are set, they are not cleared until an external signal is generated or a clear instruction is executed. Check and clear the contents of WDF and KRF after reset start operation by executing SKTCLR instruction and so on. Table 9-2 lists the contents of WDF and KRF corresponding to each signal. Figure 9-3 shows the WDF operation in generating each signal, and Figure 9-4 shows the KRF operation in generating each signal. Table 9-2. WDF and KRF Contents Correspond to Each Signal External RESET signal generation Reset signal Reset signal generation by watch- generation by the dog timer overflow KRn input 1 Hold Hold 1 WDF clear instruction execution 0 Hold KRF clear instruction execution Hold 0 Hardware Watchdog flag (WDF) Key return flag (KRF) 0 0 Figure 9-3. WDF Operation in Generating Each Signal WDF clear instruction execution Reset signal generation by watchdog timer overflow External RESET signal generation Reset signal generation by watchdog timer overflow WDF External RESET Operation mode Operation mode HALT mode Operation mode HALT mode Operation mode HALT mode Operation mode Internal reset operation Internal reset operation Internal reset operation 32 PD754202, 754202(A) Figure 9-4. KRF Operation in Generating Each Signal Reset signal generation by the KRn input STOP instruction execution External RESET signal generation Reset signal generation by the KRn input STOP instruction execution KRF clear instruction execution KRF External RESET Operation mode Operation mode STOP mode HALT mode Operation mode HALT mode Operation mode STOP mode HALT mode Operation mode Internal reset operation Internal reset operation Internal reset operation 33 PD754202, 754202(A) 10. MASK OPTION The PD754202 has the following mask options: * Mask option of P70/KR4 through P73/KR7 Pull-up resistors can be connected to these pins. (1) No pull-up resistor connection (2) Connection of a 30-k (typ.) pull-up resistor in 1-bit units. (3) Connection of a 100-k (typ.) pull-up resistor in 1-bit units. * Mask option of RESET pin Pull-up resistors can be connected to these pins. (1) No pull-up resistor connection (2) Connection of a 100-k (typ.) pull-up resistor. * Standby function mask option The wait time after RESET signal can be selected. (1) 217/fx (21.8 ms: fx = 6.0-MHz operation, 31.3 ms: fx = 4.19-MHz operation) (2) 2 15/fx (5.46 ms: fx = 6.0-MHz operation, 7.81 ms: fx = 4.19-MHz operation) 34 PD754202, 754202(A) 11. INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER PACKAGE USERS' MANUAL -- LANGUAGE (EEU-1363)". If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see PD754202 User's Manual (U11132E). Expression format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1(only in Mk II mode) caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, BC, XA, BC, DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL' Description method HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-07FFH immediate data or label 0000H-07FFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (where bit0 = 0) or label PORT3, 6, 7, 8 IEBT, IET0-IET2, IE0, IE2 RB0-RB3 MB0, MB15 Note mem can be only used for even address in 8-bit data processing. 35 PD754202, 754202(A) (2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA' extended register pair : BC' extended register pair : DE' extended register pair : HL' extended register pair : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 3, 6, 7, 8) : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Separation between address and bit : The contents addressed by xx : Hexadecimal data 36 PD754202, 754202(A) (3) Explanation of symbols under addressing area column *1 MB = MBE*MBS (MBS = 0, 15) MB = 0 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-07FFH addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *2 *3 Data memory addressing *4 *5 *6 *7 addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *8 *9 *10 *11 caddr = 0000H-07FFH faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-07FFH Program memory addressing Remarks 1. 2. 3. 4. MB indicates memory bank that can be accessed. In *2, MB = 0 independently of how MBE and MBS are set. In *4 and *5, MB = 15 independently of how MBE and MBS are set. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * When no skip is made: S = 0 * When the skipped instruction is a 1- or 2-byte instruction: S = 1 * When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of the CPU clock (= tCY); time can be selected from among four types by setting PCC. 37 PD754202, 754202(A) Number of machine cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC10-8+DE)ROM XA (PC10-8+XA)ROM XA (BCDE)ROMNote XA (BCXA)ROM Note Instruction group Transfer instruction Mnemonic Operand Number of bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 Operation Addressing area Skip condition MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA String effect A String effect A String effect B *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH XCH A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH Table reference instructions MOVT XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA *6 *6 Note "0" must be set to the B register. 38 PD754202, 754202(A) Number of machine cycles 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1, CY rp'1-XA-CY A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA CY A0, A3 CY, An-1 An AA *1 *1 *1 *1 *1 borrow borrow borrow *1 *1 Instruction group Bit transfer instructions Mnemonic Operand Number of bytes 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 Operation Addressing area *4 *5 *1 *4 *5 *1 Skip condition MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation instructions ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA carry carry carry carry carry ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA Accumulator manipulation instructions RORC NOT A A 39 PD754202, 754202(A) Number of machine cycles 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 Skip if (H+mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2+L3-2.bit(L1-0)) = 0 Skip if (H+mem3-0.bit) = 0 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 CY = 1 *1 *1 *1 *1 *3 Instruction group Increment and Decrement instructions Mnemonic Operand Number of bytes 1 1 2 2 1 2 2 1 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operation Addressing area Skip condition INCS reg rp1 @HL mem reg = 0 rp1 = 00H (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' DECS reg rp' Comparison instruction SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag manipulation instruction SET1 CLR1 SKT NOT1 CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit Memory bit manipulation instructions SET1 CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit 40 PD754202, 754202(A) Number of machine cycles 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 - Instruction group Memory bit manipulation instructions Mnemonic Operand Number of bytes 2 2 2 2 2 2 2 2 2 2 2 2 - Operation Addressing area *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 Skip condition SKTCLR fmem.bit pmem.@L @H+mem.bit Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 and clear Skip if (H+mem3-0.bit) = 1 and clear CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY v (fmem.bit) CY CY v (pmem7-2+L3-2.bit(L1-0)) CY CY v (H+mem3-0.bit) PC10-0 addr Select appropriate instruction among BR !addr, BRCB !caddr, and BR $addr according to the assembler being used. PC10-0 addr1 Select appropriate instruction among BR !addr, BRA !addr1, BRCB !caddr, and BR $addr1 according to the assembler being used. PC10-0 addr PC10-0 addr PC10-0 addr1 PC10-0 PC10-8+DE PC10-0 PC10-8+XA PC10-0 BCDENote 2 PC10-0 BCXANote 2 PC10-0 addr1 PC10-0 caddr10-0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit Branch instructions BR Note 1 addr addr1 - - *11 !addr $addr $addr1 PCDE PCXA BCDE BCXA BRANote 1 BRCB !addr1 !caddr 3 1 1 2 2 2 2 3 2 3 2 2 3 3 3 3 3 2 *6 *7 *6 *6 *11 *8 Notes 1. 2. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the MK I mode. "0" must be set to the B register. 41 PD754202, 754202(A) Number of machine cycles 3 Instruction group Subroutine stack control instructions Mnemonic Operand Number of bytes 3 Operation (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) 0, PC10-0 (SP-5) 0, 0, 0, 0 PC10-0 addr1, SP SP-6 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) 0, PC10-0 PC10-0 addr, SP SP-4 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) 0, PC10-0 (SP-5) 0, 0, 0, 0 PC10-0 addr, SP SP-6 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) 0, PC10-0 PC10-0 0+faddr, SP SP-4 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) 0, PC10-0 (SP-5) 0, 0, 0, 0 PC10-0 0+faddr, SP SP-6 PC10-0 (SP)2-0 (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 x, x, MBE, RBE (SP+4) 0, 0, 0, 0, (SP+1) PC10-0 (SP)2-0 (SP+3) (SP+2), SP SP+6 Addressing area *11 Skip condition CALLANote !addr1 CALLNote !addr 3 3 *6 4 CALLFNote !faddr 2 2 *9 3 RETNote 1 3 RETSNote 1 3+S MBE, RBE, 0, 0 (SP+1) PC10-0 (SP)2-0 (SP+3) (SP+2) SP SP+4 then skip unconditionally 0, 0, 0, 0 (SP+1) PC10-0 (SP)2-0 (SP+3) (SP+2) x, x, MBE, RBE (SP+4) SP SP+6 then skip unconditionally Unconditional RETINote 1 3 MBE, RBE, 0, 0 (SP+1) PC10-0 (SP)2-0 (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 0, 0, 0, 0 (SP+1) PC10-0 (SP)2-0 (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 PUSH rp BS 1 2 1 2 1 2 1 2 (SP-1) (SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1) (SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 POP rp BS Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 42 PD754202, 754202(A) Number of machine cycles 2 2 2 2 2 2 2 2 1 2 2 3 IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0 A PORTn PORTn A Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n MBS n * When TBR instruction PC10-0 (taddr) 2-0 + (taddr+1) ---------------------------------- Instruction group Interrupt control instructions Mnemonic Operand Number of bytes 2 Operation Addressing area Skip condition EI IExxx DI IExxx 2 2 2 2 2 2 2 1 Input/output instructions IN Note 1 A, PORTn PORTn, A (n = 3, 6, 7, 8) (n = 3, 6, 8) OUTNote 1 CPU control instructions HALT STOP NOP Special instructions SEL RBn MBn 2 2 1 (n = 0-3) (n = 0, 15) *10 ------------- GETINotes 2, 3 taddr * When TCALL instruction (SP-4) (SP-1) (SP-2) 0, PC10-0 (SP-3) MBE, RBE, 0, 0 PC10-0 (taddr) 2-0 + (taddr+1) SP SP-4 ---------------------------------- ------------- * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 * When TBR instruction PC10-0 (taddr) 2-0 + (taddr+1) * When TCALL instruction (SP-6) (SP-3) (SP-4) PC10-0 (SP-5) 0, 0, 0, 0 (SP-2) x, x, MBE, RBE PC10-0 (taddr) 2-0 + (taddr+1) SP SP-6 *10 Depending on the reference instruction ------------------------------------- ---- ------------- 4 ------------------------------------- ---- ------------- 3 * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction Notes 1. 2. 3. While the IN instruction and OUT instruction are being executed, MBS must be set to 0, or MBE must be set to 1 and MBS must be set to 15. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 43 PD754202, 754202(A) 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current, high Symbol VDD VI VO IOH Per pin Pins except P32 Only P32 All pins total Output current, low IOL Per pin All pins total Operating ambient temperature Storage temperature TA Test Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -10 -20 -30 20 90 -40 to +85 Unit V V V mA mA mA mA mA C C Tstg -65 to +150 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. Capacitance (TA = 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Test Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 44 PD754202, 754202(A) System Clock Oscillator Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Resonator Ceramic resonator Recommended Constant Parameter Oscillation Testing Conditions MIN. 1.0 (fX)Note 1 TYP. MAX. 6.0Note 2 Unit MHz X1 X2 frequency C1 C2 Oscillation stabilization timeNote 3 After VDD reaches MIN. value of oscillation voltage range 1.0 4 ms Crystal resonator Oscillation frequency(fX)Note 1 6.0Note 2 MHz X1 X2 Oscillation stabilization timeNote 3 30 ms VDD = 4.5 to 6.0 V 10 ms C1 C2 External clock X1 input 1.0 6.0Note 2 MHz X1 X2 frequency (fX)Note 1 X1 input high- and low-level widths (tXH, tXL) 83.3 500 ns Notes 1. 2. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, set the processor clock control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated machine cycle time of 0.95 s is not satisfied. 3. The oscillation stabilization time is the time required for oscillation to stabilize after application of VDD, or after the STOP mode has been released. Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: * Keep the wire length as short as possible. * Do not cross other signal lines. * Do not route the wiring in the vicinity of lines though which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillation circuit as the same potential as VSS. * Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 45 PD754202, 754202(A) RECOMMENDED CIRCUIT CONSTANTS Ceramic Resonator (TA = -20 to +80 C) Oscillation voltage range (VDD) MIN.(V) 2.0 MAX.(V) 6.0 Rd = 2.2 k - Capacitor incorporated - Capacitor incorporated 1.8 - Capacitor incorporated 2.0 - Capacitor incorporated 1.8 - Capacitor incorporated 2.9 - Capacitor incorporated 2.4 - Capacitor incorporated 1.8 2.0 1.8 Capacitor incorporated - 6.0 - Manufacturer Product Frequency (MHz) Circuit constant (pF) C1 100 100 - C2 100 100 - 30 - 30 - 30 - 30 - 30 - 30 - 100 68 - 33 Remark Murata Mfg. Co., Ltd. CSB1000JNote CSA2.00MG040 CST2.00MG040 CSA4.00MG CST4.00MGW CSA4.00MGU CST4.00MGWU CSA4.19MG CST4.19MGW CSA4.19MGU CST4.19MGWU CSA6.00MG CST6.00MGW CSA6.00MGU CST6.00MGWU 1.0 2.0 4.0 30 - 30 - 4.19 30 - 30 - 6.0 30 - 30 - Kyocera Corp. KBR-1000F/Y KBR-2.0MS KBR-4.19MKC KBR-4.19MSB PBRC4.19A PBRC4.19B KBR-6.0MKC KBR-6.0MSB PBRC6.00A PBRC6.00B 1.0 2.0 4.19 100 68 - 33 - 6.0 33 - Capacitor incorporated 33 - - - Capacitor incorporated Note If using Murata's CSB1000J (1.0 MHz) as the ceramic resonator, a limited resistor (Rd = 2.2 k) is required (see figure below). If using any other recommended resonator, no limited resistor is needed. X1 CSB1000J X2 Rd C1 C2 Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the resonator in the circuit. Please inquire directly to the maker of the resonator for data as needed. 46 PD754202, 754202(A) DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Parameter High-level output current Symbol IOH Per pin Conditions Pins except P32 Only P32, VDD = 3.0 V, VOH = VDD-2.0 V All pins total Low-level output current IOL Per pin All pins total High-level input voltage VIH1 Port 3 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V VIH2 Ports 6-8, KRREN, RESET VIH3 Low-level input voltage VIL1 X1 Port 3 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V VIL2 Ports 6-8, KRREN, RESET VIL3 High-level output voltage VOH X1 VDD = 4.5 to 6.0 V, IOH = -1.0 mA VDD = 1.8 to 6.0 V, IOH = -100 A Low-level output voltage VOL VDD = 4.5 to 6.0 V Port 3, IOL = 15 mA Ports 6, 8, IOL = 1.6 mA VDD = 1.8 to 6.0 V, IOL = 400 A High-level input leak current Low-level input leak current High-level output leak current Low-level output leak current On-chip pull-up resistance RL1 RL2 VIN = 0 V Ports 3, 6, 8 Port 7 (mask option) 50 15 50 RESET (mask option) 50 100 30 100 100 200 60 200 200 k k k k ILIH1 ILIH2 ILIL1 ILIL2 ILOH VOUT = VDD VIN = 0 V VIN = VDD Pins except X1 X1 Pins except X1 X1 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V 0.7 VDD 0.9 VDD 0.8 VDD 0.9 VDD VDD-0.1 0 0 0 0 0 VDD-1.0 VDD-0.5 0.6 2.0 0.4 -7 MIN. TYP. MAX. -5 -15 Unit mA mA -20 15 45 VDD VDD VDD VDD VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 mA mA mA V V V V V V V V V V V V V V 0.5 3.0 20 -3.0 -20 3.0 V A A A A A A ILOL VOUT = 0 V -3.0 47 PD754202, 754202(A) DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Parameter Supply current Note 1 Symbol IDD1 4.19 MHz Test Conditions VDD = 5.0 V 10 % Note 2 Note 3 MIN. TYP. 1.5 0.23 0.64 0.20 MAX. 5.0 1.0 3.0 0.9 5 Unit mA mA mA mA Crystal resonator VDD = 3.0 V 10 % IDD2 C1 = C2 = 22 pF HALT mode IDD3 X1 = 0 V STOP mode VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 1.8 to 6.0 V TA = 25 C 0.1 TA = -40 to +40 C 0.1 A A A A 1 3 1 Notes 1. Does not include current fed to on-chip pull-up resistor. 2. When processor clock control register (PCC) is set to 0011, during high-speed mode. 3. When PCC is set to 0000, during low-speed mode. 48 PD754202, 754202(A) AC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Parameter CPU clock cycle time Note 1 (Minimum instruction execution time = 1 machine cycle) Interrupt input high- and low-level widths KR4-KR7 RESET low-level width tRSL tINTH, tINTL INT0 Symbol tCY Test Conditions When system clock is used 1.8 V VDD < 2.7 V IM02 = 0 IM02 = 1 0.95 Note 2 10 10 10 64.0 2.7 V VDD 6.0 V MIN. 0.67 TYP. MAX. 64.0 Unit s s s s s s Notes 1. The CPU clock () cycle time (minimum instruction execution time) is determined by the oscillation frequency of the connected resonator (and external clock) and the processor clock control register (PCC). The figure on the right shows the cycle time tCY characteristics against the supply voltage VDD when the system clock is used. 64 60 6 5 4 Cycle time tCY [s] tCY vs VDD (During system clock operation) Operation guaranteed range 2. 2tCY or 128/fx depending on the setting of the interrupt mode register (IM0). 3 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] 49 PD754202, 754202(A) AC Timing Test Points (Excluding X1 Input) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Clock Timing 1/fX tXL tXH X1 input VDD - 0.1 V 0.1 V Interrupt Input Timing tINTL tINTH INT0, KR4-7 RESET Input Timing tRSL RESET 50 PD754202, 754202(A) Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = -40 to +85 C) Parameter Symbol Test Conditions MIN. 0 Release by RESET Release by interrupt request Note 2 Note 3 TYP. MAX. Unit Release signal set time tSREL Oscillation stabilization wait timeNote 1 tWAIT s ms ms Notes 1. 2. 3. BTM3 The oscillation stabilization wait time is the time during which the CPU operation is stopped to avoid unstable operation at oscillation start. 2 17/fx and 215/fx can be selected with mask option. Depends on setting of basic interval timer mode register (BTM) (see table below). BTM2 BTM1 BTM0 When fX = 4.19 MHz Wait Time When fX = 6.0 MHz 220/fX 217/fX 215/fX 213/fX (Approx. 175 ms) (Approx. 21.8 ms) (Approx. 5.46 ms) (Approx. 1.37 ms) - - - - 0 0 1 1 0 1 0 1 0 1 1 1 220/fX 217/fX 215/fX 213/fX (Approx. 250 ms) (Approx. 31.3 ms) (Approx. 7.81 ms) (Approx. 1.95 ms) Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD tSREL Execution of STOP instruction RESET tWAIT 51 PD754202, 754202(A) Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Data retention mode Operation mode VDD tSREL Execution of STOP instruction Standby release signal (interrupt request) tWAIT 52 PD754202, 754202(A) 13. CHARACTERISTIC CURVES (REFERENCE VALUES) IDD vs VDD (System clock: 6.0-MHz crystal resonator) (TA = 25 C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 System clock HALT mode 0.5 Supply Current IDD (mA) 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 6.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 Supply Voltage VDD (V) 5 6 7 8 53 PD754202, 754202(A) IDD vs VDD (System clock: 4.19-MHz crystal resonator) (TA = 25 C) 10 5.0 PCC = 0011 1.0 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 0.5 Supply Current IDD (mA) 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 4.19 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 6 7 8 Supply Voltage VDD (V) 54 PD754202, 754202(A) 14. PACKAGE DRAWINGS 20 PIN PLASTIC SOP (300 mil) 20 11 detail of lead end 1 A 10 H G P I J F K E C D NOTE N M M B L ITEM A B C D E F G H I J K L M N P MILLIMETERS 13.00 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 -0.05 0.10.1 1.8 MAX. 1.55 7.70.3 5.6 1.1 0.20 +0.10 -0.05 0.60.2 0.12 0.10 3 +7 -3 INCHES 0.512 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 -0.003 0.0040.004 0.071 MAX. 0.061 0.3030.012 0.220 0.043 0.008 +0.004 -0.002 0.024 +0.008 -0.009 0.005 0.004 3 +7 -3 Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. P20GM-50-300B, C-4 55 PD754202, 754202(A) 20 PIN PLASTIC SHRINK SOP (300 mil) 20 11 detail of lead end 1 A G 10 H I J F C D MM E N B K L 3 +7 -3 P20GM-65-300B-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 7.00 MAX. 0.575 MAX. 0.65 (T.P.) 0.30 0.10 0.125 0.075 2.0 MAX. 1.7 8.1 0.3 6.1 0.2 1.0 0.2 0.15 +0.10 -0.05 0.5 0.2 0.12 0.10 INCHES 0.276 MAX. 0.023 MAX. 0.026 (T.P.) 0.012+0.004 -0.005 0.005 0.003 0.079 MAX. 0.067 0.319 0.012 0.240 0.008 0.039 -0.008 0.006+0.004 -0.002 0.020 -0.009 0.005 0.004 +0.008 +0.009 56 PD754202, 754202(A) 15. RECOMMENDED SOLDERING CONDITIONS The PD754202 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions PD754202GS-xxx-BA5 PD754202GS-xxx-GJG : 20-pin plastic SOP (300 mil, 1.27-mm pitch) : 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) PD754202GS(A)-xxx-BA5 : 20-pin plastic SOP (300 mil, 1.27-mm pitch) PD754202GS(A)-xxx-GJG : 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 C, Reflow time: 30 seconds or below (at 210 C or higher), Number of reflow processes: Twice or less Package peak temperature: 215 C, Reflow time: 40 seconds or below (at 200 C or higher), Number of reflow processes: Twice or less Solder temperature: 260 C or below, Flow time: 10 seconds or below, Number of flow processes: 1 Preheating temperature: 120 C or below (package surface temperature) Partial heating Pin temperature: 300 C or below, Time: 3 seconds or below (per side of device) -- Symbol IR35-00-2 VPS VP15-00-2 Wave soldering WS60-00-1 Caution Do not use different soldering methods together (except for partial heating). 57 PD754202, 754202(A) APPENDIX A. PD754202, 75F4264 FUNCTION LIST Item PD754202 Mask ROM 0000H-07FFH (2048 x 8 bits) PD75F4264Note Flash memory 0000H-0FFFH (4096 x 8 bits) Program memory Data memory Static RAM EEPROM TM 000H-07FH (128 x 4 bits) None 75XL CPU (4 bits x 8 or 8 bits x 4 ) x 4 banks * 0.95, 1.91, 3.81, 15.3 s (system clock: at 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (system clock: at 6.0-MHz operation) 4 (on-chip pull-up resistor can be connected by mask option) 9 (on-chip pull-up resistor can be specified by software) 13 Ceramic/crystal oscillator 217/fX or 2 15/fX (selected by mask option) 215/fX 400H-43FH (32 x 8 bits) CPU General-purpose register Instruction execution time I/O port CMOS input CMOS input/output Total System clock oscillator Boot time after reset Timer 4 channels * 8-bit timer counter: 3 channels (can be used for 16-bit timer counter) * Basic interval timer/watchdog timer: 1 channel * 8-bit resolution x 2 channels (successive approximation register) * Operable VDD = 1.8 V or higher 2 channels External: 1, Internal: 5 A/D converter None Programmable threshold port Vectored interrupt Test input Supply voltage Operating ambient temperature Package None External: 1, Internal: 4 External: 1 (key return reset function provided) VDD = 1.8 to 6.0 V TA = -40 to +85 C * 20-pin plastic SOP (300 mil, 1.27-mm pitch) * 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) * 20-pin plastic SOP (300 mil, 1.27-mm pitch) Note Under development 58 PD754202, 754202(A) APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the PD754202. In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Part number (product name) Host machine OS PC-9800 Series MS-DOSTM Ver. 3.30 to Ver. 6.2 IBM PC/AT and compatible machines TM Supply media 3.5-inch 2HD 5-inch 2HD S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X Note Refer to "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Device file Host machine OS PC-9800 Series MS-DOS Ver. 3.30 to Ver. 6.2Note IBM PC/AT and compatible machines Refer to "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Supply media 3.5-inch 2HD 5-inch 2HD Part number (product name) S5A13DF754202 S5A10DF754202 S7B13DF754202 S7B10DF754202 Note Ver. 5.00 or later have the task swap function, but it cannot be used for this software. Remark Operations of the assembler and device file are guaranteed only on the above host machines and OSs. 59 PD754202, 754202(A) Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the PD754202. The system configurations are described as follows. Hardware IE-75000-RNote 1 In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X Series and 75XL Series. When developing a PD754202, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X Series and 75XL Series. When developing a IE-75001-R PD754202, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R which are sold separately must be used with the IE-75001-R. By connecting with the host machine, efficient debugging can be made. IE-75300-R-EM Emulation board for evaluating the application systems that use a PD754202. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for the PD754202. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 20-pin flexible boards EV-9500GS-20 (compatible with 20-pin plastic shrink SOP) and EV-9501GS-20 (compatible with 20-pin plastic SOP) which facilitate connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronics I/F and controls the IE-75000-R or IE-75001-R on a host machine. Host machine OS PC-9800 Series MS-DOS Ver. 3.30 to Ver. 6.2Note 2 IBM PC/AT and compatible machines Refer to "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Supply media 3.5-inch 2HD 5-inch 2HD Part number (product name) EP-754144GS-R EV-9500GS-20 EV-9501GS-20 Software IE control program S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X Notes 1. 2. Maintenance product Ver. 5.00 or later have the task swap function, but it cannot be used for this software. Remark Operation of the IE control program is guaranteed only on the above host machines and OSs. 60 PD754202, 754202(A) OS for IBM PC The following IBM PC OS's are supported. OS PC DOS TM Version Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote Ver. 5.0 to Ver. 6.22 5.0/VNote to J6.2/VNote J5.02/V Note MS-DOS IBM DOS TM Note Only English mode is supported. Caution Ver. 5.0 or later have the task swap function, but it cannot be used for this software. 61 PD754202, 754202(A) APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device related documents Document Number Document Name Japanese English This document U11132E U10453E PD754202, 754202(A) Data Sheet PD754202 User's Manual 75XL Series Selection Guide U12181J U11132J U10453J Development tool related documents Document Number Document Name Japanese Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-754144GS-R User's Manual Software RA75X Assembler Package User's Manual Operation Language EEU-846 U11354J U10695J EEU-731 EEU-730 English EEU-1416 U11354E U10695E EEU-1346 EEU-1363 Other related documents Document Number Document Name Japanese IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer Product Series Guide C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E - MEI-1202 - English Caution These documents are subject to change without notice. Be sure to read the latest documents for designing, etc. 62 PD754202, 754202(A) [MEMO] 63 PD754202, 754202(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. bare hands. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 64 PD754202, 754202(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 65 PD754202, 754202(A) EEPROM is a trademark of NEC Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2 |
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