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| DATA SHEET MOS INTEGRATED CIRCUIT PD754302,754304,754302(A),754304(A) 4-BIT SINGLE-CHIP MICROCONTROLLER The PD754304 is one of the "75XL Series" 4-bit single-chip microcontrollers with data processing capability comparable to that of 8-bit microcontrollers. The PD754303(A) has a higher reliability than the PD754304. The microcontrollers in the 75XL Series have expanded CPU functions than those of the 75X Series and can operate at a voltage of as low as 1.8 V; therefore, they are ideal for battery-driven application systems. As the one-time PROM version of the PD754304, the PD75P4308 is ideal for evaluation of a system under development or for small-scale production of application systems. Detailed information about functions can be found in the following document. Be sure to read the following document before designing. PD754304 User's Manual: U10123E FEATURES * Low-voltage operation: VDD = 1.8 to 5.5 V * Internal memory Program memory (ROM): 2048 x 8 bits (PD754302, 754302(A)) 4096 x 8 bits (PD754304, 754304(A)) Data memory (RAM): 256 x 4 bits * Variable instruction execution time effective for highspeed operation and power saving 0.95, 1.91, 3.81, or 15.3 s (at 4.19 MHz) 0.67, 1.33, 2.67, or 10.7 s (at 6.0 MHz) * Internal serial interface (1 channel) * Powerful timer function (3 channels) * Inherits instruction set of existing 75X Series for easy replacement APPLICATIONS * PD754302, 754302(A) Cordless telephones, TVs, VCRs, audio systems, household appliances, office machines, etc. * PD754304, 754304(A) Automotive appliance, etc. The PD754302 and 754304 differ from the PD754302(A) and 754304(A) only in terms of their quality grade. Unless otherwise specified, the PD754304 is treated as a representative model in this Data Sheet. For the models other than the PD754304, PD754304 can be read as the other model name. If different descriptions are made for the PD754302 and 754304, the (A) models correspond as follows: PD754302 PD754302(A), PD754304 PD754304(A) The information in this document is subject to change without notice. Document No. U10797EJ2V0DS00 (2nd edition) Date Published November 1996 N Printed in Japan The mark shows major revised points. (c) 1996 PD754302, 754304, 754302(A), 754304(A) ORDERING INFORMATION Parts Number Package 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) Quality Grade Standard Standard Special Special PD754302GS-xxx PD754304GS-xxx PD754302GS(A)-xxx PD754304GS(A)-xxx Remark x indicates a ROM code number. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Difference between PD75430x and PD75430x(A) Parts Number Item Quality grade PD754302 PD754304 Standard PD754302(A) PD754304(A) Special 2 PD754302, 754304, 754302(A), 754304(A) Functional Outline Parameter Instruction execution time On-chip memory ROM Function * 0.95, 1.91, 3.81, 15.3 s (@ 4.19 MHz with system clock) * 0.67, 1.33, 2.67, 10.7 s (@ 6.0 MHz with system clock) 2048 x 8 bits (PD754302) 4096 x 8 bits (PD754304) RAM General-purpose register 256 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 8 18 On-chip pull-up resistors can be specified by software: 7 On-chip pull-up resistors can be specified by software: 18 Input/ output port CMOS input CMOS input/output N-ch open-drain input/output pins Total Timer 4 13 V withstand voltage. On-chip pull-up resistors can be specified by mask option. 30 3 channels * 8-bit timer/event counter: 2 channels (16-bit timer/event counter) * Basic interval timer/watchdog timer: 1 channel Serial interface * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit * 2-wire serial I/O mode 16 bits * , 524, 262, 65.5 kHz (@ 4.19 MHz with system clock) * , 750, 375, 93.8 kHz (@ 6.0 MHz with system clock) External: 3, Internal: 4 External: 1 Ceramic or crystal oscillator STOP/HALT mode TA = -40 to +85 C Bit sequential buffer Clock output (PCL) Vectored interrupts Test input System clock oscillator Standby function Operating ambient temperature Power supply voltage Package VDD = 1.8 to 5.5 V 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) 3 PD754302, 754304, 754302(A), 754304(A) CONTENTS 1. PIN CONFIGURATION (Top View) ****************************************************************************************************** 6 2. BLOCK DIAGRAM ******************************************************************************************************************************* 8 3. PIN FUNCTION ************************************************************************************************************************************ 9 3.1 Port Pins ************************************************************************************************************************************* 9 3.2 Non-port Pins **************************************************************************************************************************** 10 3.3 Pin Input/Output Circuits ********************************************************************************************************* 11 3.4 Recommended Connections for Unused Pins *********************************************************************** 13 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ************************************************ 14 4.1 Difference between Mk I and Mk II Modes ****************************************************************************** 14 4.2 Setting Method of Stack Bank Select Register (SBS) *********************************************************** 15 5. MEMORY CONFIGURATION************************************************************************************************************* 16 6. PERIPHERAL HARDWARE FUNCTIONS ***************************************************************************************** 20 6.1 Digital Input Ports ******************************************************************************************************************** 20 6.2 Clock Generator *********************************************************************************************************************** 21 6.3 Clock Output Circuit **************************************************************************************************************** 22 6.4 Basic Interval Timer/Watchdog Timer ************************************************************************************ 23 6.5 Timer/Event Counter **************************************************************************************************************** 24 6.6 Serial Interface ************************************************************************************************************************** 27 6.7 Bit Sequential Buffer **************************************************************************************************************** 29 7. INTERRUPT FUNCTION AND TEST FUNCTION ****************************************************************************** 30 8. STANDBY FUNCTION *********************************************************************************************************************** 32 9. RESET FUNCTION **************************************************************************************************************************** 33 10. MASK OPTION *********************************************************************************************************************************** 36 11. INSTRUCTION SETS ************************************************************************************************************************* 37 12. ELECTRICAL SPECIFICATIONS ****************************************************************************************************** 49 13. CHARACTERISTICS CURVES (REFERENCE VALUES) ***************************************************************** 61 14. PACKAGE DRAWING *********************************************************************************************************************** 63 15. RECOMMENDED SOLDERING CONDITIONS ********************************************************************************* 64 4 PD754302, 754304, 754302(A), 754304(A) APPENDIX A. COMPARISON OF FUNCTIONS AMONG PD750004, 754304, AND 75P4308 ********** 65 APPENDIX B. DEVELOPMENT TOOLS ************************************************************************************************* 67 APPENDIX C. RELATED DOCUMENTS ************************************************************************************************ 70 5 PD754302, 754304, 754302(A), 754304(A) 1. PIN CONFIGURATION (Top View) 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) PD754302GS-xxx, PD754302GS(A)-xxx PD754304GS-xxx, PD754304GS(A)-xxx VSS X1 X2 RESET P33 P32 P31 P30 P81 P80 P23 P22/PCL P21/PTO1 P20/PTO0 P03/SI P02/SO/SB0 P01/SCK P00/INT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P13/TI0/TI1 P12/INT2 P11/INT1 P10/INT0 VDD IC IC: Internally Connected (Connect directly this pin to VDD.) 6 PD754302, 754304, 754302(A), 754304(A) PIN IDENTIFICATION P00-P03 : PORT0 P10-P13 : PORT1 P20-P23 : PORT2 P30-P33 : PORT3 P50-P53 : PORT5 P60-P63 : PORT6 P70-P73 : PORT7 P80, P81 : PORT8 KR0-KR7 : Key Return 0-7 SCK SI SO SB0 : Serial Clock : Serial Input : Serial Output : Serial data Bus 0 RESET TI0, TI1 PCL INT0, 1, 4 INT2 VSS X1, X2 IC VDD : Reset Input : Timer Input 0, 1 : Programmable Clock : External Vectored Interrupt 0, 1, 4 : External Test Input 2 : GND : System Clock Oscillation 1, 2 : Internally Connected : Positive Power Supply PTO0, PTO1 : Programmable Timer Output 0, 1 7 8 BASIC INTERVAL TIMER/ WATCHDOG TIMER 2. BLOCK DIAGRAM BIT SEQ. BUFFER (16) 4 PORT0 4 P00-P03 TOUT0 TI0/TI1/P13 PTO0/P20 PTO1/P21 INTBT INTT0 PROGRAM COUNTER Note1 ALU SP (8) CY SBS BANK 8-BIT TIMER/EVENT CASCADED COUNTER#0 16-BIT TIMER/ 8-BIT EVENT TIMER/EVENT COUNTER COUNTER#1 4 PORT1 4 P10-P13 4 PORT2 4 P20-P23 INTT1 SI/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI TOUT0 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0-KR3/P60-P63 KR4-KR7/P70-P73 ROM Note2 PROGRAM MEMORY GENERAL REG. DECODE AND CONTROL 4 PORT3 4 P30-P33 4 RAM DATA MEMORY 256 * 4 BITS PORT5 4 P50-P53 4 PORT6 4 P60-P63 PD754302, 754304, 754302(A), 754304(A) INTERRUPT CONTROL 8 fX/2N 4 CPU CLOCK F STAND BY CONTROL PORT7 4 P70-P73 2 PORT8 2 P80, P81 CLOCK CLOCK OUTPUT CLOCK GENERATOR CONTROL DIVIDER PCL/P22 X1 X2 IC VDD VSS RESET Notes 1. The PD754302 and PD754304 program counters are 11 and 12 bits, respectively. 2. The ROM capacity of the PD754302 is 2048 x 8 bits, and that of the PD754304 is 4096 x 8 bits. PD754302, 754304, 754302(A), 754304(A) 3. PIN FUNCTION 3.1 Port Pins Alternate Function INT4 SCK SO/SB0 SI INT0 INT1 INT2 TI0/TI1 Input/Output PTO0 PTO1 PCL - Input/Output - - - - Note 2 Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P50-P53 Input/Output Input Input/Output Input/Output Input Input Function 4-bit input port (PORT0). For P01 to P03, on-chip pull-up resistors can be specified by software in 3-bit units. 8-bit I/O x After Reset Input I/O Circuit TYPE Note 1 B F -A F -B B -C 4-bit input port (PORT1). On-chip pull-up resistors can be specified by software in 4-bit units. Noise elimination circuit can be selected (Only P10/INT0) 4-bit input/output port (PORT2). On-chip pull-up resistors can be specified by software in 4-bit units. x Input B -C x Input E-B Programmable 4-bit input/output port (PORT3). This port can be specified for input/output bit-wise. On-chip pull-up resistor can be specified by software in 4-bit units. N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bit-wise. On-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input/output port (PORT7). On-chip pull-up resistors can be specified by software in 4-bit units. x Input E-B Input/Output - x High level (when pull-up resistors are provided) or highimpedance M-D P60 P61 P62 P63 P70 P71 P72 P73 P80 Input/Output KR0 KR1 KR2 KR3 Input F -A Input/Output KR4 KR5 KR6 KR7 Input F -A Input/Output - P81 - 2-bit input/output port (PORT8). On-chip pull-up resistors can be specified by software in 2-bit units. x Input E-B Notes 1. Circled characters indicate the Schmitt-trigger input. 2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. 9 PD754302, 754304, 754302(A), 754304(A) 3.2 Non-port Pins Pin Name TI0/TI1 Input/Output Input Alternate Function P13 Function Inputs external event pulses to the timer/event counter. Timer/event counter output After Reset Input I/O Circuit TYPE Note B -C PTO0 PTO1 PCL SCK SO/SB0 Output P20 P21 P22 Input E-B Clock output Serial clock input/output Serial data output Serial data bus input/output Serial data input Edge detection vectored interrupt input (both rising edge and falling edge detection) Edge detection vectored interrupt input (detection edge can be selected). INT0/P10 can select a noise elimination circuit. Edge detection testable input (rising edge detection) Asynchronous with noise elimination circuit can be selected Asynchronous Asynchronous Input B -C Input Input F -A F -B Input/Output P01 P02 SI INT4 Input Input P03 P00 B -C B INT0 Input P10 Input B -C INT1 INT2 Input P11 P12 KR0-KR3 KR4-KR7 X1 Input P60-P63 P70-P73 Testable input (falling edge detection) Input F -A Input - X2 - Crystal/ceramic connection pin for the system clock oscillator. When inputting the external clock, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. - - RESET IC VDD VSS Input - - - - - - - System reset input (low-level active) Internally connected. Connect directly to VDD. Positive power supply Ground potential - - - - B - - - Note Circled characters indicate the Schmitt-trigger input. 10 PD754302, 754304, 754302(A), 754304(A) 3.3 Pin Input/Output Circuits The PD754304 pin input/output circuits are shown schematically. TYPE A TYPE D VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT CMOS specification input buffer. TYPE B Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). TYPE E-B VDD P.U.R. P.U.R. enable data Type D output disable P-ch IN IN/OUT Schmitt trigger input having hysteresis characteristic. Type A P.U.R. : Pull-Up Resistor TYPE B-C TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. enable data output disable IN Type B Type D P.U.R. P-ch P-ch IN/OUT P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor 11 PD754302, 754304, 754302(A), 754304(A) TYPE F-B VDD P.U.R. P.U.R. enable output disable (P) data output disable output disable (N) N-ch VDD P-ch IN/OUT TYPE M-D VDD P.U.R. (Mask Option) IN/OUT N-ch (+13 V) P-ch data output disable Input instruction VDD P-ch P.U.R. Note Voltage limiting circuit (+13 V) P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor Note If this pull-up resistor is not connected using the mask option it operates only when the input instruction is executed (if the pin is low, current flows from VDD to the pin). 12 PD754302, 754304, 754302(A), 754304(A) 3.4 Recommended Connections for Unused Pins Table 3-1. List of Recommended Connections for Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI P10/INT0-P12/INT2 P13/TI0/TI1 P20/PTO0 P21/PTO1 P22/PCL P23 P30-P33 P50-P53 Input state : Connect to VSS Input state : Connect to VSS or VDD through the resistor individually Output state : Leave open Connect to VSS Connect to VSS or VDD Recommended Connection Connect to VSS or VDD Connect to VSS or VDD through the resistor individually Output state : Connect to VSS (Pull-up resistor by mask option should not be connected) P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80, P81 IC Input state : Connect to VSS or VDD through the resistor individually Output state : Leave open Connect to VDD directly 13 PD754302, 754304, 754302(A), 754304(A) 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I and Mk II Modes The CPU of PD754304 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the stack bank select register (SBS). * Mk I mode: * Mk II mode: Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16K bytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I mode Number of stack bytes for subroutine instructions BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction 2 bytes 3 bytes Mk II mode Not available Available 3 machine cycles 2 machine cycles 4 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16K bytes in the 75X and 75XL series. This mode can improve software compatibility with products with a program area of more than 16K bytes. When Mk II mode is selected, the number of stack bytes when a subroutine call instruction is executed is greater by 1 byte per stack compared with the Mk I mode. When the CALL !addr or CALLF !faddr instruction is used, one more machine cycle is required. To emphasize the efficiency of the RAM and processing speed rather than software compatibility, therefore, use the Mk I mode. 14 PD754302, 754304, 754302(A), 754304(A) 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using the Mk II mode, it must be initialized to 0000B. Figure 4-1. Stack Bank Select Register Format Address F84H 3 SBS3 2 1 0 SBS0 Symbol SBS SBS2 SBS1 Stack area specification 0 0 Memory bank 0 Other than above setting prohibited 0 0 must be set in the bit 2 position. Mode switching specification 0 1 Mk II mode Mk I mode Caution Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode. 15 PD754302, 754304, 754302(A), 754304(A) 5. MEMORY CONFIGURATION * Program Memory (ROM) .... .... 2048 x 8 bits (PD754302) 4096 x 8 bits (PD754304) * Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an arbitrary address. * Addresses 0002H-000DH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt execution can be started at an arbitrary address. * Addresses 0020H-007FH Table area referenced by the GETI instruction Note. Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. * Data Memory (RAM) * Data area .... 256 words x 4 bits (000H-0FFH) * Peripheral hardware area .... 128 words x 4 bits (F80H-FFFH) 16 PD754302, 754304, 754302(A), 754304(A) Figure 5-1. Program Memory Map (1/2) (a) PD754302 Address 7 6 5 0 4 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 0 INT0 INT0 0 0 0 6 H MBE RBE 0 0 INT1 INT1 0 0 0 8 H MBE RBE 0 0 INTCSI INTCSI 0 0 0 A H MBE RBE 0 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 0 INTT1 INTT1 start address start address start address start address start address start address start address start address start address start address start address start address 0 (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) Branch destination address and subroutine entry address when GETI instruction is executed 0020H GETI instruction reference table 007FH 0080H BR $addr instruction relative branch address _15 to _1, +2 to +16 CALL !addr instruction subroutine entry address CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction 0 0 0 0 H MBE RBE 07FFH Note Can be used in the Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 17 PD754302, 754304, 754302(A), 754304(A) Figure 5-1. Program Memory Map (2/2) (b) PD754304 Address 7 6 5 0 4 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 0 INT0 INT0 0 0 0 6 H MBE RBE 0 0 INT1 INT1 0 0 0 8 H MBE RBE 0 0 INTCSI INTCSI 0 0 0 A H MBE RBE 0 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 0 INTT1 INTT1 start address start address start address start address start address start address start address start address start address start address start address start address 0 (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) BR $addr instruction relative branch address _15 to _1, +2 to +16 CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address 0 0 0 0 H MBE RBE 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH Note Can be used in the Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 18 PD754302, 754304, 754302(A), 754304(A) Figure 5-2. Data Memory Map Data memory 000H General-purpose register area 01FH Data area static RAM (256 x 4) Stack area 256 x 4 (224 x 4) 0 (32 x 4) Memory bank 0FFH Not incorporated F80H Peripheral hardware area 128 x 4 15 FFFH 19 PD754302, 754304, 754302(A), 754304(A) 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital Input Ports The following three types of I/O ports are provided. * CMOS input (Ports 0, 1) * CMOS I/O (Ports 2, 3, 6 to 8) * N-ch open-drain I/O (Port 5) Total : : 8 4 30 Table 6-1. Types and Features of Digital Ports Port Name PORT0 Function 4-bit input Operation, Features When serial interface function is used, multiplexed pin has output function depending on operation mode. Input port. Remark Multiplexed with INT4, SCK, SO/SB0, and SI pins Multiplexed with INT0 through INT2 and TI0/TI1 pins. Multiplexed with PTO0, PTO1, and PCL pins. PORT3 PORT5 4-bit I/O (N-ch opendrain, 13 V) 4-bit I/O Can be set in input or output mode in 1-bit units. Can be set in input or output mode in 4-bit units. Pull-up resistor can be connected in 1-bit units by mask option. -- : 18 PORT1 PORT2 4-bit I/O Can be set in input or output mode in 4-bit units. PORT6 Can be set in input or output mode in 1-bit units. Ports 6 and 7 are used in pairs and can input or output data in 8-bit units. Multiplexed with KR0 through KR3 pins. Multiplexed with KR4 through KR7 pins. -- PORT7 Can be set in input or output mode in 4-bit units. 2-bit I/O PORT8 Can be set in input or output mode in 2-bit units. 20 PD754302, 754304, 754302(A), 754304(A) 6.2 Clock Generator * Clock generator configuration The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is shown in Figure 6-1. The operation of the clock generator is set with the processor clock control register (PCC). The instruction execution time can be changed. * 0.95, 1.91, 3.81, 15.3 s (system clock operating at 4.19 MHz) * 0.67, 1.33, 2.67, 10.7 s (system clock operating at 6.0 MHz) Figure 6-1. Clock Generator Block Diagram * Basic interval timer (BT) * Timer/event counters 0, 1 * Serial interface * INT0 noise eliminator * Clock output circuit X1 System clock oscillator fX 1/1 to 1/4096 Divider 1/2 1/4 1/16 Oscillation stop Divider Selector 1/4 * CPU * INT0 noise eliminator * Clock output circuit X2 PCC Internal bus PCC0 PCC1 4 PCC2 HALTNote STOPNote PCC3 R Q HALT F/F S PCC2, PCC3 Clear STOP Q F/F S Wait signal from BT RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. 2. 3. 4. fX = System clock frequency = CPU clock PCC: Processor Clock Control Register One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. 21 PD754302, 754304, 754302(A), 754304(A) 6.3 Clock Output Circuit The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to apply for remote controller waveform output or to supply clock pulse peripheral LSIs. * Clock output (PCL) : , 524, 262, 65.5 kHz (during 4.19-MHz operation) , 750, 375, 93.8 kHz (during 6.0-MHz operation) Figure 6-2. Clock Output Circuit Block Diagram From clock generator fX/23 Selector fX/24 fX/26 PCL/P22 Output buffer PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 22 PD754302, 754304, 754302(A), 754304(A) 6.4 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. * Interval timer operation to generate a reference time interrupt * Watchdog timer operation to detect a runaway of program and reset the CPU * Selects and counts the wait time when the standby mode is released * Reads the contents of counting Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator fX/25 fX/27 MPX fX/29 fX/212 3 BT Clear Clear Basic interval timer (8-bit frequency divider) Set BT interrupt request flag Vectored interrupt IRQBT request signal Wait release signal when standby is released. Internal reset signal WDTM SET1 Note 1 BTM3 BTM2 BTM1 BTM0 BTM SET1 Note 4 8 Internal bus Note Instruction execution 23 PD754302, 754304, 754302(A), 754304(A) 6.5 Timer/Event Counter The PD754304 has two channels of timer/event counters. Its configuration is shown in Figures 6-4 and 6-5. The timer/event counter has the following functions. * Programmable interval timer operation * Square wave output of any frequency to the PTOn pin (n = 0, 1) * Event counter operation * Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency divider operation). * Supplies the shift clock to the serial interface circuit. * Reads the count value. The timer/event counter operates in the following two modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Mode 8-bit timer/event counter mode 16-bit timer/event counter mode Channel 1 24 Figure 6-4. Timer/Event Counter (Channel 0) Block Diagram Internal bus 8 TM0 8 TMOD0 Decoder Modulo register (8) 8 Match Comparator (8) 8 T0 Count register (8) CP Clear TOE0 PORT 2.0 Bit 2 of PMGB T0 P20 Port 2 enable flag output latch I/O mode P20/PTO0 TM06 TM05 TM04 TM03 TM02 TM01 TM00 PORT1.3 Input buffer TI0/TI1/P13 fX/22 4 From clock fX/26 fX/2 generator fX/28 fX/210 MPX TOUT F/F Reset Overflow Output buffer To serial interface Timer/event counter (channel 1) clock input PD754302, 754304, 754302(A), 754304(A) 16-bit timer/event counter mode INTT0 IRQT0 set signal IRQT0 clear signal Timer operation start RESET Timer/event counter (channel 1) TM12 signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) match signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) clear signal (When 16-bit timer/event counter mode) 25 26 8 PORT1.3 Input buffer TI0/TI1/P13 Timer/event counter (channel 0) output fX/22 fX/26 From clock fX/28 generator fX/210 fX/212 MPX Figure 6-5. Timer/Event Counter (Channel 1) Block Diagram Internal bus TM1 -- TM16 TM15 TM14 TM13 TM12 TM11 TM10 Decoder 8 TMOD1 Modulo register (8) 8 Match Comparator (8) 8 CP Count register (8) Clear T1 TOUT F/F Reset Output buffer P21/PTO1 TOE1 T1 enable flag PORT2.1 P21 output latch Bit 2 of PMGB Port 2 input/output mode PD754302, 754304, 754302(A), 754304(A) RESET Timer operation start 16 bit timer/event counter mode Timer/event counter (channel 0) TM02 signal (When 16 bit timer/event counter mode) Selector IRQT1 clear signal Timer/event counter (channel 0) match signal/operation start (When 16-bit timer/event counter mode) Timer/event counter (channel 0) comparator (When 16-bit timer/event counter mode) INTT1 IRQT1 set signal PD754302, 754304, 754302(A), 754304(A) 6.6 Serial Interface The PD754304 incorporates the clocked 8-bit serial interface, and the following three modes are provided. * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode 27 28 8/4 Bit test CSIM P03/SI Selector P02/SO/SB0 P01/SCK P01 output Iatch Figure 6-6. Serial Interface Block Diagram Internal bus 8 8 8 Slave address register (SVA) (8) Matching RELT signal (8) Bit manipulation SBIC CMDT Address comparator SET CLR Shift register (SIO) (8) D Q SO latch PD754302, 754304, 754302(A), 754304(A) Serial clock counter INTCSI control circuit INTCSI IRQCSI set signal Serial clock control circuit Serial clock selector fX/23 fX/24 fX/26 TOUT F/F (from timer/event counter 0) External SCK PD754302, 754304, 754302(A), 754304(A) 6.7 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. The data memory is composed of 16 bits and the pmem.@L addressing of a bit manipulation instruction is possible. The bit can be specified indirectly by the L register. In this case, processing can be done by moving the specified bit in sequence by incrementing and decrementing the L register in the program loop. Figure 6-7. Bit Sequential Buffer Format Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0 BSB3 BSB2 BSB1 BSB0 L register L = FH L = CH L = BH L = 8H L = 7H L = 4H L = 3H DECS L L = 0H INCS L Remarks 1. 2. In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification. 29 PD754302, 754304, 754302(A), 754304(A) 7. INTERRUPT FUNCTION AND TEST FUNCTION The PD754304 has seven kinds of interrupt sources and one kind of test source. Two types of edge detection testable inputs are provided for INT2 of the test source. The interrupt control circuit of the PD754304 has the following functions. (1) Interrupt function * Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). * Can set any interrupt start address. * Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). * Test function of interrupt request flag (IRQxxx). An interrupt generated can be checked by software. * Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function * Test request flag (IRQxxx) generation can be checked by software. * Release the standby mode. The test source to be released can be selected by the test enable flag. 30 Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 2 1 4 IME IPS IM2 IM1 IM0 Interrupt enable flag (IE xxx ) Decoder INTBT INT4/P00 INT0/P10 INT1/P11 Note Selector IST1 IST0 IRQBT VRQn Both edge detector Edge detector Edge detector INTCSI INTT0 INTT1 IRQ4 IRQ0 PD754302, 754304, 754302(A), 754304(A) IRQ1 IRQCSI IRQT0 IRQT1 IRQ2 Priority control circuit Vector table address generator INT2/P12 Rising edge detector Selector KR0/P60 KR7/P73 Falling edge detector Standby release signal IM2 Note Noise eliminator (Standby release is disabled when noise eliminator is selected.) 31 PD754302, 754304, 754302(A), 754304(A) 8. STANDBY FUNCTION In order to save dissipation power while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD754304. Table 8-1. Operation Status in Standby Mode Item Set instruction Operation status Clock generator Mode STOP mode STOP instruction The system clock stops oscillation. HALT mode HALT instruction Only the CPU clock halts (oscillation continues). Operable (The IRQBT is set in the reference interval). Operable Basic interval timer/ Watchdog timer Serial interface Operation stops. Operable only when an external SCK input is selected as the serial clock. Operable only when a signal input to the TI0 and TI1 pins are specified as the count clock. The INT1, 2, and 4 are operable. Only the INT0 is not operated Note. The operation stops. Timer/event counter Operable External interrupt CPU Release signal Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag or RESET signal input. Note Operable only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 32 PD754302, 754304, 754302(A), 754304(A) 9. RESET FUNCTION There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/ watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure 9-1 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal RESET signal RESET signal sent from the basic interval timer/watchdog timer WDTM Internal bus Generation of the RESET signal initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Operation mode Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms : @ 6.0 MHz, 31.3 ms: @ 4.19 MHz) 2 15/fX (5.46 ms : @ 6.0 MHz, 7.81 ms: @ 4.19 MHz) 33 PD754302, 754304, 754302(A), 754304(A) Table 9-1. Status of Each Hardware After Reset (1/2) RESET signal generation in the standby mode RESET signal generation in operation Sets the low-order 3 bits of program memory's address 0000H to the PC10-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 4 bits of program memory's address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Undefined 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 Undefined 0 0 Undefined 0 0 Hardware Program counter (PC) PD754302 Sets the low-order 3 bits of program memory's address 0000H to the PC10-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 4 bits of program memory's address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Held 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 Held 0 0 Held 0 0 PD754304 PSW Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval timer/watchdog timer Timer/event counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer/event counter (T1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Serial interface Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Clock generator, clock output circuit Processor clock control register (PCC) Clock output mode register (CLOM) 34 PD754302, 754304, 754302(A), 754304(A) Table 9-1. Status of Each Hardware After Reset (2/2) RESET signal generation in the standby mode Reset (0) 0 0 0, 0, 0 Off Cleared (0) 0 0 Held RESET signal generation in operation Reset (0) 0 0 0, 0, 0 Off Cleared (0) 0 0 Undefined Hardware Interrupt function Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt priority select register (IPS) INT0, 1, 2 mode registers (IM0, IM1, IM2) Digital port Output buffer Output latch I/O mode registers (PMGA, B, C) Pull-up resistor setting registers (POGA, B) Bit sequential buffers (BSB0-BSB3) 35 PD754302, 754304, 754302(A), 754304(A) 10. MASK OPTION The PD754304 has the following mask options: * Mask option of P50 through P53 Pull-up resistors can be connected to these pins. (1) Specify connection of a pull-up resistor in 1-bit units. (2) Do not specify connection of a pull-up resistor. * Standby function mask option The wait time when the RESET signal is input can be selected. (1) 2 17/fX (21.8 ms: fX = 6.0 MHz, 31.3 ms: fX = 4.19 MHz) (2) 2 15/fX (5.46 ms: fX = 6.0 MHz, 7.81 ms: fX = 4.19 MHz) 36 PD754302, 754304, 754302(A), 754304(A) 11. INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to RA75X ASSEMBLER PACKAGE USERS' MANUAL----LANGUAGE (EEU-1363). If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, refer to the PD754304 USER'S MANUAL (U10123E). Representation format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, BC, XA, BC, DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL' Description method HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label Note FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-07FFH immediate data 0000H-0FFFH immediate data 0000H-07FFH immediate data 0000H-0FFFH immediate data 12-bit immediate data or label 11-bit immediate data or label or or or or label label label label (PD754302) (PD754304) (PD754302) (PD754304) 20H-7FH immediate data (where bit 0 = 0) or label PORT0-PORT3, PORT5-PORT8 IEBT, IET0, IET1, IE0-IE2, IE4, IECSI RB0-RB3 MB0, MB15 Note mem can be only used for even address in 8-bit data processing. 37 PD754302, 754304, 754302(A), 754304(A) (2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA' expanded register pair : BC' expanded register pair : DE' expanded register pair : HL' expanded register pair : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 0-3, 5-8) : Interrupt master enable flag : Interrupt priority select register : Interrupt enable flag : Register bank select register : Memory bank select register : Processor clock control register : Separation between address and bit : The contents addressed by xx : Hexadecimal data 38 PD754302, 754304, 754302(A), 754304(A) (3) Explanation of symbols under addressing area column *1 MB = MBE*MBS (MBS = 0, 15) MB = 0 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH *2 *3 Data memory addressing *4 *5 *6 PD754302 PD754304 addr = 0000H-07FFH addr = 0000H-0FFFH *7 addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *8 PD754302 PD754304 caddr = 0000H-07FFH caddr = 0000H-0FFFH (PC12 = 0) Program memory addressing *9 *10 *11 faddr = 0000H-07FFH taddr = 0020H-007FH PD754302 PD754304 addr1 = 0000H-07FFH addr1 = 0000H-0FFFH Remarks 1. 2. 3. 4. MB indicates memory bank that can be accessed. In *2, MB = 0 independently of how MBE and MBS are set. In *4 and *5, MB = 15 independently of how MBE and MBS are set. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * When no skip is made: S = 0 * When the skipped instruction is a 1- or 2-byte instruction: S = 1 * When the skipped instruction is a 3-byte instruction Note : S=2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 39 PD754302, 754304, 754302(A), 754304(A) Number of machine cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg1 XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa) XA (HL) A (mem) XA (mem) A reg1 XA rp' q PD754302 Instruction group Transfer Mnemonic Operand Number of bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 Operation Addressing area Skip condition MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg1 XA, rp' reg1, A rp'1, XA String effect A String effect A String effect B *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH XCH A, @HL A, @HL+ A, @HL- A, @rpa XA, @HL A, mem XA, mem A, reg1 XA, rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH Table reference MOVT XA, @PCDE XA (PC10-8+DE)ROM q PD754304 XA (PC11-8+DE)ROM XA, @PCXA 1 3 q PD754302 XA (PC10-8+XA)ROM q PD754304 XA (PC11-8+XA)ROM XA, @BCDE XA, @BCXA 1 1 3 3 XA (BCDE)ROM XA (BCXA)ROM Note Note *6 *6 Note To use the PD754302, clear the most significant bit of the register C and register B to "0". To use the PD754304, clear the register B to "0". 40 PD754302, 754304, 754302(A), 754304(A) Number of machine cycles 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1, CY rp'1-XA-CY A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA CY A0, A3 CY, An-1 An AA reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 *1 *3 reg=0 rp1=00H (HL)=0 (mem)=0 reg=FH rp'=FFH *1 *1 *1 *1 *1 borrow borrow borrow *1 *1 Instruction group Bit transfer Mnemonic Operand Number of bytes 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 Operation Addressing area *4 *5 *1 *4 *5 *1 Skip condition MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA carry carry carry carry carry ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA Accumulator manipulation Increment and decrement RORC NOT INCS A A reg rp1 @HL mem DECS reg rp' 41 PD754302, 754304, 754302(A), 754304(A) Number of machine cycles 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit)=1 Skip if (fmem.bit)=1 Skip if (pmem7-2+L3-2.bit(L1-0))=1 Skip if (H+mem3-0.bit)=1 Skip if (mem.bit)=0 Skip if (fmem.bit)=0 Skip if (pmem7-2+L3-2.bit(L1-0))=0 Skip if (H+mem3-0.bit)=0 Skip if (fmem.bit)=1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY v (fmem.bit) CY CY v (pmem7-2+L3-2.bit(L1-0)) CY CY v (H+mem3-0.bit) *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 CY=1 *1 *1 *1 Instruction group Comparison Mnemonic Operand Number of bytes 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operation Addressing area Skip condition SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' reg=n4 (HL) = n4 A = (HL) XA = (HL) A=reg XA=rp' Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit Memory bit manipulation SET1 CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit 42 PD754302, 754304, 754302(A), 754304(A) Instruction group Branch Number of bytes - Number of machine cycles - Addressing area *6 Mnemonic BR Note Operand Operation Skip condition addr PC10-0 addr * PD754302 Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. PC11-0 addr * PD754304 Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. addr1 - - PC10-0 addr * PD754302 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. *11 PC11-0 addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. !addr 3 3 * PD754304 * PD754302 PC10-0 addr *6 * PD754304 PC11-0 addr $addr 1 2 * PD754302 PC10-0 addr *7 * PD754304 PC11-0 addr $addr1 1 2 * PD754302 * PD754304 PC10-0 addr1 PC11-0 addr1 PCDE 2 3 * PD754302 * PD754304 PC10-0 PC10-8+DE PC11-0 PC11-8+DE PCXA 2 3 * PD754302 * PD754304 PC10-0 PC10-8+XA PC11-0 PC11-8+XA Note The above operations in the double boxes can be performed only in the Mk II mode. 43 PD754302, 754304, 754302(A), 754304(A) Number of machine cycles 3 Instruction group Branch Mnemonic Operand Number of bytes 2 Operation Addressing area *6 Skip condition BR BCDE * PD754302 * PD754304 PC10-0 BCDE Note1 PC11-0 BCDE Note2 BCXA 2 3 * PD754302 * PD754304 *6 PC10-0 BCXA Note1 PC11-0 BCXA Note2 BRA Note3 !addr1 3 3 * PD754302 * PD754304 *11 PC10-0 addr1 PC11-0 addr1 BRCB !caddr 2 2 * PD754302 * PD754304 *8 PC10-0 caddr10-0 PC11-0 caddr11-0 Subroutine stack control CALLANote3 !addr1 3 3 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC10-0 (SP-5) 0, 0, 0, 0 PC10-0 addr1, SP SP-6 * PD754302 *11 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr1, SP SP-6 CALL Note3 !addr 3 3 * PD754304 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC10-0 PC10-0 addr, SP SP-4 * PD754302 *6 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 addr, SP SP-4 4 * PD754304 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC10-0 (SP-5) 0, 0, 0, 0 PC10-0 addr, SP SP-6 * PD754302 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr, SP SP-6 * PD754304 Notes 1. 2. 3. "0" must be set to the most significant bit of the register C and register B. "0" must be set to register B. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 44 PD754302, 754304, 754302(A), 754304(A) Number of machine cycles 2 Instruction group Subroutine stack control Mnemonic CALLF Note Operand Number of bytes 2 Operation Addressing area *9 Skip condition !faddr (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC10-0 PC10-0 faddr, SP SP-4 * PD754302 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 0+faddr, SP SP-4 3 * PD754304 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC10-0 (SP-5) 0, 0, 0, 0 PC10-0 faddr, SP SP-6 * PD754302 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 0+faddr, SP SP-6 RET Note * PD754304 1 3 PC10-0 (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 * PD754302 * PD754304 * PD754302 PC11-0 (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 x, x, MBE, RBE (SP+4) 0, 0, 0, 0, (SP+1) PC10-0 (SP) (SP+3) (SP+2), SP SP+6 x, x, MBE, RBE (SP+4) 0, 0, 0, 0 (SP+1) PC10-0 (SP) (SP+3) (SP+2), SP SP+6 RETS Note 1 3+S * PD754304 * PD754302 SP SP+4 Unconditional MBE, RBE, 0, 0 (SP+1) PC10-0 (SP) (SP+3) (SP+2) then skip unconditionally MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally * PD754304 Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 45 PD754302, 754304, 754302(A), 754304(A) Number of machine cycles 3+S Instruction group Subroutine stack control Mnemonic RETS Note1 Operand Number of bytes 1 Operation Addressing area Skip condition 0, 0, 0, 0 (SP+1) PC10-0 (SP) (SP+3) (SP+2) x, x, MBE, RBE (SP+4) SP SP+6 then skip unconditionally * PD754302 Unconditional 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) x, x, MBE, RBE (SP+4) SP SP+6 then skip unconditionally RETI Note1 1 3 * PD754304 MBE, RBE, 0, 0 (SP+1) PC10-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 * PD754302 MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 * PD754304 0, 0, 0, 0 (SP+1) PC10-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 * PD754302 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 PUSH rp BS POP rp BS Interrupt control DI IExxx Input/output IN Note2 A, PORTn XA, PORTn OUT Note2 PORTn, A PORTn, XA EI IExxx 1 2 1 2 2 2 2 2 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1) (SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA (n = 0-3, 5-8) (n = 6) (n = 2, 3, 5-8) (n = 6) * PD754304 Notes 1. 2. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. 46 PD754302, 754304, 754302(A), 754304(A) Number of machine cycles 2 2 1 2 2 3 Instruction group CPU control Mnemonic Operand Number of bytes 2 2 1 Operation Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n MBS n (n = 0-3) (n = 0, 15) Addressing area Skip condition HALT STOP NOP Special SEL RBn MBn 2 2 1 GETI Notes 1, 2 taddr * PD754302 * When TBR instruction PC10-0 (taddr) 2-0 + (taddr+1) ---------------------------------- *10 ------------ * When TCALL instruction (SP-4) (SP-1) (SP-2) PC10-0 (SP-3) MBE, RBE, 0, 0 PC10-0 (taddr) 2-0 + (taddr+1) SP SP-4 ---------------------------------- ------------ * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction * PD754304 * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1) ---------------------------------- ------------ * When TCALL instruction (SP-4) (SP-1) (SP-2) PC11-0 (SP-3) MBE, RBE, 0, 0 PC11-0 (taddr) 3-0 + (taddr+1) SP SP-4 ---------------------------------- ------------ * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 Depending on the reference instruction *10 * PD754302 * When TBR instruction PC10-0 (taddr) 2-0 + (taddr+1) * When TCALL instruction (SP-6) (SP-3) (SP-4) PC10-0 (SP-5) 0, 0, 0, 0 (SP-2) x, x, MBE, RBE PC10-0 (taddr) 2-0 + (taddr+1) SP SP-6 ---------------------------------------- ------------ 4 ---------------------------------------- ------------ 3 * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction Notes 1. 2. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 47 PD754302, 754304, 754302(A), 754304(A) Number of machine cycles 3 Instruction group Special Mnemonic GETI Notes 1, 2 taddr Operand Number of bytes 1 Operation Addressing area *10 Skip condition * PD754304 * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1) * When TCALL instruction (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 (SP-2) x, x, MBE, RBE PC11-0 (taddr) 3-0 + (taddr+1) SP SP-6 ---------------------------------------- ------------ 4 ---------------------------------------- ------------ 3 * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction Notes 1. 2. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. The above operations in the double boxes can be performed only in the Mk II mode. 48 PD754302, 754304, 754302(A), 754304(A) 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Except port 5 Port 5 Pull-up resistor incorporated N-ch open-drain Output voltage Output current, high VO IOH Per pin For all pins Output current, low IOL Note Test Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +14 -0.3 to VDD + 0.3 -10 -30 30 220 -40 to +85 Unit V V V V V mA mA mA mA C C Per pin For all pins Operating ambient temperature Storage temperature TA Tstg -65 to +150 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. Capacitance (TA = 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Test Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 49 PD754302, 754304, 754302(A), 754304(A) System Clock Oscillator Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Resonator Ceramic resonator Recommended Constant Parameter Oscillation Testing Conditions MIN. 1.0 Note1 TYP. MAX. Unit 6.0 Note2 MHz X1 X2 frequency (fX) C1 C2 Oscillation stabilization time Note 3 After VDD reaches MIN. value of oscillation voltage range 1.0 Note1 4 ms Crystal resonator X1 X2 Oscillation frequency(fX) Oscillation stabilization time C1 C2 Note3 6.0Note2 MHz VDD = 4.5 to 5.5 V 10 ms 30 ms External clock X1 X2 X1 input frequency (fX) Note1 1.0 6.0 Note2 MHz X1 input high- and low-level widths (tXH, tXL) 83.3 500 ns Notes 1. 2. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, set the processor control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated cycle time of 0.95 s is not satisfied. 3. Oscillation stabilization time is a time required for oscillation to stabilize after application of VDD, or after the STOP mode has been released. Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: * Keep the wire length as short as possible. * Do not cross other signal lines. * Do not route the wiring in the vicinity of lines though which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillation circuit as the same potential as VSS. * Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 50 PD754302, 754304, 754302(A), 754304(A) Recommended Oscillation Circuit Constants Ceramic Resonator (TA = -40 to +85 C) Manufacturer Product Frequency Recommended Circuit Constants (pF) Oscillation Voltage Range (VDD) (MHz) Murata Mfg. Co., Ltd CSB1000J Note Remarks C1 100 30 - C2 100 30 - 30 - 30 - 30 - 30 - 30 - 30 - 100 47 33 - 33 - 33 MIN. 2.7 1.8 MAX. 5.5 5.5 Capacitor incorporated Rd = 5.6 k 1.0 2.0 CSA2.00MG CST2.00MG CSA3.58MG CST3.58MGW CSA3.58MGU CST3.58MGWU CSA4.00MG CST4.00MGW CSA4.00MGU CST4.00MGWU CSA6.00MG CST6.00MGW CSA6.00MGU CST6.00MGWU 3.58 30 - 30 - 1.8 5.5 Capacitor incorporated Capacitor incorporated 2.0 5.5 Capacitor incorporated 1.8 Capacitor incorporated 2.9 5.5 Capacitor incorporated 1.8 Capacitor incorporated 1.8 2.0 1.8 5.5 5.5 5.5 Capacitor incorporated, TA = -20 to +80 C TA = -20 to +80 C Capacitor incorporated, TA = -20 to +80 C 1.8 5.5 TA = -20 to +80 C TA = -20 to +80 C 4.0 30 - 30 - 6.0 30 - 30 - Kyocera Corp. KBR-1000F/Y KBR-2.0MS KBR-4.0MSA KBR-4.0MKS PBRC 4.00A PBRC 4.00B KBR-6.0MSA PBRC 6.00A PBRC 6.00B TDK CCR1000K2 CCR2.0MC33 CCR4.19MC3 FCR4.19MC5 CCR6.0MC3 1.0 2.0 4.0 100 47 33 - 33 - 6.0 33 - 1.0 2.0 4.19 100 - - 100 - 1.8 5.5 Capacitor incorporated, TA = -20 to +80 C Capacitor incorporated 6.0 51 PD754302, 754304, 754302(A), 754304(A) Note If using Murata's CSB1000J (1.0 MHz) as the ceramic resonator, a limited resistor (Rd = 5.6 k) is required (see figure below). If using any other recommended resonator, no limited resistor is needed. X1 CSB1000J X2 Rd C1 C2 Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the resonator in the circuit. Please inquire directly to the maker of the resonator for data as needed. 52 PD754302, 754304, 754302(A), 754304(A) DC Characteristics (TA = -40 to + 85 C, VDD = 1.8 to 5.5 V) Parameter Output current, low Symbol IOL Per pin For all pins Input voltage, high VIH1 Ports 2, 3, 8 2.7 VVDD5.5 V 1.8 VVDD<2.7 V VIH2 Ports 0, 1, 6, 7, RESET 2.7 VVDD5.5 V 1.8 VVDD<2.7 V VIH3 Port 5 Pull-up resistor incorporated N-ch open drain 2.7 VVDD5.5 V 1.8 VVDD<2.7 V 2.7 VVDD5.5 V 1.8 VVDD<2.7 V VIH4 Input voltage, low VIL1 X1 Ports 2, 3, 5, 8 2.7 VVDD5.5 V 1.8 VVDD<2.7 V VIL2 Ports 0, 1, 6, 7, RESET 2.7 VVDD5.5 V 1.8 VVDD<2.7 V VIL3 Output voltage, high Output voltage, low VOH VOL1 X1 SCK, SO, ports 2, 3, 6, 7, 8 SCK, SO, ports 2, 3, 5, 6, 7, 8 IOH = -1 mA IOL = 15 mA VDD = 5 V10% IOL = 1.6 mA VOL2 Input leak current, high ILIH1 ILIH2 ILIH3 Input leak current, low ILIL1 ILIL2 ILIL3 VI = 13 V VI = 0 V SB0 VI = VDD N-ch open-drain pull-up resistor1 k Pins other than X1 X1 Port 5 (N-ch open drain) Pins other than X1 and port 5 X1 Port 5 (N-ch open drain) Other than input instruction execution time Port 5 (N-ch open drain) Input Input instruction execution time -10 -3 Output leak current, high ILOH1 VO = VDD SCK, SO/SB0, ports 2, 3, 6, 7, 8, port 5 (with on-chip pull-up resistor) Port 5 (N-ch open drain) -30 -27 -8 3 0.4 0.2 VDD 3 20 20 -3 -20 -3 V V 0.7 VDD 0.9 VDD 0.8 VDD 0.9 VDD 0.7 VDD 0.9 VDD 0.7 VDD 0.9 VDD VDD-0.1 0 0 0 0 0 VDD-0.5 0.2 2.0 Test Conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD VDD VDD 13 13 VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 Unit mA mA V V V V V V V V V V V V V V V V A A A A A A A A A A A A k k ILOH2 Output leak current, low ILOL On-chip pull-up resistor RL1 RL2 VO = 13 V VO = 0 V VI = 0 V 20 -3 Ports 0 to 3 and 6 to 8 (except P00 pin) Port 5 50 15 100 30 200 60 53 PD754302, 754304, 754302(A), 754304(A) DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter Supply current Note1 Symbol IDD1 6.00 MHz Test Conditions VDD = 5.0 V 10% Note2 Note3 MIN. TYP. 1.50 0.33 0.61 0.24 1.20 0.17 0.40 0.13 0.05 0.02 MAX. 5.00 1.00 1.85 0.75 3.50 0.55 1.50 0.50 10.0 5.00 3.00 Unit mA mA mA mA mA mA mA mA Crystal resonator VDD = 3.0 V 10% IDD2 C1 = C2 = 22 pF HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10% IDD1 4.19 MHz VDD = 5.0 V 10% Note2 Note3 Crystal resonator VDD = 3.0 V 10% IDD2 C1 = C2 = 22 pF HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10% IDD5 STOP mode VDD = 5.0 V 10% VDD = 3.0 V 10% TA = 25 C A A A 0.02 Notes 1. 2. 3. Does not include current fed to on-chip pull-up resistor. When processor clock control register (PCC) is set to 0011, during high-speed mode. When PCC is set to 0000, during low-speed mode. 54 PD754302, 754304, 754302(A), 754304(A) AC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter CPU clock cycle time Note1 Symbol tCY Test Conditions When system clock is used VDD = 2.7 to 5.5 V MIN. 0.67 0.95 TYP. MAX. 64 64 1 275 Unit s s MHz kHz (Minimum instruction execution time = 1 machine cycle) TI0, TI1 input frequency fTI VDD = 2.7 to 5.5 V 0 0 TI0, TI1 input high- and low-level width Interrupt input high- and low-level width tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 1.8 s s s s s s s tINTH, tINTL INT0 IM02 = 0 IM02 = 1 Note 2 10 10 10 10 INT1, 2, 4 KR0-7 RESET low-level width tRSL Notes 1. The CPU clock () cycle time (minimum instruction execution time) is determined by the ocillation frequency of the connected resonator and the processor clock control register (PCC). The figure on the right shows the cycle time tCY characteristics against the supply voltage VDD when the system clock is used. the interrupt mode register (IM0). Cycle time tCY [m s] tCY vs VDD (During system clock operation) 64 60 6 5 4 3 Operation guaranteed range 2. 2tCY or 128/fx depending on the setting of 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] 55 PD754302, 754304, 754302(A), 754304(A) Serial Transfer Operation 2-wire and 3-wire Serial I/O Mode (SCK...Internal clock output) (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY1 Test Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high- and low-level width SINote1 setup time tKL1, tKH1 tSIK1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKCY1/2-50 tKCY1/2-150 150 500 tKSI1 VDD = 2.7 to 5.5 V 400 600 tKSO1 R = 1 k, C = 100 pF Note2 TYP. MAX. Unit ns ns ns ns ns ns ns ns (to SCK) SINote1 hold time (from SCK) SCKSONote1 output delay time VDD = 2.7 to 5.5 V 0 0 250 1000 ns ns Notes 1. 2. SB0 in the 2-wire serial I/O mode. R and C are the load resistance and load capacitance of the SO output line. 2-wire and 3-wire Serial I/O Mode (SCK...External clock input) (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY2 Test Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high- and low-level width SI Note1 setup time (to SCK) SI Note1 hold time (from SCK) SCKSONote1 output delay time tKSO2 R = 1 k, C = 100 pF Note2 TYP. MAX. Unit ns ns ns ns ns ns ns ns tKL2, tKH2 tSIK2 VDD = 2.7 to 5.5 V 400 1600 VDD = 2.7 to 5.5 V 100 150 tKSI2 VDD = 2.7 to 5.5 V 400 600 VDD = 2.7 to 5.5 V 0 0 300 1000 ns ns Notes 1. 2. SB0 in the 2-wire serial I/O mode. R and C are the load resistance and load capacitance of the SO output line. 56 PD754302, 754304, 754302(A), 754304(A) AC Timing Test Points (Excluding X1 Input) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Note For the values, refer to the DC Characteristics. Clock Timing 1/fX tXL tXH X1 input VDD - 0.1 V 0.1 V TI0, TI1 Timing 1/fTI tTIL tTIH TI0, TI1 57 PD754302, 754304, 754302(A), 754304(A) Serial Transfer Timing 3-wire Serial I/O Mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SI Input data tKSO1, 2 SO Output data 2-wire Serial I/O Mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0 tKSO1, 2 58 PD754302, 754304, 754302(A), 754304(A) Interrupt Input Timing tINTL tINTH INT0,1,2,4 KR0-7 RESET Input Timing tRSL RESET Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = -40 to +85 C) Parameter Symbol Test Conditions MIN. 0 Release by RESET Release by interrupt request Note2 Note3 TYP. MAX. Unit Release signal set time tSREL Oscillation stabilization wait time Note1 s ms ms tWAIT Notes 1. 2. 3. BTM3 The oscillation stabilization wait time is the time during which the CPU operation is stopped to avoid unstable operation at oscillation start. 2 17/fx and 215/fx can be selected with mask option. Depends on setting of basic interval timer mode register (BTM) (see table below). BTM2 BTM1 BTM0 When fX = 4.19 MHz Wait Time When fX = 6.0 MHz 220/fX 217/fX 215/fX 213/fX (Approx. 175 ms) (Approx. 21.8 ms) (Approx. 5.46 ms) (Approx. 1.37 ms) - - - - 0 0 1 1 0 1 0 1 0 1 1 1 220/fX 217/fX 215/fX 213/fX (Approx. 250 ms) (Approx. 31.3 ms) (Approx. 7.81 ms) (Approx. 1.95 ms) 59 PD754302, 754304, 754302(A), 754304(A) Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD VDDDR Execution of STOP instruction tSREL RESET tWAIT Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Data retention mode Operation mode VDD VDDDR Execution of STOP instruction tSREL Standby release signal (interrupt request) tWAIT 60 PD754302, 754304, 754302(A), 754304(A) 13. CHARACTERISTICS CURVES (REFERENCE VALUES) IDD 10 VS VDD (System Clock: 6.0-MHz Crystal Resonator) (TA = 25 C) 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 System clock HALT Mode 0.5 Supply Current IDD (mA) 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 6.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 Supply Voltage VDD (V) 5 6 7 8 61 PD754302, 754304, 754302(A), 754304(A) IDD 10 VS VDD (System Clock: 4.19-MHz Crystal Resonator) (TA = 25 C) 5.0 PCC = 0011 1.0 PCC = 0010 PCC = 0001 0.5 PCC = 0000 System clock HALT mode Supply Current IDD (mA) 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 4.19 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 6 7 8 Supply Voltage VDD (V) 62 PD754302, 754304, 754302(A), 754304(A) 14. PACKAGE DRAWING 36 PIN PLASTIC SHRINK SOP (300 mil) 36 19 detail of lead end 1 A 18 55 H I G J F K E C D MM N B L P36GM-80-300B-3 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 15.54 MAX. 0.97 MAX. 0.8 (T.P.) +0.10 0.35 -0.05 INCHES 0.612 MAX. 0.039 MAX. 0.031 (T.P.) 0.014+0.004 -0.003 0.005 0.003 0.071 MAX. 0.061 0.303 0.012 0.220 0.043 0.008+0.004 -0.002 0.024 -0.009 0.004 0.004 +0.008 0.125 0.075 1.8 MAX. 1.55 7.7 0.3 5.6 1.1 0.20 +0.10 -0.05 0.6 0.2 0.10 0.10 63 PD754302, 754304, 754302(A), 754304(A) 15. RECOMMENDED SOLDERING CONDITIONS The PD754304 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions PD754302GS-xxx: 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) PD754304GS-xxx: 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) PD754302GS(A)-xxx: 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) PD754304GS(A)-xxx: 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) Soldering Method Infrared rays reflow Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (at 210 C or higher), Count: Twice or less Package peak temperature: 215 C, Time: 40 seconds max. (at 200 C or higher), Count: Twice or less Solder temperature: 260 C or below, Time: 10 seconds max., Count: Once, Preheating temperature: 120 C MAX. (package surface temperature) Partial heating Pin temperature: 300 C or below, Time: 3 seconds max. (per pin row) -- Symbol IR35-00-2 VPS VP15-00-2 Wave soldering WS60-00-1 Caution Do not use different soldering methods together (except for partial heating). 64 PD754302, 754304, 754302(A), 754304(A) APPENDIX A. COMPARISON OF FUNCTIONS AMONG PD750004, 754304, AND 75P4308 Item Program memory PD750004 Mask ROM 0000H-0FFFH (4096 x 8 bits) 000H-1FFH (512 x 4 bits) 75XL CPU PD754304 Mask ROM 0000H-0FFFH (4096 x 8 bits) 000H-0FFH (256 x 4 bits) PD75P4308 One-time PROM 0000H-1FFFH (8192 x 8 bits) Data memory CPU Instruction execution time I/O port w/main system clock * 0.67, 1.33, 2.67, or 10.7 s (at 6.0 MHz) * 0.95, 1.91, 3.81, or 15.3 s (at 4.19 MHz) * 122 s (at 32.768 kHz) No subsystem clock w/subsystem clock CMOS input CMOS I/O N-ch open-drain I/O (withstand 13 V) Total 8 (of which 7 can be connected with on-chip pull-up resistor via software) 18 (on-chip pull-up resistor can be connected via software) 8 (pull-up resistor can be connected by mask option) 34 4 channels * Basic interval timer/ watchdog timer * 8-bit timer/event counter * 8-bit timer * Watch timer 4 (pull-up resistor can be connected by mask option) 30 (no port 4 pins) 3 channels * Basic interval timer/watchdog timer * 8-bit timer/event counter 0 (fX/2 2 added) * 8-bit timer/event counter 1 (TI1, fX/22 added) (can be used as 16-bit timer/event counter) 4 (no mask option) Timer Clock output (PCL) * , 524, 262, or 65.5 kHz (main system clock: 4.19 MHz) * , 750, 375, or 93.8 kHz (main system clock: 6.0 MHz) Provided 3 modes are supported * 3-wire serial I/O mode *** MSB/LSB first selectable * 2-wire serial I/O mode * SBI mode Provided None 2 modes are supported * 3-wire serial I/O mode *** MSB/LSB first selectable * 2-wire serial I/O mode BUZ output Serial interface Watch mode register (WM) System clock control register (SCC) Suboscillation circuit control register (SOS) MBS register Stack area (SBS1, 0) None MB0, 1 MB0 only 65 PD754302, 754304, 754302(A), 754304(A) Item TM0, 1 registers PD750004 Bits 0, 1, and 7 are fixed to 0 External: 3, internal: 4 External: 1, internal: 1 Provided PD754304 - PD75P4308 Vectored interrupt Test input Test enable flag (IEW) Test request flag (IRQW) Supply voltage Operating ambient temperature Package External: 1 None VDD = 2.2 to 5.5 V TA = -40 to +85 C * 42-pin plastic shrink DIP (600 mil) * 44-pin plastic QFP (10 x 10 mm) VDD = 1.8 to 5.5 V * 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) 66 PD754302, 754304, 754302(A), 754304(A) APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for development of application systems using the PD754304. In the 75XL Series, a common relocatable assembler is used in combination with a device file dedicated to each model. Language processor RA75X relocatable assembler Host machine OS PC-9800 series MS-DOSTM Ver. 3.30 to Ver. IBM or compatible machine PC/ATTM 6.2 Note 3.5" 2HC 5" 2HC Supply media 3.5" 2HD 5" 2HD Order code (part number) S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X Refer to "OS for IBM PC" Device file Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 Note IBM PC/AT or compatible machine Refer to "OS for IBM PC" 3.5" 2HC 5" 2HC Supply media 3.5" 2HD 5" 2HD Order code (part number) S5A13DF754304 S5A10DF754304 S7B13DF754304 S7B10DF754304 PROM writing tools Hardware PG-1500 The PG-1500 is a PROM programmer that can program PROM-contained single-chip microcontrollers in the standalone mode or under control of a host machine, when connected with an accessory board and an optional programmer adapter. It can also program representative PROMs including 256K-bit to 4M-bit models. This is a PROM programmer adapter dedicated to the PD75P4308GS and connected to the PG-1500. This connects the PG-1500 and a host machine with a serial or parallel interface to control the PG-1500 from the host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 Note IBM PC/AT or compatible machine Refer to "OS for IBM PC" 3.5" 2HD 5" 2HC Supply media 3.5" 2HD 5" 2HD Order code (part number) PA-75P4308GS Software PG-1500 controller S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500 Note Although Ver.5.00 and later have a task swap function, this function cannot be used with this software. Remark The operation of the assembler, device file and PG-1500 controller is guaranteed only on the above host machine and OS. 67 PD754302, 754304, 754302(A), 754304(A) Debugging tools The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the PD754304. The system configurations are described as follows. Hardware IE-75000-R Note 1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a PD754304 subseries, the emulation board IE-75300-R-EM and emulation probe that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a PD754304 subseries, the emulation board IE-75300-R-EM and emulation probe which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. Emulation board for evaluating the application systems that use a PD754304 subseries. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for the PD754304GS. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the flexible board EV-9500GS-36 which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the IE-75000-R or IE-75001-R on a host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 Note 2 IBM PC/AT or compatible machine Refer to "OS for IBM PC" 3.5" 2HC 5" 2HC Supply media 3.5" 2HD 5" 2HD Order code (Part number) IE-75001-R IE-75300-R-EM EP-754304GS-R EV-9500GS-36 Software IE control program S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X Notes 1. 2. Maintenance parts Although Ver.5.00 and later have a task swap function, this function cannot be used with this software. Remark Operation of the IE control program is guaranteed only on the above host machines and OSs. 68 PD754302, 754304, 754302(A), 754304(A) OS for IBM PC The following IBM PC OS's are supported. OS PC DOSTM Version Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/V Note Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note J5.02/V Note MS-DOS IBM DOSTM Note Only English version is supported. Caution Ver. 5.0 and later have the task swap function, but this function cannot be used for this software. 69 PD754302, 754304, 754302(A), 754304(A) APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device related documents Document Number Document Name Japanese English This document U10909E U10123E -- U10453E PD754302, 754304 Data Sheet PD75P4308 Data Sheet PD754304 User's Manual PD754304 Instruction Table 75XL Series Selection Guide U10797J U10909J U10123J IEM-5605 U10453J Development tool related documents Document Number Document Name Japanese Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-754304GS-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Language PG-1500 Controller User's Manual PC-9800 series (MS-DOS) base PC-9800 series (PC DOS) base EEU-846 U11354J U10677J EEU-651 EEU-731 EEU-730 EEU-704 English EEU-1416 EEU-1493 U10677E EEU-1335 EEU-1346 EEU-1363 EEU-1291 EEU-5008 U10540E Other related documents Document Number Document Name Japanese IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Static Electricity Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer Related Product Guide - Other Manufacturers C10943X C10535J C11531J C10983J MEM-539 MEI-603 MEI-604 C10535E IEI-1209 C10983E - MEI-1202 - English Caution These documents are subject to change without notice. Be sure to read the latest documents. 70 PD754302, 754304, 754302(A), 754304(A) [MEMO] 71 PD754302, 754304, 754302(A), 754304(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 72 PD754302, 754304, 754302(A), 754304(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 73 PD754302, 754304, 754302(A), 754304(A) MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 74 |
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