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TE CH
T35L6432B
SYNCHRONOUS BURST SRAM
FEATURES
* Fast Access times: 9 / 10 / 11 / 12 ns * Single 3.3V (+0.3V/-0.165V) power supply * Common data inputs and data outputs * Individual BYTE WRITE ENABLE and GLOBAL WRITE control * Three chip enables for depth expansion and address pipelining * Clock-controlled and registered address, data I/Os and control signals * Internally self-timed WRITE CYCLE * Burst control pins ( interleaved or linear burst sequence) * High 30pF output drive capability at rated access time * SNOOZE MODE for reduced power standby * Burst Sequence : - Interleaved (MODE=NC or VCC) - Linear (MODE=GND)
64K x 32 SRAM
Flow-Through Burst Mode
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous Burst RAM family employs high-speed, low power CMOS design using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The T35L6432B SRAM integrates 65536 x 32 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining inputs (ADSC , chip enable (
CE ), depth-
expansion chip enables (CE2 and CE2), burst control
ADSP, and ADV ), write enables ( BW1, BW2 , BW3, BW4 , and BWE ), and
global write (GW ). Asynchronous inputs include the output enable (OE ), Snooze enable (ZZ) and burst mode control (MODE). The data outputs (Q), enabled by OE , are also asynchronous. Addresses and chip enables are registered with either address status processor (ADSP) or address status controller (ADSC ) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV ). Address and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual
OPTIONS
MARKING -9 Access 9ns Flowtime through Cycle 2-1-1-1 10.5ns time -10 10ns 15ns -11 11ns 15ns -12 12ns 15ns
PACKAGE
100-pin QFP 100-pin TQFP
package code
Q T
Part Number Examples
PART NO. T35L6432B-10Q T35L6432B-12T speed 10ns 12ns Package QFP TQFP
BW1 controls DQ1-DQ8. BW2 controls DQ9-DQ16. BW3 controls DQ17BW4 controls DQ25-DQ32. BW1 , DQ 24. BW2 , BW3, and BW4 can be active only with BWE being LOW. GW being LOW causes all
byte to be written. bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance.
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P. 1
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A0-A15 MODE ADV CLK
TE CH
T35L6432B
FUNCTIONAL BLOCK DIAGRAM
16 ADDRESS REGISTER 16 14 16
A0
A1
Q1 BINARY COUNTER & LOGIC Q0
A1'
A0'
ADSC ADSP
CLR
BWE BYTE 4 WRITE REGISTER BW4
8 BYTE 4 WRITE DRIVER
8
8 BYTE 3 WRITE REGISTER BW3 8 BYTE 2 WRITE REGISTER BW2 8 BYTE 1 WRITE REGISTER BW1 GW ENABLE REGISTER BYTE 1 WRITE DRIVER BYTE 2 WRITE DRIVER BYTE 3 WRITE DRIVER
8 32 64K x 8 x 4 MEMORY ARRAY 8 SENSE AMPS 32 32
OUTPUT BUFFERS
DQ1 . . . DQ32
8
INPUT REGISTERS
CE CE2 CE2
4 OE
Note:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 2
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NC D Q 17 D Q 18 VCCQ VSSQ D Q 19 D Q 20 D Q 21 D Q 22 VSSQ VCCQ D Q 23 D Q 24 NC VCC NC VSS D Q 25 D Q 26 VCCQ VSSQ D Q 27 D Q 28 D Q 29 D Q 30 VSSQ VCCQ D Q 31 D Q 32 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TE CH
T35L6432B
PIN ASSIGNMENT (Top View)
A D SC A D SP BW E BW 4 BW 3 BW 2 BW 1 ADV VCC CLK VSS CE2 CE2 GW OE CE A9 A6 A7 A8
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 NC D Q 16 D Q 15 VCCQ VSSQ D Q 14 D Q 13 D Q 12 D Q 11 VSSQ VCCQ D Q 10 DQ9 VSS NC VCC ZZ DQ8 DQ7 VCCQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VCCQ DQ2 DQ1 NC
1 0 0 - p in Q F P or 1 0 0 - p in T Q F P
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
VCC
VSS
A 10
A 11
A 12
A 13
A 14
A 15
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P. 3
NC
NC
NC
NC
NC
A3
A5
A4
A2
A1
A0
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PINS
TE CH
T35L6432B
PIN DESCRIPTIONS
DESCRIPTION Addresses: These inputs are registered and must meet the setup and 32-37, 44-49, Inputhold times around the rising edge of CLK. The burst counter 81, 82, 99, A0-A15 Synchronous generates internal addresses associated with A0 and A1, during 100, burst cycle and wait cycle. Byte Writes: A byte write is LOW for a WRITE cyle and HIGH for BW1 a READ cycle. BW1 controls DQ1-DQ8. BW2 controls DQ9InputBW2 93-96 DQ16. BW3 controls DQ17-DQ24. BW4 controls DQ25BW3 Synchronous DQ32. Data I/O are high impedance if either of these inputs are BW4 LOW , conditioned by BWE being LOW. 87
BWE
SYM.
TYPE
Write Enable: This active LOW input gates byte write operations Inputand must meet the setup and hold times around the rising edge of Synchronous CLK. Global Write: This active LOW input allows a full 32-bit WRITE to Inputoccur independent of the BWE and BWn lines and must meet Synchronous the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, Inputwritecontrol and burst control inputs on its rising edge. All Synchronous synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable Inputthe device and conditions internal use of ADSP. This input is Synchronous sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable Inputthe device. This input is sampled only when a new external address Synchronous is loaded. This input can be used for memory depth expansion. Synchronous Chip Enable: This active HIGH input is used to enable Inputthe device. This input is sampled only when a new external address Synchronous is loaded. This input can be used for memory depth expansion. Input Output enable: This active LOW asynchronous input enables the data output drivers.
88
GW
89
CLK
98
CE
92
CE2
97
CE2
86
OE
83
ADV
Address Advance: This active LOW input is used to control the Inputinternal burst counter. A HIGH on this pin generates wait cycle Synchronous (no address advance). Address Status Processor: This active LOW input, along withCE Inputbeing LOW, causes a new external address to be registered and a Synchronous READ cycle is initiated using the new address.
84
ADSP
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85
TE CH
T35L6432B
SYM. TYPE DESCRIPTION
PIN DESCRIPTIONS (continued)
QFP PINS Address Status Controller:This active LOW input causes Inputdevice to be deselected or selected along with new external Synchronous address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Do not alter input state while device is operating. Snooze Enable: This active HIGH asynchronous input causes the device to enter a low-power standby mode in which all data in the memory arry is retained. Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25DQ32. Input data must meet setup and hold times around the rising edge of CLK. Power Supply: 3.3V (+0.3V/-0.165V) Ground: GND Output Buffer Supply: 3.3V (+0.3V/-0.165V) Output Buffer Ground: GND
ADSC
31
MODE
64 2, 3, 6-9, 12, 13, 18, 19, 22-25, 28, 29, 52, 53, 56-59, 62, 63, 68, 69, 72-75, 78, 79, 15,41,65,91 17,40,67,90 4,11,20,27,54, 61,70,77 5,10,21,26,55, 60,71,76 1,14,16,30,38, 39,42,43,50,51, 66,80
ZZ
Input
DQ1DQ32
Input/ Output
VCC VSS VCCQ VSSQ
Supply Ground I/O Supply I/O Ground
NC
-
No Connect: These signals are not internally conntected.
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TE CH
T35L6432B
INTERLEAVED BURST ADDRESS TABLE (MODE = NC/VCC)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00
LINEAR BURST ADDRESS TABLE (MODE = GND)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10
PARTIAL TRUTH TABLE FOR READ/WRITE
Function READ READ WRITE one byte WRITE all byte WRITE all byte
GW
H H H H L
BWE
H L L L X
BW1
X H L L X
BW2
X H H L X
BW3
X H H L X
BW4
X H H L X
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TE CH
T35L6432B
TRUTH TABLE
OPERATION
Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Snooze Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst
ADDRESS USED CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ
None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L L X L L L L L X X H H X H X X H H X H X X H X H X L L L L L X X X X X X X X X X X X X L X L X X H H H H H X X X X X X X X X X X X L L L L L H L L L L L L L L L L L L L L L L L X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Note: 1. X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means any one or more byte write enable signals (BW1, BW2 , BW3 or BW4 ) and BWE are LOW, or GW equals LOW. WRITE = H means all byte write signal are HIGH. 2. BW1= enables write to DQ1-DQ8. BW2 = enables write to DQ9-DQ16. BW3 = enables write to DQ17-DQ24. BW4 =enables write to DQ25-DQ32. 3. All inputs except OE and ZZ must meet setup and hold times around the rising edge ( LOW to HIGH) of CLK. 4. Suspending burst generates wait cycle. 5. For a write operation following a read operation. OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be High-Z during power-up. 7. ADSP= LOW along with chip being selected always initiates an internal READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
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TE CH
T35L6432B
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS. ............-0.5V to +4.6V I/O Supply Voltage VccQ ........... Vss -0.5V to Vcc VIN......................................... -0.5V to Vcc +0.5V Storage Temperature (plastic)...... -55C to +150C Junction Temperature ............................... +150C Power Dissipation ........................................ 1.0W Short Circuit Output Current...................... 100mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0C Ta 70C; VCC = 3.3V (+0.3V/-0.165V) unless otherwise noted) DESCRIPTION Input High (Logic) voltage Input Low (Logic) voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage CONDITIONS SYM. VIH VIL 0V VIN VCC Output(s) disabled, 0V VOUT VCC IOH = -4.0 mA IOL = 8.0 mA ILI ILO VOH VOL Vcc MIN 2 -0.3 -2 -2 2.4 3.1 0.4 3.6 MAX.
CONDITIONS Device selected; all inputs VIL or Power Supply VIH; cycle time tKC MIN; VCC Current : Operating = MAX; outputs open Device selected;ADSC ,ADSP , Power Supply Current: Idle DESCRIPTION SYM. TYP ICC -9 -10 -11 -12 UNITS NOTES mA 3, 12, 13
MAX VCCQ + 0.3 0.8 2 2
UNITS V V uA uA V V V
NOTES 1, 2 1, 2 14
1, 11 1, 11 1
TBD 250 200 150 120
ADV , GW ,BWE VIH; all other
inputsVIL orVIH; VCC = MAX; cycle time tKC MIN: outputs open Device deselected; VCC = MAX; all inputs VSS + 0.2 or VCC - 0.2; all inputs static; CLK frequency =0 Device deselected; all inputs VIL or VIH; all inputs static; VCC = MAX;CLK frequency = 0 Device deselected; all inputs VIL or VIH; VCC =MAX; CLK cycle
ISB1 TBD
60
60
60
60
mA
12, 13
CMOS Standby
ISB2 TBD
10
10
10
10
mA
12, 13
TTL Standby
ISB3 TBD
25
25
25
25
mA
12, 13
Clock Running
ISB4 TBD
60
60
60
60
mA
12, 13
time tKCMIN Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P.8 Publication Date: JUL. 2002 Revision: A
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TE CH
T35L6432B
AC ELECTRICAL CHARACTERISTICS (Note 5) (0CTA70C;VCC=3.3V +0.3V/-0.165V)
DESCRIPTION Clock Clock cycle time Clock to output valid Clock to output invalid Clock to output in Low-Z Output Times Clock HIGH time Clock LOW time Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup Times Address Address Status( ADSC , ADSP ) Address Advance ( ADV ) Byte Write Enables ( BW1~ BW4 , BWE , GW ) Data-in Chip Enables( CE , CE2 ,CE2) Hold Times Address Address Status( ADSC , ADSP ) Address Advance ( ADV ) Byte Write Enables ( BW1~ BW4 , BWE , GW ) Data-in Chip Enables( CE , CE2 ,CE2) -9
SYM.
-10
-11
-12
MIN MAX MIN MAX MIN MAX MIN MAX
UNITS NOTES
tKC tKQ tKQX tKQLZ tKH tKL tKQHZ tOEQ tOELZ tOEHZ tAS tADSS tAAS tWS tDS tCES tAH tADSH tAAH tWH tDH tCEH
10.5 9.0 3 3 1.8 1.8 5 5 0 5 1.7 1.7 1.7 1.7 1.7 1.7 0.5 0.5 0.5 0.5 0.5 0.5
15 10 3 3 1.9 1.9 5 5 0 5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5
15 11 3 3 2.0 2.0 5 5 0 5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5
15 12 3 3 2.0 2.0 5 5 0 5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6, 7 6, 7 9 6, 7 6, 7 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10
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P.9
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TE CH
T35L6432B
CAPACITANCE
DESCRIPTION Input Capacitance Input/ Output Capacitance(DQ) CONDITIONS TA = 25C; f = 1 MHz VCC = 3.3V SYM. CI CO TYP 3 6 MAX 4 7 UNITS NOTES pF pF 4 4
THERMAL CONSIDERATION
DESCRIPTION Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case CONDITIONS Still air, soldered on 4.25x1.125 inch 4-layer PCB SYM. QFP TYP UNITS JA JB 20 1 C/W C/W NOTES
AC TEST CONDITIONS
Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2
7. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 8. A READ cycle is defined by byte write enables all HIGH or ADSP LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE. 9. OE is a "don't care" when a byte write enable is sampled LOW. 10.This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined in the truth table. 11.AC I/O curves are available upon request. 12."Device Deselected means the device is in POWER-DOWN mode as defined in the truth table. "Device Selected" means the device is active. 13.Typical values are measured at 3.3V, 25C and 20ns cycle time. 14.MODE pin has an internal pull-up and exhibits an input leakage current of 10A.
Notes:
1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +3.6 V for t tKC/2. Undershoot: VIL -1.0 V for t tKC/2. 3. Icc is given with no output current. Icc increases with greater output loading and faster cycle times. 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. Output loading is specified with CL = 5 pF as in Fig. 2.
OUTPUT LOADS
3 .3 V 317 ohm DQ 50 ohm Z0 = 50 ohm V t = 1 .5 V F ig . 2 o u tp u t lo a d e q u iv a le n t ( f o r tK Q H Z ,tK Q L Z ,tO E H Z ,tO E L Z ) 351 ohm 5 pF
DQ
F ig . 1 o u tp u t lo a d e q u iv a le n t
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P.10
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TE CH
T35L6432B
device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, IZZ is guaranteed after the setup time tZZ is met. Any access pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed.
SNOOZE MODE
SNOOZE MODE is a low current, "power down" mode in which the device is deselected and current is reduced to IZZ. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After entering SNOOZE MODE, the clock and all other inputs are ignored. The ZZ pin (pin 64) is an asynchronous, active HIGH input that causes the
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SNOOZE MODE ZZ HIGH to SNOOZE MODE time SNOOZE MODE Operation Recovery Time CONDITIONS ZZ VIH SYMBOL IZZ tZZ tRZZ 2(tKC) 2(tKC) MIN MAX 5 UNITS mA ns ns 4 4 NOTES
SNOOZE MODE WAVEFORM
CLK
CE
tR ZZ
ZZ
tZZ
ISU PPL Y
IZZ
ISU PPL Y :D o n 't c a r e
Note:
1. The CE signal shown above refers to a TRUE state on all chip selects for the device. 2. All other inputs held to static CMOS levels (VIN Vss + 0.2 V or Vcc -0.2 V).
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P.11
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CLK ADSP
TE CH
T35L6432B
tK C
READ TIMING
tK H tA D S S tA D S H tK L
tA D S S
tA D S H
ADSC
tA S tA H
D e s e le c t C y c le (N o te 4 )
A D D RESS
A1
A2
tW S tW H
G W ,B W E B W 1 -B W 4
tC E S tC E H
CE (N O T E 2 )
tA A S tA A H
ADV
A D V su s p e n d s b u rs t
OE
tO E Z tK Q L Z tO E H Z tO E L Z tK Q tK Q X
Q (A 1 ) Q (A 2 )
Q (A 2 + 1 )
tK Q H Z
Q
tK Q
Q (A 2 + 2 )
Q (A 2 + 3 )
Q (A 2 )
Q (A 2 + 1 )
Q (A 2 + 2 )
B u rs t w ra p s a ro u n d to its in ita l s ta te S in g le R E A D BURST READ
: D o n 't c a r e :U N D E F IN E D
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. 2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge. 4. Output are disabled tKQHZ after diselect.
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P. 12
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CLK AD SP
TE CH
tK
T35L6432B
C
WRITE TIMING
tK tA
DSS
H
tA
tK
DSH
L
tA
DSS
tA
A D S C e x te n d s b u rs t
DSH
tA
DSS
tA
DSH
AD SC
tA
S
tA
H
AD DRESS
A1
A2
B Y T E W R IT E s ig n a ls a re ig n o re d fo r firs t c y c le w h e n A D S P in itia lte s b u rs t
A3
tW
S
tW
H
BW E B W 1 -B W 4
tW
S
tW
H
(N o te 5 )
GW
tC E S tC E H
CE
(N o te 2 )
tA
AS
tA
AH
ADV
(N o te 4 ) A D V su sp n d s b u rst
OE
(N o te 3 )
tD
S
tD
H
D
H ig h -Z
D (A 1 )
D (A 2 )
D (A 2 + 1 )
D (A 2 + 1 )
D (A 2 + 2 )
D (A 2 + 3 )
D (A 3 )
D (A 3 + 1 )
D (A 3 + 2 )
tO
(N o te 1 )
EHS
Q
BU RST REA D
S in g le W R IT E
B U R S T W R IT E
E x te n d B U R S T W R IT E
: D o n 't c a r e :U N D E F IN E D
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. 2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW , CE2 is LOW and CE2 is HIGH. When CE is HIGH , CE2 is HIGH and CE2 is LOW. 3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time. This prevents input/output data contention for the time period to the byte write enable inputs being sampled. 4. ADV must be HIGH to permit a WRITE to the loaded address. 5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4 LOW. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 13 Publication Date: JUL. 2002 Revision: A
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CLK ADSP
TE CH
tK C
T35L6432B
READ/WRITE TIMING
tK H tA D S S tA D S H tK L
ADSC
tA S tA H
A DD RESS
A1
A2
A3
A4
A5
A6
tW
S
tW
H
BW E B W 1 -B W 4
tC E S tC E H
CE (N O T E 2 )
ADV
OE
tD S tD H
D
H ig h -Z
D (A 3 )
tO E L Z tK Q
(N O T E 1 )
D (A 5 )
D (A 6 )
tO E H Z
Q
Q (A 1 )
Q (A 2 )
Q (A 4 )
Q (A 4 + 1 )
Q (A 4 + 2 )
Q (A 4 + 3 )
B a c k -to -B a c k R E A D s
S in g le W R I T E
BURST READ
B a c k -to -B a c k W R IT E s
: D o n 't c a r e :U N D E F IN E D
Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst address following A4. 2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC or ADV cycle is performed. 4. GW is HIGH. 5. Back-to-back READs may be controlled by either ADSP or ADSC . Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 14 Publication Date: JUL. 2002 Revision: A
tm
100 1
TE CH
T35L6432B
PACKAGE DIMENSIONS 100-LEAD QFP SSRAM (14 x 20 mm)
HD' D 81
80
b
30
51
31
50
t A S e a tin g P la n e y c A1 A2 L' L1 '
SYMBOL A A1 A2 b D E e HD' HE' L' L1' t y
DIMENSIONS IN INCHES 0.130(MAX) 0.1120.005 0.004(MIN) 0.012+0.004-0.002 0.5510.005 0.7870.005 0.0260.006 0.6770.008 0.9130.008 0.0320.008 0.0630.008 0.006+0.004-0.002 0.004(MAX) 0~12
HE'
e
E
DIMENTION IN MM 3.302(MAX) 2.8450.127 0.102(MIN) 0.300+0.102-0.051 14.0000.127 20.0000.127 0.6500.152 17.2000.203 23.2000.203 0.8000.203 1.6000.203 0.150+0.102-0.051 0.102(MAX) 0~12
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P.15
Publication Date: JUL. 2002 Revision: A
tm
100 1
TE CH
T35L6432B
PACKAGE DIMENSIONS 100-LEAD TQFP SSRAM (14 x 20 mm)
HD' D 81
80
b
30
51
31
50
t A S e a tin g P la n e y c A1 A2 L' L1 '
SYMBOL A A1 A2 b D E e HD' HE' L' L1' t y
DIMENSIONS IN INCHES 0.063(MAX) 0.0550.005 0.002(MIN) 0.013+0.002-0.004 0.5510.004 0.7870.004 0.0260.006 0.6300.004 0.8660.004 0.0240.006 0.0390.006 0.0060.002 0.003(MAX) 0~7
HE'
e
E
DIMENTION IN MM 1.600(MAX) 1.4000.050 0.050(MIN) 0.320+0.060-0.100 14.0000.100 20.0000.100 0.6500.152 16.0000.100 22.0000.100 0.6000.150 1.0000.150 0.150+0.050-0.060 0.080(MAX) 0~7
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P.16
Publication Date: JUL. 2002 Revision: A

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