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CXA2054S
US Audio Multiplexing Decoder
Description The CXA2054S is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction and sound processor. Various kinds of filters are built in while adjustment, mode control and sound processor control are all executed through I2C BUS. Features * Audio multiplexing decoder, dbx noise reduction decoder and sound processor (surround, volume limiter, bass * treble, volume) are all included in a single chip. Almost any sort of signal processing is possible through this IC. * All adjustments are possible through I2C BUS to allow for automatic adjustment. * Various built-in filter circuits greatly reduce external parts. * There are two channel external inputs for LSOUT outputs. * Automatic volume control between input sources is possible through volume limiter. Standard I/O Level * Input level COMPIN (Pin 19) AUX1-L/R (Pins 40 and 39) AUX2-L/R (Pins 42 and 41) SURRIN (Pin 4) Pin Configuration (Top View)
48 47 46 45 44 43 42 41 40 39 38 37 36
48 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VCC 11 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -65 to +150 * Allowable power dissipation PD 2.2 Range of Operating Supply Voltage 90.5
V C C W
V
Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC * Output level TVOUT-L/R (Pins 44 and 43) LSOUT-L/R (Pins 7 and 6) SURROUT (Pin 5)
245 mVrms 490 mVrms 490 mVrms 490 mVrms
490 mVrms 490 mVrms 490 mVrms
A license of the dbx-TV noise reduction system is required for the use this device.
35 34 33 32 31 30 29 28 27 26 25
AUX2-L
SURRTC
BASSL1
VCATC
SAPIN
VETC
TVOUT-L
TVOUT-R
NOISETC
SURROUT
VCAWGT
LSOUT-R
MAINOUT
LSOUT-L
MAININ
PCINT1
COMPIN
BASSL2
SURRIN
PCINT2
SCL
SAPTC
23
DGND
TRER
TREL
PLINT
IREF
VGR
SDA
GND
SAD
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NC
16
17
18
19
20
21
22
24
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
VCC
SUBOUT
VLTC
SAPOUT
AUX2-R
BASSR2
VEWGT
AUX1-L
VCAIN
VLDC
BASSR1
VEOUT
VE
AUX1-R
STIN
E96Y15B86-TE
PCINT1
PLINT
PCINT2
SUBOUT
MAININ
AUX1-L
MAINOUT
AUX1-R
Block Diagram
16 FEXT1 SW1 VCO MATRIX FLT VOLLIM LPF VCA FEXT2 SW2 1/4 1/2
17
18
25
14
13
40
39
STLPF
"FILTER"
LFLT
44 TVOUT-L 43 TVOUT-R 42 AUX2-L 41 AUX2-R 37 VLDC 38 VLTC 45 SURRTC SURROUND 48 BASSL1
COMPIN 19 DeEm NRSW/FOMO/SAPC (+6dB) STIND LOGIC LPF
"STEREO"
VCA
LPF
WIDEBAND
VL EXT1/EXT2/M1
PREVOL
VCC 24
SURR PR-VOL
ATT
1 BASSL2
BASS BASS BASS
46 BASSR1 47 BASSR2 VCA
GND 22
SAPVCO
HPF SAPIND "SAP"
RMSDET
SAPTC 23
TREBLE
TREB
TREB
VOL-L
VOL-R
VOL-S
M2 VOL-L VOL-R
20
21
12
11
10
9
SDA SAPIN SAPOUT
28
29
26
30
31
32
33
34
36
35
7
STIN VE VETC VEOUT VCAIN VEWGT VCATC LSOUT-L VCAWGT
6
LSOUT-R
5
SURROUT
(L-R)
VGR
IREF
SAD
DGND
SCL
VOL-SURR
--2--
LPF DeEm NOISE DET "NOISE" VE SPECTRAL AMP (+4dB) LPF LPF I2C BUS I/F
"PONRES"
BPF
NOISETC 27
3 TREL 2 TRER
MATRIX
RMSDET
VCO
FILTER
SURRSW SW3
4 SURRIN
IREF
SW
CXA2054S
CXA2054S
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
VCC
(Ta=25 C, VCC=9 V) Description BASS filter pin. (Left channel) (Connect a 15 nF capacitor between Pins 1 and 48.) The cutoff frequency is determined by the built-in resistor and the external capacitance. BASS filter pin. (Right channel) (Connect a 15 nF capacitor between Pins 47 and 46.) The cutoff frequency is determined by the built-in resistor and the external capacitance.
1
BASSL2
4.0 V
3k
1
47
580 13.2k 10.7k 8.57k 6.89k 580
48
BASSL1
4.0 V
47
BASSR2
4.0 V
5.66k 4.44k 3.67k
VCC 46 48
46
BASSR1
4.0 V
4V
15.3k
VCC 3k
2
TRER
4.0 V
4.2k 3.42k 2.73k 2.2k 1.8k 1.42k VCC 1.17k 4.88k
580 580
TREBLE filter pin. (Right channel) (Connect a 6.8 nF capacitor between this pin and GND.)
3
TREL
4.0 V
2 3
TREBLE filter pin. (Left channel) (Connect a 6.8 nF capacitor between this pin and GND.)
VCC 10k
4
27.5k
4
SURRIN
4.0 V
47k 4V 20k 20k
Surround external input pin.
--3--
CXA2054S
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC
5
SURROUT
4.0 V
VCC 580
(L-R) signal output pin.
6
LSOUT-R
4.0 V
5 6 7
580
LSOUT right channel output pin.
7
LSOUT-L
4.0 V
LSOUT left channel output pin.
8
NC
--
8
--
VCC 7.5k 35 2.1V x2 4k x5
9
SDA
--
7.5k
4.5k
3k
Serial data I/O pin. VIH > 3.0 V VIL < 1.5 V
9
VCC 7.5k 35 2.1V 4k
10
SCL
--
10.5k
x4
3k
Serial clock input pin. VIH > 3.0 V VIL < 1.5 V
10
11
DGND
--
11
Digital block GND.
--4--
CXA2054S
Pin No.
Symbol
Pin voltage
VCC
Equivalent circuit
Description
2V 40k 80k
12
12
SAD
--
10k
Slave address control switch. The slave address is selected by changing the voltage applied to this pin.
VCC 10k
VCC
13
MAININ
4.0 V
147 13 53k 4V
VCC 15k VCC 147 14 x4
Input the (L+R) signal from MAINOUT (Pin 14).
14
MAINOUT
4.0 V
(L+R) signal output pin.
200
1k
15
NC
--
15
--
VCC
16
147
16
PCINT1
4.0 V
30k 22k
VCC 147 17
Stereo block PLL loop filter integrating pin.
17
PCINT2
4.0 V
2k
10k x2 4k
10k
--5--
CXA2054S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 15k 15k
Description
147
18
PLINT
5.1 V
20k 20k
18
Pilot cancel circuit loop filter integrating pin. (Connect a 1 F capacitor between this pin and GND.)
26
20k
50
10k
VCC
50k
147 3k
19
COMPIN
4.0 V
19
Audio multiplexing signal input pin.
4k
16k
3k
147
20
VGR
1.3 V
9.7k
19.4k x4
VCC 11k
Band gap reference output pin. (Connect a 10 F capacitor between this pin and GND.)
20
2.06k
VCC 40k 40k 30k 30k
VCC
21
IREF
1.3 V
30p 1.8k 21 147
Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62 k (1 %) resistor between this pin and GND.)
16k
--6--
CXA2054S
Pin No. 22
Symbol
Pin voltage --
Equivalent circuit
22
Description
GND
Analog block GND.
VCC 8k 10k 3k 1k VCC 4k 50 23
23
SAPTC
4.5 V
Set the time constant for the SAP carrier detection circuit. (Connect a 4.7 F capacitor between this pin and GND.)
24
VCC
--
24
Supply voltage pin.
VCC 2k 2k 10P 4k
580
25
SUBOUT
4.0 V
2k 2k 14.4k 580 147
25
(L-R) signal output pin.
2k
4k
1k
VCC
26
STIN
4.0 V
23k
23k
Input the (L-R) signal from SUBOUT (Pin 25).
11.7k 147 26 18k 4V 20k 147 29 18k 4V
29
SAPIN
4.0 V
Input the (SAP) signal from SAPOUT (Pin 28).
--7--
CXA2054S
Pin No.
Symbol
Pin voltage
8k
Equivalent circuit
VCC 3.3k
Description
10k
27
NOISETC
3.0 V
1k x2 3k VCC
2k 4k 4V 3k
Set the time constant for the noise detection circuit. (Connect a 4.7 F capacitor between this pin and GND.)
200k
27
VCC 5P
580
28
SAPOUT
4.0 V
580
10k 28 147
SAP FM detector output pin.
24k 10
4k 50
VCC 7.5k
147
30
VE
4.0 V
30
Variable de-emphasis integrating pin. (Connect a 2700 pF capacitor and a 3.3 k resistor in series between this pin and GND.)
VCC
580
4V
2.9V
31
VEWGT
4.0 V
31 147 580 36k
Weight the variable deemphasis control effective value detection circuit. (Connect a 0.047 F capacitor and a 3 k resistor in series between this pin and GND.)
8k
30k 8
4k 50
--8--
CXA2054S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC
Description
32
VETC
1.7 V
x4
32 x4
4k 50
20k 7.5
Determine the restoration time constant of the variable deemphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3 F capacitor between this pin and GND.)
VCC 5P 580
33
VEOUT
4.0 V
33 10k 580
Variable de-emphasis output pin. (Connect a 4.7 F non-polar capacitor between Pins 33 and 34.)
VCC
47k 20k VCC 34
47k
34
VCAIN
4.0 V
VCA input pin. Input the variable deemphasis output signal from Pin 33 via a coupling capacitor.
VCC
x4
35 x4
35
VCATC
1.7 V
50
4k
7.5
20k
Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10 F capacitor between this pin and GND.)
--9--
CXA2054S
Pin No.
Symbol
Pin voltage
40k
Equivalent circuit
VCC 40k 3P
Description
580
36
VCAWGT
4.0 V
2.9V 36k
36 580 147
Weight the VCA control effective value detection circuit. (Connect a 1 F capacitor and a 3.9 k resistor in series between this pin and GND.)
50
4k 8
30k
8k
VCC 3k 147
37
VLDC
0.7 V
37
Volume limiter detection circuit bias pin. (Connect a 1 M resistor between pins 37 and 38.)
VCC
200
200 147 100k 100k
38
VLTC
38
Set the time constant for the volume limiter detection circuit.
39
AUX1-R
4.0 V
10k
VCC
Right channel external input 1 pin. Left channel external input 1 pin. Right channel external input 2 pin. Left channel external input 2 pin.
40
AUX1-L
4.0 V
27.5k 47k 4V 20k 20k
39 40 41 42
41
AUX2-R
4.0 V
42
AUX2-L
4.0 V
--10--
CXA2054S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 3k
Description
43
TVOUT-R
580 43 44 580 147
TVOUT right channel output pin. 4.0 V
44
TVOUT-L
TVOUT left channel output pin.
VCC 10k 20k 40k 580 24k 580 45
45
SURRTC
4.0 V
20k VCC
Set the central frequency of the SURROUND circuit phase shifter. The frequency is determined by the built-in resistor and the external capacitance. (Connect a 0.022 F capacitor between this pin and GND.)
--11--
Electrical Characteristics
COMP IN input level (100 % modulation level)
Main (L+R) (Pre-Emphasis : OFF) SUB (L-R) (dbX-TV : OFF) Pilot SAP Carrier fH =245 mVrms =490 mVrms =49 mVrms =147 mVrms =15.734 kHz (Ta=25 C, VCC=9 V)
Mode Input pin Filter Min. 37 43/44 20 log ('5 k'/'1 k') 20 log ('12 k'/'1 k') 15 kLPF 15 kLPF 20 log ('100 %'/'0 %') 15 kLPF 43/44 43/44 43/44 43/44 25 20 log ('12 k'/'1 k') 15 kLPF 15 kLPF 15 kLPF 25 25 25 25 43/44 440 -1.2 -3.0 -- -- 61 150 -3.0 -- -- 56 47 490 0 -1.0 0.1 0.15 69 190 -0.5 0.1 0.2 64 Typ. No signal MONO 19 19 19 19 19 19 19 19 19 19 19 MONO MONO MONO MONO MONO ST ST ST ST ST Input signal Measurement conditions Output pin Max. 57 540 1.0 1.0 0.5 0.5 -- 230 1.0 1.0 2.0 -- Unit mA mVrms dB dB % % dB mVrms dB % % dB
No.
Item
Symbol
1
Current consumption
ICC
2
Main output level
Vmain
3
FCdeem
4
Main de-emphasis frequency characteristic Main LPF frequency characteristic
FCmain
--12--
SAP 19 1 kBPF ST 19 PILOT (fH) 0 dB 20 log ('100 %'/'0 %') 20 log ('NRSW=0'/ 'NRSW=1') 20 log ('out'/'in') fH BPF
5
Main distortion
THDm
6
Main overload distortion
THDmmax
7
Main S/N
SNmain
8
Sub output level
Vsub
9
Sub LPF frequency characteristic
FCsub
10
Sub distortion
THDsub
11
Sub overload distortion
THDsmax
12
Sub S/N
SNsub
13
ST SAP
Cross talk
CTst
Mono 1 kHz 100 % mod. Pre-em. on Mono 5 kHz 30 % mod. Pre-em. on Mono 12 kHz 30 % mod. Pre-em.on Mono 1 kHz 100 % mod. Pre-em. on Mono 1 kHz 200 % mod. Pre-em off Mono 1 kHz, Pre-em on SUB (L-R), 1 kHz, 100 % mod., NR OFF SUB (L-R) 12 kHz, 30 % mod., NR OFF SUB (L-R) 1 kHz, 100 % mod., NR OFF SUB (L-R), 1 kHz, 200 % mod., NR OFF SUB (L-R) 1 kHz, NR OFF SUB (L-R) 1 kHz, 100 % mod., NR ON SAP Carrier (5 fH) 44 60 25 --
70
--
dB
CXA2054S
14
Sub pilot leak
PCsub
-42
-30
dB
No. Filter Min. Max. -3.0 10.0 230 610 2.5 2.5 0.6 -- 46 -8.5 43/44 44 -- 60 -12.0 BUS RETURN 2.0 15 kLPF 15 kLPF 15 kLPF 15 kLPF 43/44 43/44 43/44 43/44 43/44 23 23 23 23 -0.5 55 -7.0 -75 70 -9.0 4.0 35 35 35 35 0 6.0 1.5 -- -5.5 -54 -- -6.5 6.0 -- -- -- -- 0.5 dB mVrms mVrms dB % % dB dB dBm dB dB dB dB dB dB dB dB dB Unit -9.0 2.0 28 150 370 -3.0 -- 0 490 190 43/44 28 15 kLPF 15 kLPF 15 kLPF 28 15 kLPF 1 kBPF 28 43/44 28 6.0 -6.0 Typ. 0 dB=49 mVrms 20 log (`on level'/'off level') BUS RETURN
Item
Symbol
Mode Input pin Input signal
Measurement conditions
Output pin
15 ST 19 Change PILOT (fH) Level
Stereo ON level
THst
16
Stereo ON/OFF hysteresis
HYst
17 SAP 19
Vsap1
SAP output level
18 SAP 19
Vsap2
19
SAP LPF frequency characteristic
FCsap
20 SAP 19
THDsap1
SAP distortion
21 SAP 19 19 -- 19 Change SAP 19 SAP Carrier (5 fH) Level ST 19 19 19 19 39/40 ST ST ST EXT No signal SAP 1 kHz, 100 % mod. NR OFF SAP 1 kHz, NR OFF SAP SAP ST 20 log ('100 %'/'0 %')
THDsap2
SAP 1 kHz 100 % mod. NR OFF SAP 1 kHz 100 % mod. NR ON SAP 10 kHz, 30 % mod. 20 log NR OFF ('10 k'/'1 k') SAP 1 kHz 100 % mod. NR OFF SAP 1 kHz 100 % mod. NR ON
22
SAP S/N
SNsap
23
SAP soft mute
Smute
--13--
SAP 1 kHz, 100 % mod. 20 log (`NRSW=1' NR ON, Pilot (fH) /`NRSW=0') 0 dB=147 mVrms 20 log (`on level'/'off level') ST-L 300 Hz 30 % mod. 20 log NR ON (`Lch'/`Rch') ST-R 300 Hz 30 % mod. 20 log NR ON (`Rch'/`Lch') ST-L 3 kHz 30 % mod. 20 log NR ON (`Lch'/`Rch') ST-R 3 kHz 30 % mod. 20 log NR ON (`Rch'/`Lch') Sine wave 1 kHz, 0 dB=490 mVrms 490 mVrms
24
dbx out noise level
Ndbx
25
SAP ST
Cross talk
CTsap
26
SAP ON level
THsap
27
SAP ON/OFF hysteresis
HYsap
28
ST separation 1 L R
STLsep1
29
ST separation 1 R L
STRsep1
30
ST separation 2 L R
STLsep2
31
ST separation 2 R L
STRsep2
32
TVOUT output level
Vtv
CXA2054S
No. Mode Min. Max. -60 -80 -70 -75 25 0.01 88 75 -- 0.1 0.5 -- 1.0 dB dB dB mV % dB % dB Unit -- -- -- -- -25 -- 0 -90 -85 -90 -75 Typ. INT 1 kBPF 43/44 43/44 1 kBPF 43/44 43/44 15 kLPF
20 log ('490 mVrms'/'No signal')
Item Filter 43/44 39/40 19 19 0 dB=490 mVrms
20 log (M1="0"/M1="1") 20 log (M1="0"/M1="1")
Symbol
Input pin
Input signal
Output pin
33 EXT INT EXT 0 dB=490 mVrms
Mute (M1=0)/DC difference when there is no signal
34
TVOUT cross talk 0 dB=490 mVrms INT EXT
CTtv1
Measurement conditions 0 dB=490 mVrms EXT INT
CTtv2
35 39/40 -- 39/40 43/44 43/44 43/44 39/40 15 kLPF 15 kLPF 0 dB=490 mVrms 6/7 0 dB=490 mVrms 0 dB=490 mVrms EXT INT 0 dB=490 mVrms INT EXT
20 log (M2="0"/M2="1")
36 INT EXT No signal EXT EXT EXT INT EXT INT EXT EXT -- No signal 39/40 41/42 19 19 39/40
TVOUT muted amount
MUtv1
MUtv2
Sine wave 1 kHz, 490 mVrms MONO 1 kHz, 100 %, mod. Pre-em. on MONO 1 kHz, 100 %, mod. Pre-em. on Sine wave 1 kHz, 490 mVrms
37
TVOUT DC offset
OStv
38
TVOUT distortion
THDtv
39
TVOUT S/N
SNtv
40
TVOUT overload distortion
THDtvmax
Vls1
41
LSOUT output level
-0.9
0
0.9
dB
--14--
39/40 41/42 39/40 41/42 1 kBPF 0 dB=490 mVrms
Mute (M2=0)/DC difference when there is no signal
Vls2
42
CTls1
6/7 6/7 1 kBPF 6/7 6/7 15 kLPF 6/7
-- -- -- -25 --
-75 -90 -90 0 0.01
-60 -80 -75 25 0.5
dB dB dB mV %
LSOUT cross talk
43
CTls2
44 INT EXT EXT EXT EXT EXT EXT
LSOUT muted amount
MUls
Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 490 mVrms/No signal Sine wave 1 kHz, 2 Vrms MONO 1 kHz, 100 %, mod. Pre-em. on Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 490 mVrms MONO 1 kHz, 100 %, mod. Pre-em. on Sine wave 1 kHz, 490 mVrms
45
LSOUT DC offset
OSls
46
LSOUT distortion
THDls
47
LSOUT S/N
SNls
20 log ('490 mVrms'/'No signal')
15 kLPF 15 kLPF
6/7 6/7 6/7 6/7
75 -- 11 -13
88 0.1 12 -12
-- 1.0 13 -11
dB % dB CXA2054S dB
48
LSOUT overload distortion
THDlsmax
49
BASS maximum value
TBmax
50
BASS minimum value
TBmin
39/40 41/42 39/40 41/42 39/40 41/42 39/40 41/42 39/40 41/42
Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 2 Vrms Sine wave 100 Hz, 245 mVrms Sine wave 100 Hz, 245 mVrms
BASS="F" 0 dB=245 mVrms BASS="0" 0 dB=245 mVrms
No. Filter Min. Max. Unit dB dB dB dB -75 4.6 6.0 220 175 200 -- 250 0.04 7.5 265 300 0.2 dB dB mVrms mVrms mVrms 13 -11 -75 11 -13 -- -- 1.3 4.5 3.0 -90 -90 -12 12 Typ. 6/7 6/7 1 kBPF 1 kBPF 7 7 6/7 6/7 1 kBPF 43/44 5 6/7 EXT EXT EXT EXT EXT 40/42 40/42 VL="1" VL="1" M1=M2="0" EXT EXT EXT INT 19
VOL-L="0", VOL-R="0"
Item
Symbol
Mode Input pin Input signal
Output pin
51
TREBLE maximum value
TTmax
52
TREBLE minimum value
TTmin
Measurement conditions TREBLE="F" 0 dB=245 mVrms TREBLE="0" 0 dB=245 mVrms
53
Volume minimum value
VOLmin
54
SVOLmin
39/40 41/42 39/40 41/42 39/40 41/42 39/40 41/42
55
Sr1
56
SURROUT volume minimum value SURROUND frequency characteristic 1 SURROUND frequency characteristic 2
Sr2
0 dB=490 mVrms VOL-SURR="0" 0 dB=490 mVrms SURR="1" 0 dB=490 mVrms SURR="1" 0 dB=490 mVrms
57
VL limit level 1
VL1
58
VL limit level 2
VL2
39/40 41/42 39/40 41/42
59
TVOUT overload leak
Oltv
Sine wave 10 kHz, 245 mVrms Sine wave 10 kHz, 245 mVrms Sine wave 1 kHz, 490 mVrms Sine wave 1 kHz, 490 mVrms Sine wave 330 Hz, 490 mVrms Sine wave 10 kHz, 490 mVrms Sine wave 1 kHz, 220 mVrms Sine wave 1 kHz, 1 Vrms Sine wave 1 kHz, 9 Vp-p
--15--
INT 19 Sine wave 1 kHz, 9 Vp-p M1=M2="0" VOL-L=VOL-R= VOL-SURR="0" 1 kBPF
60
LSOUT overload leak SURROUT
Olls
5/6/7
--
0.04
0.2
mVrms
CXA2054S
CXA2054S
I2C BUS block items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Item High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 9) during 3 mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Symbol VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD : STA tLOW tHIGH tSU : STA tHD : DAT tSU : DAT tR tF tSU : STO Min. 3.0 0 -- -- 0 3 -- 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 10 10 0.4 -- 10 100 -- -- -- -- -- -- -- 1 300 -- Unit V A V mA pF kHz
s
ns s ns s
I2C BUS load conditions :
Pull-up resistor 4 k (Connect to +5 V) Load capacity 200 pF (Connect to GND)
I2C BUS Control Signal
SDA tBUF SCL tSU;STA tSU;DAT Sr tSU;STO P tR tF tHD;STA
P
S tHD;STA
tLOW
tHD;DAT
tHIGH
--16--
C1 15n
48
BASSL2 TRER TREL SURRIN SURROUT LSOUT-R LSOUT-L NC SDA SCL DGND SAD MAININ MAINOUT NC PCINT1 PCINT2 PLINT COMPIN VGR IREF GND SAPTC VCC
C2
47
6.8n C4
46
6.8n C5
45
4.7 C8
4.7 C10
SIGNAL GENERATOR
4.7 C12
4.7
41
V3
AC
R1
220 R2 220
C24
18 31
1 C26
19 30
4.7 C28
20 29
10 R9 62k METAL 1%
GND VCC 9V V7 GND
C31 4.7 C33 100
Electrical Characteristics Measurement Circuit
--17--
1 2 3 4
BASSL1 BASSR2 BASSR1 SURRTC TVOUT-L TVOUT-R AUX2-L AUX2-R AUX1-L AUX1-R VLTC VLDC VCAWGT VCATC VCAIN VEOUT VETC VEWGT VE SAPIN SAPOUT NOISETC STIN SUBOUT
C3 15n
C6 0.022 4.7
44
AC
GENERATOR
V1 SIGNAL
GND GND GND
5 6 7 8 9
10
C7 4.7
43 42 40 39
C9 4.7 C11 4.7 C13 4.7 C14 4.7 C15 4.7
AC AC
V2 V4
SIGNAL SIGNAL GENERATOR GENERATOR
I2C BUS DATA
5600p C22 R5 100k 0.012
AC
V5 SIGNAL
11 12 13 C18
C21 R6 1MEG
38 37 36
GENERATOR
1MEG
C16
R3
1
4.7
R4
C17 3.9k 10 C19
TANTALUM
14 15 16 17
35 34 33 32
S7 S6 S5 S4 S3 S2 S1
C20
C23
BUFF
TANTALUM
0.047 R7 C25 3k 2700P R8 C27 3.3k
4.7
3.3
FILTERS
15kHz LPF fHBPF 1kHz BPF
AC
GENERATOR
V1 SIGNAL
C29
4.7
MEASURES
21 22 23 24
28 27 26 25
4.7 C30
C32 4.7
A
CXA2054S
CXA2054S
I2C BUS Register Data Standard Setting Values Number Classifi- Standard Setting value when electrical Contents of bit cation setting characteristics are measured ATT 4 A 9 VCO 6 A 1F FILTER 6 A 1F Center point Adjustment point SPECTRAL 6 A 1F WIDEBAND 6 A 1F TEST-DA 1 T 0 TEST1 1 T 0 Normal mode FST 1 T 0 PR-VOL 4 U F F=0 dB VOL-L 6 U 3F 3 F=0 dB VOL-R 6 U 3F 3 F=0 dB VOL-SURR 6 U 3F 3 F=0 dB TREBLE 4 U 8 7 or 8=0 dB BASS 4 U 8 7 or 8=0 dB NRSW 1 U -- According to the modecontrol table FOMO 1 U -- FEXT1 1 U 0 AUX1 forced MONO OFF FEXT2 1 U 0 AUX2 forced MONO OFF VL 1 U 0 VL OFF SURR 1 U 0 Surround OFF SURRSW 1 U 0 Internal mode selection EXT1 1 U 0 TV decoder output selection EXT2 1 U 0 M1 1 U 1 Mute OFF M2 1 U 1 ATTSW 1 S -- Fixed by the set specifications SAPC 1 S -- Register Classification A: U: S: T: Adjustment User control Proper to set Test
--18--
CXA2054S
List of Adjustment Contents
Adjustment item 1 MAIN VCA 2 3 ST & SAP VCO ST & SAP & dbx FILTER Low frequency 4 ST separation High frequency ST separation Adjustment data ATT VCO FILTER WIDEBAND SPECTRAL Input pin Input signal data Measurement TVOUT-L TVOUT-R STA5 TVOUT-R output level TVOUT-R output level Adjustment contents Adjust as close to 490 mVrms as possible Adjust as close to Adjust to the center of the FILADJ=1 condition Minimize the output level Minimize the output level TEST-DA=1 TEST1=1 Test mode setting
COMPIN 100 Hz (Pin 19) None
245 mVrms output level None
output frequency 62.936 kHz as possible
COMPIN 9.4 kHz (Pin 19) (Pin 19) (Pin 19) COMPIN ST-L 30 % 300 Hz 3 kHz COMPIN ST-L 30 %
600 mVrms (FILADJ)
--19--
CXA2054S
Adjustment Method (Adjust this through Tuner and IF when this IC is mounted on the set.) 1. ATT adjustment 1) TEST BIT is set to "TEST1=0" and "TEST-DA=0". 2) Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then, adjust the "ATT" data for ATT adjustment so that the TVOUT-L output goes to the standard value (490mVrms). 3) Adjustment range : 30 % Adjustment bits : 4 bits 2. Stereo, SAP VCO adjustment 1) TEST BIT is set to "TEST1=0" and "TEST-DA=1". 2) Monitor the TVOUT-R output (4 fH free running) frequency in a no input state, and adjust "VCO" adjustment data so that this frequency is as close to 4 fH (62.936 kHz) as possible. 3) Adjustment range : 20 % Adjustment bits : 6 bits 3. Stereo, SAP, dbx filter adjustment 1) TEST BIT is set to "TEST1=1" and "TEST-DA=0". 2) Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA5) condition, adjust the "FILTER" adjustment data. 3) Adjustment range : 20 % Adjustment bits : 6 bits Align with the center of the STA5=1 (adjustment OK) condition range.
Adjustment point Control data "FILTER"
0 1 0
3F
Measurement data STA5 "FILTER"
4. Separation adjustment 1) TEST BIT is set to "TEST1=0" and "TEST-DA=0". 2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30 %, frequency 300 Hz NR-ON) to COMPIN. At this time, adjust the "WIDEBAND" adjustment data to reduce TVOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3 kHz and adjust the "SPECTRAL" adjustment data to reduce TVOUT-R output to the minimum. 4) Then, the adjustments in 2 and 3 above are performed to optimize the separation. 5) "WIDEBAND" "SPECTRAL" Adjustment range : 30 % Adjustment range: 15 % Adjustment bits : 6 bits Adjustment bits: 6 bits
--20--
CXA2054S
Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV kHz 50 AM-DSB-SC 50
25
25
L-R dbx-TV BR
PILOT
15 SAP dbx-TV NR FM 10kHz 50-10kHz 2fH 3fH 4fH 5fH TELEMETRY FM 3kHz 3 6fH 6.5fH f
L+R 50-15KHZ
5
fH
fH=15.734kHz
Fig. 1. Base band spectrum
PLL (VCO 8fH) (COMPIN) 19 MVCA STEREO LPF PILOT CANCEL 2fHL0 fHL90 fHL0 PILOT DET I2C BUS DECODER MODE CONTROL (MAIN OUT) 14 L+R L-R (DSB) DET 4.7 MATRIX (Lch) NR SW (MAIN IN) 13
MAIN LPF DE.EM
SUB LPF WIDEBAND (SUBOUT) (STIN) SUBVCA 25 L-R 4.7 SAP BPF SAP (FM) SAP LPF DET INJ. LOCK NOISE DET SAP DET (SAP OUT) 28 (SAP IN) I2C BUS DECODER 4.7 29 26
A
dbx-TV BLOCK
B
(Rch)
TO SW
I2C BUS DECODER MODE CONTROL
MODE CONTROL
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
(STIN) 26 NR SW
FIXED DEEMPHASIS VARIABLE DEEMPHASIS
A
(VE OUT) (VCAIN) 33 34 4.7 VCA
B
TO MATRIX
29 (SAPIN) LPF
HPF RMS DET LPF RMS DET
Fig 3. dbx-TV block --21--
CXA2054S
(TVOUT-L) (TVOUT-R)
44
43
(AUX2-L) (AUX2-R)
(LSOUT-L) 41 40 BASS TREBLE VOL-L
7
(LSOUT-R)
(AUX1-L) 40 SW1 39 (AUX1-R) (Lch) (Rch) from MATRIX SW2 VOLLIM PREVOL
SURROUND
VOL-R
6
(SURROUT)
SW3
VOL-S
5
4
(SURRIN)
Fig. 4. Sound processor block (1) L+R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 19) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L-R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (deemphasized) and input to the matrix. (2) L-R (SUB) The L-R signal follows the same course as L+R before the pilot signal is canceled. L-R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L-R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L-R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5 fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 28 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5 fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25 kHz after FM detection of SAP signal. (5) dbx-TV block Either the SAP signal or L-R signal input respectively from ST IN (Pin 26) or SAP IN (Pin 29) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix.
--22--
CXA2054S
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix, SW1, SW2 The signals (L+R, L-R, SAP) input to "MATRIX" become the outputs for the ST-L, ST-R, MONO and SAP signals according to the BUS data and whether there is ST/SAP discrimination. "SW1" switch the "MATRIX" output signal, external input signal (input to AUX1-L, R (Pins 40 and 39)) and external forced MONO. "SW2" switch the "SW1" output signal, external input signal (input to AUX2-L, R (Pins 42 and 41)) and external forced MONO. (7) Sound processor block The sound processor block contains "VOLUME LIMITER", "PREVOL", "BASS/TREBLE" tone control functions, "SURROUND" (quasi-surround function) and "VOLUME". VL : 250 mVrms (limit level) BASS : 12 dB (1.7 dB/STEP at 100 Hz) TREBLE : 12 dB (1.7 dB/STEP at 10 kHz) VOLUME : 0 to -80 dB (-1.25 dB/STEP) * Prevolume "PREVOL" controls the input signal level of the sound processor block. When turning on the bass boost, treble boost or surround, attenuate the input signal to the sound processor block using "PREVOL" so that the signal is not dissipated inside the processor. PR-VOL : 0 to -13.75 dB (-1.25 dB/STEP) * Surround At "SURROUND", the L and R differential components are phase-shifted and these components are added to the left and right channels. When surround is OFF (SURR=0) Inputs are output as is. Lout=Lin Rout=Rin
{
When surround is ON (SURR=1) 1-jRC Lout=Lin - (Lin-Rin) 1+jRC 1-jRC Rout=Rin + (Lin-Rin) 1+jRC
{
{ C=0.022 F (Externally attached to Pin 45)
(Lin, Lout) and (Rin, Rout) indicate the left- and right- channel I/O of the surround circuit.
R=24 k (IC on-chip)
--23--
CXA2054S
(8) Others "MVCA" is a VCA which adjusts the input signal level to the standard level of this IC. "Bias" supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 21) with GND become the reference current. Standard input and output levels Input pin Pin No. COMPIN 19 AUX1-L/AUX1-R 40/39 AUX2-L/AUX2-R 42/41 SURRIN 4 1 2 3 4
Input level 245 mVrms 1 490 mVrms 490 mVrms 490 mVrms
TVOUT output level 490 mVrms 2 490 mVrms -- --
LSOUT output level 3 490 mVrms 2 490 mVrms 490 mVrms 490 mVrms 4
MONO, 25 kHz Deviation, Pre-Em. off MONO, 25 kHz Deviation, Pre-Em. on VOLUME MAX, PREVOL MAX, BASS & TREBLE CENTER, SURROUND OFF, VL OFF Only SURROUT output
--24--
CXA2054S
Register Specifications Slave address SAD pin GND VCC Register table SUB ADDRESS MSB LSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 DATA BIT7 EXT1 BIT6 BIT5 TEST-DA BIT4 TEST1 BIT3 BIT2 ATT (4) BIT1 BIT0 SLAVE RECEIVER 80 H 8 AH SLAVE TRANSMITTER 81 H 8 BH
EXT2 VL
VCO (6) FILTER (6) SPECTRAL (6) WIDEBAND (6) M2 NRSW FOMO SAPC ATTSW SURRSW FST FEXT1 SURR PR-VOL (4) VOL-L (6) VOL-R (6) VOL-SURR (6) TREBLE (4) BASS (4)
M1 FEXT2
: Don't care
Status Registers When TEST1=0 STA1 BIT7 POWER ON RESET When TEST1=1 STA1 BIT7 POWER ON RESET STA2 BIT6 STEREO STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 FILADJ STA6 BIT2 -- STA7 BIT1 -- STA8 BIT0 -- STA2 BIT6 STEREO STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 -- STA6 BIT2 -- STA7 BIT1 -- STA8 BIT0 --
--25--
CXA2054S
Description of Registers Control registers Number of bits Classification Contents 4 A Input level adjustment STEREO VCO and SAP VCO free running frequency VCO 6 A adjustment FILTER 6 A STEREO, SAP and dbx filter adjustment SPECTRAL 6 A Adjustment of stereo separation (3 kHz) WIDEBAND 6 A Adjustment of stereo separation (300 Hz) Turn to DAC test mode and STVCO adjustment mode by TEST-DA 1 T means of TEST-DA=1. Turn to test mode by means of TEST=1. TEST1 1 T (Adjustment of FILTER) FST 1 T Turn to forced stereo by means of FST=1. PR-VOL 4 U Input signal level control of sound processor block VOL-L 6 U LSOUT-L output signal level control VOL-R 6 U LSOUT-R output signal level control VOL-SURR 6 U SURROUT output signal level control TREBLE 4 U LSOUT output treble control BASS 4 U LSOUT output bass control NRSW 1 U Selection of the output signal (Stereo mode, SAP mode) Turn to forced MONO by means of FOMO=1. FOMO 1 U (Left channel only is MONO during SAP output.) FEXT1 1 U External input 1 forced MONO (1 : forced MONO ON) FEXT2 1 U External input 2 forced MONO (1 : forced MONO ON) VL 1 U Selection of volume limiter function ON/OFF (0 : OFF, 1 : ON) SURR 1 U Selection of quasi-surround function ON/OFF (0 : OFF, 1 : ON) SURRSW 1 U Selection of internal or external mode for SURROUT output Selection of TV mode or external input mode for TVOUT EXT1 1 U output Selection of internal mode or external input mode for LSOUT EXT2 1 U output Selection of TVOUT mute ON/OFF M1 1 U (0 : mute ON, 1 : mute OFF) Selection of LSOUT mute ON/OFF M2 1 U (0 : mute ON, 1 : mute OFF) ATTSW 1 S Turn the input stage MVCA off when ATTSW=1. Selection of SAP mode or L+R mode according to the SAPC 1 S presence of SAP broadcasting Classification U : U: S: T: User control Adjustment Proper to set Test --26-- Register ATT
CXA2054S
Status registers Register PONRES STEREO SAP NOISE FILADJ Number of bits 1 1 1 1 1 Contents POWER ON RESET detection; Stereo discrimination of the COMPIN input signal; SAP discrimination of the COMPIN input signal; Noise level discrimination of the SAP signal; Status of FILTER adjustment; 1 : RESET 1 : Stereo 1 : SAP 1 : Noise 1 : OK range
Description of Control Registers ATT (4) : Adjust the signal level input to COMPIN (Pin 19) to the standard input level. Variable range of the input signal : 245 mVrms -5.0 dB to +3.0 dB 0 = Level min. F = Level max. VCO (6) : Adjust STEREO & SAP VCO free running frequency (fo). Variable range : fo 20 % 0 = Free running frequency min. 3F = Free running frequency max. Adjust the filter fo of the ST, SAP and dbx blocks. Variable range : fo 20 % 0 = Frequency min. 3F = Frequency max. Perform high frequency (fs=3 kHz) separation adjustment. 0 = Level max. 3F = Level min. Perform low frequency (fs=300 Hz) separation adjustment. 0 = Level min. 3F = Level max. Set DAC output test mode and VCO adjustment mode. 0 = Normal mode 1 = DAC output test mode and STVCO adjustment mode In addition, the following outputs are present at Pins 44 and 43. TVOUT-L (Pin 44) : DA control DC level TVOUT-R (Pin 43) : STEREO VCO oscillation frequency (4fH) Set filter adjustment mode. 0 = Normal mode 1 = FILTER (STA5) adjustment mode In addition, the following outputs are present at Pins 44 and 43. TVOUT-L (Pin 44) : SAP BPF OUT TVOUT-R (Pin 43) : NR BPF OUT
FILTER (6) :
SPECTRAL (6) :
WIDEBAND (6) :
TEST-DA (1) :
TEST1 (1) :
--27--
CXA2054S
FST (1) :
Select forced STEREO mode 0 = Normal mode 1 = Forced stereo mode Input signal level control of sound processor block When turning on the bass boost, treble boost or surround, attenuate the input signal to the sound processor block using "PR-VOL" so that the signal is not dissipated inside the processor. 4 = Volume Min. (-13.75 dB) F = Volume Max. (0 dB) -1.25 dB/STEP LSOUT-L output signal level control 0 = Volume Min. (-80 dB) 3F = Volume Max. (0 dB) -1.25 dB/STEP LSOUT-R output signal level control 0 = Volume Min. (-80 dB) 3F = Volume Max. (0 dB) -1.25 dB/STEP SURROUT output signal level control 0 = Volume Min. (-80 dB) 3F = Volume Max. (0 dB) -1.25 dB/STEP LSOUT output treble control 0 = Treble Min. 7 & 8 = Treble Center (0 dB) F = Treble Max. LSOUT output bass control 0 = Bass Min. 7 & 8 = Bass Center (0 dB) F = Bass Max. Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode
PR-VOL (4) :
VOL-L (6) :
VOL-R (6) :
VOL-SURR (6) :
TREBLE (4) :
BASS (4) :
NRSW (1) :
FOMO (1) :
--28--
CXA2054S
FEX1 (1) :
Turn external input [1] to forced MONO. 0 = Normal mode 1 = External input [1] is forced MONO. Input the same signal to both AUX1-L and AUX1-R. Turn external input [2] to forced MONO. 0 = Normal mode 1 = External input [2] is forced MONO. Input the same signal to both AUX2-L and AUX2-R. Volume limiter function selection 0 = Volume limiter OFF 1 = Volume limiter ON Surround function selection 0 = Surround OFF 1 = Surround ON Select INT mode or EXT mode for SURROUT output 0 = INT mode 1 = EXT mode Select TV mode or external input mode for TVOUT output. 0 = TV mode 1 = External input mode Select internal mode or external input mode for LSOUT output. 0 = internal mode 1 = External input mode Mute the TVOUT-L and TVOUT-R output. 0 = Mute ON 1 = Mute OFF Mute the LSOUT-L and LSOUT-R output. 0 = Mute ON 1 = Mute OFF Select BYPASS SW of Main VCA 0 = Normal mode 1 = Main VCA is passed Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L+R output is selected 1 = SAP output is selected --29--
FEX2 (1) :
VL (1) :
SURR (1) :
SURRSW (1) :
EXT1 (1) :
EXT2 (1) :
M1 (1) :
M2 (1) :
ATTSW (1) :
SAPC (1) :
CXA2054S
Description of Mode Control Priority ranking : M1/M2 > EXT1/EXT2 > TEST-DA > TEST1 > (NRSW & FOMO & SAPC) Mode control SAPC=0 "Select dbx input and TV decoder output" Conditions : FOMO = 0 NRSW=0 (MONO or ST output) left channel: right channel: * During other input : left channel: right channel: * During ST input : L, R L+R, L+R SAPC=1 "Select dbx input and TV decoder output" Conditions : FOMO = 0 NRSW=0 (MONO or ST output) As on the left
NRSW
NRSW=1 (SAP output) NRSW = 1 (SAP output) * When there is "SAP" during * Regardless of the presence of SAP SAPdiscrimination discrimination, dbx input : "SAP" -left channel : SAP, right channel : SAP left channel : SAP, right channel : SAP * When there is "No SAP", output is the However, when there is no SAP, SAPOUT same as when NRSW=0. output is soft muted (-7 dB) "Forced MONO" FOMO FOMO=1 * During SAP output: left channel : L+R, right channel : SAP * During ST or MONO output: left channel : L+R, right channel : L+R Change the selection conditions for "MONO or ST output" and "SAP output". SAPC=0 : Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC=1 : Switch to SAP output regardless of whether there is SAP discrimination. "MUTE" M1=0 : TVOUT output is muted. M2=0 : LSOUT output is muted. "TV mode/external input mode selection" EXT1=0 : Set TVOUT output to TV mode. EXT1=1 : Set TVOUT output to external input [1] mode. EXT2=0 : Set LSOUT output to internal mode. EXT2=1 : Set LSOUT output to external input [2] mode. "TEST1" TEST1=1 Return adjustment data with STATUS REGISTER as an adjustment mode. In addition, outputs are as follows. left channel : SAP BPF OUT right channel : NR BPF OUT "TEST-DA" TEST-DA=1 Used to adjust the D/A TEST and STVCO. left channel : D/A output right channel : STVCO oscillation frequency (4fH) --30--
SAPC
M1/M2
EXT1/EXT2
TEST1
TEST-DA
CXA2054S
Decoder Output and Mode Control Table 1 (SAPC=1) Input signal mode ST 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 Mode detection SAP NOISE 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 Mode control NRSW FOMO SAPC 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 dbx input MUTE SAP SAP MUTE (SAP) (SAP) L-R MUTE L-R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L-R MUTE SAP SAP (SAP) (SAP) Output Lch Rch L+R L+R SAP SAP L+R SAP L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP)
MONO 1)
STEREO 1)
MONO & SAP
STEREO & SAP
Note (SAP) :
The SAPOUT output signal is soft muted (approximately -7 dB). The signal is soft muted when NOISE=1. : Don't care. 1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
--31--
CXA2054S
Decoder Output and Mode Control Table 2 (SAPC=0) Input signal mode ST 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Mode detection SAP NOISE 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 Mode control NRSW FOMO SAPC 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 dbx input MUTE MUTE MUTE (SAP) (SAP) L-R MUTE L-R MUTE L-R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE (SAP) (SAP) L-R MUTE SAP SAP L-R MUTE (SAP) (SAP) Output Lch Rch L+R L+R L+R L+R L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R L R L+R L+R (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP L+R L+R L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R SAP SAP L+R SAP L R L+R L+R SAP (SAP) L+R (SAP)
MONO 1)
STEREO 1)
MONO & SAP
STEREO & SAP
Note (SAP) :
The SAPOUT output signal is soft muted (approximately -7 dB). The signal is soft muted when NOISE=1. : Don't care. 1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
--32--
CXA2054S
Mode Control Table 3
EXT1 EXT2 FEXT1 FEXT2 0 0 * 1 0 0 1 0 1 1 0 M1 1 1 1 1 M2 1 1 1 1 TV OUT-L TV-L AUX1-L AUX1-L Selected according to the EXT1, FEXT1 conditions Selected according to the EXT1, FEXT1 conditions MUTE TV OUT-R TV-R AUX1-R AUX1-L Selected according to the EXT1,FEXT1, conditions Selected according to the EXT1,FEXT1, conditions MUTE LS OUT-L TV-L AUX1-L AUX1-L AUX2-L LS OUT-R TV-R AUX1-R AUX1-L AUX2-R
1
1
1
1
AUX2-L
AUX2-L

0
1
Selected according to Selected according to the EXT2, FEXT2, the EXT2, FEXT2, conditions conditions MUTE

1
0
Selected according to Selected according to the EXT1, FEXT1 the EXT1,FEXT1, MUTE conditions conditions
TV-L/TV-R are selected in Matrix. TV-L : MONO, ST-L, SAP (SAPBFout, D/A out) TV-R : MONO, ST-R, SAP (NRBPFout, STVCO free run (4fH))
I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal. * Accordingly there are 3 values outputs, H, L and HIZ.
H
L
HIZ
L
* I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S SDA Stop Condition P
SCL
--33--
CXA2054S
* I2C data Write (Write from I2C controller to the IC)
L during Write SDA MSB HIZ MSB LSB HIZ
SCL 1 S Address MSB LSB HIZ HIZ ACK Sub Address ACK 2 3 4 5 6 7 8 9 1 8 9
1 DATA (n)
8
9 ACK
1 DATA (n+1)
8
9 ACK DATA (n+2)
HIZ
HIZ
8 DATA
9 ACK
1 DATA
8
9 ACK P
Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically.
* I2C data Read (Read from the IC to I2C controller)
H during Read SDA HIZ
SCL 1 S 6 Address 7 8 9 ACK 1 7 DATA 8 9 ACK P
* Read timing
MSB IC output SDA LSB
SCL
9
1
2
3
4
5
6
7
8
9
Reat timing ACK DATA ACK
Data Read is performed during SCL rise. --34--
CXA2054S
Input level vs. Distortion characteristics 1 (MONO)
Input signal : MONO (Pre-emphasis on), 1kHz 0dB=100% modulation level VCC=9V, 30kHz using LPF Measurement point : TVOUT-L/R
Input level vs. Distortion characteristics 2 (Stereo)
Input signal : Stereo L=-R (dbx-TVNR ON), 1kHz 0dB=100% modulation level VCC=9V, 30kHz using LPF, ST mode Measurement point : TVOUT-L/R
1.0
10
Distortion (%)
0.1
Standard level (100%) -10 0 Input level (dB) 10 Standard level (100%) -10 0 Input level (dB) 10
Input level vs. Distortion characteristics 3 (SAP)
Input signal : SAP (dbx-TVNR ON) 1kHz, 0dB=100% modulation level VCC=9V, 30kHz using LPF, SAP mode Measurement point : TVOUT-L/R
10
Distortion (%)
1.0
Standard level (100%)
-10
0 Input level (dB)
10
--35--
Distortion (%)
1.0
CXA2054S
Stereo LPF frequency characteristics
10
5
Gain (dB)
0
-5
-10 0 20 40 60 80 100
Frequency (kHz)
Main LPF and Sub LPF frequency characteristics
30
Gain (FC main and FC sub) (dB)
20 10 0 -10 -20 -30 -40 -50 1 2 5 7 10 20 50 70 100 Frequency (kHz)
SAP frequency characteristics and group delay
100 20 5fH 10 Gain 90 80
Gain (dB)
60 0 50 40 -10 Group delay 3.8 fH 20 40 60 80 Frequency (kHz) 6.2fH 100 0 120 30 20 -20 10
--36--
Group delay (s)
70
CXA2054S
BASS - TREBLE characteristics
BASS.MAX +12 TREBLE.MAX
+8
Boost amount (dB)
+4
0
-4
-8
-12 BASS. MIN 20 100 1k Frequency (Hz) TREBLE.MIN 10k 20k
Input : AUXIN (Pins 40/39 and 42/41) 245 mVrms Output : LSOUT (PINS 5, 6 and 7)
Volume characteristics
0
-20
LSOUT output level (dB)
-40
-60
-80
Input : AUXIN (Pins 40/39 and 42/41) 1kHz, 490mVrms Output : LSOUT (Pins 5, 6 and 7)
-100 0 F 1F 2F 3F Control data VOL-L, VCL-R, VOL-SURR
Volume limiter characteristics
500
100
OUT (mVrms)
10
10-2
10-1 IN (Vrms)
1
--37--
CXA2054S
Package Outline
Unit : mm
48PIN SDIP (PLASTIC)
+ 0.1 5 0.0 0.25 -
25
+ 0.4 43.2 - 0.1 48
15.24 + 0.3 13.0 - 0.1
0 to 15
1 1.778
24
0.5 0.1 0.9 0.15
Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 5.1g
SONY CODE EIAJ CODE JEDEC CODE
SDIP-48P-02 SDIP048-P-0600
--38--
3.0 MIN
LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
+ 0.4 4.6 - 0.1
0.5 MIN

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