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CXD2453Q
Timing Generator for LCD Panels For the availability of this product, please contact the sales office.
Description The CXD2453Q is a timing signal generator for driving the LCX017AL and LCX023AL LCD panels. This chip outputs timing signals which support XGA signals (1024 x 768 dots) and S-XGA signals (1280 x 1024 dots). Features * Supports various XGA signals (1024 x 768 dots) having horizontal scanning frequencies of 44-69kHz and vertical scanning frequencies of 55 to 85Hz. * Supports S-XGA (1280 x 1024 dots) pulse eliminator (horizontal scanning frequency of 69kHz or less). * Controls the sample-and-hold position of the CXA2112R sample-and-hold driver. * Line inversion and field inversion signal generation * AC drive of LCD panels during no signal. Applications LCD projectors, etc. Structure Silicon gate CMOS IC Note: Company names and product names, etc. contains in these materials are the trademarks or registered trademarks of the respective companies. 80 pin QFP (Plastic)
Absolute Maximum Ratings (VSS = 0V) * Supply voltage VDD VSS - 0.5 to +4.0 * Input voltage VI (3.3V input pin) VSS - 0.5 to VDD + 0.5 (5.0V input pin) VSS - 0.5 to VDD + 2.5 * Output voltage VO VSS - 0.5 to VDD + 0.5 * Storage temperature Tstg -55 to +125
V V V V C
Recommended Operating Conditions * Supply voltage VDD +3.0 to +3.6 * Operating temperature Topr -20 to +75
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97425B7Y-PS
CXD2453Q
Block Diagram
SLCK1
CKI2
SLCK2
30
XCKI1
CKI3
XCKI3
CKI1
3
4
26
11
21
22
13
CKI4
XCLR 78
Direct Clear Master Clock (Main) Master Clock (Sub)
9 34 35 36 74
TST2 TST7 TST8 TST9 TST11 TST12 TST13
TST5
24
VSYNC 28 HSYNC 29
SYNC DETECTOR
AUX V COUNTER
75 76
SLHR 17 HRET 38 IRACT 69 PLL COUNTER
V POSITION COUNTER
43
BLK
19 V TIMING GENERATOR H POSITION COUNTER 41 44 45
SLFR VCK VST FRP
1 15 CLP1 39 CLP2 40 LINE CONTROLLER 16 27
TST1 TST3 TST4 TST6
72 TST10 79 H TIMING GENERATOR 80 67 ADDITIONAL PULSE GENERATOR 68 TST14 TST15 XVS XHS
ENB 47 PRG 48 PCG 49
HCK1 51 HCK2 53 HST 55
70 ORACT
SCLK SDAT SCTL
6 7 8 SERIAL DATA I/F
18 32 33 46
VDD VDD VDD VDD
73 VDD
56 57 58 59 60 61 62 64 65 66
2
5 10 12 14 20 23 25 31 37 42 50 52 54 63 71 77
SHPA
HB
Vss
INV
Vss
Vss
Vss
VB
Vss
SHPD
RGT
Vss
Vss
Vss
SHPC
XRGT
Vss
Vss
SHPB
DWN
Vss
Vss
Vss
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Vss
Vss
Vss
Vss
CXD2453Q
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol TST1 VSS CKI1 XCKI1 VSS SCLK SDAT SCTL TST2 VSS CKI2 VSS CKI4 VSS TST3 TST4 SLHR VDD SLFR VSS CKI3 XCKI3 VSS TST5 VSS SLCK1 TST6 VSYNC HSYNC SLCK2 VSS VDD VDD TST7 TST8 TST9 I/O -- -- I -- I I I -- -- I -- I -- -- -- I -- I -- I -- -- -- I -- I I I -- -- -- -- -- -- Test pin (Not connected.) GND Master clock input 1 (differential) GND Serial data clock input Serial data input Serial data control signal input Test pin (connect to GND) GND Master clock input 2 GND Master clock input 4 GND Test pin (Not connected.) Test pin (Not connected.) Reset by HSYNC of PLL counter (High: Disabled, Low: Enabled) Power supply FRP polarity inversion cycle selection (High: Field inversion, Low: Line inversion) GND Master clock input 3 (differential) GND Test pin (Not connected.) GND Clock input selection 1 (High: CKI2, Low: CKI1) Test pin (Not connected.) Vertical sync signal input Horizontal sync signal input Clock input selection 2 (High: CKI4, Low: CKI3) GND Power supply Power supply Test pin (connect to VDD) Test pin (connect to VDD) Test pin (connect to VDD) -3- Description Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- L -- -- -- -- -- L -- -- -- L -- -- -- -- -- --
CXD2453Q
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Symbol VSS HRET CLP1 CLP2 VCK VSS BLK VST FRP VDD ENB PRG PCG VSS HCK1 VSS HCK2 VSS HST SHPA SHPB SHPC SHPD INV VB HB VSS DWN XRGT RGT XVS XHS IRACT ORACT VSS TST10
I/O -- O O O O -- O O O -- O O O -- O -- O -- O O O O O O O O -- O O O O O O O -- -- GND
Description
Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Phase comparison pulse output Pedestal clamp pulse 1 output Pedestal clamp pulse 2 output V clock pulse output GND BLK pulse output V start pulse output AC drive inversion pulse output Power supply ENB pulse output PRG pulse output PCG pulse output GND H clock 1 pulse output GND H clock 2 pulse output GND H start pulse output External sample-and-hold driver control signal output External sample-and-hold driver control signal output External sample-and-hold driver control signal output External sample-and-hold driver control signal output External sample-and-hold driver control signal output VB signal output HB signal output GND Up/down inversion signal output Left/right inversion signal (reverse polarity) output Left/right inversion signal output Auxiliary pulse output Auxiliary pulse output Auxiliary pulse output Auxiliary pulse output GND Test pin (Not connected.)
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CXD2453Q
Pin No. 73 74 75 76 77 78 79 80
Symbol VDD TST11 TST12 TST13 VSS XCLR TST14 TST15
I/O -- -- -- -- -- I -- -- Power supply Test pin (connect to VDD) Test pin (connect to VDD) Test pin (connect to VDD) GND System clear (Low: All clear) Test pin (Not connected.) Test pin (Not connected.)
Description
Input pin for open status -- -- -- -- -- H -- -- H: Pull-up, L: Pull-down
Electrical Characteristics * DC characteristics Item Supply voltage Input voltage 1 Input voltage 2 Symbol VDD VIH1 VIL1 VIH2 VIL2 Input voltage 3 VIH3 VIL3 VC (center level) VIH41 VIL41 Output voltage 1 VOH VOL VOH VOL VOH VOL IOH = -4mA IOL = 4mA IOH = -8mA IOL = 8mA IOH = -12mA IOL = 12mA Pull-up VI = 0V Pull-down VI = VDD Master clock = 95MHz VDD = 3.3V Output load = 30pF Conditions -- 3.3V CMOS input Min. 3.0 0.65VDD VSS 0.65VDD VSS 0.8VDD VSS (VDD x 0.606) - 0.1 VIL4 + 0.3 VSS VDD - 0.5 VSS VDD - 0.5 VSS VDD - 0.5 VSS 25 Typ. 3.3 -- -- -- -- -- -- VDD x 0.606 -- -- -- -- -- -- -- -- 50
(Topr = -20 to +75C, VSS = 0V) Max. 3.6 VDD 0.25VDD VDD + 1.9 0.25VDD VDD + 1.9 0.2VDD (VDD x 0.606) + 0.1 VDD VIH4 - 0.3 VDD 0.4 VDD 0.4 VDD 0.4 200 k VCK, BLK, VST, ENB, PCG HCK1, HCK2, HST SLHR, XCLR SLFR, SLCK1/2 mA -- 2 V Unit Applicable pins -- SLHR, SLFR, XCLR, SLCK1/2 CKI2, CKI4 SCLK, SDAT, SCTL, VSYNC, HSYNC
5.0V CMOS input 5.0V CMOS Schmitt trigger input
Input voltage 4
Low amplitude differential input
CKI1/XCKI1, CKI3/XCKI3
Output voltage 2
Output voltage 3
Input pull-up/pullRP down resistance Current consumption IDD
--
--
40
1 VIH4 > (max. value of VC) and VIL4 < (min. value of VC) 2 Output pins other than those indicated in items output voltage 2 and output voltage 3. -5-
CXD2453Q
* AC characteristics Item Clock input cycle Symbol --
(Topr = -20 to +75C, VDD = 3.3V 0.3V, VSS = 0V) Applicable pins CKI1/XCKI1, CKI3/XCKI3 CKI2, CKI4 Conditions -- -- Min. 10.5 10.5 Typ. -- -- Max. -- -- Unit
Output rise/fall delay time Output rise/fall delay time Output rise/fall delay time Cross-point time difference Duty ratio Timing Definitions
tpr/tpf tpr/tpf tpr/tpf
t
HCK1, HCK2, HST CL = 90pF ns VCK, BLK, VST, ENB, PCG Other output pins HCK1, HCK2 HCK1, HCK2 CL = 50pF CL = 30pF CL = 90pF CL = 90pF -5 48 -- 50 5 52 % -- -- 25
tH/ (tH + tL)
VDD CKI1, CKI2, CKI3, CKI4 50% 0V VDD Output 50% 0V tpr VDD Output 50% 0V tpf
VDD HCK1 50% 50% 0V VDD HCK2 t 50% t 50% 0V
tH
tL
HCK1, HCK2
50%
50%
50%
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CXD2453Q
Serial Interface AC Characteristics Item SCTL setup time with respect to rise of SCLK SCTL hold time with respect to rise of SCLK SDAT setup time with respect to rise of SCLK SDAT hold time with respect to rise of SCLK SCLK pulse width 3 T: Master clock cycle (ns)
(Topr = -20 to +75C, VDD = 3.3V 0.3V, VSS = 0V) Symbol Min. 8T3 8T 4T 4T 4T Typ. -- -- -- -- -- Max. -- -- -- -- --
ts0 th0 ts1 th1 tw1
Timing Definitions
ts0 SCTL 50% tw1 SCLK 50% ts1 SDAT 50% (D15) th1 50% (D0) tw1 50% th0 50%
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LCD Panel Dot Arrangement
The dot arrangement of the LCD panel (LCX017AL) driven with this IC is shown below. The dot arrangement is a square arrangement. The shaded region in the diagram is not displayed.
Gate SW Gate SW
Photo-shielding area Display area
768 dots
1024 dots 1032 dots 4 dots
2 dots 2 dots 772 dots
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CXD2453Q
4 dots
CXD2453Q
Description of Operation * Sync signal input pins (HSYNC, VSYNC) Horizontal and vertical separate SYNC signals are input to the HSYNC (Pin 29) and VSYNC (Pin 28). The sync signals are compatible with both positive and negative polarity according to serial data settings. (Refer to the section on serial data interface for details regarding serial data.) The CXD2453Q supports signals which are shown in the following table. Effective dots 1024 x 768 (XGA) 1280 x 1024 (S-XGA) Horizontal scanning Vertical scanning frequency frequency 44kHz to 69kHz 69kHz 55Hz to 85Hz Roughly 65Hz Scanning line conversion from 1024 to 768 vertical lines Remarks
In the case of signals defined by special protocols that do not satisfy the conditions in the diagram below, it may not be possible to obtain a complete display even for the above signals when the image display position is properly set on the LCD panel. This IC does not support interlace signals.
Image display period HSYNC ENB PCG Min. 0.72s Min. 0.17s Horizontal blanking period Image display period
* Master clock input pins (CKI1/XCKI1, CKI2, CKI3/XCKI3, CKI4) and Clock Selection Pins (SLCK1, SLCK2) Since this IC does not contain a built-in phase comparator, phase comparison is performed externally and a divided clock is input. The 1/N (N is the clock number during 1 horizontal period) frequency divider output is output from the HRET (Pin 38) for the external phase comparator. The clock input pin consists of two channels for small amplitude differential input (center level: 2.0V, amplitude: 0.4V), and two channels for CMOS level input for a total of four channels. These are selected according to the SLCK1 (Pin 26), SLCK2 (Pin 30) and serial data. (1) During normal operation (serial data SLLAP = 0) All internal circuits of the IC operate with CKI1 or CKI2. CKI1/XCKI1 are selected when SLCK1 = L (Pins 3/4, small amplitude differential input), and CKI2 is selected when SLCK1 = H (Pin 11, CMOS level input). (2) When using scan converter (serial data SLLAP = 1) This is used when the input signal clock and output signal clock are different such as when performing dot conversion using a scan converter. Only the serial data interface and PLL counter of the IC internal circuits operate with CKI1 or CKI2 (clock synchronized with input signal). All other blocks operate with CKI3 or CKI4 (output signal clock). CKI3/XCKI13 are selected when SLCK2 = L (Pins 21/22, small amplitude differential input), and CKI4 is selected when SLCK2 = H (Pin 13, CMOS level input). * Internal frequency divider reset selection pin (SLHR) This selects whether reset of the PLL counter (loop counter) with HSYNC is to be enabled or disabled. In the case of performing phase comparison of the HSYNC and HRET pulses with an external phase comparator, the SLHR (Pin 17) is set to H (reset disabled). When phase comparison and frequency division are performed externally and HRET pulses for phase comparison are not used, the SLHR is set to L (reset enabled). At this time, the output of each pulse is delayed by approximately 8 clocks as compared with using HRET pulses for phase comparison. * Signal inversion type selection pin (SLFR) This selects the inversion cycle of the polarity inversion pulse (FRP pulse) for AC driving. Setting the SLFR (Pin 19) to H results in field inversion, while setting the SLFR to L results in line inversion. -9-
CXD2453Q
* System clear pin (XCLR) All internal circuits are initialized when the XCLR (Pin 78) is L. Always make sure to initialize all internal circuits when the power has been turned on. * Serial data interface Operating mode and other settings in this IC are performed by serial data. When the power is turned on, all data are set to the default values when the internal circuits are initialized. When the power supply is turned on, the value of SDAT is read with the rise of SCLK in groups of 16 bits consisting of 8 address bits and 8 data bits as shown in the Timing Chart below. The data that has been read is enabled by being transferred to the register corresponding to each address 10 clocks after the rise of SCLK of the 16th bit. The Timing Chart and Data Format during transmission of serial data are as shown below. Timing Chart
SCTL (Pin 8)
SCLK (Pin 6)
SDAT (Pin 7)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Address (8 bits)
Data (8 bits)
Data Format Address D15 to D8 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF D7 -- PLP7 HP7 VP7 -- -- -- IRD7 -- IRU7 -- ORP7 -- ORD7 -- ORU7 D6 -- PLP6 HP6 VP6 -- -- -- IRD6 -- IRU6 -- ORP6 -- ORD6 -- ORU6 D5 -- PLP5 HP5 VP5 -- VPOL HB IRD5 -- IRU5 -- ORP5 -- ORD5 -- ORU5 D4 -- PLP4 HP4 VP4 INV HPOL VB IRD4 -- IRU4 Data D3 -- PLP3 HP3 VP3 SHP3 VSCN D2 PLP10 PLP2 HP2 VP2 SHP2 HSCN D1 PLP9 PLP1 HP1 VP1 SHP1 SLXG IRD9 IRD1 IRU9 IRU1 D0 PLP8 PLP0 HP0 VP0 SHP0 SLSX IRD8 IRD0 IRU8 IRU0 ORP8 ORP0 ORD8 ORD0 ORU8 ORU0 PLL counter frequency division ratio Screen horizontal position Screen vertical position CXA2112R S/H control Operating mode, etc. Operating mode, etc./ IRACT fall position IRACT rise position ORACT reset cycle/ ORACT division frequency ORACT fall position Settings
SLLAP IRD10 IRD3 -- IRU3 IRD2 IRU10 IRU2
ORRS1 ORRS0 ORP10 ORP9 ORP4 -- ORD4 -- ORU4 ORP3 -- ORD3 -- ORU3 ORP2 ORP1
ORD10 ORD9 ORD2 ORD1
ORU10 ORU9 ORU2 ORU1
ORACT rise position
Note) --: Don't care
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CXD2453Q
The following provides a detailed description of each setting. (a) Setting of PLL counter frequency division ratio This is used to set the frequency division ratio of the 1/N frequency divider (PLL counter) for phase comparison. The value of (total number of dots of 1 horizontal period N) - 1 is set with PLP10 (MSB) through PLP0 (LSB). The frequency division ratio can be set up to 2048. Only even numbers can be set for the value of N. When it is necessary to set an odd number, use an external frequency divider. In this case, set the value of the frequency division ratio of the PLL counter to N-2. The default value is 10100111111 (N = 1344). (b) Setting of screen horizontal position The horizontal display start position is set with HP7 (MSB) through HP0 (LSB). This setting enables the phase relationships of pulses HST, HCK1/2, ENB, PCG, PRG and CLP1/2 as well as the changing positions of VCK/FRP relative to HSYNC to change in an interlocked manner. Settings can be made in 1 dot units. Refer to the Timing Chart for the relationship between the set value and each pulse position. The default value is 01000100. (c) Setting of screen vertical position The vertical display start position is set with VP7 (MSB) through VP0 (LSB). This setting enables the phase relationships of signals VST, VCK and FRP to change relative to VSYNC in an interlocked manner. Settings can be made in 1 line units. Refer to the Timing Chart for the relationship between the set value and each signal. The default value is 00100011. 00000000 and 11111111 are not used. (d) S/H control of CXA2112R This is used to set the sample-and-hold position for the CXA2112R (sample-and-hold driver). INV setting data is output directly from the INV (Pin 60). Setting data of SHP3 (MSB) through SHP0 (LSB) is reflected as shown below in the SHPA through SHPD (Pins 56 to 59). Refer to the specifications of the CXA2112R for details. Setting data SHP3 to SHP0 0000 0001 0010 0011 0100 0101 0110 0111 SHPA L H Z Z L H Z Z Output SHPB L H L H L H L H SHPC L L L L H H H H SHPD L L L L H H H H Setting data SHP3 to SHP0 1000 1001 1010 1011 1100 1101 1110 1111 SHPA L H Z Z L H Z Z Output SHPB L H L H L H L H SHPC Z Z Z Z Z Z Z Z SHPD L L L L H H H H
Note) Z: High impedance state
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CXD2453Q
(e) Setting of operating mode, etc. * VPOL, HPOL: These are used to set the polarity of VSYNC and HSYNC. A setting of "1" denotes positive polarity, while a setting of "0" denotes negative polarity. The default values are VPOL = 0, HPOL = 0. * VSCN, HSCN: These are used to set the vertical and horizontal scanning directions of the LCD panel. VSCN = 1 denotes downward scanning, while VSCN = 0 denotes upward scanning. HSCN = 1 denotes rightward scanning, while HSCN = 0 denotes leftward scanning. Setting data of VSCN is output from the DWN (Pin 64), while setting data of HSCN is output from the RGT (Pin 66). The default values are VSCN = 0, HSCN = 1. * SLXG, SLSX: These are used to set the input signals (operating mode). This IC has the following three operating modes. The default values are SLXG = 0, SLSX = 0. Operating mode XGA-I XGA-II S-XGA Note) X: Don't care The XGA-I mode supports typical XGA signals. The XGA-II mode is for XGA signals in which there is a low number of dots during a portion of the horizontal blanking period (typically when HSYNC + back porch is 240 dots or less). Select the appropriate operating mode to satisfy the conditions in the diagram on page 6 corresponding to the input signal. In the S-XGA mode, 1024 vertical lines are displayed decimating to 768 lines corresponding to the S-XGA signal (1280 x 1024 dots). These are used to switch the number of display dots on the LCD panel. The display is set to 960 dots horizontally when HB = 0, and to 640 lines vertically when VB = 0. The data of each setting is output from the HB (Pin 62) and VB (Pin 61), respectively. Refer to the specifications of the LCX017AL for details. The default values are HB = 1, VB = 1. This is used when the input signal clock and output signal clock differ such as when converting the number of dots using a scan converter. When SLLAP = 1, only the serial data interface and PLL counter of the IC internal circuits operate with CKI1 or CKI2 (clock synchronized with input signal), while other sections operated with CKI3 or CKI4 (output signal clock). When SLLAP = 0, all internal IC circuits operate with CKI1 or CKI2. The default value is 0. SLXG 0 1 X SLSX 0 0 1
* HB, VB:
* SLLAP:
(f) Setting of IRACT fall/rise positions * IRACT pulse A pulse synchronized with HSYNC of the input signal can be output at any position and width. The fall position of the pulse is set with IRD10 (MSB) through IRD0 (LSB), while the rise position is set with IRU10 (MSB) through IRU0 (LSB). The values of IRD0 and IRU0 are ignored, and settings are made in 2-dot increments. The setting range is from "0" to (N - 2). The same value cannot be set for IRD and IRU. Refer to the Timing Chart for the relationship between setting values and pulse positions. The default values are IRD10 through IRD0 = 00000000000, and IRU10 through IRU0 = 00010000000. - 12 -
CXD2453Q
(g) Setting of ORACT reset cycle/ORACT frequency division ratio * ORACT pulses ORACT pulses are completely identical to IRACT pulses when serial data SLLAP = 0, when SLLAP = 1, they are generated by a dedicated counter (loop counter similar to the PLL counter) that operates according to an independent clock (CKI3 or CKI4) different from the clock synchronized with input signal HSYNC (CKI1 or CKI2). Since pulses for driving the LCD panel are also generated based on this counter at this time, the LCD panel can be driven based on a clock and cycle that are different from the input signal. ORACT pulses are synchronized with the cycle of the pulse for driving the LCD panel at this time, and can be output at any position and width. The frequency division ratio of the above dedicated counter is set with ORP10 (MSB) through ORP0 (LSB). The value of (number of counter counts M) - 1 is the actual setting value. Only even numbers can be set for M, and settings are made in 2 dot increments. The maximum setting is 2048 counts. This counter is reset with VSYNC and HSYNC of a fixed cycle in order to synchronize it with the input signal, the interval of H at which it is to be reset with this HSYNC is set with ORRS1 and ORRS0. Setting data (ORRS1/ORRS0) Reset cycle
00 01 10 11
Every 3H
Every 4H
Every 5H
Every 1H
The default values are ORRS1 = 1, ORRS0 = 1, and ORP10 through ORP0 = 10100111111. (h) Setting of ORACT fall/rise positions The fall position of the ORACT pulse is set with ORD10 (MSB) through ORD0 (LSB), while the rise position of the ORACT pulse is similarly set with ORU10 (MSB) through ORU0 (LSB). The values of ORD0 and ORU0 are ignored, and settings are made in 2-dot increments. The setting range is from "0" to (M - 2). The same value cannot be set for ORD and ORU. The relationship between setting values and pulse positions is as indicated below. The default values are ORD10 through ORD0 = 00000000000, and ORU10 through ORU0 = 00010000000.
HSYNC (HSYNC when reset is applied to counter) ORACT (default setting) 8ck 128ck
ORD = 000/HEX
ORU = 080/HEX
* XHS pulse and XVS pulse The XHS pulse is output over a width of 32 clocks 34 clocks after the fall of the IRACT pulse when SLLAP = 0. The pulse has negative polarity. When SLLAP = 1, the pulse is similarly output over a width of 34 clocks after the fall of the ORACT pulse. The XVS pulse is VSYNC latched with the XHS pulse. Its polarity is always negative regardless of the polarity of the input VSYNC. * AC driving of LCD panels for no signal When VSYNC has not been input for a specified period, a judgment of "no signal" is made to allow AC driving of LCD panels even when there is no signal. A vertical start pulse and polarity inverted pulse (FRP) are output at a specified cycle. The timing by which a judgment of "no signal" is made and the free running cycle are as indicated below. Operating mode All modes - 13 - Free running detection timing (no signal period) and VST cycle during free running
1600H
Horizontal Direction Timing Chart (XGA-I (1024 x 768 dots))
PLP = 53F/HEX, HP = 44/HEX, HPOL = 0, HSCN = 1, SLXG = 0, SLSX = 0, IRD = 000/HEX, IRU = 080/HEX SLHR: H, SLFR: L
CKI
HSYNC
HRET 188fH 66fH 140fH 30fH 24fH 104fH 20fH
CLP1
CLP2
HST
HCK1
HCK2 70fH 148fH 78fH 156fH 132fH
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34fH 128fH 32fH
ENB
PCG
PRG
VCK
FRP
XHS
IRACT
ORACT
2fH
CXD2453Q
Note) The phases of HCK1 and HCK2 are respectively reversed when HSCN = 0 (left/right inversion). The polarity of 1H and 1V cycle of FRP is not defined.
Horizontal Direction Timing Chart (XGA-II (1024 x 768 dots))
PLP = 51F/HEX, HP = 14/HEX, HPOL = 0, HSCN = 1, SLXG = 1, SLSX = 0, IRD = 000/HEX, IRU = 080/HEX SLHR: H, SLFR: L
CKI
HSYNC
HRET 116fH 66fH 100fH 24fH 22fH 80fH 20fH
CLP1
CLP2
HST
HCK1
HCK2 42fH 104fH 108fH 62fH 124fH
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34fH 128fH 32fH
ENB
PCG
PRG
VCK
FRP
XHS
IRACT
ORACT
2fH
CXD2453Q
Note) The phases of HCK1 and HCK2 are respectively reversed when HSCN = 0 (left/right inversion). The polarity of 1H and 1V cycle of FRP is not defined.
Vertical Direction Timing Chart (XGA-I/II (1024 x 768 dots))
VP = 23/HEX, VPOL = 0, SLSX = 0, IRD = 000/HEX, IRU = 080/HEX, SLFR: L
HSYNC
HRET
VSYNC
VST
VCK
FRP
HST
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ENB
PCG
PRG
BLK
XHS
XVS
IRACT
ORACT
CXD2453Q
Note) The polarity of 1H and 1V cycle of FRP is not defined.
Vertical Direction Timing Chart (XGA-I/II (during display of 640 vertical lines))
VP = 23/HEX, VPOL = 0, SLSX = 0, VB = 0, IRD = 000/HEX, IRU = 080/HEX, SLFR: L
HSYNC
HRET
VSYNC
VST
VCK
FRP
HST
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ENB
PCG
PRG
BLK
XHS
XVS
IRACT
ORACT
CXD2453Q
Note) The polarity of 1H and 1V cycle of FRP is not defined.
Horizontal Direction Timing Chart (S-XGA (1280 x 1024 dots displayed on 960 x 768 dots))
PLP = 4F1/HEX, HP = 12/HEX, HPOL = 1, HSCN = 1, SLSX = 1, IRD = 000/HEX, IRU = 080/HEX SLHR: H, SLFR: L
CKI
HSYNC
HRET 144fH 86fH 120fH 24fH 26fH 102fH 18fH
CLP1
CLP2
HST
HCK1
HCK2 184fH 114fH 136fH 102fH
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34fH 128fH 32fH
ENB
22fH
PCG
PRG
VCK
FRP
XHS
IRACT
ORACT
2fH
CXD2453Q
Note) The phases of HCK1 and HCK2 are respectively reversed when HSCN = 0 (left/right inversion). The polarity of 1H and 1V cycle of FRP is not defined.
Vertical Direction Timing Chart (S-XGA (1280 x 1024 dots displayed on 960 x 768 dots))
VP = 24/HEX, VPOL = 1, SLSX = 1, IRD = 000/HEX, IRU = 080/HEX, SLFR: L
HSYNC
HRET
VSYNC
VST
VCK
FRP
HST
- 19 -
ENB
PCG
PRG
BLK
XHS
XVS
IRACT
ORACT
CXD2453Q
Note) The polarity of 1H and 1V cycle of FRP is not defined.
CXD2453Q
Application Circuit
LCD Panel
CXA2112R (when not using CXA2111R)
LCD Panel
SN74HC244 (Vcc = 5.0V)
(POS CNT2)
(POS CNT1)
(INV CNT)
SN74HC04 (Vcc = 5.0V) 10
10
10 SN74HC86 (Vcc = 5.0V)
SN74HC244 (Vcc = 5.0V)
10
47k 3.3V
47k 10 0.1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
10
PCG
SHPA
SHPB
HCK1
SHPC
DWN
SHPD
HCK2
ENB
65 66 67 68 69
PRG
VCK
XRGT RGT XVS XHS IRACT
CLP2
40
10
CLP1 39 HRET VSS TST9 TST8 TST7 VDD VDD VSS SLCK2 HSYNC 38 37 36 35 34 33 32 31 30 29 COMS 0.1
70 ORACT 71 VSS 0.1 72 TST10 73 VDD 74 TST11 75 10k 76 77 78 1 TST12 TST13 VSS XCLR
VSYNC 28 TST6 27 SLCK1 VSS 26 25 Differential SLCK1
79 TST14 80 TST15
XCKI1
SDAT
SLHR
SCLK
SCTL
TST1
SLFR
TST2
TST3
TST4
XCKI3
CKI2
VDD
VSS
VSS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
10 Serial data
0.1
PLL IC
VSS
TST5
CKI1
CKI4
VSS
VSS
VSS
CKI3
VSS
HSYNC
VSYNC
PLL IC: Sony CXA3106Q (built-in phase comparator and frequency divider) is recommended.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 20 -
Driver IC/Circuit
10
INV
HST
FRP
VST
BLK
VB
VSS
VSS
HB
VDD
VSS
VSS
VSS
CXD2453Q
Package Outline
Unit: mm
80PIN QFP(PLASTIC)
23.90 0.40 20.00 0.20 64 41 3.35MAX 0.05MIN 0.10
65
40
14.00 0.20
17.90 0.40
A B
INDEX
80
25
1 0.80 0.35 0.10
24 0.16 M
0.18MAX
0.58MAX
0.25
0.30
0 to 10 DETAIL A DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L022 QFP080-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 1.7g
- 21 -
0.80 0.20
16.30 0.40

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