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MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER
DESCRIPTION
The M66271FP is a graphic display-only controller for displaying a high duty dot matrix type LCD which is used widely for PPC,FAX and multi-function telephones. It is capable of controlling a monochrome STN LCD system of up to 320 x 240 dots. The IC has a built-in 9600-byte VRAM as a display data memory. All of the VRAM addresses are externally opened. Address mapping in the MPU memory space allows direct addressing of all display data from the MPU,thus providing efficient display data processing such as drawing. The built-in arbiter circuit (cycle steal system) which gives priority to display access allows timing-free access from MPU to VRAM, preventing display screen distortion. The IC provides interface with a 8-bit/16-bit MPU with a READY(WAIT) pin. And this IC has a function for LCD module built-in system by lessening connect pins between MPU.
qInterface with MPU
*Capability of switching 8-bit type MPU/16-bit type MPU *With WAIT output pin (Accessing register from MPU without WAIT output. Accessing VRAM from MPU with WAIT output.) *Capability of controlling BHE or LWR/ HWR at the interface with a 16-bit MPU. qInterface with LCD *LCD display data are 4-bit parallel output *4 kinds of control signals: CP,LP,FLM and M qDisplay functions *Graphic display only (characters drawn graphically) *Binary display only (without tone display function) *Vertical scrolling is allowed within memory range (small size LCD only) qAdditional function for LCD module built-in system *15 kinds of interface with MPU : A<4:1>,D<7:0>,IOCS,LW R,RD *Accessing VRAM from MPU through I/O register *Capability of interfacing with 8-bit type MPU only q5V single power supply q80-pin QFP
FEATURES
q Displayable LCD *Monochrome STN dot matrix type LCD of up to 76800 dots (equivalent to 320 x 240 dots) *Maximum display duty : 1/240 (set to 240 Line) : 1/255 (Max) q Display memory *Built-in 9600-byte(76800-bit)VRAM (equivalent to one screen of 320 x 240 dots LCD) *All addresses of built-in VRAM are externally opened.
APPLICATION
*PPC/FAX operation panel,display/operation panel of other OA equipment *Multi-function/public telephones *PDA/electronic notebook/information terminal *Other applications using LCD of 76800 dots or less
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VSS DISPLAY DATA TRANSFER CLOCK CP DISPLAY DATA LATCH PULSE LP FIRST LINE MARKER FLM UD<0> UD<1> LCD DISPLAY DATA BUS UD<2> UD<3> N.C N.C N.C N.C VDD OSCILLATOR INPUT OSC1 OSCILLATOR OUTPUT OSC2 VSS
41
VSS VDD LCD ALTERNATING SIGNAL M LC D EN B LCD CONTROL SIGNAL D<15> D<14> D<13> D<12> MPU DATA BUS D<11> D<10> D<9> D<8> VDD VSS D<7> D<6> D<5> D<4> MPU DATA BUS D<3> D<2> D<1> D<0> VDD VSS
PIN CONFIGURATION(TOP VIEW)
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 20 21 22 23 10 11 12 13 14 15 16 17 18 19 24 1 2 3 4 5 6 7 8 9
40 39 38 37 36 35 34
M66271FP
33 32 31 30 29 28 27 26 25
VSS N.C N.C N.C N.C VSS VDD N.C N.C A<13> A<12> A<11> MPU ADDRESS BUS A<10> A<9> A<8> VSS
CONTROL REGISTER CHIP SELECT IOCS HIGH WRITE STROBE HWR
Outline 80P6N-A
LWR READ STROBE RD VRAM CHIP SELECT MCS WAIT W AIT VDD MPU CLOCK MPUCLK VSS RESET RESET 8/16 MPU SELECT MPUSEL VSS BUS HIGH ENABLE BHE A<0> A<1> A<2> A<3> MPU ADDRESS BUS A<4> A<5> A<6> A<7> VDD VSS
VSS
LOW W RITE STROBE
N.C : No Connection
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER BLOCK DIAGRAM 1
15
VDD
8 23 34 42 52 63 77
MPU ADDRESS BUS
-
A<13:0>
22 26
-
ADDRESS BUFFER CONTROL REGISTER
LCD DISPLAY TIMING CONTROL CIRCUIT
61
LCDENB CP LP FLM M
LCD CONTROL SIGNAL DISPLAY DATA TRANSFER CLOCK DISPLAY DATA LATCH PULSE F I RST L I NE MARKER SIGNAL LCD ALTERNATING SIGNAL
31
66 67 68 62
43
-
MPU DATA BUS
D<15:0>
50 53 60
DATA BUFFER
-
VRAM IOCS MCS HIGH WRITE STROBE HWR LOW W RITE STROBE LWR READ STROBE RD 8/16 MPU SELECT MPUSEL RESET RESET BUS HIGH ENABLE BHE MPUCLK MPU CLOCK WAIT WAIT
CONTROL REGISTER CH I P SELECT VRAM CH I P SELECT
2 6 3 4 5 12 11 14 9 7
9600byte
LCD DISPLAY DATA CONTROL CIRCUIT
69 70 71 72
UD<3:0>
LCD DISPLAY DATA BUS
MPU I/F CONTROL CIRCUIT
BUS ARBITER TIMING CONTROL CLOCK CONTROL
(BASIC TIMING CONTROL)
OSCILLATOR INPUT OSCILLATOR OUTPUT
OSC1 OSC2
78 79
(CYCLE STEAL CONTROL)
1 10 13 24 25 35 40 41 51 64 65 80
32 33 36 37 38 39 73 74 75 76
VSS
N.C
BLOCK DIAGRAM 2 (In case of LCD module built-in system)
NO USE PINS
3 6 7 9 11 12 14 15 20 - 22 26 - 31 53 - 60
VDD
8 23 34 42 52 63 77
MPU ADDRESS BUS
16
A<4:1>
19
ADDRESS BUFFER
61
LCDENB CP LP FLM M
CONTROL REGISTER
66
LCD DISPLAY TIMING CONTROL CIRCUIT
67 68 62
MPU DATA BUS
D<7:0>
43 50
DATA BUFFER
VRAM ADDRESS INDEX REGISTER DATAPORT REGISTER
LCD CONTROL SIGNAL DISPLAY DATA TRANSFER CLOCK DISPLAY DATA LATCH PULSE F I RST L I NE MARKER SIGNAL LCD ALTERNATING SIGNAL
-
-
VRAM 9600byte
LCD DISPLAY DATA CONTROL CIRCUIT
69 70 71 72
CONTROL REGISTER CH I P SELECT
IOCS
2
UD<3:0>
LOW W RITE STROBE READ STROBE
LWR RD
4 5
MPU I/F CONTROL CIRCUIT
LCD DISPLAY DATA BUS
OSCILLATOR INPUT OSCILLATOR OUTPUT
OSC1 OSC2
78 79
CLOCK CONTROL
(BASIC TIMING CONTROL)
BUS ARBITER TIMING CONTROL
1 10 13 24 25 35 40 41 51 64 65 80
32 33 36 37 38 39 73 74 75 76
VSS
N.C
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER PIN DESCRIPTIONS
Item Pin name Input/ Output Function MPU data bus Connect to MPU data bus. Selecting 8bit MPU by MPUSEL input, D<15:8> connect to VDD or VSS.
Number of pins
D<15:0> Input/ Output
16
A<13:0> Input
MPU address bus Connect to MPU address bus. When selecting 8- MPU, use A<13:0>. And selecting bit 14 16-bit MPU, use A<13:1> for the address bus with combining A<0> and BHE by the method of access to internal VRAM (Refer to Figure-1). Use A<4:0> for selecting address of control register. Chip select input of control register When this pin is "L", select the internal control register. Assign to I/O space of MPU. Chip select input of VRAM When this pin is "L", select the internal VRAM. Assign to memory space of MPU. High-Write strobe input When this pin is "L", data write to the internal VRAM. HWR is valid only in using 16-bit MPU controlled byte access by LWR and HWR. (Refer to Figure-1) Low-Write strobe input When this pin is "L", data write to the internal control register or VRAM. (Refer to Figure-1) Read strobe input When this pin is "L", data read from the internal control register or VRAM.(Refer to Figure-1) 8/16-bit MPU select input According to MPU, set "VSS" for 8bit MPU and set "VDD" for 16bit MPU. Reset input Use reset signal of MPU.When this pin is "L", initialize all internal control register and counter. MPU clock Input of MPU clock. Bus-High-Enable input This pin is valid when using 16-bit MPU controlled byte access by A<0> and BHE (Refer to Figure1). Connect to "VDD" when using 8-bit MPU. Set to "L" when using the additional function for the LCD Module built-in system. WAIT output for MPU This signal makes WAIT for MPU. Change WAIT "L" at timing of falling edge of overlapping with MCS and (RD or LWR or HWR). And return to "H" at synchronizing with the rising edge of MPUCLK after internal processing. (Output WAIT only when requested access from MPU to VRAM during cycle steal access.) Display data bus for LCD Transfer the LCD display data with 4-bit parallel signal. Mutually output upper/lower data every CP output. Display data transfer clock Shift clock for the transfer of display data to LCD. Take the display data of UD<3:0> to LCD at falling edge of CP. Display data latch pulse This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal. LP output when finish the transfer of display data of a line. Latch of display data and the transfer of scanning signal at falling edge of LP. First line marker signal Output the start pulse of scanning line. This signal is "H" active,the IC for driving scanning line catch FLM at falling edge of LP. LCD alternating signal output Signal for driving LCD by alternating current. LCD(ON/OFF) control signal output Output data which is set at bit"0 " of mode register(R1) in control register. This signal can use for controlling the LCD power supply, because LCDENB set to "L" byRESET. Input pin for oscillator Output pin for oscillator Power supply.(source +5V ) Ground No connection Generate an internal clock. For crystal oscillator or external clock signal. 1 1
IOCS MCS
Input Input
HWR
Input
1
MPU interface
LWR RD
Input Input
1 1 1 1 1
MPUSEL Input RESET Input
MPUCLK Input
BHE
Input
1
WAIT
Output
1
UD<3:0> Output
4
CP
Output
1
LP LCD interface FLM M
Output
1
Output Output
1 1
LCDENB Output OSC1
Oscillator
1 1 1 7 12 10
Input Output
OSC2 VDD Others VSS N.C
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER OUTLINE
M66271FP is graphic display only controller for displaying a dot matrix type LCD. This IC has a built-in display data memory (VRAM) which is equivalent to 320x240 dots LCD. q Control register When access the control register from MPU side, use IOCS, LWR,RD,A<4:0> and D<7:0>. Refer to Table-1,when set control type inputs. Control registers are R1 - R8 for the normal mode function and R9 - R11 for the exclusive register for the LCD module built-in system. q VRAM When access VRAM from MPU side, use MCS,HWR,LWR, RD,BHE, A<13:0> and D<15:0>. And enable to correspond to both 8-bit and 16-bit MPU by using MPUSEL input. Refer to Figure-1 and Table-2 - 6 for a form of VRAM and input setting for 8/16-bit MPU. q Cycle steal system Cycle steal is interact method of transferring display data for LCD from VRAM and accessing VRAM from MPU on the basic cycle of OSC. Basic timing is two clocks of OSC,and assign first clock to the access from MPU to VRAM and second clock to the transfer of display data from VRAM to LCD. In accessing VRAM from MPU,output WAIT. Change WAIT to "L" at the timing of the falling edge of overlapping with MCS and (RD or LWR/HWR). And return to "H" at synchronizing with rising edge of MPUCLK after internal processing. Cycle steal system can transfer data with more efficient. This function access with the cycle steal method as taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On other side, don't output WAIT for keeping throughput of MPU during horizontal synchronous term with no necessity for the display data transfer from VRAM to LCD side. Refer to the following description of cycle steal. q Output to LCD side LCD display data UD<3:0> output synchronized with the rising edge of CP output per 4bits. LP output synchronized with the falling edge of OSC when finish the transfer of display data for a line. Enable to adjust the fittest value of the frame frequency requested by the LCD PANEL side with adjusting pulse width by LPW register. FLM output, when finish the transfer of display data of 1st line. M output is the LCD alternating signal which is signal for driving LCD by alternating current. M-cycle enable to set variably by M-cycle variable register in line unit, and enable to utilize for preventting LCD from being inferior.
Difference in VRAM between 8-bit and 16-bit MPU
(1) When accessing built-in VRAM by 8-bit MPU
(MPUSEL="L",BHE="H",HWR="H" :set)
A<13:0> MCS LWR D<7:0>
A<13:0> CEC
VRAM
WEC DI<7:0> DO<7:0>
9600byte
RD (2) When accessing built-in VRAM by 16-bit MPU
(2-1) In case MPU use A<0> and BHE for byte access (MPUSEL="H",HWR="H":set) (2-2) In case MPU use LWR and HWR for byte access (MPUSEL="H",BHE="H",A<0>="H":set)
A<13:1> A<0> MCS LWR D<7:0>
A<13:1> A<0>
A<13:1>
VRAM
A<13:1>
CEC
4800byte
WEC DI<7:0> DO<7:0> (Lower byte)
MCS LWR D<7:0>
VRAM
CEC
4800byte
WEC DI<7:0> DO<7:0> (Lower byte)
A<13:1>
A<13:1>
BHE
A<0> CEC WEC
VRAM 4800byte
CEC
VRAM 4800byte
D<15:8> RD
(Upper byte) DI<15:8> DO<15:8>
HWR D<15:8> RD
WEC DI<15:8> DO<15:8>
(Upper byte)
Figure-1 Difference in VRAM between 8- and 16-bit MPU bit
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER Combination of control input pins for MPU interface
Table-1 - 6 show conditions of input setting when access the control register and VRAM from MPU (1) Access control register (Use address=A<4:0>,Data=D<7:0>) Table-1 IOCS LWR L L H L H X RD H L X Operation Write to control register Read from control register Invalid
(2) Writing to VRAM (2-1) When use 8-bit MPU (MPUSEL="L",BHE=HWR="H":set) Table-2
MPU SEL
MCS BHE A<0> HWR LWR L H L H X X H L H X
Odd address Invalid Write Invalid
Even address Write Invalid Invalid
Valid data bus width of MPU
L
8-bit
H
(2-2) When use 16-bit MPU (In MPU controls byte access with A<0> and BHE. Table-3
MPU SEL
MPUSEL=HWR="H":set)
Valid data bus width of MPU
MCS BHE A<0> HWR LWR L L L H L H H H X X H L H L H L H L H X
Upper byte Write Invalid Write Invalid Invalid Invalid Invalid Invalid
Lower byte Write Invalid Invalid Invalid Write Invalid Write Invalid
H
16-bit Upper 8-bit Lower 8-bit Lower 8-bit
Even if A<0>="H", enable to write
(2-3) When use 16-bit MPU (In MPU controls byte access with LWR and HWR. Table-4
MPU SEL
MPUSEL=BHE=A<0>="H":set)
Valid data bus width of MPU
MCS BHE A<0> HWR LWR L H H L H H X L H L H X
Upper byte Write Write Invalid Invalid
Lower byte Write Invalid Write Invalid
H
16-bit Upper 8-bit Lower 8-bit
(3) Reading from VRAM (3-1) When use 8-bit MPU (MPUSEL="L",BHE="H":set) Table-5
MPU SEL
MCS BHE A<0> L H L H X
RD L H X
Odd address Invalid Read Invalid
Even address Read Invalid Invalid
Valid data bus width of MPU
L
8-bit
H
(3-2) When use 16-bit MPU (MPUSEL="H":set) Table-6
MPU SEL
MCS BHE A<0> L H X X
RD L H X
Upper byte Read Invalid
Lower byte Read Invalid
Valid data bus width of MPU
H
16-bit
Note:Avoid setting combination except above,as cause of error action :X="L" or "H"
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER Description of cycle steal
BASIC TIMING
Basic timing of M66271FP is two clocks of OSC (internal clock after dividing OSC1 input). Assign first clock to accessing from MPU to VRAM and second clock to transferring of display data from VRAM to LCD
Access from MPU to VRAM Data transfer from VRAM to LCD
MPU
LCD
OSC
(Internal clock after dividing OSC1 input)
CP output
(Display data transfer)
Basic cycle
Figure-2 BASIC TIMING
Operation cycle of MPU access(during WAIT output)
Writing or Reading operation for VRAM during cycle steal needs 1 cycle in best case or 3 cycles in worst case,
Ex.) Assuming that MCS input is later than RD,LWR and HWR input.
Cycle of LCD access Cycle of MPU access
Operation cycle of MPU access
according to the condition of the internal cycle steal at staring access requested from MPU.
Cycle of LCD access Cycle of MPU access Cycle of LCD access
Best case
MCS
WAIT
Cancel WAIT,when synchronize with rising edge of MPUCLK
MPUCLK Worst case
MCS
Operation cycle of MPU access
WAIT
Cancel WAIT,when synchronize with rising edge of MPUCLK
MPUCLK
Figure-3 Operation cycle of MPU access
Function of cycle steal control
M66271FP has a function for processing data of a line with more efficient. This function access with the cycle steal method as taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On other side, don't output WAIT for keeping throughput of Ex.) Assuming 320x240 dots LCD
1 Line
MPU during the horizontal synchronous term with no necessity for the display data transfer from VRAM to LCD side. But certainly set a term of accessing with the cycle steal method by CSW register, for controlling an error action near the end of horizontal synchronous term.
LP
1
2 3
Output when finish transfer of display data with a line 78
79 80
1 Output every transfer of a display data
CP UD<3:0>
Setting by CR register Displaying term (Cycle steal method) (Necessity for data transfer from VRAM to LCD side) Setting by LPW register Horizontal synchronous term (No necessity for data transfer from VRAM to LCD side)
4bit transfer
CSE
(Internal signal) Setting by CSW register Start WAIT for MPU according to cycle steal access. Access with bus timing of MPU without WAIT for MPU. Start WAIT for MPU in timing of CSE "H" according to bus timing of MPU.
Figure-4 Function of cycle steal control
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER Handling of oscillator pin
<1> Crystal oscillator <2> Input from external clock directly Clock generator
Crystal oscillator OSC1 C1 Rf Rd
M66271FP
OSC1
M66271FP
OSC2 C2
Open
OSC2
As far as possible, connect C,R and the crystal oscillator at near the pin.
Figure-5 Oscillator pin
Additional function for LCD module built-in system
As all of the VRAM address in M66271FP are externally opened for addressing VRAM from MPU directly. When consider the LCD module built-in system,connect pins are increased. But M66271FP has an additional function for the LCD module built-in system by lessening connect pins. Outline of the additional function for the LCD module built-in system q Interface pins with MPU 15 kinds of Interface with MPU:A<4:1>,D<7:0>,IOCS,LWR,RD q Method of accessing the internal VRAM Access the internal VRAM through the VRAM address index register (IDXL,IDXH) and the Data port register (DP) which are used for I/O register. The following show the process of accessing VRAM.
Setting to MPUSEL,BHE="L"
q No use pins set the following. HWR="H",MCS="H",WAIT= open,MPUCLK="L",MPUSEL="L", BHE="L",A<0>="L",A<13:5>="L",D<15:8>="L", q RESET=Power on reset or soft ware reset. (In case of soft ware reset RESET ="H" :set) q Enable to change IDXL and IDXH,even if either.
Select VRAM address index register (IDXL, IDXH),and write access address(14bit) as data.
q Access the DP after writing the mode register (DISP(R1-D2)) =" 0". Always enable to access (CSES register ="0"),because the display signal fix "H" or "L" in DISP="0" and a term is no wait access. q Access DP without WAIT function.
Select Data port register (DP). Reading/Writing data for appointed VRAM address.
VRAM address is increased of +1.
q VRAM address is automatically increased of +1 ,when finished access to DP. When access to continuous address,it doesn't need to set IDXL and IDXH.
Application
MPU side A<4:1> D<7:0> IOCS LWR RD M66271FP Segment driver LCD side Common driver Graphic LCD PANEL
Crystal Oscillator
LCD module of small size for only graphics
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER Control register
M66271FP has 9 kinds of control register. To set mode from MPU to control register,use IOCS, LWR,RD,A<4:0> and D<7:0>.
(1) Kind of control register
Control register Table
Kind of register No. Name Address A4 A3 A2 A1 A0 D7 D6 D5 Data Functions of register D4 D3 D2 D1 D0 D6 - D0 set the basic mode. D7 is the status register of cycle steal state. Set the number of horizontal display characters per line. R/W
R/W
D7=Only "R"
R1 Mode register
00000
CSES RESET
OSCC
DISP
REV
LCDE
Horizontal display R2 character number register
Horizontal
00010
CR
W
R3 synchronous pulse
width register
00100
LPW
Set the pulse width of LP per line.
W
Cycle steal enable R4 width register 00110
CSW
Set the term of cycle steal enable access during horizontal synchronous term.
W
R5
Vertical line number register
01000
SLT
Set the number of display line of vertical direction.
W
R6 Display start address register R7
01010
SAL
Set the display start address of VRAM. Set lower 8-bit to SAL and upper 6-bit to SAH. Max=257FH
R/W
01100
SAH
R8 M cycle variable register
01110
MT
Set the cycle of LCD alternating signal from M .
W
R9
Data port register
10000
DP
Data port register for accessing VRAM through the register. Set the address for accessing VRAM. Set lower 8-bit to IDXL and upper 6-bit to IDXH. Max=257FH And automatically increase in continuous address .
R/W
R10 VRAM address index register R11
10010
IDXL
R/W
10100
IDXH
Note:Data port register(DP) and VRAM address index register(IDXL,IDXH) are exclusive register,when using this IC for the LCD module built-in system. When RESET,each register is initialize the setting which is assumed LCD size of 320x240 dots. Then,even if each register has not setting,output the signal to LCD side ,it is possible to be alternation of LCD.
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER (2) Description of register
(2-1) Mode register [R1]
Address R/W Function Reset
D7 CSES
0 1
No wait access Cycle steal access
* Status register for identifying active or inactive in cycle steal function. * Set "1" during active with cycle steal function. * CSES is for only reading,not for writing.
0
D6 RESET 0 Reset OFF 1 Reset ON
OSCC D4 0 0 1 1 0
* Software reset. * Surely return to reset off after reset on.
0
R/W 00000
D7= Only "R"
D5 0 0 0 0 1
D3 0 1 0 1 0
Division of OSC1
1 1/2 Division 1/4 Division 1/8 Division 1/16 Division
* Set the division of OSC clock for internal operation from OSC1 input pin. * When reset,OSCC=000,OSC1 clock doesn't divide. * Don't set except left table.
000
D2 DISP 0 Display OFF 1 Display ON D1 REV
0 Normal display 1 Reversal display
* Control the displaying ON/OFF of LCD. * When reset,DISP=0,set display OFF. * REV(D1) set "1", and when DISP= "0" display data UD<3:0> output "1" in reversal mode. * Control normal/reversal of LCD display. * When reset,REV=0,set normal display . * In using LCD of permeation method,REV="1" has effect.
0
0
D0 LCDE
0 LCDENB="0"output 1 LCDENB="1"output
* Set the output data from LCDENB output pin. * When reset,LCDE=0,LCDENB output "0"(VSS potential). * This function is prepared for controlling the voltage of LCD. When the power supply is ON after finish each register setting ,LCDE="1",supply voltage of LCD. Conversely for setting power supply OFF,first LCDE="0",the voltage of LCD is OFF. Therefore enable to prevent LCD from being unusual voltage as DC. This function use for satisfy the need of LCD.
0
(2-2) Horizontal display characters number register [R2]
Address R/W Function Reset
Display dot number
CR
D7 D6 D5 D4 D3 D2 D1 D0
Character number
00010
W
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 1 0
1 2
8 16
28H
1
1
1
1
1
1
63
504
* The number of horizontal display characters per line can set to the extent of max=504 dots(=63 characters) * When reset,CR= "28H"(=40 characters =320 dots)
Note: Definition of the number of display characters The number of display characters means data which is corresponding with 1 byte of VRAM. In case of binary,1 bit of VRAM corresponds to 1 dot of display,then 1 character means 8 dots of display.
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER (2-3) Horizontal synchronous pulse width register [R3]
Address R/W Function Reset
LPW
D7 D6 D5 D4 D3 D2 D1 D0
Character number
0 0 0 00100 W 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 1 1
0 1 0 1
1 2
01H
255
* Set the length of horizontal synchronous pulse width which appeared per line in character unit. Horizontal synchronous pulse output from LP output pin,and use for changing serial/parallel of displaying data. Adjusting this pulse width is possible to set frame frequency the fittest value. And the actual LP output pulse is (LPW setting value - 1CP) in consideration of timing with CP output. * When reset,LPW= "01H"(=1 character)
(2-4) Cycle steal enable width register [R4]
Address R/W Function Reset
CSW
D7 D6 D5 D4 D3 D2 D1 D0
Character number
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 1 1
0 1 0 1
1 2
00110 W
255
00H
* During the horizontal synchronous term, set term of access by cycle steal method in character number unit. Setting value of CSW sets below LPW value. * When reset,CSW= "00H". Note: Be careful with first and second byte of display data UD<3:0> output indefinite data when setting value of CSW is still reset (00H). Surely CSW set over 01H. (When select 8-bit MPU,1 byte is indefinite. When 16-bit and SAL:D<0>=0, 2 byte are indefinite. When 16-bit and SAL:D<0>=1, 1 byte is indefinite.)
(2-5) Vertical line number register [R5]
Address R/W Function Reset
SLT
D7 D6 D5 D4 D3 D2 D1 D0
Vertical line number
01000 W
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 1 0
1 2
F0H
1
1
1
1
1
1
1
1
255
* SLT combine the setting of display driving duty of LCD. * Setting of SLT is sure to adjust to the number of display line of LCD. * When reset,SLT= "F0H"(=240 lines).
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER (2-6) Display start address register [R6,R7]
Address R/W Function Reset
SAH
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
SAL
D4 D3 D2 D1 D0
Display start address
01010 SAL
0 0 0 1
R/W
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0 0 0 1
0 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 1 1
0 1 0 1
0000H 0001H 0002H 257FH 0000H
01100 SAH
* D6 and D7 output "0" when read SAH. * It is possible to set display start address to the extent of 257FH (=9600 address). * Don't set over 2580H. * When reset,SAL and SAH= "0000H". * Display start address is established by the writing data to SAH register. Even if only change SAL, surely set SAH after SAL. * When select 8-bit MPU,start address set in SAL + SAH . When select16-bit MPU,start address set in SAL + SAH . * Even if selecting 16-bit MPU,enable to set display start address in character unit. In case the display reading data from VRAM start at D<15:12>,set SAL ="0", and if start at D<7:4>,set SAL ="1". (Refer to Figure-8)
(2-7) M cycle variable register [R8]
Address R/W Function Reset Cycle of M
Toggle change at every 1 frame. Toggle change at every 1 line(1LP). Toggle change at every 2 lines.
MT
D7 D6 D5 D4 D3 D2 D1 D0
01110
W
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 1 1
0 1 0 1
00H
Toggle change at every 255 lines.
* Set the cycle of M. In case of MT=01H,M repeat reversal(toggle) at every 1 line (at every 1 count of LP). * When reset,MT="00H",toggle M signal at every 1 frame. * We recommend this register set suitable value for user's LCD.
(2-8) Data port register [R9]
Address R/W Function Reset
DP
D7 D6 D5 D4 D3 D2 D1 D0
Data port (8bit)
10000
R/W
XXH
* Exclusive data port register for the LCD module built-in system. Reading or writing 8bit data between MPU and VRAM through this register. * VRAM address index register (IDXL,IDXH) is increased of +1,when finished access to DP. * Output indefinite data when reset.
(indefinite)
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER (2-9) VRAM address index register [R10,R11]
Address R/W Function Reset
IDXH 10010 IDXL
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
IDXL
D4 D3 D2 D1 D0
Accessing VRAM address
0 0 0
R/W
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0 0 0 1
0 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 1 1
0 1 0 1
0000H 0001H 0002H 0000H 257FH
1 10100 IDXH
* Exclusive VRAM address index register for the LCD module built-in system. * It is possible to change the register only one side,because IDXH and IDXL are independent each other. * It is possible to set VRAM access address to the extent of 257FH (=9600 address). * Don't set address over 2580H. * D6 and D7 output "0" when read IDXH * When reset,IDXL and IDXH="0000H".
Description of LCD display Relation between setting of control register and LCD displaying
1 horizontal line CR LPW CSW
Expectant LCD PANEL
SLT
Condition of control register > (CR x 8)x SLT -- 76800 dots
1 horizontal line
CR Character number of horizontal display LPW Horizontal syncronous pulse width
x Vertical line number
SLT
OSC
1 2 3 n-2 n-1
n
1
2
CP UD<3:0>
1 Character number=8 dots display Data is indefinite
LP
(1) Time for proccessing a horizontal line(TH) 2 x (CR+LPW) TH =
fOSC
CR, LPW,CSW : Unit of character number SLT : Unit of line number fOSC : Internal OSC clock frequency after dividing OSC1 input By adjusting LPW,it is possible to set a frame frequency which is requested from LCD PANEL the fittest value.
(2) Time for proccessing a frame(TFR) TFR= TH x SLT
Figure-6 Relation between setting of control register and LCD displaying
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER Relation between address of VRAM and LCD display
ex.1) When display start address =0000H
0000H 0001H
VRAM address mapping on the LCD PANEL
0000H 0001H
VRAM 9600byte
257EH 257FH
LCD PANEL
257EH CRx8 dots 257FH
SLT line
ex.2) When display start address =1000H
0000H 0001H 1000H 1001H
VRAM 9600byte
1000H 1001H 257EH
LCD PANEL
257FH 0000H 0001H
257EH
257FH
Remark) VRAM address counter return to "0000H", after count up address to "257FH".
Figure-7 Relation between address of VRAM and LCD display
Relation between VRAM data ,LCD display and display start address register
(1) When select 8-bit MPU
UD3 D7 1 UD2 D6 0 UD1 UD0 D5 1 D4 0 UD3 D3 0 UD2 D2 1 UD1 D1 0 UD0 D0 1
LCD display data Data of one address for VRAM
LCD PANEL
(2) When select 16-bit MPU (SAL :D0="0")
UD3 D15 1 UD2 D14 0 UD1 UD0 D13 1 D12 0 UD3 D11 0 UD2 D10 1 UD1 D9 0 UD0 D8 1 UD3 D7 0 UD2 D6 0 UD1 UD0 D5 0 D4 0 UD3 D3 1 UD2 D2 1 UD1 D1 1 UD0 D0 1
LCD display data Data of one address for VRAM
LCD PANEL
(3) When select 16-bit MPU (SAL :D0="1")
Invalid display data
D15 1 D14 0 D13 1 D12 0 D11 0 D10 1 D9 0 D8 1 UD3 D7 0 UD2 D6 0 UD1 UD0 D5 0 D4 0 UD3 D3 1 UD2 D2 1 UD1 D1 1 UD0 D0 1
LCD display data Data of one address for VRAM
LCD PANEL
* Only upper byte data of the display start address is invalid data(cut off data). * Output the display data normally from next address of the display start address.
Figure-8 Relation between VRAM data ,LCD display and display start address register
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER Output signal of LCD side
Ex.) Assuming 320x240 dots LCD (In setting of CR=40characters,LPW=2characters,SLT=240lines,OSCC=1division,MT=1toggle per line)
(1) Output signal per line
OSC1
80 1 2 79 80 1 2
Division of OSC1 = 1. Output every display data transfer.
CP UD<3:0> LP
(2) Output signal per frame
239 240 1 239 240 1
4bit parallel output Output when finish the transfer of one line of display data.
LP FLM M
(3) LCDENB output signal
Output at finishing the transfer of first line display data.
Cycle of reversing output of M is able to be set by MT register.
OSC1 LCDENB
(4) Reset - 1st line of 1st frame
RESET OSC1 LCDENB LP FLM M
1 2 3 4 5 6
"L"
CP
1st line of 1st frame (5) 1st line - 2nd line
OSC1 LP FLM M
76 77 78 79 80 1 2 3 4 5 6 7 8
CP
1st line (6) 240th line of 1st frame - 1st line of 2nd frame 2nd line
OSC1 LP FLM M
76 77 78 79 80 1 2 3 4 5 6 7 8
"L"
CP
240th line of 1st frame 1st line of 2nd frame
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER ABSOLUTE MAXIMUM RATINGS (Ta=0 - +70C unless otherwise noted)
Symbol Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Storage temperature Conditions Ratings Unit
VDD VI VO IO Pd Tstg
-0.3 - +6.5 -0.3 - VDD+0.3 -0.3 - VDD+0.3 10 600 -55 - +150
V V V mA mW C
RECOMMENDED OPERATING CONDITIONS (Ta=0 - +70C unless otherwise noted)
Limits Symbol Parameter Supply voltage Supply voltage Input voltage Output voltage Operating temperature Conditions Min. Typ. Max. Unit
VDD VSS VI VO Topr
4.5 0 0 0
5.0 0
5.5 VDD VDD
V V V V C
+25
+70
ELECTRICAL CHARACTERISTICS (VDD=5V10%, Ta=0 - +70C unless otherwise noted)
Symbol Parameter High-level input voltage Low-level input voltage High-level input voltage
OSC1
All inputs except for OSC1,RESET and MPUSEL
Conditions VDD=5.5V VDD=4.5V VDD=5.5V VDD=4.5V VDD=5.0V VDD=5.0V IOH=-4mA VDD=4.5V IOL= 4mA IOH=-50uA
OSC2
Limits Min. 2.2 0.8 3.5 1.0 2.3 1.25 4.1 0.4 4.1 0.4 10 -10 10 -10 40 500 3.7 2.3 Typ. Max.
Unit V V V V V V V V V V A A A A mA A
VIH VIL VIH VIL VT + VT - VOH VOL VOH VOL IIH IIL IOZH IOZL
Low-level input voltage
Positive-going threshold voltage Negative-going threshold voltage
MPUSEL, RESET All outputs except for OSC2 and outputs of D<15:0>
High-level output voltage Low-level output voltage High-level output voltage
VDD=4.5V IOL= 50uA VDD=5.5V,VI=VDD VDD=5.5V,VI=VSS VDD=5.5V,VO=VDD
Low-level output voltage High-level input current Low-level input current
Off-state high-level output current Off-state low-level output current
D<15:0>
VDD=5.5V,VO=VSS
VDD=5.5V,VI=VDD or VSS fosc=10MHz,Output=open VDD=5.5V, IOCS,MCS=VDD Other's VI=VDD or VSS (valid)
current IDD(A) Operating supply (Average)
IDD(S) Stand-by supply current
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER
SWITCHING CHARACTERISTICS
Symbol
ta(IOCS-D) ta(MCS-D) ta(RD-D) tdis(IOCS-D) tdis(MCS-D) tdis(RD-D) tpHL(MCS-WAIT) tpHL(WR-WAIT) tpHL(RD-WAIT) tpLH(CLK-WAIT) tpd(OSC-CP) tpLH(OSC-LP) tpHL(OSC-LP) ta(UD) tpLH(OSC-FLM) tpHL(OSC-FLM) tpd(OSC-M) tpLH(OSC-LE) tpHL(OSC-LE) tpd(D-WAIT)
(VDD=5V10%, Ta=0 - +70C)
Test condition Min. Limits Typ. Max.
70
Parameter
IOCS data access time MCS data access time RD data access time Output disable time after IOCS Output disable time after MCS Output disable time after RD WAIT output propagation time after MCS WAIT output propagation time after WR WAIT output propagation time after RD WAIT output propagation time after MPUCLK CP output propagation time after OSC LP output propagation time after OSC UD access time FLM output propagation time after OSC M output propagation time after OSC LCDENB output propagation time after OSC Data definite time before cancelling WAIT
Unit
ns
20 40 20
ns ns ns ns ns ns ns ns ns ns
CL=50pF
40 40 40 40 40 40 0
TIMING REQUIREMENTS
Symbol
tW(IOCS) tW(LWR) tsu(D-IOCS) tsu(D-LWR) th(IOCS-D) th(LWR-D) tsu(A-IOCS) tsu(A-LWR) tsu(A-RD) th(IOCS-A) th(LWR-A) th(RD-A)
(VDD=5V10%, Ta=0 - +70C)
Parameter Test condition Limits Typ. Unit
ns ns ns ns
(1) Accessing to control register Min.
70 0 15 15
Max.
IOCS pulse width LWR pulse width Data set up time before falling edge of IOCS Data set up time before falling edge of LWR Data hold time after rising edge of IOCS Data hold time after rising edge of LWR Address set up time before falling edge of IOCS Address set up time before falling edge of LWR Address set up time before falling edge of RD Address hold time after rising edge of IOCS Address hold time after rising edge of LWR Address hold time after rising edge of RD
15
ns
(2) Accessing to VRAM Symbol
tW(MCS) tW(WR) tsu(D-MCS) tsu(D-WR) th(MCS-D) th(WR-D) tsu(A-MCS) tsu(A-WR) tsu(A-RD) th(MCS-A) th(WR-A) th(RD-A)
Parameter
MCS pulse width WR pulse width Data set up time before falling edge of MCS Data set up time before falling edge of WR Data hold time after rising edge of MCS Data hold time after rising edge of WR Address set up time before falling edge of MCS Address set up time before falling edge of WR Address set up time before falling edge of RD Address hold time after rising edge of MCS Address hold time after rising edge of WR Address hold time after rising edge of RD
Test condition
Min.
70 0 15
Limits Typ.
Max.
Unit
ns ns ns
15
ns
15
ns
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER (3) Clock and accessing to LCD display
Symbol
tC(CLK) tWH(CLK) tWL(CLK) tC(OSC) tWH(OSC) tWL(OSC) tC(CP) tWH(CP) tWL(CP) tW(FLM)
Parameter
MPUCLK cycle time MPUCLK "H" pulse width MPUCLK "L" pulse width OSC cycle time OSC "H" pulse width OSC "L" pulse width CP cycle time CP "H" pulse width CP "L" pulse width FLM pulse width
Test condition
Limits MIn.
50 tC(CLK) 2 50(note) tC(OSC) 2 tC(OSC)
(1/n)
Typ.
Max.
Unit
ns
ns
ns
ns
ns
tC(OSC) 2*(1/n) 2*tC(OSC)*LPW
(1/n)
ns
ns
Note: Clock frequency of OSC1 input is less than fmax=20MHz. Limit of OSC clock for the internal operation is fmax=10MHz. When OSC1 is more than 10MHz from external input, set OSC clock up to 10MHz by using division of OSCC register. Division is set with rising edge of OSC1 input.
1/n =Division of OSC1 LPW=Setting value of LPW register
Test circuit
VDD Input VDD
RL=1K SW1
Parameter
D<15:0>
SW2
tdis(LZ) tdis(HZ) ta(ZL) ta(ZH)
SW1 Closed Open Closed Open
SW2 Open Closed Open Closed
P.G
50
DUT
CL RL=1K
(1) Input pulse level : 0 - 3V
VSS
CL
Outputs except for D<15:0>
Input pulse rise/fall time : tr,tf=3ns Input decision voltage : 1.5V Output decision voltage : VDD/2 (However,tdis(LZ) is 10% of output amplitude and tdis (HZ) is 90% of that for dezision.)
(2) Load capacity CL include float capacity of connection
and input capacity of probe.
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER TIMING DIAGRAM (1) Write to control register ( RD = "H" ) Without WAIT
tw(IOCS)
IOCS
tw(LWR)
LWR "H" WAIT
tsu(D-IOCS) tsu(D-LWR) th(IOCS-D) th(LWR-D)
D<7:0>
tsu(A-IOCS) tsu(A-LWR)
Data input is established
th(IOCS-A) th(LWR-A)
A<4:0>
Address is established
(2) Read from control register (LWR= "H" ) Without WAIT IOCS
RD "H" WAIT
ta(IOCS-D) ta(RD-D) tdis(IOCS-D) tdis(RD-D)
D<7:0>
tsu(A-IOCS) tsu(A-RD)
Data output is established
th(IOCS-A) th(RD-A)
A<4:0>
Address is established
Note 1: Writing/Reading operation for the control register is performed during overlapping IOCS and (LWR or RD). Limits of IOCS,LWR and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access.
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER (3) Write to VRAM ( RD = "H" ) Term of non cycle steal access
tw(MCS)
MCS
tw(WR)
LWR (+HWR) "H" WAIT
tsu(D-MCS) tsu(D-WR) th(MCS-D) th(WR-D)
D<7:0> (D<15:0>) A<13:0> (+BHE)
Data input is established
tsu(A-MCS) tsu(A-WR) th(MCS-A) th(WR-A)
Address is established
(4) Read from VRAM (LWR,HWR = "H" ) Term of non cycle steal access MCS
RD "H"
ta(MCS-D) ta(RD-D) tdis(MCS-D) tdis(RD-D)
WAIT D<7:0> (D<15:0>)
tsu(A-MCS) tsu(A-RD)
Data output is established
th(MCS-A) th(RD-A)
A<13:0>
Address is established
Note 2: Writing/Reading operation for VRAM during non cycle steal access is performed during overlapping MCS and [LWR(+HWR) or RD]. Limits of MCS,LWR(+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access.
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER (5) Write to VRAM ( RD = "H" )
Term of cycle steal access
tC(CLK) tWH(CLK) tWL(CLK)
MPUCLK
tw(MCS)
MCS
tw(WR)
LWR (+HWR) WAIT
tpHL(MCS-WAIT) tsu(D-MCS) tpHL(WR-WAIT) tsu(D-WR) th(WR-D) tpLH(CLK-WAIT)
th(MCS-D)
D<7:0> (D<15:0>) A<13:0> (+BHE)
Data input is established
tsu(A-MCS) tsu(A-WR) th(MCS-A) th(WR-A)
Address is established
(6) Read from VRAM ( LWR,HWR = "H" )
Term of cycle steal access
tC(CLK) tWH(CLK) tWL(CLK)
MPUCLK MCS
RD WAIT
tpLH(CLK-WAIT)
tpHL(MCS-WAIT) tpHL(RD-WAIT) ta(MCS-D) ta(RD-D)
tpd(D-WAIT)
tdis(MCS-D) tdis(RD-D)
D<7:0> (D<15:0>) A<13:0>
Data output is established
tsu(A-MCS) tsu(A-RD) th(MCS-A) th(RD-A)
Address is established
Note 3: Reading/writing operation for VRAM during cycle steal needs 1tc(Internal) in best case or 3tc(Internal) in worst case,according to the condition of the internal cycle steal at starting access requested from MPU. tc(Internal) = Clock cycle time after setting division of OSC1. Data output D in reading is established before changing WAIT to "H". 4: Limits of MCS,LWR(+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access. 5: Always once return MCS,LWR(+HWR) or RD to "H" after canceling WAIT output. In case of latching "L",as don't output next WAIT,this is cause of error action.
MITSUBISHI
M66271FP
OPERATION PANEL CONTROLLER (7) Interface timing with LCD (OSCC = 1 division : set)
* When OSCC = 1 division ,OSC clock for internal operation = OSC1 input.
<7-1> Transfer of LCD display data
tWH(OSC) tC(OSC) tWL(OSC)
OSC1
tpd(OSC-CP) tC(CP) tWH(CP) tWL(CP)
CP
tpLH(OSC-LP) tpHL(OSC-LP)
LP
ta(UD)
UD<3:0>
Data is indefinite
<7-2> LCD control signal OSC1 CP LP
tpLH(OSC-FLM) tpHL(OSC-FLM)
FLM
tW(FLM) tpd(OSC-M)
M
tpLH(OSC-LE) tpHL(OSC-LE)
LCDENB
Note 6: Output signal to LCD side is syncronized with OSC clock for internal operation. When division is set to 1/2 - 1/16 by OSCC register, switching characteristics is defined by rising edge of OSC1.

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