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E2B0039-27-Y2 Semiconductor
Semiconductor MSM6255
DOT MATRIX LCD CONTROLLER
This version: Nov. 1997 MSM6255 Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSM6255 is a CMOS si-gate LSI designed to display characters and graphics on a DOT MATRIX LCD panel.
FEATURES
* Display control capacity - Graphic mode - Character mode
: 512,000 dots (216 bytes) Memory address MA0 to MA15 : 65,536 characters (216 bytes) Display address MA0 to MA15
* Direct interface with 8085 or Z80 CPU * Duty : 1/2 to 1/256 selectable * Attributes - Screen clear - Cursor ON/OFF/blink * Scrolling and paging * Display system : AC inversion at each frame * Data output (upper and lower display outputs) 4-bit parallel output, 2-bit parallel output, 1-bit serial output * Crystal oscillation/external clock selectable * Single +5V power supply * Package options: 80-pin plastic QFP (QFP80-P-1420-0.80-K) (Product name: MSM6255GS-K) 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM6255GS-BK)
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RD SLR Start address (lower) Start SUAR address (upper)
WR
CS CUP Cursor address CMP
BLOCK DIAGRAM
Semiconductor
DB0 - DB7 CLR Cursor address CMP
Input register
Output register
Instruction register
R/W control CPR Cursor generation circuit CMP ADF CMP Vp counter Cursor position (upper) CMP Linear address counter MA0 - MA15
3-state output
RES CPR Cursor position (lower)
VDD Number DPR of Vp
MPX
VSS Number DUR of duty CMP Duty counter
A0 - A15 DIEN
Number of HNR characters horizontal direction CMP Shift clock suspension counter PR Number of Hp Character counter
Raster address
RA0 - RA3
2-bit parallel output Timing control 4-bit parallel output UD0 - UD3 LD0 - LD3 CLP CE
CH
8-bit parallel/ serial
XT Dot counter
XT
OSC
T
Q
Timing generator circuit for CH PS and Load
RD0 - RD7 CH BUSY LIP FRP FRMB
MSM6255
DIV
2/39
Semiconductor
MSM6255
PIN CONFIGURATION (TOP VIEW)
69 TEST2
68 TEST1
76 MA10
75 MA11
74 MA12
73 MA13
72 MA14
71 MA15
80 MA6
79 MA7 78 MA8
77 MA9
70 DIV
67 VSS
66 XT
65 XT
MA5 MA4 MA3 MA2 MA1 MA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 FRP LIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64 RA3 63 RA2 62 RA1 61 RA0 60 RD7 59 RD6 58 RD5 57 RD4 56 RD3 55 RD2 54 RD1 53 RD0 52 DB7 51 DB6 50 DB5 49 DB4 48 DB3 47 DB2 46 DB1 45 DB0 44 RES 43 WR 42 RD 41 CS
CEf 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
CLP FRMB LD0 LD1 LD2 LD3 VDD UD0 UD1 UD2 UD3 CHf BUSY DIEN ADF
80-Pin Plastic QFP
40
3/39
Semiconductor
MSM6255
PIN DESCRIPTIONS
Pin 1-6 71 - 80 7 22 23 24 25 26 27 28 31 32 33 36 37 38 39 40 41 42 43 44 45 52 53 60 61 64 65 66 67 70 Symbol MA0 O MA15 A0 I A15 FRP LIP CE CLP FRMB LD0 O LD3 VDD UD0 O UD3 CH Busy DIEN ADF CS RD WR RES DB0 I/O DB7 RD0 I RD7 RA0 O RA3 XT XT VSS DIV I X'tal osc. When an external clock is used by setting DIV to "H", feeds it to XT. O -- I Ground pin. "H" : EXT clock "L" : Self oscillation Raster address output. *This output is not used in the graphic mode. RA0 - RA3 are high impedance when ADF = "L". ROM/RAM data input. Dot pattern data for the character generator 8-bit data bus. Common pins for 3-state I/O. O O I I I I I I O Supply voltage Display data parallel output, Upper display 4-bit output (OD1, ED1, OD2 and ED2 outputs) Character clock Ready state signal. This signal is used while serial transmission stops. Display enable signal. When this signal is "H", display is enabled. Address floating input. When this signal is "L", MA0 - MA15, RA0 - RA3 are high impedance, and when it is "H", A0 - A15 or a refresh address is output to MA0 - MA15. Chip select. CS = "L" Read. Reading data is valid when RD = "L" Write. Data is written when WR = "H" Reset. Resets each counter. Display data parallel output for lower side O O O O O Frame signal. Synchronization of display Display data latch signal Chip enable clock for LCD segment driver Display data shift clock Alternate signal output pin Memory address input pins Type Description Address output for displaying RAM. MA0 - MA15 are high impedance when ADF = "L".
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Semiconductor
MSM6255
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Storage Temperature Symbol VDD VI TSTG Condition Ta = 25C Ta = 25C -- Rating -0.3 to +6 -0.3 to VDD -50 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Operating Temperature Operating Frequency Symbol VDD Top fosc Condition VSS = 0V -- VDD = 5V 10% Range 4.5 to 5.5 -20 to +85 0 to 11 Unit V C MHz
ELECTRICAL CHARACTERISTICS
Input Characteristics
(VDD = 5V 5%, Ta = -20 to +85C) Parameter "H" Input Voltage "L" Input Voltage "H" Input Voltage "L" Input Voltage "H" Input Current "L" Input Current "H" Input Current "L" Input Current Symbol VIH VIL VIH VIL IIH IIL IIH IIL Min. 2.4 -- 4.5 -- -- -- 25 -- Typ. Max. -- -- -- -- -- -- -- -- -- 0.7 -- 1.0 1 -1 100 -1 Unit V V V V mA mA mA mA Applicable pin DB0 - DB7, CS, RD, WR, A0 - A15, DIEN, ADF, RD0 - RD7 RES, DIV, XT DB0 - DB7, CS, RD, WA, A0 - A15, DIEN, ADF, RD0 - RD7, RES, DIV TEST1, TEST2
Output Characteristics
(VDD = 5V 5%, Ta = -20 to +85C) Parameter Symbol Condition Min. Typ. Max. Unit Applicable pin LD0 - LD3 "H" Output Current IOH VOH = 2.8V -500 -- -- mA UD0 - UD3 MA0 - MA15 RA0 - RA3 CH, CE, LIP, FRP "L" Output Current IOL VOL = 0.4V 2.4 -- -- mA FRMB, BUSY, CLP DB0 - DB7
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Semiconductor Supply Current
MSM6255
(VDD = 5V 5%, Ta = -20 to +85C) Parameter Static Current Dynamic Current Symbol IDDS IDD VDD 5 5 Condition fosc = 0 Hz, no load fosc = 10 MHz, no load Min. -- -- Typ. -- -- Max. 50 15 Unit mA mA
Note: TEST 1 and TEST2 are open, and other inputs are either VDD or GND.
Switching Characteristics
0.8 VDD 0.2 VDD
0.8 VDD 0.2 VDD
tr
tf
(VDD = 5V 5%, Ta = -20 to +85C) Parameter Rise Time Fall Time Symbol tr tf Condition CL = 60 pF CL = 60 pF Min. -- -- Typ. Max. -- -- 100 100 Unit ns ns Applicable pin All output pins
Operating Frequency
(VDD = 5V 5%, Ta = -20 to +85C) Parameter Oscillating Frequency Basic Clock Frequency Symbol fosc fs Condition DIV = "L" DIV = "H" Min. -- -- Typ. Max. -- -- 11 5.5 Unit MHz MHz Notes Crystal oscillator External clock
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Semiconductor
MSM6255
TIMING DIAGRAM
LCDC Control Signal Timing Characteristics
(CL = 30pF, VDD = 5V 5%, Ta = -20 to +85C) Parameter Clock Cycle Time Clock "H" Level Pulse Width Clock "L" Level Pulse Width Clock Rise/Fall Time Character Clock Delay Time Memory Address Clock Delay Time Memory Address Disable Delay Time Memory Address Enable Delay Time CPU Address Delay Time Refresh Address Delay Time Reset "H" Level Pulse Width CPU Address Delay Time Symbol tCP PWH PWL tcr/tcf tCH tMA tAD1 tAD2 tAD3 tAD4 tRES tAD5 Min. 180 80 80 -- -- -- -- -- -- -- 1 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 20 200 100 40 40 100 100 -- 100 Unit ns ns ns ns ns ns ns ns ns ns ms ns
tCP PWL XT (External clock) tcr CH tCH MA0 - MA15
Upper Side Address Lower Side Address
PWH tcf
tMA ADF
tMA
MA0 - MA15 RA0 - RA3
VALID
Floating
VALID
tAD1 DIEN
tAD2
MA0 - MA15
Refresh Address
CPU Address
Refresh Address
tAD3 RES tRES A0 - A15 tAD5 MA0 - MA15
tAD4
tAD5
7/39
Semiconductor Bus Timing Characteristics
MSM6255
(CL = 50pF, VDD = 5V 5%, Ta = -20 to +85C) Parameter Ao, CS Setup Time RD, WR Pulse Width Address Hold Time Data Setup Time Data Hold Time Output Disable Time Access Time Symbol tCS tCW tAH tDS tDH tOH tACC Min. 30 200 10 60 20 0 -- Typ. -- -- -- -- -- -- -- Max. -- -- -- -- -- 40 200 Unit ns ns ns ns ns ns ns
tAH A0, CS tcs WR, RD tDS DB0 - DB7 (WRITE)
VALID
tcw
tDH
DB0 - DB7 (READ) tACC
VALID
tOH
8/39
Semiconductor LCDC Driver Interface Timing Characteristics
MSM6255
(CL = 30pF, VDD = 5V 5%, Ta = -20 to +85C) Parameter Data Delay Time 1 Character Cycle Time Latch Signal Delay Time Latch Signal "H" Time Chip Enable Clock Delay Time Chip Enable Clock "H" Time Ready Signal Delay Time Ready Signal "H" Time Frame Signal Delay Time Alternating Frame Signal Delay Time Symbol tDA tCH tR tLIP tCE tCE tB tBUSY tFRP tFR Min. -- 730 -- 1.46 -- 730 -- 5.11 2tCH -- Typ. -- -- -- -- -- -- -- -- -- -- Max. 100 -- 200 -- 200 -- 200 -- 2tCH +200 200 Unit ns ns ns ms ns ns ns ms ns ns
CLP
UD0 - UD3 LD0 - LD3 tDA CH
tCH
LIP t CE tCE BUSY
tLIP t tCE tCE tBUSY tB tB
LIP
FRP tFRP FRMB tFRP
tFR
tFR
9/39
Semiconductor Timing for Fetching Pattern Data
MSM6255
(VDD = 5V 5%, Ta = -20 to +85C) Parameter Upper Side Data Setup Time Upper Side Data Hold Time Lower Side Data Setup Time Lower Side Data Hold Time Symbol tUDS tUDH tLDS tLDH Min. 120 0 120 0 Typ. -- -- -- -- Max. -- -- -- -- Unit ns ns ns ns
CH
q
MA0 - MA15
w Lower side Upper side Lower side
Upper side
RD0 - RD7
Upper side data of q
Lower side data of q tLDH
Upper side data of w
Lower side data of w
tUDS
tLDS tUDH
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Semiconductor
MSM6255
FUNCTIONAL DESCRIPTION
LCDC Internal Registers The internal registers include one instruction register (IR) and nine data registers. (See Table 1.)
Table 1 MSM6255 Internal Registers
Instruction register Register 3210 H L L L L L L L L L L X H L L L L L L L L L XXXX XXXX LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL - IR MOR PR HNR DVR CPR SLR SUR CLR CUR Invalid Instruction register Mode control register Character pitch register Horizontal character number register Duty number register Cursor form register Start address (lower) register Start address (upper) register Cursor address (lower) register Cursor address (upper) register X X X - - XXXX X X
CS A0
Register name
READ WRITE
Data bit 76543210
Note: "L" is read if the data of the registers marked X is read. - Instruction register The instruction register is a register for specifying the address of the data register which is accessed. This register is cleared when RES input is "L".
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Semiconductor
MSM6255
- Mode control register The mode control register is specified by writing "00H" in the instruction register.
Register Instruction register Mode control register A0 H L D7 L L D6 L D5 L D4 L D3 L D2 L D1 L D0 L
MODE DATA
D6
D5
D4
D3
D2 L H X
D1 L L H H L L H H
4-bit parallel/ 1-bit serial
D0
Output mode 1-bit serial 2-bit parallel Character display 4-bit parallel 1-bit serial
L
H/L
H/L
H/L
H/L
X L H X X
2-bit parallel
H
2-bit parallel 4-bit parallel
Graphics
Cursor blink
Blink time
Cursor ON/OFF
Display ON/OFF
H: Display ON L: Display OFF D5 D4 L L H H L H L H Cursor OFF Cursor OFF Cursor ON Cursor blink
H: 16 frames L: 32 frames
Half of blinking cycle
Mode
12/39
Semiconductor - Character pitch register
Register Instruction register Character pitch register A0 H L D7 L D6 L D5 L D4 L D3 L L D2 L
MSM6255
D1 L (Hp - 1)
D0 H
(Vp - 1)
Hp represents the number of bits to be displayed among one byte display data sent from RAM. The value of Hp is the following five types.
Hp 4 5 6 7 8 D2 L H H H H D1 H L L H H D0 H L H L H
- Horizontal character number register
Register Instruction register Character number register A0 H L D7 L L D6 L D5 L D4 L D3 L (HN - 1) D2 L D1 H D0 L
Assuming that the total horizontal dot number of the display is nH, nH = Hp x HN, where HN = 2 to 128.
The maximum value of nH = 8 x 128 = 128 bytes = 1,024 dots. - Duty number register
Register Instruction register Time division register A0 H L D7 L D6 L D5 L D4 L D3 L D2 L D1 H D0 H
(NX - 1)
Nx = 2 to 256 - Cursor form register
Register Instruction register Cursor position register A0 H L D7 L D6 L D5 L D4 L D3 L D2 H D1 L D0 L
(Cpu - 1)
(Cpd - 1)
The cursor is displayed on the lines from Cpu to Cpd in the character display mode. The length of the cursor in the horizontal direction is equal to the character pitch in the horizontal direction, Hp. The cursor is not displayed in graphic mode. The relation between the cursor and Vp is as follows. 13/39
Semiconductor Font configuration of Hp = 7 and Vp = 8
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
MSM6255
Cpu = 8, Cpd = 8
Cpu = 7, Cpd = 8
Cpu = 2, Cpd = 6
Notes: (1) Setting of Cpu, Cpd > Vp is not available. (2) The cursor signal and pattern data are displayed subject to EX-OR. - Start address (lower) register
Register Instruction register Display start address register (lower byte) A0 H L D7 L D6 L D5 L D4 L D3 L D2 H D1 L D0 H
Start address (lower)
- Start address (upper) register
Register Instruction register Display start address register (upper byte) A0 H L D7 L D6 L D5 L D4 L D3 L D2 H D1 H D0 L
Start address (upper)
The display start address shows an address of the RAM which stores data displayed at the left end and the most upper position. The start address is composed of upper and lower 8 bits (16 bits in total). - Cursor address (lower) register
Register Instruction register Cursor address register (lower byte) A0 H L D7 L D6 L D5 L D4 L D3 L D2 H D1 H D0 H
Cursor address (lower)
- Cursor address (upper) register
Register Instruction register Cursor address register (upper byte) A0 H L D7 L D6 L D5 L D4 L D3 H D2 L D1 L D0 L
Cursor address (upper)
By this instruction, the value of the cursor address is written in the cursor address register. The cursor is displayed at the position specified by the cursor address register. 14/39
Semiconductor
MSM6255
HN RD7 Hp RD0
Vp
Cpu Cpd
V (Lower)
V (Upper)
Fig. 1 Cursor Address (Upper) Register
Table 2 Legend
Symbol Hp Vp HN V Cpu Cpd Name Horizontal pitch Vertical pitch Number of characters in one line Number of rows Cursor start position Cursor end position Meaning Pitch of characters in horizontal direction Pitch of characters in vertical direction Number of characters per line or number of words per line Display duty A position where the cursor starts display A position where the cursor stops display Value 4 - 8 dots 1 - 16 dots 2 - 128 characters 2 - 256 Line 1 - 16 Line 1 - 16
15/39
Semiconductor
MSM6255
- Built-in Bus Averter The bus averter which switches the address buses A0 - A15 of the CPU with the memory address buses of the refresh. The refresh memory addresses are output to MA0 - MA15 when the DIEN pin is set at high level and A0 - A15 are output to MA0 - MA15 when the DIEN pin is set at low level. - External Clock Operation An external clock enables the MSM6255 to operate when the DIV pin is set at high level. Input the external clock to XT.(Leave XT open.) When the DIV pin is set at low level, the IC enters the crystal oscillation mode. - Address Output Floating MA0 - MA15 and RA0 - RA3 become high impedance when the ADF pin is set at low level. MA0 - MA15 and RA0 - RA3 become normal impedance when the ADF pin is set at high level. - Power Down Function The chip select function becomes enabled for the segment driver by connecting the CEf pin to the ECLK input of the MSM5279. The power down function is valid only in 4-bit parallel output mode. - Refresh Memory Address (MA0 - MA15) Operation In the horizontal direction, MAxx is counted up at the falling edge of CHf. Upper side is addressed while CHf is set at low level and lower side is addressed while CHf is set at high level. MAxx is counted up even if it exceeds the number of horizontal display characters, but this does not affect the display since no data is being transferred at the time. The period in which the data transfer is suspended corresponds to eight characters. When the period passes, one horizontal cycle is completed and the next cycle is commenced. Memory address operation in the graphic mode is shown in Fig. 2 and that in the character mode is shown in Fig. 3.
16/39
Semiconductor Address configuration of display RAM
MSB MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 LSB MA0
MSM6255
HN 1 word 0000 0050 0001 0051 004E 009E 004F 009F
Suspension of data transfer
Upper
1EF0 1F40 1F90
1EF1 1F41 1F91
1F3E 1F8E
1F3F 1F8F
1FDE 1FDF
Lower
3E30
3E31
3E7E
3E7F
Fig. 2 Memory Address in Graphic Mode (640 x 200)
Note: "L" is output for RA0 - RA3.
17/39
Semiconductor
MSM6255
HN (Number of characters in horizontal display line)
Raster address 000 001 010 011 100 101 110 111 000 1 character 0000 0000 0001 0001 004E 004E 004F 004F Suspension of data transfer
Line 1
0000 0050
0001 0051
004E 009E
004F 009F
Line 2 Upper 111 0050 0051 009E 009F
000
0370
0371
03BE
03BF
Line 12
111 000
0370 03C0
0371 03C1
03BE 040E
03BF 040F
Line 13
111
03C0
03C1
040E
040F
Lower
000
0730
0731
077E
077F
Line 24
111
0730
0731
077E
077F
Note : Start address is 0000, 80 characters x 24 lines and Vp = 8
Fig. 3 Memory Address in Character Mode (80 characters x 24 lines)
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Semiconductor - Output Mode
MSM6255
Three kinds of modes, 1-bit serial, 2-bit parallel and 4-bit parallel, are available as output modes. Data flows of each mode are shown below.
Segment driver
Data shift UD0
Upper Lower
LCD panel
Segment driver
UD1 Data shift Fig. 4 1-Bit Serial Data Transfer
Data shift
UD1 UD0
Upper Lower
LCD panel
Data shift Fig. 5 2-Bit Parallel Data Transfer
UD2 UD3
19/39
Semiconductor
MSM6255
UD0 - UD3 CE
4
Upper LCD panel Lower
LD0 - LD3
4
Fig. 6 4-bit Parallel Data Transfer
Time charts corresponding to data transfers shown in Fig. 4 - Fig. 6 are shown in Fig. 7 - Fig. 9. fs, the dot clock, shown in Figs.7-9, is a signal inside the IC. For more information see "Relation between Reference Clock (fs) and External Clock" on page 601.
20/39
fs
Semiconductor
CH
MA0 - MA15 STAN STAM STAN+1 STAM+1
ENDN
ENDM
Suspension of data transfer
CLP
UD0 ENDN data STAN data
D7 6 5 4 3 2 1 D0
D7 6 5 4 3 2 1 D0 D7 6 5 4 3 2 1 D0
STAN+1 data
UD1 ENDM data
D7 6 5 4 3 2 1 D0
D7 6 5 4 3 2 1 D0 D7 6 5 4 3 2 1 D0
STAM data
STAM+1 data
STAN: STAM: ENDN: ENDM:
First memory address of one horizontal line in the upper side First memory address of one horizontal line in the lower side Last memory address of one horizontal line in the upper side Last memory address of one horizontal line in the lower side Fig. 7 1-bit Serial Data Transfer
MSM6255
21/39
fs
CH
Semiconductor
MA0 - MA15
ENDN
ENDM
STAN
STAM
STAN+1
STAM+1
Suspension of data transfer
CLP
UD0
D7
D5
D3
D1
D7
D5
D3
D1
D7
D5
D3
D1
UD1 D2
ENDN data STAN data
D6
D4
D0
D6
D4
D2
D0
D6
D4
D2
D0
STAN+1 data
UD2
D7
D5
D3
D1
D7
D5
D3
D1
D7
D5
D3
D1
UD3
ENDM data
D6
D4
D2
D0
D6
D4
D2
D0
D6
D4
D2
D0
STAM data
STAM+1 data
STAN: STAM: ENDN: ENDM:
First memory address of one horizontal line in the upper side First memory address of one horizontal line in the lower side Last memory address of one horizontal line in the upper side Last memory address of one horizontal line in the lower side Fig. 8 2-bit Parallel Data Transfer
MSM6255
22/39
fs
CH STAN Suspension of data transfer STAM STAN+1 STAM+1
Semiconductor
MA0 - MA15
ENDN
ENDM
ENDN+1
ENDM+1
CLP D3 D7 D3 D7 D3
UD3
D7
D3
D7
UD2
D6
D2
D6
D2
D6
D2
D6
D2
UD1 D1
D5
D1
D5
D5
D1
D5
D1
UD0 D0
D4
D0
D4
D4
D0
D4
D0
ENDN-1 data D3
ENDN data
STAN data D7 D3
STAN+1 data D7 D3
UD3
D7
D3
D7
UD2
D6
D2
D6
D2
D6
D2
D6
D2
UD1 D1
D5
D1
D5
D5
D1
D5
D1
UD0
D4
D0
D4
D0
D4
D0
D4
D0
ENDM-1 data
ENDM data
STAM data
STAM+1 data
MSM6255
Fig. 9 4-bit Parallel Data Transfer
23/39
Semiconductor
MSM6255
- Relation Between Duty and Number of Lines Number of lines is determined by Vr, number of lines in vertical direction(display duty). Number of lines = Vr x 2 Note: In the character display mode, number of lines should not be odd number.
- Calculation of Crystal Oscillation Frequency (fosc) Table 3 Calculation Formula of fosc
DIV L H Output mode q w q w Calculation formula of fosc FRP x (HN + 8) x Hp x Vr x 2 FRP x (HN + 8) x Vr x 4 FRP x (HN + 8) x Hp x Vr FRP x (HN + 8) x Vr x 2 Calculation exmaple (MHz) 9.856 2.464 4.928 1.232
Note: (1) Table 3 shows a calculation example assuming that FRP = 70 Hz, HN = 80, Hp = 8 and Vr = 100. However, the example of Hp = 4 to 7 in 4-bit parallel is not included. (2) Output mode q : Hp = 4 to 7 in 1-bit serial, 2-bit parallel and 4-bit parallel Output mode w : Hp = 8 in 4-bit parallel - Calculation of Character Clock (CHf) Frequency CH = FRP x (HN + 8) x Vr Example: Assuming FRP = 70 Hz, HN = 80 and Vr= 100, CHf = 1.62 (ms)
- Calculation of Shift Clock (CLP) Frequency Table 4 Calculation Formula of CLP
Output mode 1-bit serial 2-bit parallel 4-bit parallel Calculation formula of CLP RP x (HN + 8) x Hp x Vr FRP x (HN + 8) x Hp x Vr x 1/2 FRP x (HN + 8) x Hp x Vr x 1/4 Calculation exmaple (MHz) 4.928 2.464 1.232
Note: Table 4 shows a calculation example assuming that FRP = 70 Hz, HN = 80, Hp = 8 and Vr= 100.
24/39
Semiconductor - Relation Between Reference Clock (fs) and External Clock
DIV
MSM6255
XT fs Q XT T
XT
fs
(DIV = 1)
fs functions as a dot clock in LCDC and the dot counter inside the IC is counted up at the trailing edge of fs. The dot counter operates as a N-ary counter on a basis of HP and generates the character clocks (CHf). (Refer to the time charts Fig. 7 - 9 and Fig. 14.) - Access to the Display RAM In writing/reading the data to/from the display RAM, DIEN should be low level. By setting DIEN signal at low level, the address from the CPU are output from MA0 - MA15, and this enables the access to the display RAM. There are three methods of accessing display RAM from the CPU. (1) Direct access from CPU Display RAM is accessed directly from the CPU, irrespective of the condition of MSM6255 (refresh cycle or not). In this method, the RAM address changes to the CPU address when the display is on the screen. So, frequent access to the RAM causes flickering on the screen. (2) Access while BUSY signal is high BUSY signal indicates the period when the data transfer stops, and BUSY signal is set high when the data transfer stops. The period when BUSY signal is high corresponds to that of seven characters'. If display RAM is accesed during this period (when BUSY is high), the display on the screen does not flicker. Note: This method is effective when the size of screen is small. In the case of big size screen, 640 x 200 dots, 1character needs approx. 1.6ms. So, in this case, the period when BUSY is at high level is 11.2ms, which is impossible to write or read a lot of data. (3) Synchronized access (only for operating the IC by external clock) Refresh cycle and CPU cycle are alternately performed. So, there is not flickering on the screen and there is no need to sense the BUSY signal. When using this method, however, some external circuitry is necessary. The timing chart of this method is described in the Figure 10 below. 25/39
Semiconductor
MSM6255
CH TC DIEN CPU LCDC CPU LCDC CPU LCDC CPU LCDC TL
display RAM OUT tRAM
fetching the pattern data N tUDS M N+1 M+1
tUDH
Fig. 10 Basic Timing of Synchronized Access to Display RAM Legend TC TL tRAM tUDS tUDH : : : : : Period when the address bus is occupied by CPU Period when the LCDC fetches the refreshed data Refresh address delay time + memory access time Upper side data set-up time Upper side data hold time
When DIEN is high, MA0 - MA15 output address to the upper side when CHf is low and to the lower side when CHf is high. To perform synchronized access method, the timing between DIEN and CHf should be as described in Figure 10.
WR VDD PR PR PR PR
M-WR M-RD V-RAM SELECT
D
Q
D
Q
D
Q
D
Q
CL Q
CL Q
CL Q
CL Q
DIEN READY
DATA LATCH
Fig. 11 Wait Function Controlling Circuit Display RAM must meet the following condition: TL > tRAM + tUDS In writing data into the display RAM, LCDC should be synchronized so that the write pulse occurs during the period of TC. In reading the pattern data from the CPU, the data of display RAM should be latched first. Figure 11 shows the controlling circuit. 26/39
Semiconductor
MSM6255
- DIEN DIEN has to be generated when the display RAM is accessed by Synchronized access method. (1) When the LCD screen is not split into upper and lower ones If, for example, an LCD panel with a total of 64 dots in vertical direction is displayed at 1/64 duty, either the upper side data or the lower side data becomes unnecessary, and then the CHf signal can be used as a DIEN signal. (2) When the LCD screen is split into upper and lower ones If 4-bit parallel output mode is set and HP=8, the timing diagram of the dot clock and the character clock is as shown below.
XT (dot clock)
CH tCH
DIEN signal is generated by XT and CH. DIEN signal generating circuit is shown below.
DIEN CH XT(dot clock) DQ Q
When Hp 8 in the 1-bit serial, 2-bit parallel and 4-bit parallel mode, the relation between XT and CH should be referred to Figures 7 and 8. - ScrollPaging Scrollpaging is enabled by setting the display start address to the scroll address register. (1) Memory address of vertical scrollpaging Figure 2 shows the memory address when the start address is 0000. When the start address is set at 0050, the display will be vertically shifted by +1. By setting the starting address one by one, the screen will scroll vertically. paging will be performed by setting the start address as 3E80. (2) Memory address of horizontal scroll When the starting address is set at 0001 in Figure 2, the display on the screen will be shifted by +1 byte horizontally. The data shown as 004F in Figure 2 corresponds to the memory data in the 2nd line shown as 0050.
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Semiconductor
MSM6255
APPLICATION CIRCUITS
Interface With CPU
MSM6255 8085 WR RD IO/M
A1 - A 7
WR RD
Decoder
CS
AD0 - AD7
ALE HLDA A8 - A15
OC
DB0 - DB7 A0 - A15
MSM6255 Z80 WR RD IORQ
A1 - A 7
WR RD
Decoder
CS
D 0 - D7 A0 - A15
DB0 - DB7 A0 - A15
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Semiconductor
MSM6255
MSM6255 8086 WR RD
M/IO DT/R DEN AD0 - AD15 A16 - A19 Transceiver Latch BHE ALE
D0 - D15
A1 - A15
Decoder
CS
D1 - D7
DB0 - DB7 A0 - A15
A0 - A19
BHE
*Minimum mode
MSM6255 6800 2 VMA RD/WR RD WR
A1 - A15
Decoder
CS
D0 - D 7 A0 - A15
DB0 - DB7 A0 - A15
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CS DB0 - DB7 UD3 CLP CE DIEN RD0 - RD7 LIP FRP FRMB MSM 6698
~
RD WR UD0 4 bit MSM 5299C
Semiconductor
System Configuration
B
40H245
A
CPU
I/O
WR
Display RAM MSM6255
MA0 - MA15 LD0 - LD3 A0 - A15
Decoder
A0 - A15
MSM6255
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Fig. 12 System Configuration in Graphic Mode
CS UD0 UD3 RD0 - DB7 CLP CE RA0 - RA3 LIP MSM6255 FRMB DIEN DB0 - DB7 FRP MSM 6698
~
RD WR MSM 5299C 4 bit
Semiconductor
Character generator
CPU
DIEN
WR MA0 - MA15
Display RAM A0 - A15
Decoder
MSM6255
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Fig. 13 System Configuration in Character Mode
Semiconductor
Ts fs Memory address
N
N+1
N+2
STA
STA
STA
STA
STA
STA
STA
STA + 1
STA + 2
STA + 3
Start address LIP TLIP
CE
TCE
BUSY TBUSY FRP CH
CH
Fig. 14 Timing Chart During Suspension of Shift Clock CH = Ts x Hp Condition : 4-bit parallel output mode HP = 5 32/39 TLIP = 2CH TCE = CH TBUSY = 7CH MSM6255
Semiconductor
Line 1 Memory address
Suspension of shift clock
Line 2
****** **
** **** **
** **** **
** **** **
LIP
FRP
FRMB
X driver
Line N
Line 1
Line 2
Y1 Y driver Y2
---
YN
MSM6255
Fig. 15 Timing Chart of LIP, FRP and FRMB
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Semiconductor
MSM6255
LIP CLP
Counter (Inside the IC) 0 1 2 19 0
CEf Carry output of segment driver
Valid
Fig.16 Timing Chart of CLP and CEf
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HC257
50 pF
A15
X1
14
6.144 MHz
13
X2 +5V
12
1Y 2Y 3Y 4Y
M .RD M .WR IO.RD IO.WR
Semiconductor
50 pF
11
9
8
ADR- 5 ADR-14 ADR-13 ADR-12 ADR-11 ADR-10 ADR- 9 ADR- 8
G 1A 3B 2A 4B 1B 2B 3A 4A SEL(A) HC138 A B C Y0
1 2 3 4 5 6 7
80C85A
D7
6
HCT373
D Q LCDC-CS
5
4
+5V
3
2
51 kW
1
+5V D PR Q CL VRAMSEL
RESET SW
RST-IN
0
ADR-7 ADR-6 ADR-5 ADR-4 ADR-3 ADR-2 ADR-1 ADR-0 G2A G2B G1
2.2F +5V
ALE
OE
HCT245
A B
RD
DIR OE
D.BUS-7 D.BUS-6 D.BUS-5 D.BUS-4 D.BUS-3 D.BUS-2 D.BUS-1 D.BUS-0 +5V
WR
IO/M
PR D Q HC74 CL Q READY HC04
Figures 17-1, 17-2, and 18 show application circuits. In these examples, the size of LCD module is 640 x 200 dots. 4-bit data transfer is applied and Hp = 8. The synchronized access method is used as a method of access to the display VRAM.
CLK RSTOUT READY
CLK RES CLK-OUT
Fig. 17-1
MSM6255
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+5V RP Q HC74 Q CL CH Q RES D Q HC74 CL RP
D
RP D
Q
HC04
HC08
ADR-14
HC08
HC74
ADR-15
CL
Q
MSM5165
MSM5165
+5V
UD0 UD1 UD2 UD3 LD0 LD1 LD2 LD3 FRP FRMB LIP CE CIP
Semiconductor
M-WR HC08
HC00
HC08
M-RD RES HC04 CE1 WE OE HCT244 HC04 D0 A G1 G2 Y OE WE CE1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13
LCD
VRAMSEL READY
+5V
HC86
MSM6255
D
PR
Q
HC74
CL
Q
1 2 3 4 5 6 7
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
+5V HCT374
DIV ADF +5V
CLK-OUT Q D
HC32
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DIEN
HC32 OE
XT CS RD WR
HC32
HC32
HC32
HC04
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
ADR-0 ADR-1 ADR-2 ADR-3 ADR-4 ADR-5 ADR-6 ADR-7 ADR-8 ADR-9 ADR-10 ADR-11 ADR-12 ADR-13 ADR-14 ADR-15
D.BUS-0 D.BUS-1 D.BUS-2 D.BUS-3 D.BUS-4 D.BUS-5 D.BUS-6 D.BUS-7
CLK
LCDC-CS
IO-RD
IO-WR
MSM6255
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Fig. 17-2
CS DB0 - DB7 BUSY LS125 RD WR DIEN LS244 RD A "H" = A A12
~
DB0 - DB7
DB1
Semiconductor
RD WR MREQ
Y
RD0 - RD7
G A DO0 - DO7 A8 for CGROM LS245 CE OE A0 - A7 A11 DIR 1G 2G B
B
DQ CK LS74
RA0 - RA3
Z80
MSM6255
2764
4 I/O1 - I/O8 WE CE2 OE A0 - A12 CE1 A0 - A12 A0 - A12 CE1 CE1 OE OE A0 - A12 CE2 CE2 5V WE WE WE 5V 5V I/O1 - I/O8 I/O1 - I/O8 I/O1 - I/O8 5V CE2 OE CE1
DO0 ~ DO7
MAM5165RS (8K x 8 bit)
CE
OE
A0 - A12
MA0 - MA12 MA0 - MA15
30pF XT XT DIV 2.5 MHz
for software
5V 5V
A0 - A12 LS13B A11 - A15
Y0 Y5 Y7 G1 G2A G2B A~B
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 LS13B G1 G2A G2B A~B MA13 - MA
ADF MA12 - MA15
A0 - A15
A0 - A15 RES
RES
MSM6255
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Fig. 18
Semiconductor
MSM6255
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM6255
(Unit : mm) QFP80-P-1420-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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