View UPD4704_143328.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD4704
EXTENSION 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS
DESCRIPTION
The PD4704 is 8-bit up/down counters for extension of the PD4702 incremental encoder counter. They perform an up/down-count using an 8-bit width with a PD4702 carry or borrow signal as input. In addition, a carry output and borrow output are also provided for further extension of the count width, enabling extension to be performed in 8-bit units.
FEATURES
* 8-bit up/down counter for extension of PD4702 * Count data output controllable (latch and 3-state output) * Extension carry and borrow outputs * CMOS, single +5 V power supply
PIN NAMES
Up Down Reset STB OE CD0-7 Carry : Up-count input : Down-count input : Counter reset input : Latch strobe signal input : Output control signal input : Count data outputs : Carry pulse output
PIN CONFIGURATION (Top View)
Reset A B NC CD0 CD1 CD2 CD3
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD Carry Borrow STB OE CD7 CD6 CD5 CD4 NC
Borrow : Borrow pulse output
ORDERING INFORMATION
Part Number Package 20-pin plastic DIP 20-pin plastic SOP (300 mil) (300 mil)
NC VSS
PD4704C PD4704G
Document No. IC-3305A (2nd edition) (O. D. No. IC-8762B) Date Published April 1997 P Printed in Japan
(c)
1993
PD4704
BLOCK DIAGRAM
Reset
A Phase Discrimination Edge Detection B 8-Bit Up/Down Counter
Carry
Borrow
8-Bit Latch 3-State Output
STB OE
CD0-7
PIN FUNCTIONS
Pin Name Up Down D0 to 7
Input/Output Input
Function Up-count & down-count signal input pins Count is performed on rise of signal. Count data output pins. Activated when OE is "L", high impedance outputs when OE is "H". 8-bit counter carry signal output pin (active-low) 8-bit counter borrow signal output pin (active-low) 8-bit counter reset signal output pin Counter is reset when this pin is "H". Count data output control signal input pin Counter data output latch signal. Data is latched on the fall of STB, and is held while STB = "L". Power supply input pin Ground pin
Output (3-state) Output Output Input (Schmitt) Input Input
Carry Borrow RESET
OE STB
VDD GND
2
PD4704
TRUTH TABLE 1 (COUNTER BLOCK)
x : H or L UP x H H H L L H L L H DOWN x RESET H H L L L L L L Carry x x x x x x H L x x x x L H Borrow x Reset Reset Down-count Up-count Disabled (count undefined) Disabled (count undefined) Borrow output when count = 00H Carry output when count = 0FFH Remarks
TRUTH TABLE 2 (LATCH & OUTPUT BLOCKS)
x : H or L STB x x H L OE H L x x CD0 to CD7 Output disable (3-state) Output enable Data through (count value load) Data latch (count value retention)
3
PD4704
1. DESCRIPTION OF OPERATIONS
(1) Count operation The PD4704 is designed as 8-bit up/down counter for extension of the PD4702. The first-stage Carry output is connected to the UP input of the PD4704, and similarly, the Borrow output is connected to the DOWN input. A count is executed on the rising edge of the UP input or DOWN input. If the PD4704 is to be used alone, without being connected to the PD4702, either UP or the DOWN must be "H". If a count pulse is input to UP or DOWN while the other is "L", the count value may change. (2) Latch operation An R-S flip-flop is inserted in the latch circuit input as shown in Fig. 1, and when STB is changed from "H" to "L" while the UP or DOWN input is "L", the internal latch signal STB' remains at "H" until the end of the count operation. Therefore, latching is not performed during a count operation. If STB changes from "H" to "L" tSUDSTB1 (40 ns) or more after the falling edge of UP or DOWN, the post-count data is latched, and if STB changes from "H" to "L" within tSUDSTB2 (10 ns) after the falling edge of UP or DOWN, then conversely, the pre-count data is latched. Caution is required since, when UP or DOWN is "L" (during a count operation), the latch operation is kept waiting even if STB is changed from "H" to "L", and therefore if a reset is executed the latch contents will also be reset (see Figs. 2 and 3). Fig. 1 STB Input Circuit
From UP/DOWN Circuit
Count Clock
STB' STB
4
PD4704
Fig. 2 Relation Between STB Timing and Counter Value
UP/DOWN
STB
tSUDSTB1
tSUDSTB2
Pre-count value latched
Post-count value latched Either pre- or post-count value latched
Fig. 3 STB and RESET Timing
UP/DOWN
tSUDSTB1
tDUDCD
RESET STB
If STB changes from "H" to "L" and a reset is executed in this period, the latch is also reset.
(3) Carry & borrow outputs If the counter performs an up-count operation when the count value is 0FFH, an active-low pulse is output to the Carry output (the pulse width is virtually the same as the UP or DOWN pulse L period). Similarly, if the counter performs a down-count operation when the count value is 00H, an active-low pulse is output to the Borrow output. A Borrow pulse is also output if a down-count operation is performed while RESET is "H" (during a reset), and therefore, when a PD4704 is added, a reset must be executed at the same time.
5
PD4704
2. OPERATING PRECAUTIONS
As the PD4704 incorporates an 8-bit counter, a large transient current flows in the case of a count value which changes all the bits (such as 00H 0FFH or 7FH 080H). This will cause misoperation unless the impedance of the power supply line is sufficiently low. It is therefore recommended that a decoupling capacitor (of around 0.1 F) be connected between VDD and VSS right next to the IC as shown in Fig. 4. Fig. 4 Decoupling Capacitor
+5 V C VDD
PD4704
C : 0.1 uF tantalum electrolytic laminated ceramic capacitor, etc.
VSS
6
PD4704
ABSOLUTE MAXIMUM RATINGS (TA = 25 C, VSS = 0 V)
PARAMETER Supply voltage Input voltage Output voltage Operating temperature Storage temperature Permissible loss SYMBOL VDD VI VO Topt Tstg PD 500 (DIP) RATING -0.5 to +7.0 -1.0 to VDD +1.0 -0.5 to VDD +0.5 -40 to +85 -65 to +150 200 (SOP) UNIT V V V C C mW
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = +5 V 10 %)
RATING PARAMETER Input voltage low Input voltage high VIH Output voltage low Output voltage high Static consumption current Input current 3-state output leak current Dynamic consumption current Hysteresis voltage VOL VOH IDD II IOFF IDD dyn VH fIN = 16 MHz, CL = 50 pF Reset 0.2 Other than the above IOL = 12 mA IOH = -4 mA VI = VDD, VSS VI = VDD, VSS -1.0 -10 VDD - 0.8 50 1.0 10 12 2.2 0.45 V V V SYMBOL VIL VIH Reset 2.6 TEST CONDITIONS MIN. MAX. 0.8 V V UNIT
A A A
mA V
AC CHARACTERISTICS (TA = -40 to +85 C, VDD = +5 V 10 %)
PARAMETER Cycle Up Down Setup time Up/down switchover setupt time Reset time Output delay CD0 to 7 Output delay Output delay Float time Carry Borrow Output pulse width RESET STB Reset pulse width Setting time tSUDSTB2 10 ns tPWCB tPWRS tSUDSTB1 30 40 40 ns ns ns Output delay tDUDCB2 100 ns tSRSUD tSUDM tDRSCD tDUDCD tDOECD tDSTBCD tFOECD tDUDCB1 0 100 60 70 50 50 40 50 ns ns ns ns ns ns ns ns Input pulse width tPWUDH 35 ns SYMBOL tCYCT tPWUDL TEST CONDITIONS fin = 16 MHz MIN. 60 25 MAX. UNIT ns ns
7
PD4704
AC Timings Fig. 1 Up/Down Signal Input Timing
tCYCT tPWUDL UP/DOWN tCYCT tSUDM tPWUDL tPWUDH tPWUDH
Fig. 2 Count Data Output Timing
tPWRS tSRSUD
RESET
UP/DOWN tDRSCD CD0-CD7 Hi-Z tDOECD OE tSUDSTB1 STB tDSTBCD tDSTBCD tDUDCD Hi-Z tFOECD
Fig. 3 Carry/Borrow Signal Output Timing
tDUDCB1 UP/DOWN tDUDCB2
tPWCB Carry tDUDCB1 tPWCB Borrow tDUDCB2
Fig. 4 Strobe Signal Output Timing
tSUDSTB1 UP/DOWN tSUDSTB2
STB
8
PD4704
Consumption Current Measurement Circuit
Measurement Conditions A, B inputs fIN = 16 MHz A B D0 CL D1 CL VDD STB OE D7 CL 0.8 V STB input connected to VDD or OE input connected to VSS. Load on all outputs, CL = 50 pF. 2.6 V
AC Test Input Waveform
VIH
VIL VIH = 2.6 V (RESET input) VIH = 2.2 V (inputs other than RESET) VIL = 0.8 V Timing measurement is performed at 1.5 V.
*
3 state output
Output tDOECD 1.5 V Output 1.5 V 10 % VOL R = 1 k C = 50 pF tDFOECD VOH 90 % 0V VDD Output C VDD R R C
OE
1.5 V
9
PD4704
Sample Application Circuits 16-bit counter
8 Data Bus Incremental Rotary Encoder A Carry
8 UP Down D0 STB OE R D7
8
B Borrow D0 STB OE RESET R D7
PD4702
CSL CSH
PD4704
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
10
PD4704
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product. Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. TYPES OF SURFACE MOUNT DEVICE For more details, refer to our document "Semiconductor Device Mounting Technology Manual" (IEI-1207).
PD4704G
Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 C or below, Reflow time: 30 seconds or below (210 C or higher), Number of reflow process: 2, Exposure limit*: None Peak package's surface temperature: 215 C or below, Reflow time: 40 seconds or below (200 C or higher), Number of reflow process: 2, Exposure limit*: None Solder temperature: 260 C or below, Flow time: 10 seconds or below, Number of flow process: 1, Exposure limit*: None Terminal temperature: 300 C or below, Flow time: 10 seconds or below, Exposure limit*: None Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating method
q
*
Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 C and relative humidity at 65 % or less.
Note Do not apply more than a single process at once, except for "Partial heating method".
TYPES OF THROUGH HOLE MOUNT DEVICE
PD4704C
Soldering process Wave soldering Soldering conditions Solder temperature: 260 C or below, Flow time: 10 seconds or below Symbol
REFERENCE
Dcodument name NEC semiconductor device reliability/quality control system Quality grade on NEC semiconductor devices Semiconductor device mounting technology manual Semiconductor device package manual Guide to quality assurance for semiconductor devices Semiconductor selection guide Document No. IEI-1212 IEI-1209 IEI-1207 IEI-1213 MEI-1202 MF-1134
11
PD4704
20PIN PLASTIC DIP (300 mil)
20 11
1
A I
10
K P L
J
H G
F B D N
M
C M R
NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N P R
MILLIMETERS 25.40 MAX. 1.27 MAX. 2.54 (T.P.) 0.500.10 1.1 MIN. 3.50.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 7.62 (T.P.) 6.4 0.25 +0.10 -0.05 0.25 0.9 MIN. 0~15
INCHES 1.000 MAX. 0.050 MAX. 0.100 (T.P.) 0.020 +0.004 -0.005 0.043 MIN. 0.1380.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.300 (T.P.) 0.252 0.010 +0.004 -0.003 0.01 0.035 MIN. 0~15
P20C-100-300A,C-1
12
PD4704
20 PIN PLASTIC SOP (300 mil)
20 11 detail of lead end
1 A
10 H
G
P I
J
F
K
E
C D
NOTE
N M
M
B
L
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 13.00 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 -0.05 0.10.1 1.8 MAX. 1.55 7.70.3 5.6 1.1 0.20 +0.10 -0.05 0.60.2 0.12 0.10 3 +7 -3
INCHES 0.512 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 -0.003 0.0040.004 0.071 MAX. 0.061 0.3030.012 0.220 0.043 0.008 +0.004 -0.002 0.024 +0.008 -0.009 0.005 0.004 3 +7 -3
Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
P20GM-50-300B, C-4
13
PD4704
[MEMO]
14
PD4704
[MEMO]
15
PD4704
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

▲Up To Search▲

Price & Availability of UPD4704

	To Download UPD4704 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .