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CXA1951AQ
GPS Down Converter
Description The CXA1951AQ is an IC developed as a GPS down converter, featuring low current consumption and small package. This IC is suitable for the mobile GPS (Global Positioning System). Features * Includes all functions required for the GPS converter * Total gain: 100 dB or more * Operating supply voltage range: 2.7 to 5.5 V * Low current consumption: ICC = 30 mA (Typ. at VCC = 3 V) * Excellent temperature characteristics Applications GPS (Global Positioning System) Structure Bipolar silicon monolithic IC 40 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25 C) * Supply voltage VCC 7.0 * Operating temperature Topr -40 to +85 * Storage temperature Tstg -65 to +150 * Allowable power dissipation PD 200 Operating Conditions Supply voltage
V C C mW
VCC
2.7 to 5.5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E96743-TE
CXA1951AQ
Block Diagram and Pin Configuration
LIM DEC2
LIM DEC1
LIM VCC
IF DEC2
IF DEC1
LIM IN
IF OUT
IF VCC
IF IN2
22
30 LIM OUT 31 LIM GND 32 N.C 33 REF INV 34 REF IN 35 PLL GND 36 FC 37 TEST OUT 38 LOCK DET 39 PLL VCC 40
29
28
27
26
25
24
23
21 20 IF GND 19 RF OUT2 18 RF OUT1 17 RF VCC 16 RF IN2
1/4 or 1/6 PLL
IF IN1
15 RF IN1 14 RF GND 13 RF GND 12 OSC DEC 11 OSC VCC 10
1/338 or 1/570
OSC
1
NSW
2
CP OUT
3
N.C
4
OSC GND
5
OSC GND
6
OSCB1
7
OSCE1
8
OSCE2
9
OSCB2
--2--
OSC GND
CXA1951AQ
Pin Description Pin No. Symbol Pinvoltage
VCC 40k 200
Equivalent circuit
Description
1
NSW
--
1
20k 40k 81k GND VCC
Internal PLL frequency division value switching
200
2
CPOUT
--
2
Charge pump output
GND
3, 33 NC 4, 5, OSC GND 10
-- 0V
VCC 1.6k 1k 1k 1.6k
Not connected Ground for the internal oscillator
6 9 7 8
OSCB1 OSCB2 OSCE1 OSCE2
2.5 V 1.7 V 1.7 V 2.5 V
6 7
12k GND
9 8
12k
Connects the internal oscillator resonator. Connects to main counter input via the internal buffer.
11
OSC VCC
3V
12
OSC DEC
1.7 V
13, 14 RF GND
0V
VCC
Internal oscillator power supply Connects decoupling capacitor for the internal oscillator bias power supply RF amplifier ground
15, 16
RF IN1 RF IN2
1.6 V 1.6 V
15 16 12k 12k GND
RF amplifier input. When using as a single input, ground Pin 16 via the capacitor.
--3--
CXA1951AQ
Pin No. 17
Symbol RF VCC
Pinvoltage 3V
Equivalent circuit
Description RF amplifier power supply
VCC 19
2k 18
18, 19
RF OUT1 RF OUT2
-- --
RF amplifier mixer output
GND
20
IF GND
0V
VCC
IF amplifier ground
21, 22
IF IN1 IF IN2
1.9 V 1.9 V
IF amplifier input
21 990 22 990 99k 200 99k
23, 24
IF DEC1 IF DEC2
1.9 V 1.9 V
200 GND 23 VCC 990 25 24
IF amplifier decoupling
25
IF OUT
2.7 V
IF amplifier mixer output
GND
26 27
IF VCC LIM VCC
3V 3V
VCC
IF amplifier power supply Limiter buffer power supply
28
LIM IN
2.1 V
200 28 1k 1k 96k 29
Limiter input
LIM DEC1 29, 30 LIM DEC2
2.1 V 2.1 V
30 200 96k GND
Limiter decoupling
--4--
CXA1951AQ
Pin No.
Symbol
Pinvoltage
VCC
Equivalent circuit
Description
31
LIM OUT
31
Limiter buffer output
GND
32
LIM GND
0V
VCC
34
REF INV
High: 2.2 V Low: 2.0 V
39.6k 200 35 200 34 39.6k
35 36
REF IN PLL GND
2.1 V 0V
GND
Limiter buffer ground Reference frequency signal output. The reference frequency signal can also be made by connecting this pin and Pin 35 with a crystal oscillator to configure an oscillator. Reference frequency input and reference counter input PLL ground
VCC 81k 200
37
FC
--
37 100k 100k GND
Switching for the charge pump output status and for the signal output to Pin 38
VCC
38
High: 2.2 V TEST OUT Low: 2.0 V
200 38
Output of the frequency division signal by the counter
GND
--5--
CXA1951AQ
Pin No.
Symbol
Pinvoltage
VCC
Equivalent circuit
Description
39
LOCK DET
High: 2.2 V Low: 0.1 V
200
39
Lock detection signal output
GND
40
PLL VCC
3V
PLL power supply
--6--
CXA1951AQ
Electrical Characteristics Item Current consumption Front-end conversion gain 2nd mixer conversion gain Limiter gain Limiter output level Input High current FC Input Low current Input High current NSW Input Low current Charge pump output H current L LOCK DET output H voltage L 1st IF output resistance 1st IF input resistance 2nd IF output resistance Limiter input resistance Symbol ICC CGmix1 Measurement conditions fin = 1575.42 MHz, -60 dBm fout = 20.46 MHz fosc = 1554.96 MHz, -10 dBm fin = 20 MHz, -60 dBm fref = 16 MHz, -10 dBm fin = 4 MHz, -80 dBm fin = 4 MHz, -30 dBm Pin = VCC PIN = GND Pin = VCC PIN = GND Vcpout = VCC/2 Vcpout = VCC/2 Load current = 0.1 mA Load current = 0.1 mA Balanced output Single input Single output Single input Min.
(VCC = 3 V, Ta = 25 C) Typ. 30 16 Max. 40 Unit mA dB
14
CGmix2 PGlim Volim IIH IIL IFCin IFCin IOH IOL VOH VOL Romix1 Rimix2 Romix2 Rilim
24.5 59 0.7 -16.5 -36 -3 2 1.4 0.84 0.69 0.84
26.5 63 0.75 9.5 -11.5 25 -25 -2 2
dB dB Vp-p A A A A mA mA V mV k k k k
0.8 14 36
3 500 2.6 1.56 1.3 1.56
2 1.2 1 1.2
--7--
CXA1951AQ
Design Reference Values Item Noise figure 1st IF output capacitance 1st IF input capacitance 2nd IF output capacitance Limiter input capacitance IF amplifier band width Symbol NF Measurement conditions f = 1.58 GHz DBS measurement Balanced output Single input Single output Single input Input Level = -60 dBm Min.
(VCC = 3 V, Ta = 25 C) Typ. 7 2 2 2 2 41 Max. Unit dB pF pF pF pF MHz
BWif
2k : 50 Noise Source Matching Circuit 100p RF MIX 1n IN 100p OUT 1n NF Meter
NF Measurement
--8--
CXA1951AQ
Electrical Characteristics Measurement Circuit
VCC 68 51 4.7 100n 1n
VCC 68
4.7 1n 51
10n 100n 30 0.1 31 32 N. C 33 10n 34 51 35 10n 36 37 38 39 68 VCC 4.7 1n 40 11 1n 4.7 1/4 or 1/6 PLL 1/338 or 1/570 15 10n VCC 14 13 OSC 12 100n 68 VCC 51 16 100p 17 1n 4.7 20 10n 19 VCC 18 68 VCC 29 100n 28 27 26 100n 25 24 10n 23 10n 22 10n 21
1
2
3
N. C
4
5
6
1n
7
1n
8
9
1n
10
VCC
--9--
CXA1951AQ
Application Circuit
L7, L8, C10 : Jumper L9, C9 : Open LQH1NR56K04/LQH1NR47K04 LQH3N331J04/LQS33N220G04 VCC L10 330/22 C17 82p C11 L6 0.56/0.47 51p/62p L5 0.56/0.47 10n C12 21 20 19 18 17 1n C6 35 CN2 C26 10n 36 37 38 39 47 40 C27 1/4 or 1/6 CXA1951AQ 15 f = 1575.42MHz PLL 1/338 or 1/570 OSC Lock detect (1521fo/1520fo) 12 1n 11 C3 14 3p 13 TZC03P060A110 100n C37 C4 100p 16 C5 100p 68 L3 LQS33N680G04 RF input LQP21A3N3J04 CN1 3.9n CV1 L2 4.7 C7 C8 4.7
100n
100n
LQS33N680G04 68 L11 C23 L12 4.7 LQS33N680G04 68 1M R1 0.1 31 32 NC 33 34
100n
100n
C18
C18
C15
C14 10n C13 23 22
4.7
4.7
10n
10n
C22 30
C21 29 28
(19fo/20fo)
C20 27 26
C19 25 24
0.1 C25 IC2 C24 Output (fo/4fo)
TC7SU04F
68 L4
18.414 or 16.368MHz TCXO (18fo/16fo) input
SW2 Test output
100 R2
1
100 fo/4fo SW1 R3
2
10n
3
NC
4
5
6
7
C35
8
9
10
4.7 C2
C32
100p L14 D1
1p
100p L15 D1
C33
10n
680
51k
51k
C29
1T365 1T365
10n
C28
0 R5
68 L1
68 L13 LQS33N680G04
R4 680
R4 1n C30
R6 R7 2.4k 1.5n C31 R8 VCC
C1 4.7
Notice: Two component values are indicated, the order is depending on the output frequency. The first value is as for 'fo output' and the second value is as for `4fo output'.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
0
--10--
LQS33N680G04
CXA1951AQ
Description of Operation This IC down-converts the GPS (Global Positioning System) frequency of 1.57542 GHz to fo (fo: 1.023 MHz) or 4fo. The internal configuration is divided into the analog block, consisting of the amplifier and mixer, and the digital block (including limiter), which forms the PLL. The two-stage analog block has an external filter; it converts the frequency and amplifies the signal. The PLL frequency division ratio can be switched in the digital block in order to down-convert the output signal to fo or 4fo. 1. Oscillator Transistor and bias circuits are incorporated in this IC. A Colpitts or Hartley oscillator can be configured by adding an external resonator. Also, the oscillator is a paired circuit so as to enable balanced output.
IC
6
7
8
9
Example of Colpitts Oscillator Configuration (one side)
IC
6
7
8
9
CP
Example of Balanced Configuration A varactor (variable capacitance) diode, as shown by the dotted line, is added to this IC to configure a VCO, and the resonant frequency is varied depending on the control voltage of Pin 2 (charge pump output) to CP.
--11--
CXA1951AQ
2. 1st IF Output Pins 18 and 19 are open collector outputs. The bias signal is supplied by the coils, and the output is connected to the 2nd mixer input Pins 21 and 22 via the filter. Use a capacitor to cut direct current. Decoupling for Pins 23 and 24 should be done as close to the IC as possible.
Filter
24
23
22
21
20
When fo is selected for IF, the frequency here is 19fo. When 4fo is selected for IF, the frequency here is 20fo.
19
VCC
18
3. 2nd IF Output Pin 25 is emitter follower output. After passing via the filter, the direct current is cut, and input is to the limiter input Pin 28. fo or 4fo is output from the limiter output Pin 31. (Pin 31 is emitter follower output.) Decoupling for Pins 29 and 30 must be done as close to the IC as possible.
Filter
30
29
28
25
IF output (fo/4fo)
31
--12--
CXA1951AQ
4. NSW (Pin 1) The internal counter frequency division value is determined by connecting this pin to VCC or GND when selecting fo or 4 fo for IF, as shown in the table below. IF NSW VCO counter Reference frequency counter fo VCC 338 frequency division 4 frequency division 4fo GND 570 frequency division 6 frequency division
5. CPOUT (Pin 2) A current output charge pump configures an external loop filter for VCO control voltage.
R2
2
R1 C1 C2
6. FC (Pin 37) This pin performs two functions when connected to VCC or GND; CPOUT (Pin 2) output status switching and TEST OUT (Pin 38) selector switch. (See Table 1) 7. TEST OUT (Pin 38) This is the monitor pin for the internal counter frequency division output. The frequency division signals for VCO counter and reference frequency counter can be switched depending on FC status. (See Table 1) FC to VCC CPOUT TESTOUT L fr Z fr H fr Table 1 Z: High-impedance H: High L: Low fr: Reference frequency counter output frequency fm: VCO counter output frequency FC to GND CPOUT TESTOUT H fm Z fm L fm
fr > fm fr = fm fr < fm
8. LOCK DET (Pin 39) This pin detects PLL lock status. When PLL is not locked, the pin voltage is not set; when locked, it is 2V DC. Note) * The voltages mentioned are for supply voltage of 3 V, load current of 100 A. * A thin pulse will be observed on monitoring this pin with an oscilloscope, but this is normal.
--13--
CXA1951AQ
9. REF IN (Pin 35) and REF INV (Pin 34) The signal input from the external oscillator to REF IN can be used as the reference signal. Further, a reference signal can be generated by connecting a crystal oscillator between Pin 35 and Pin 34. (1) Example of reference signal generated by the external oscillator As shown in the figure below, input to RFIN via the capacitor to use the external oscillator signal as the reference signal.
34 35
(2) Example of reference signal generated by the crystal oscillator As shown below, connect the crystal oscillator between Pin 34 and Pin 35, making sure that the oscillation stability, etc. is satisfactory. Further, the capacitance ratio of CI and CO should be 1 to 2 : 1 (CI : CO). Select the capacitance values so that the serial capacitance of CI and CO may be the load capacitance specified by the crystal oscillator.
34 35
CO
Xtal
CI
10. Power supply pin and OSC DEC (Pin 12) decoupling This IC has five power supply and ground systems, due to the following reasons: 1) It handles high frequency signals. 2) The total gain is high. (100 dB or more) 3) It combines analog and digital blocks. Therefore, it is absolutely necessary to decouple these power supply lines as close to the IC as possible. When necessary, insert the inductor (about 6.8 ) in series in the power supply line.
VCC GND
As short as possible L C
Power supply
OSC DEC is the internal reference voltage decoupling pin, and must be grounded with a capacitor (about 100 nF).
Notes on Operation Make sure to take measures for static electric damage because the high frequency signals are handled so that protection elements are omitted from this IC.
--14--
CXA1951AQ
2nd MiXer BW (O/P)
6.5MHZ@-3dB 30 25
2nd MiXer Conversion Gain
VCC = 3.0V fIF2 = 4.092MHz
26
CG [dB]
CG [dB]
23
VCC = 2.7V fin = 20.368MHz PLo = -10dBm Pin = -60dBm fLo = variable 1 f output [MHz] 10 100
20 15 10 1 75C 25C 0C 40C 10 fIF1 [MHz] 100
0.1
Lim Amp Gain
65 60 20 0
F/E 2-signal characteristics
P - 1dBm -28dBm IP3 IIP3 = -15dBm
Gain [dB]
50 45 40 35 30 1 10 Frequency [MHz] 102 VCC = 3.0V Input Level = -80dBm 25C 0C -40C 85C
Pout [dBm]
55
-20 -40 -60 -80 -100 -100 -80 -60 VCC = 2.7V fRF = 1574.42MHz fRF2 = 1575.42MHz fref = 16.368MHz Pref = -10dBm N = 190 -40 -20 Pin [dBm] 0 20
VCC vs. Current consumption
40 19 Ta = 25C 35 35 25 20 7 15 2.5 3 3.5 4 4.5 5 5.5 6 5 1450 17
Front End conversion GAIN, NF
Current consumption [mA]
CG, NF [dB]
15 13 11 9
VCC = 3V Ta = 25C CG NF
1500
1550
1550
1650
1700
VCC [V]
Frequency [MHz]
--15--
CXA1951AQ
Package Outline
Unit : mm
40PIN QFP (PLASTIC)
9.0 0.4 + 0.4 7.0 - 0.1 30 21
+ 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1
31
20
A
40 1 0.65 + 0.15 0.3 - 0.1 + 0.15 0.1 - 0.1
11
10 0.12 M
0.5 0.2
(8.0)
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.2g
DETAIL A SONY CODE EIAJ CODE JEDEC CODE QFP-40P-L01 QFP040-P-0707
--16--

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