View UPC1935_152792.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
BiCMOS INTEGRATED CIRCUIT
PC1935
DC-DC CONVERTER CONTROL IC
DESCRIPTION
The PC1935 is a low-voltage input DC-DC converter control IC that can configure a three-output (step-up x 2, inverted output x 1) DC-DC converter at an input voltage of 3, 3.3, or 5 V. Because of its wide operating voltage range, this IC can also be used to control DC-DC converters using an AC adapter for input.
FEATURES
* Low supply voltage: 2.5 V (MIN.) * Operating voltage range: 2.5 to 20 V (breakdown voltage: 30 V) * Can control three output channels. * Timer latch circuit for short-circuit protection. * Ceramic capacitor with low capacitance (0.1 F) can be used for short-circuit protection. * Dead times of channels 2 (step-up) and 3 (inverted output) can be set from external resistors. Dead time of channel 1 (step-up) is internally fixed to 85 %. * Soft start of each channel can be set independently. * Each channel can be turned ON/OFF independently.
ORDERING INFORMATION
Part Number Package 16-pin plastic TSSOP (5.72 mm (225))
PC1935GR
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. G13418EJ3V0DS00 (3rd edition) Date Published March 2000 NS CP (K) Printed in Japan
The mark 5 shows major revised points. 1998
PC1935
BLOCK DIAGRAM
Channel 3: for inversion DTC3 16 Il3 15 FB3 14 OUT3 13 DTC2 12 Il2 11 Channel 2: for step-up FB2 10 OUT2 9
- + - - +
- + + + -
Internal fixed voltage
Internal fixed voltage
Soft start select switch
+ - +
Internal fixed voltage
-
Reference voltage section
Oscillation section
Timer latch for short-circuit protection section
+
Internal fixed voltage 6 7 FB1 Channel 1: for step-up 8 OUT1
1 VCC
2 VREF
3 RT
4 GND
5 DLY
II1
2
Data Sheet G13418EJ3V0DS00
PC1935
PIN CONFIGURATION (Top view)
16-pin plastic TSSOP (5.72 mm (225)) * PC1935GR
VCC VREF RT GND DLY II1 FB1 OUT1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
DTC3 II3 FB3 OUT3 DTC2 II2 FB2 OUT2
PIN FUNCTIONS
Pin No. 1 2 3 4 5 Symbol VCC VREF RT GND DLY Power supply Reference voltage output Frequency setting resistor connection Ground Short-circuit protection/channel 1 soft start capacitor connection 6 7 8 II1 FB1 OUT1 Channel 1 error amplifier inverted input Channel 1 error amplifier output Channel 1 open-drain output 14 15 16 FB3 II3 DTC3 Channel 3 error amplifier output Channel 3 error amplifier inverted input Channel 3 dead time setting Function Pin No. 9 10 11 12 13 Symbol OUT2 FB2 II2 DTC2 OUT3 Function Channel 2 open-drain output Channel 2 error amplifier output Channel 2 error amplifier inverted input Channel 2 dead time setting Channel 3 open-drain output
Data Sheet G13418EJ3V0DS00
3
PC1935
CONTENTS 1. ELECTRICAL SPECIFICATIONS ................................................................................................................ 5 2. CONFIGURATION AND OPERATION OF EACH BLOCK.................................................................... 11
2.1 Reference Voltage Generator ...........................................................................................................................12 2.2 Oscillator ...........................................................................................................................................................12 2.3 Under Voltage Lock-out Circuit ........................................................................................................................12 2.4 Error Amplifiers.................................................................................................................................................12 2.5 PWM Comparators............................................................................................................................................12 2.6 Timer Latch-Method Short Circuit Protection Circuit ....................................................................................13 2.7 Output Circuit....................................................................................................................................................13
3. NOTES ON USE........................................................................................................................................ 14
3.1 Setting the Output Voltage ...............................................................................................................................14 3.2 Setting the Oscillation Frequency ...................................................................................................................15 3.3 Preventing Malfunction of the Timer Latch-Method Short Circuit Protection Circuit..................................15 3.4 Connecting Unused Error Amplifiers ..............................................................................................................16 3.5 ON/OFF Control.................................................................................................................................................17 3.5.1 Channel 1 (for step-up) ............................................................................................................................17 3.5.2 Channel 2 (for step-up) ............................................................................................................................18 3.5.3 Channel 3 (for inverted output) ................................................................................................................19 3.6 Maximum Duty Limit .........................................................................................................................................20 3.7 Notes on Actual Pattern Wiring........................................................................................................................20
4. APPLICATION EXAMPLE ......................................................................................................................... 21
4.1 Application Example.........................................................................................................................................21 4.2 List of External Parts ........................................................................................................................................22
5. PACKAGE DRAWING ................................................................................................................................ 23 6. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 24
4
Data Sheet G13418EJ3V0DS00
PC1935
1. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (unless otherwise specified, TA = 25 C)
Parameter Supply voltage Output voltage Output current (open drain output) Total power dissipation Operating ambient temperature Storage temperature Symbol VCC VO IO PT TA Tstg Ratings 30 30 21 400 -20 to + 85 -55 to + 150 Unit V V mA mW C C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter Supply voltage Output voltage Output current Operating temperature Oscillation frequency Symbol VCC VO IO TA fOSC -20 20 MIN. 2.5 0 TYP. MAX. 20 20 20 +85 800 Unit V V mA C kHz
Caution
The recommended operating range may be exceeded without causing any problems provided that the absolute maximum ratings are not exceeded. However, if the device is operated in a way that exceeds the recommended operating conditions, the margin between the actual conditions of use and the absolute maximum ratings is small, and therefore thorough evaluation is necessary. The recommended operating conditions do not imply that the device can be used with all values at their maximum values.
Data Sheet G13418EJ3V0DS00
5
PC1935
Electrical Characteristics (unless otherwise specified, TA = 25 C, VCC = 3 V, fOSC = 100 kHz)
Block Under voltage lock-out section Reference voltage section Parameter Start-up voltage Operation stop voltage Hysteresis voltage Reset voltage (timer latch) Reference voltage Line regulation Load regulation Temperature coefficient Oscillation section fOSC setting accuracy fOSC total stability Symbol VCC (L-H) VCC (H-L) VH VCCR VREF REGIN REGL VREF/T fOSC fOSC Conditions IREF = 0.1 mA IREF = 0.1 mA IREF = 0.1 mA IREF = 0.1 mA IREF = 1 mA 2.5 VVCC20 V 0.1 mAIREF1 mA -20 CTA+85 C, IREF = 0 A RT = 18 k -20 CTA+85 C, 2.5 VVCC20 V Duty setting section Input bias current Channel 1 maximum duty Channel 1 soft start time Low-level threshold voltage IBD DMAX. tSS VTH (L) CDLY = 0.1 F Duty = 0 % (channels 1 and2) Duty = 100 % (channel 3) High-level threshold voltage VTH (H) Duty = 100 % (channel 2) Duty = 0 % (channel 3) Error amplifier section Input threshold voltage Input bias current Open loop gain Unity gain Maximum output voltage (+) Maximum output voltage (-) Maximum sink current Output source current Output section Output ON voltage Rise time Fall time Short-circuit protection section UV sense voltage Source current on short-circuiting Delay time Overall Circuit operation current Input sense voltage VITH IB Av funity VOM VOM
+ -
MIN.
TYP. 1.57 1.5
MAX.
Unit V V mV V
30
70 1.0
2.0
2.1 2 1 0.5
2.2 12.5 7.5
V mV mV %
-20 -30
+30 +50
% %
(Channels 2 and 3 only) 85 50 1.2
1.0
A
% ms V
1.6
V
0.285 -100 VO = 0.3 V VO = 0.3 V IO = -45 A IO = 45 A VFB = 0.5 V VFB = 1.6 V RL = 150 RL = 150 RL = 150 Channels 1 and 2 Channel 3 1.75 0.5 0.8 1.6 70
0.3
0.315 +100
V nA dB MHz V
80 1.5 2 0.02 1.4 -70 0.2 50 50 1.9 0.63 0.8 2.05 0.75 0.85 2.7 -45 0.6 0.5
V
IOsink IOsource VOL tr tf VTH1, VTH2 VTH3 VUV IOUV tDLY ICC
A A
V ns ns V V V
1.0 CDLY = 0.1 F VCC = 3 V 1.8
1.6 50 3.1
A
ms
5.1
mA
Caution Connect a capacitor of 0.01 to 10 F to the VREF pin.
2
PC1935
4
CREF = 0.01 to 10 F
6
Data Sheet G13418EJ3V0DS00
Timing Charts (sequence operation of power application channel 1 channel 2 channel 3)
FB1
Channel 1 DLY
OUT1 Channel 1 starts.
OFF
ON
FB2
Data Sheet G13418EJ3V0DS00
Channel 2 DTC2
OUT2 Channel 2 starts.
OFF
ON
DTC3
Channel 3 FB3
OUT3 Channel 3 starts.
OFF ON
PC1935
7
PC1935
Typical Characteristic Curves (unless otherwise specified, VCC = 3 V, fOSC = 100 kHz, TA = 25 C) (Nominal)
PT vs TA 0.5
Total power dissipation PT (W)
VREF vs VCC 2.5
Reference voltage VREF (V)
IREF = 0 A
0.4 0.3 0.2 0.1 0 312.5 C/W
2.0 1.5 1.0 0.5 0
0 25 50 75 100 125 150 Operating ambient temperature TA (C)
0
1 2 3 4 Supply voltage VCC (V)
5
VREF vs TA 2.13
Reference voltage VREF (V)
fOSC vs RT 1000
Oscillation frequency fOSC (kHz)
IREF = 0 A
2.12 2.11 2.10 2.09 2.08 2.07 -25 0 25 50 75 100 Operating ambient temperature TA (C) fOSC vs TA
100
10
1
1
10 Timing resistance RT (k)
100
VOL vs IO 0.5
Output ON voltage VOL (V)
Oscillation frequency accuracy fOSC (%)
8
RT = 18 k
4
0.4 0.3 0.2 0.1 0
0
-4
-8 -25 0 25 50 75 100 Operational ambient temperature TA (C)
0
2
4 6 8 10 12 14 16 18 20 Output current IO (mA)
8
Data Sheet G13418EJ3V0DS00
PC1935
VOL vs TA 0.4 90 DMAX. vs RT
Channel maximum duty DMAX. (%)
IO = 20 mA
Output ON voltage VOL (V)
0.3
80
0.2
70
0.1
60
0 -25 0 25 50 75 100 Operating ambient temperature TA (C) VTH (H) vs TA
50 1 10 Timing resistance RT (k) VTH (L) vs TA 100
High-level threshold voltage VTH (H) (V)
RT = 18 k 1.62
Low-level threshold voltage VTH (L) (V)
1.64
1.24 RT = 18 k 1.22
1.60
1.20
1.58
1.18
1.56 -25 0 25 50 75 100 Operating ambient temperature TA (C) tSS vs CDLY 600
1.16 -25 0 25 50 75 100 Operating ambient temperature TA (C) tDLY vs CDLY 600 500 400 300 200 100
500 400 300 200 100
Short-circuit protection circuit delay time tDLY (ms)
Channel soft start time tSS (ms)
0 0.2 0.4 0.6 0.8 1 DLY pin capacitor capacitance CDLY ( F)
0
0.2 0.4 0.6 0.8 1 DLY pin capacitor capacitance CDLY ( F)
Data Sheet G13418EJ3V0DS00
9
PC1935
tDLY vs TA 60 CDLY = 0.1 F 50 80 135 90 45 Av 20 0 -20 100 0 100 Av, vs f 180
Delay time tDLY (ms)
30 20 10 0 -25 0 25 50 75 100 Operating ambient temperature TA (C) ICC vs VCC 4
Gain Av (dB)
40
60 40
-45 -90 10 M
1k
10 k 100 k 1 M Frequency f (Hz) ICC vs TA
5
Circuit operation ICC (mA)
Circuit operation ICC (mA)
3
4 3 2 1 0 -25 0 25 50 75 100 Operating ambient temperature TA (C)
2
1
0
0
5
10 15 20 25 Supply voltage VCC (V)
30
10
Data Sheet G13418EJ3V0DS00
Phase (deg)
PC1935
2. CONFIGURATION AND OPERATION OF EACH BLOCK
Figure 2-1 Block Diagram
(common to each channel) 3 RT
Oscillation section FB1 II1 7 6 Error amplifier 0.3 V DTC2 FB2 II2 12 10 11 Error amplifier 0.3 V DTC3 FB3 II3 16 14 15 Error amplifier 0.3 V VREF 2
8
OUT1
PWM comparator
Output section
9
OUT2
PWM comparator
Output section
13
OUT3
PWM comparator Under voltage lock-out section
Output section
VCC
1
Reference voltage section
Dead time setting: 85 % (internally fixed)
SCP comparator Q1 1.9 V 0.63 V Q2
S
Q 4 Q GND
DLY
Soft start select switch 5 CDLY
Timer latch for short-circuit protection section
Data Sheet G13418EJ3V0DS00
11
PC1935
2.1 Reference Voltage Generator
The reference voltage generator is comprised of a band-gap reference circuit, and outputs a temperature-compensated reference voltage (2.1 V). The reference voltage can be used as the power supply for internal circuits, or as a reference voltage, and can also be accessed externally via the VREF pin (pin 2).
2.2
Oscillator
The oscillator self-oscillates if a timing resistor is attached to the RT pin (pin 3). This oscillator waveform is input to the inverted input pins (channel 1 and 2) or non-inverted input pin (channel 3) of the three PWM comparators to determine the oscillation frequency.
2.3
Under Voltage Lock-out Circuit
The under voltage lock-out circuit prevents malfunctioning of the internal circuits when the supply voltage is low, such as when the supply voltage is first applied, or when the power supply is interrupted. When the voltage is low, the three output transistors are cut off at the same time.
2.4
Error Amplifiers
The non-inverted input pins of the error amplifiers E/A1, E/A2, and E/A3 are connected internally to 0.3 V (the input threshold voltages are all 0.3 V (TYP .)). The circuits of the error amplifiers E/A1, E/A2, and E/A3 are exactly the same. The first stage of the error amplifier is a P-channel MOS transistor input.
2.5
PWM Comparators
The output ON duty is controlled according to the outputs of the error amplifiers and the voltage input to the Dead Time Control pin (fixed internally for channel 1). A triangular waveform is input to the inverted pin, and the error amplifier output and Dead Time Control pin voltage (fixed internally for channel 1) are input to the non-inverted pins of the PWM comparators for channel 1 and channel 2. Therefore, the output transistor ON period is the period when the triangular waveform is lower than the error amplifier output and Dead Time Control pin voltage (fixed internally for channel 1). Channel 3 is the logical inverse of channel 1 and channel 2. Consequently, the triangular waveform is input to the noninverted input pin, and the error amplifier output and Dead Time Control pin voltage are input to the inverted input pins of the PWM comparator for channel 3. Therefore, the transistor ON period is the period when the triangular waveform is higher than the error amplifier output and Dead Time Control pin voltage (refer to Timing Charts).
12
Data Sheet G13418EJ3V0DS00
PC1935
2.6 Timer Latch-Method Short Circuit Protection Circuit
When the outputs of the converters for each channel drop, the FB outputs of the error amplifiers of those outputs go high (FB3 output goes low). If the FB output exceeds the timer latch input detection voltage (VTH = 1.9 V) (FB3 output goes lower than the timer latch input detection voltage (VTH = 0.63 V)), then the output of the SCP comparator goes low, and Q1 goes off. When Q1 turns OFF, the constant-current supply charges CDLY via the DLY pin. The DLY pin is internally connected to a flip-flop. When the DLY pin voltage reaches the UV detection voltage (VUV = 0.8 V (TYP the output Q of the flip-flop goes .)), low, and the output stage of each channel is latched to OFF (refer to Figure 2-1 Block Diagram). The logic of channels 1 and 2 is reverse to that of channel 3. Consequently, an inverter circuit is inserted between the FB output of channels 1 and 2, and SCP comparator input. Make the power supply voltage briefly less than the reset voltage (VCCR, 1.0 V TYP to reset the latch circuit when the .) short-circuit protection circuit has operated.
2.7
Output Circuit
The output circuit has an N-channel open-drain output providing an output withstand voltage of 30 V (absolute maximum rating), and an output current of 21 mA (absolute maximum rating).
Data Sheet G13418EJ3V0DS00
13
PC1935
3. NOTES ON USE
3.1
Setting the Output Voltage
Figure 3-1 illustrates the method of setting the output voltage. The output voltage is obtained using the formula shown in the figure. The input threshold value of the error amplifier is 0.3 V (TYP for all the error amplifiers, E/A1, E/A2, and E/A3. .) Therefore, select a resistor value that gives this voltage.
Figure 3-1 Setting the Output Voltage
(1) When setting a positive output voltage using error amplifier E/A1.
VOUT (positive voltage)
VOUT = 1 + R1 R2
0.3
R1 6 CNF R2 RNF 7 0.3 V E/A1
(2) When setting a positive output voltage using error amplifier E/A2.
VOUT (positive voltage)
VOUT = 1 + R1 R2
0.3
R1 11 CNF R2 RNF 10 0.3 V E/A2
14
Data Sheet G13418EJ3V0DS00
PC1935
(3) When setting a negative output voltage using error amplifier E/A3.
2 R1 15 CNF R2 RNF 14
VREF
E/A3
0.3 V
VOUT (negative voltage)
VOUT = 1 + R2 R1
0.3
R2 R1
VREF
3.2
Setting the Oscillation Frequency
Choose RT according to the oscillation frequency (fOSC) vs timing resistor (RT) characteristics (refer to Typical Characteristics Curves fOSC vs RT). The formula below (3-1) gives an approximation of fOSC. However, the result of formula 3-1 is only an approximation, and the value must be confirmed in actual operation, especially for high-frequency operation.
fOSC[Hz] 1.856 x 109/RT[]
(3-1)
3.3
Preventing Malfunction of the Timer Latch-Method Short Circuit Protection Circuit
The timer latch short-circuit protection circuit operates when the error amplifier outputs of channel 1 or channel 2 (pin 7 and 10) exceed approximately 1.9 V, or when the error amplifier output of channel 3 (pin 14) goes below approximately 0.63 V, and cuts off the output. However, if the rise of the power supply voltage is fast, or if there is noise on the DLY pin (pin 5), the latch circuit may malfunction and cut the output off. To prevent this, keep the wiring impedance between the DLY pin and the GND pin (pin 4) low, and avoid applying noise to the DLY pin.
Data Sheet G13418EJ3V0DS00
15
PC1935
3.4 Connecting Unused Error Amplifiers
When the unused circuit of the three control circuits provided internally is error amplifier E/A2, connect the circuit in such a way as to make sure that the output of the error amplifier is low. When the unused circuit is error amplifier E/A3, connect the circuit in such a way as to make sure that the output of the error amplifier is high. In the case of error amplifier E/A1, the Dead Time Control pin is fixed internally, so be sure to always use this amplifier. Figure 3-2 shows examples of how to connect unused error amplifiers.
Figure 3-2 Examples of Connecting Unused Error Amplifiers
(1) Error amplifier E/A2
2
VREF
11
E/A2
10
0.3 V
12 DTC2
(2) Error amplifier E/A3
2
VREF
15
E/A3
14
0.3 V
16 DTC3
16
Data Sheet G13418EJ3V0DS00
PC1935
3.5 ON/OFF Control
3.5.1
Channel 1 (for step-up)
The ON/OFF signal control method of the output oscillation of channel 1 is to input the ON/OFF signal from ON1 as shown in Figure 3-3. For channel 1, soft start or timer latch (SCP) is internally selected. Soft start is executed when the first start signal is input. When the end of soft start is detected, the soft start select switch is turned OFF and the timer latch circuit operates.
Figure 3-3 ON/OFF Control (channel 1 for step-up)
VO1 (Converter output voltage)
R11 II1
-
FB1 SCP comparator (common to each channel) Error amplifier
+ -
R12
+
Q1
0.3 V D11 Dead time setting: 85 % (internally fixed) VREF R1
+ + -
0.63 V
To output stage PWM comparator
ON1
Q11 CDLY DLY
SW
Oscillation section (common to each channel)
(1) When ON1 is high: OFF status Q11: ON DLY pin: Low level Output duty of PWM comparator: 0 % D11: ON II1 pin: High level FB1 output: Low level
(2) When ON1 is low: ON status (start up) Q11: OFF CDLY is charged in the sequence of [VREF R1 SW DLY pin CDLY] Soft start D11: OFF II1 pin: Low level FB1 output: High level
(3) When ON1 goes high again after start up (SW: OFF): OFF status Q11: ON DLY pin: Low level (Nothing happens because SW is OFF.) D11: ON II1 pin: High level FB1 output: Low level PWM comparator output duty: 0 % Converter output voltage (VO1) drops.
Caution Even if start up is executed by making ON1 low again after (3), soft start is not executed because the soft start select switch (SW) remains OFF. To execute soft start of channel 1 again, drop VCC to 0 V once.
Data Sheet G13418EJ3V0DS00
17
PC1935
3.5.2 Channel 2 (for step-up)
The ON/OFF signal control method of the output oscillation of channel 2 is to input the ON/OFF signal from ON2 as shown in Figure 3-4. The PWM converter can be turned ON/OFF by controlling the level of the DTC2 pin. However, it is necessary to keep the level of the FB2 output low (the SCP comparator input high) so that the timer latch does not start when the PWM converter is OFF. In this circuit example, the FB2 output level is controlled by controlling the level of the II2 pin.
Figure 3-4 ON/OFF Control (channel 2: step-up)
VO2 (Converter output voltage)
R21 II2
-
FB2 SCP comparator (common to each channel)
+ -
DLY Q1 CDLY
R22
Error 0.3 V amplifier
+
0.63 V D21 VREF R23 DTC2 ON2 Q21 R24 C21 To output stage
+ + -
PWM comparator
Oscillation section (common to each channel)
(1) When ON2 is high: OFF status Q21: ON DTC2 pin: Low level Output duty of PWM comparator: 0 % D21: ON II2 pin: High level FB2 output: Low level SCP comparator output: High level Timer latch stops.
(2) When ON2 is low: ON status Q21: OFF C21 is charged in the sequence of [VREF R23 C21] DTC2 pin voltage rises Soft start D21: OFF II2 pin: Low level FB2 output: High level SCP comparator output: Low level Q1 is OFF Charging CDLY starts (timer latch start).
Caution Keep the low-level voltage of the DTC2 pin within 1.2 V and the high-level voltage of the II2 pin at 0.3 V or higher. The maximum voltage that is applied to the II2 pin must be equal to or lower than VREF.
18
Data Sheet G13418EJ3V0DS00
PC1935
3.5.3 Channel 3 (for inverted output)
The ON/OFF signal control method of the output oscillation of channel 3 is to input the ON/OFF signal from ON3 as shown in Figure 3-5. The PWM converter can be turned ON/OFF by controlling the level of the DTC3 pin. However, it is necessary to keep the level of the FB3 output high so that the timer latch does not start when the PWM converter is OFF. In this circuit example, the FB3 output level is controlled by controlling the level of the II3 pin. Because channel 3 supports an inverted converter, its PWM comparator logic is different from that of channels 1 and 2.
Figure 3-5 ON/OFF Control (channel 3: for inverted output)
VREF R31 II3
-
FB3 SCP comparator (common to each channel)
+ -
DLY Q1 CDLY
Q33
R32 -VO3 (Converter output voltage) VREF Q32 R33 C31 DTC3
Error 0.3 V amplifier
+
0.63 V
To output stage
- - +
PWM comparator
ON3
Q31 R34
Oscillation section (common to each channel)
(1) When ON3 is high: OFF status Q31: ON Q32: ON DTC3 pin: High level Output duty of PWM comparator: 0 % Q33: ON II3 pin: Low level FB3 output: High level SCP comparator output: High level Q1 is ON. Timer latch stops.
(2) When ON3 is low: ON status Q31: OFF Q32 is OFF. C31 is charged in the sequence of [VREF C31 R34] DTC3 pin voltage drops. Soft start Q33: OFF II3 pin: High level FB3 output: Low level SCP comparator output: Low level Q1: OFF Charging CDLY starts (timer latch start).
Caution
Keep the high-level voltage of the DTC3 pin at 1.6 V or higher and the low-level voltage of the II3 pin within 0.3 V. The maximum voltage that is applied to the II3 pin must be equal to or lower than VREF.
Data Sheet G13418EJ3V0DS00
19
PC1935
3.6 Maximum Duty Limit
Channel 1 is switched internally between Soft Start and Timer Latch. For this reason, the DTC voltage is fixed internally, and the maximum duty is limited to 85%. The DTC voltage for channel 2 and channel 3 can be set externally, so the maximum duty is not limited.
3.7
Notes on Actual Pattern Wiring
When actually carrying out the pattern wiring, it is necessary to separate control-related grounds and power-related grounds, and make sure that they do not share impedances as far as possible. In addition, make sure the high-frequency impedance is lowered using capacitors and other components to prevent noise input to the VREF pin.
20
Data Sheet G13418EJ3V0DS00
4.
4.1
VIN = +3 V CH2 VO2 = +5 V IO = 50 mA
COM
Application Example
R21 47 k Q22 C23 100 pF C22 Q23 R210 7.5 k 100 pF R212 20 k COM Q32 R39 20 C32 Q33 100 pF R310 470 R312 20 k Q31 D31
11 10
R28 470 R211 68 Q21 C21 68 F
L21 47 H
D21
C25 2.2 F R27 150 R29 20 k
APPLICATION EXAMPLE
R24 C24 3300 pF D22 1SS220 R213 30 k R311 10 L31 47 H C31 68 F
R25
VR26
5.1 k
12 k 5 k
Q24
R22 2.4 k VR23 1 k
0.1 F
1F 1F 1F 1F 1F 1F
C0 R31 20 k
16
DTC3 II3
C35 2.2 F
15 14 13 12
C33 3300 pF R313 30 k 9 VR33 10 k 100 pF R32 54 k C33 FB3 OUT3 DTC2 II2 FB2 OUT2
R34
R35 VR36
10 k Q34
12 k 5 k
PC1935
Vcc VREF RT GND DLY 1 R11 120 k R14 150 C13 100 pF Q13 R16 20 k R12 2.4 k VR13 1 k R15 470 Q12 2 3 4 5 6 7 8 II1 FB1 OUT1
CH3 VO3 = -5 V IO = 50 mA
Q35 CH1 VO1 = +12 V IO = 50 mA L11 47 H R18 10 C12 100 pF R17 7.5 k R19 20 k Q11 C11 68 F D11
Figure 4-1 Chopper-Method/Inverting-Type Switching Regulator
Figure 4-1 shows an example circuit for obtaining 5 V/50 mA and +12 V/50 mA from a +3 V power supply.
Data Sheet G13418EJ3V0DS00
RT 3.9 k Q14 D12 1SS220 CSS 0.1 pF R214 10 k R111 5.1 k ON/OFF 1 R112 10 k ON/OFF 2 R215 10 k R110 30 k C13 3300 pF
R38 R37 10 k 5.1 k
Q36
R314 5.1 k
ON/OFF 3
R315 10 k
PC1935
21
PC1935
4.2 List of External Parts
The list below shows the external parts.
Table 4-1 List of External Parts
Symbol C11 D11 L11 Q11 Q12 Q13 D12 Q14 C21 D21 L21 Q21 Q22 Q23 D22 Q24 C31 D31 L31 Q31 Q32 Q33 Q34 Q35 Q36 47 H 68 F 47 H 68 F 47 H Parameter 68 F Function Output capacitor Schottkey diode Choke inductor Switching transistor Buffer transistor Buffer transistor Switching diode Transistor for switch Output capacitor Schottkey diode Choke inductor Switching transistor Buffer transistor Buffer transistor Switching diode Transistor for switch Output capacitor Schottkey diode Choke inductor Switching transistor Buffer transistor Buffer transistor Transistor for switch Transistor for switch Transistor for switch Part number 20SA68M D1FS4 636FY-470M 2SD2403 2SA812 2SC1623 1SS220 2SK2158 20SA68M D1FS4 636FY-470M 2SD2403 2SA812 2SC1623 1SS220 2SK2158 20SA68M D1FS4 636FY-470M 2SB1572 2SA812 2SC1623 2SA812 2SC1623 2SC1624 Maker SANYO SHINDENGEN TOKO NEC NEC NEC NEC NEC SANYO SHINDENGEN TOKO NEC NEC NEC NEC NEC SANYO SHINDENGEN TOKO NEC NEC NEC NEC NEC NEC D73F series OS-CON, SA series D73F series OS-CON, SA series D73F series Remark OS-CON, SA series
Remarks 1. The capacitors that are not specified in the above list are multilayer ceramic capacitors. 2. The resistors that are not specified in the above list are 1/4W resistors.
22
Data Sheet G13418EJ3V0DS00
PC1935
5. PACKAGE DRAWING
16-PIN PLASTIC TSSOP (5.72 mm (225))
16 9 detail of lead end F G R
P
L S
1
8
E
A A' S
H I J
C D
NOTE
K B
N
S
M
M
Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A A' B C D E F G H I J K L M N P R S
MILLIMETERS 5.150.15 5.00.1 0.375 MAX. 0.65 (T.P.) 0.24 +0.06 -0.04 0.09 +0.06 -0.04 1.01 +0.09 -0.06 0.92 6.40.2 4.40.1 1.00.2 0.145+0.055 -0.045 0.5 0.10 0.10 3 +5 -3 0.25 0.60.15 S16GR-65-PJG-1
Data Sheet G13418EJ3V0DS00
23
PC1935
6. RECOMMENDED SOLDERING CONDITIONS
Recommended solder conditions for this product are described below. For details on recommended soldering conditions, refer to Information Document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended, consult NEC.
Surface Mount Type
PC1935GR: 16-pin plastic TSSOP (5.72 mm (225))
Soldering Method Soldering Conditions Symbol of Recommended Conditions Infrared reflow Package peak temperature: 235 C, Time: 30 seconds MAX. (210 C MIN.), Number of times: 3 MAX. VPS Package peak temperature: 215 C, Time: 40 seconds MAX. (200 C MIN.), Number of times: 3 MAX. Wave soldering Soldering bath temperature: 260 C MAX., Time: 10 seconds MAX., Number of times: 1, Preheating temperature: 120 C MAX. (package surface temperature) WS60-00-1 VP15-00-3 IR35-00-3
Caution Do not use two or more soldering methods in combination.
24
Data Sheet G13418EJ3V0DS00
PC1935
[MEMO]
Data Sheet G13418EJ3V0DS00
25
PC1935
[MEMO]
26
Data Sheet G13418EJ3V0DS00
PC1935
NOTES FOR BiCMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note:
Strong electric field, when exposed to a device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS Note:
No connection for device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. Input levels of devices must be fixed high or low by using a pull-up or pulldown circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF BiCMOS DEVICES Note:
Power-on does not necessarily define initial status of device. Production process of BiCMOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet G13418EJ3V0DS00
27
PC1935
[MEMO]
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

▲Up To Search▲

Price & Availability of UPC1935

	To Download UPC1935 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .