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DATA SHEET MOS INTEGRATED CIRCUIT PD77018A, 77019 16 bits, Fixed-point Digital Signal Processor PD77018A, 77019 are 16 bits fixed-point DSPs (Digital Signal Processors) developed for digital signal processing with its demand for high speed and precision. Maximum operating speed of the PD77018A, 77019 is improved compared with the PD77015, 77017, 77018. And the PD77019 internal instruction RAM (4K x 32 bits) is suitable for program code replacement. FEATURES * FUNCTIONS * Instruction cycle: 16.6 ns (MIN.) Operation clock: 60 MHz External clock: 60, 30, 20, 15, 7.5 MHz Crystal: 60 MHz * On-chip PLL to provide higher operation clock than the external clock * Dual load/store * Hardware loop function * Conditional execution * Executes product-sum operation in one instruction cycle * PROGRAMMING * 16 bits x 16 bits + 40 bits 40 bits multiply accumulator * 8 general registers (40 bits each) * 8 ROM/RAM data pointer: each data memory area has 4 registers * 10 source interrupts (external: 4, internal: 6) * 3 operand instructions (example: R0 = R0 +R1LR2L) * Nonpipeline on execution stage * MEMORY AREAS * Instruction memory area : 64K words x 32 bits * Data memory areas : 64K words x 16 bits x 2 (X memory, Y memory) In this document, all descriptions of the PD77018A also apply to the PD77019, unless otherwise specified. The information in this document is subject to change without notice. Document No. U11849EJ2V0DS00 (2nd edition) Date Published October 1997 N Printed in Japan The mark shows major revised points. (c) 1996 PD77018A, 77019 * CLOCK GENERATOR * Mask option for CLKOUT pin: Fixed to the low level. Does not output the internal system clock. * Selectable source clock: external clock input and crystal resonator [External clock] On-chip PLL to provide higher operation clock (60 MHz max.) than the external clock. Variable multiple rates (1, 2, 3, 4, 8) by mask option. [Crystal resonator] Oscillation frequency corresponds directly to the system clock frequency (Sure to specify the mask option frequency multiple as "1"). * ON-CHIP PERIPHERAL * I/O port: 4 bits * Serial I/O (16 bits): 2 channels * Host I/O (8 bits): 1 channel * CMOS * +3 V single power supply ORDERING INFORMATION Part Number Package 100-pin plastic TQFP (FINE PITCH) (14 x 14 mm) 100-pin plastic TQFP (FINE PITCH) (14 x 14 mm) PD77018AGC-xxx-9EU PD77019GC-xxx-9EU Remark xxx indicates a code suffix. 2 BLOCK DIAGRAM X-Bus External Memory Y-Bus Serial I/O #1 X Memory Data Pointers X Memory Y Memory Data Pointers Y Memory R0-R7 Serial I/O #2 Main Bus ALU (40) Ports Loop Control Stack Instruction Memory MPY 16x16+40 40 PC Stack Interrupt Control Host I/O CPU Control PD77018A, 77019 Wait Controller INT1 - INT4 WAIT RESET CLKOUT X1 X2 IE I/O 3 PD77018A, 77019 FUNCTIONAL PIN GROUPS +3 V SO1 SORQ1 SOEN1 Serial Interface #1 SCK1 SI1 SIEN1 SIAK1 SO2 SOEN2 Serial Interface #2 SCK2 SI2 SIEN2 Ports P0 - P3 HCS HA0, HA1 HRD HRE HWR HWE HD0 - HD7 VDD RESET INT1 INT2 INT3 INT4 X1 X2 CLKOUT TDO, TICE TCK, TDI, TMS HOLDRQ Debugging Interface Interrupts (2) (3) (4) BSTB HOLDAK X/Y DA0 - DA13 D0 - D15 WAIT MRD MWR (14) (16) Data Bus Control (2) Host Interface External Data Memory (8) GND 4 Functional Differences among the PD7701x Family Item Internal instruction RAM Internal instruction ROM External instruction memory Data RAM (X/Y memory) Data ROM (X/Y memory) External data memory Instruction cycle (Maximum operation speed) External clock (at maximum operation speed) Crystal (at maximum operation speed) Instruction Serial interface (2 Channels) 66 MHz PD77016 1.5K words None 48K words 2K words each None 48K words each PD77015 PD77017 256 words PD77018 PD77018A PD77019 4K words 4K words 12K words None 24K words 1K words each 2K words each 2K words each 4K words each 16K words each 3K words each 12K words each 30 ns (33 MHz) 33/16.5/8.25/4.125 MHz Variable multiple rate (1, 2, 4, 8 ) by mask option. 16.6 ns (60 MHz) 60/30/20/15/7.5 MHz Variable multiple rate (1, 2, 3, 4, 8 ) by mask option. 60 MHz STOP instruction is added. - - Channel 1 has the same functions as channel 2. 5V 160-pin plastic QFP 33 MHz Channel 1 has the same functions as that of the PD77016. Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection). 3V 100-pin plastic TQFP Power supply Package PD77018A, 77019 5 PD77018A, 77019 PIN CONFIGURATION 100-pin plastic TQFP (FINE PITCH) (14 x 14 mm ) (Top View) HOLDRQ HOLDAK TDO CLKOUT VDD BSTB WAIT MWR HWR TICE MRD VDD GND GND HRD TMS RESET INT4 INT3 INT2 INT1 I.C. X/Y DA13 DA12 GND VDD DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 GND VDD DA3 DA2 DA1 DA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 HCS HD0 HD1 TCK HA1 HA0 TDI X1 X2 HD2 HD3 HD4 HD5 HD6 HD7 VDD GND HWE HRE P0 P1 P2 P3 SI2 SIEN2 SCK2 SO2 SOEN2 VDD GND SOEN1 SORQ1 SO1 SIAK1 D15 D14 D13 D12 GND D11 D10 D9 D8 GND VDD D7 D6 D5 D4 GND D3 D2 D1 D0 SI1 SIEN1 6 SCK1 VDD VDD PD77018A, 77019 PIN IDENTIFICATION BSTB: CLKOUT: D0-D15: DA0-DA13: GND: HA0,HA1: HCS: HD0-HD7: HOLDAK: HOLDRQ: HRD: HRE: HWE: HWR: I.C.: INT1-INT4: MRD: MWR: P0-P3: RESET: SCK1,SCK2: SI1,SI2: SIAK1: SIEN1,SIEN2: SO1,SO2: SORQ1: TCK: TDI: TDO: TICE: TMS: VDD: WAIT: X1: X2: X/Y: Bus Strobe Clock Output 16 Bits Data Bus External Data Memory Address Bus Ground Host Data Access Host Chip Select Host Data Bus Hold Acknowledge Hold Request Host Read Host Read Enable Host Write Enable Host Write Internally connection Interrupt Memory Read Output Memory Write Output Port Reset Serial Clock Input Serial Data Input Serial Input Acknowledge Serial Input Enable Serial Data Output Serial Output Request Test Clock Input Test Data Input Test Data Output Test In-Circuit Emulator Test Mode Select Power Supply Wait Input Clock input/crystal connection Crystal connection X/Y Memory Select SOEN1,SOEN2: Serial Output Enable 7 PD77018A, 77019 PIN NAME Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Symbol RESET INT4 INT3 INT2 INT1 I.C. Note X/Y DA13 DA12 GND VDD DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 GND VDD DA3 DA2 DA1 DA0 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol D15 D14 D13 D12 GND VDD D11 D10 D9 D8 GND VDD D7 D6 D5 D4 GND VDD D3 D2 D1 D0 SI1 SIEN1 SCK1 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Symbol SIAK1 SO1 SORQ1 SOEN1 GND VDD SOEN2 SO2 SCK2 SIEN2 SI2 P3 P2 P1 P0 HRE HWE GND VDD HD7 HD6 HD5 HD4 HD3 HD2 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol HD1 HD0 HCS HRD HWR HA0 HA1 GND X2 X1 VDD CLKOUT TDO TICE TCK TDI TMS HOLDRQ HOLDAK MWR GND VDD MRD BSTB WAIT Note I.C. (Internally Connected): Leave this pin open. 8 PD77018A, 77019 CONTENTS 1. PIN FUNCTIONS ............................................................................................................................... 10 1.1 1.2 Pin Functions ........................................................................................................................................... 10 Recommended Connection for Unused Pins ....................................................................................... 15 2. FUNCTIONS ...................................................................................................................................... 16 2.1 Pipeline Processing ................................................................................................................................ 16 2.1.1 2.1.2 2.2 2.3 Outline ........................................................................................................................................... 16 Instructions with Delay .................................................................................................................. 16 Program Control Unit .............................................................................................................................. 17 Operation Unit ......................................................................................................................................... 17 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 General register (R0 to R7) ........................................................................................................... 17 MAC: Multiply ACcumulator ......................................................................................................... 18 ALU: Arithmetic Logic Unit ........................................................................................................... 18 BSFT: Barrel ShiFTer ................................................................................................................... 18 SAC: Shifter And Count Circuit .................................................................................................... 18 CJC: Condition Judge Circuit ....................................................................................................... 19 Instruction RAM Outline ................................................................................................................ 20 Data Memory Outline .................................................................................................................... 21 Data Memory Addressing .............................................................................................................. 22 Serial Interface Outline .................................................................................................................. 22 Host Interface Outline ................................................................................................................... 22 General Input/output Ports Outline ................................................................................................ 22 Wait Cycle Register ....................................................................................................................... 22 2.4 Memory ..................................................................................................................................................... 19 2.4.1 2.4.2 2.4.3 2.5 On-chip Peripheral Circuit ...................................................................................................................... 22 2.5.1 2.5.2 2.5.3 2.5.4 3. INSTRUCTIONS ................................................................................................................................ 23 3.1 3.2 Outline ...................................................................................................................................................... 23 Instruction Set and Operation ................................................................................................................ 24 4. ELECTRICAL SPECIFICATIONS ..................................................................................................... 32 5. PACKAGE DRAWING ...................................................................................................................... 53 6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 54 9 PD77018A, 77019 1. PIN FUNCTIONS 1.1 Pin Functions * Power supply Symbol Pin No. 11, 21, 31, 37, 43, 56, 69, 86, 97 10, 20, 30, 36, 42, 55, 68, 83, 96 I/O Function VDD - +3V power supply GND - Ground * System control Symbol X1 85 Pin No. I/O I Function Clock input / crystal connection pin * The clock signal is connected to X1, when using external clock for system clock. Crystal connection pin * X2 should be left open when using external clock for system clock. Internal system clock output Internal system reset signal input X2 84 _ CLKOUT RESET 87 1 O I * Interrupt Symbol INT4 - INT1 2-5 Pin No. I/O I Function Maskable external interrupt input * Falling edge detection 10 PD77018A, 77019 * External data memory interface Symbol X/Y 7 Pin No. I/O O (3S) Function Memory select signal output * 0: X memory is used. * 1: Y memory is used. Address bus to external data memory * External data memory is accessed. * During the external memory is not accessed, these pins keep the previous level. These pins are set to low level; 0000H, by reset. They continue outputting low level until the first external memory access. 16 bits data bus to external data memory * External data memory is accessed. Read output * Reads external memory Write output * Writes external memory Wait signal input * Wait cycle is input when external memory is read. 1: No wait 0: Wait Hold request signal input * Input low level when external data memory bus is expected to use. Bus strobe signal output * Outputs low level while the PD77018A is occupying external memory bus. Hold acknowledge signal output * Outputs low level when the PD77018A permits external device to use external data memory bus. DA13 - DA0 8, 9, 12 -19, 22 - 25 O (3S) D15 - D0 26 -29, 32 - 35, 38 - 41, 44 - 47 98 I/O (3S) O (3S) O (3S) I MRD MWR 95 WAIT 100 HOLDRQ 93 I BSTB 99 O HOLDAK 94 O Remark The state of the pins added 3S becomes high impedance when bus release signal (HOLDAK = 0) is output. 11 PD77018A, 77019 * Serial interface Symbol SCK1 SORQ1 SOEN1 SO1 SIEN1 SI1 SCK2 SOEN2 SO2 SIEN2 SI2 SIAK1 50 53 54 52 49 48 59 57 58 60 61 51 Pin No. I/O I O I O (3S) I I I I O (3S) I I O Clock input for serial 1 Serial output 1 request Serial output 1 enable Serial data output 1 Serial input 1 enable Serial data input 1 Clock input for serial 2 Serial output 2 enable Serial data output 2 Serial input 2 enable Serial data input 2 Serial input 1 acknowledge Function Remark The state of the pins added 3S becomes high impedance, when data output have been finished or RESET is input. 12 PD77018A, 77019 * Host interface Symbol HA1 82 Pin No. I/O I Function Specifies register which HD7 to HD0 access 1: Accesses HST: Host interface status register when HA1 = 0 0: Accesses HDT(in): Host transmit data register when HWR = 0 0: Accesses HDT(out): Host receive data register when HRD = 0 Specifies bits of registers which HD7 to HD0 access * 1: Accesses bits 15-8 of HST, HDT(in) or HDT(out) * 0: Accesses bits 7-0 of HST, HDT(in) or HDT(out) Chip select input Host read input Host write input Host read enable output Host write enable output 8 bits host data bus HA0 81 I HCS HRD HWR HRE HWE HD7 - HD0 Remark 78 79 80 66 67 70 - 77 I I I O O I/O (3S) The state of the pins added 3S becomes high impedance when the host does not access host interface. * I/O port Symbol P3 - P0 62 - 65 Pin No. I/O I/O I/O port Function 13 PD77018A, 77019 * Debugging interface Symbol TDO TICE TCK TDI TMS 88 89 90 91 92 Pin No. I/O O O I I I For debugging For debugging For debugging For debugging For debugging Function * Other Symbol I.C. 6 Pin No. I/O _ Function Internal connected pin. Leave this pin open. Caution When any signal is applied to or read out from this pin, normal operation of the PD77018A is not assured. 14 PD77018A, 77019 1.2 Recommended Connection for Unused Pins Pin INT1 - INT4 X/Y DA0 - DA13 D0 - D15 Note1 MRD MWR WAIT HOLDRQ BSTB HOLDAK SCK1, SCK2 SI1, SI2 SOEN1, SOEN2 SIEN1, SIEN2 SORQ1 SO1, SO2 SIAK1 HA0, HA1 HCS HRD HWR HRE HWE HD0 - HD7 Note2 P0 - P3 TCK TDO, TICE TMS, TDI CLKOUT I/O I O O I/O O O I I O O I I I I O O O I I I I O O I/O I/O I O I O connect to GND, via a resistor open open(pull-up internally) open connect to VDD or GND, via a resistor open connect to VDD or GND connect to VDD open connect to GND connect to VDD or GND open connect to VDD connect to VDD or GND, via a resistor open Recommended connection connect to VDD open Notes 1. Can leave open, if no access to external data memory is executed in the whole of program. 2. Can leave open, if HCS, HRD, HWR are fixed to high level. Remark I: O: Input pin Output pin I/O: Input/Output pin 15 PD77018A, 77019 2. FUNCTIONS 2.1 Pipeline Processing This section describes the PD77018A pipeline processing. 2.1.1 Outline The PD77018A basic operations are executed in following 3-stage pipeline. (1) instruction fetch; if (2) Instruction decoding; id (3) execution; ex When the PD77018A operates a result of a instruction just executed before, the data is input to ALU in parallel with written back to general registers. Pipeline processing actualizes programming without delay time to execute instructions and write back data. Three successive instructions and their processing timing are shown below. Pipeline Processing Timing if1 id1 ex1 if2 id2 ex2 if3 id3 ex3 1 instruction cycle 2.1.2 Instructions with Delay The following instructions have delay time in execution. (1) Instructions to control interrupt 2 instruction cycles have been taken between instruction fetch and execution. (2) Inter-register transfer instructions and immediate data set instructions When data is set in data pointer, it needs 2 instruction cycles before the data is valid. 16 PD77018A, 77019 2.2 Program Control Unit Program control unit controls not only count up of program counter in normal operation, but loop, repeat, branch, halt and interrupt. In addition to loop stack of loop 4 level and program stack of 15 level, software stack can be used for multiloop and multi-interrupt/subroutine call. The PD77018A has external 4 interruptions and internal 6 interruptions from peripheral, and specifies interrupt enable or disable independently. The HALT and STOP instructions cause the PD77018A to place in low power standby mode. When the HALT instruction is executed, power consumption decreases. HALT mode is released by interrupt input or hardware reset input. It takes several system clock to recover. When the STOP instruction is executed, power consumption decreases. STOP mode is released by hardware reset input. It takes a few ms to recover. 2.3 Operation Unit Operation unit consists of the following five parts. - 40 bits general register x 8 for data load/store and input/output of operation data - 16 bits x 16 bits + 40 bits 40 bits multiply accumulator - 40 bits Data ALU - 40 bits barrel shifter - SAC: shifter and count circuit. Standard word length is 40 bits to make overflow check and adjustment easy, and to accumulate the result of 16 bits x 16 bits multiplication correctly. 39 32 31 10 0 SSSSSSSS Head room Result of multiplication among two's complement data 2.3.1 General register (R0 to R7) The PD77018A has eight 40 bits registers for operation input/output and load/store with memory. General register consists of the following three parts. - R0L to R7L (bit 15 to bit 0) - R0H to R7H (bit 31 to bit 16) - R0E to R7E (bit 39 to bit 32) But each of RnL, RnH and RnE are treated as a register in the following conditions. (1) General register used as 40 bits register General registers are treated as 40 bits register, when they are used for the following aims. (a) Operand for triminal operation (except for multiplier input) (b) Operand for dyadic operation (except for multiplier and shift value) (c) Operand for monadic operation (except for exponent instructions) (d) Operand for operation (e) Operand for conditional judge (f) Destination for load instruction (with sign extension and 0 clear) 17 PD77018A, 77019 (2) General register used as 32 bits register Bit 31 to bit 0 of general register are treated as 32 bits register, when it is used for a operand of exponent instruction. (3) General register used as 24 bits register Bit 39 to bit 16 of general register are treated as 24 bits register, when it is used for destination with extended sign for a load/store instruction. (4) General register used as 16 bits register Bit 31 to bit 16 of general register are treated as 16 bits register, when it is used for the following aims. (a) Signed operand for multiplier (b) Source/destination for load/store instruction Bit 15 to bit 0 of general register are treated as 16 bits register, when it is used for the following aims. (c) Unsigned operand for multiplier (d) Shift value for shift instruction (e) Source/destination for load/store instruction (f) (f) Source/destination for inter-register transfer instruction Hardware loop times (g) Destination for immediate data set instruction (5) General register used as 8 bits register Bit 39 to bit 32 of general register are treated as 8 bits register, when it is used for source/destination of load/ store instruction. 2.3.2 MAC: Multiply ACcumulator MAC multiplies a pair of 16 bits data, and adds or subtract the result and 40 bits data. MAC outputs 40 bits data. MAC operates three types of multiplication: signed data x signed data, signed data x unsigned data and unsigned data x unsigned data. Result of multiplication and 40 bits data for addition can be added after 1 or 16 bits arithmetic shift right. 2.3.3 ALU: Arithmetic Logic Unit ALU performs arithmetic operation and logic operation. Both input/output data are 40 bits. 2.3.4 BSFT: Barrel ShiFTer BSFT performs shift right/left operation. Both input/output data are 40 bits. There are two types of shift right operations; arithmetic shift right which sign is extended, and logic shift right which is input 0 in MSB first. 2.3.5 SAC: Shifter And Count Circuit SAC calculates and outputs shift value for normalization. SAC is input 32 bits data and outputs the 40 bits data. Then, bit 39 to bit 5 of output data is always 0. 18 PD77018A, 77019 2.3.6 CJC: Condition Judge Circuit CJC judges whether condition is true or false with 40 bits input data. A conditional instruction is executed when the result is true, and not executed when the result is false. 2.4 Memory The PD77018A has one instruction memory area (64K words x 32 bits) and two data memory areas (64K words x 16 bits each). It adopts Harvard-type architecture, with instruction memory area and data memory areas separated. The PD77018A has 2 sets of data addressing units, which are dedicated for addressing data memory area. Each addressing unit consists of four data pointers, four index registers, a modulo register and addressing ALU. X memory area addresses are specified by DP0 to DP3, and Y memory area addresses are specified by DP4 to DP7. After memory access, DPn (with the same subscript), can be modified by DNn value. Modulo operation is performed with DMX for DP0 to DP3, with DMY for DP4 to DP7. 19 PD77018A, 77019 2.4.1 Instruction RAM Outline The PD77018A has an instruction ROM (24K words x 32 bits) and instruction RAM (256 words x 32 bits). The PD77019 has an instruction ROM (24K words x 32 bits) and instruction RAM (4K words x 32 bits). A system vector area is assigned to 64 words of the instruction RAM. Internal instruction RAM is initialized and rewritten by boot program. Boot up ROM contains the program loading instruction code to internal instruction RAM. PD77018A FFFFH PD77019 System (24K words) System (24K words) A000H 9FFFH Internal Instruction ROM (24K words) Internal Instruction ROM (24K words) 4000H 3FFFH System (11.5K words) System (15.25K words) 1200H 11FFH Internal Instruction RAM (4K words) Vector (64 words) System (256 words) Bootup ROM (256 words) 0300H 02FFH 0240H 023FH 0200H 01FFH 0100H 00FFH 0000H Internal Instruction RAM (256 words) Vector (64 words) System (256 words) Bootup ROM (256 words) Caution When any data is accessed or stored to system address, normal operation of the device is not assured. 20 PD77018A, 77019 2.4.2 Data Memory Outline The PD77018A and the PD77019 each has two data memory areas (64K words x 16 bits each) in X and Y memory areas. Every memory areas consists of 3K words x 16 bits data RAM and 12K words x16 bits data ROM . As the PD77018A and the PD77019 each has interface with the external data memory, 16 K words x 16 bits external data memory space can be added to X/Y memories. Each data memory area includes on-chip peripheral area which consists of 64 words. When the external data memory area is accessed, instruction cycle can be 2 or more by wait function. PD77018A, 77019 FFFFH External Data Memory (16K words) C000H BFFFH System (20K words) 7000H 6FFFH Data ROM (12K words) 4000H 3FFFH 3840H 383FH 3800H 37FFH System (1984 words) Peripheral (64 words) System (11K words) 0C00H 0BFFH Data RAM (3K words) 0000H Caution When any data is accessed or stored to system address, normal operation of the device is not assured. 21 PD77018A, 77019 2.4.3 Data Memory Addressing There are following two types of data memory addressing. * Direct addressing The address is specified in the instruction field. * Indirect addressing The address is specified by the data pointer (DP). DP can get a bit reverse before addressing. It can update the DP value after accessing data memory. 2.5 On-chip Peripheral Circuit The PD77018A includes serial interface, host interface, general input/output ports and wait cycle registers. They are mapped in both X and Y memory areas, and are accessed as memory mapped I/O by the PD77018A CPU. 2.5.1 Serial Interface Outline The PD77018A has 2 channel serial interfaces. Serial I/O clock must be provided from external. Frame length can be programmed independently to be 8 bits or 16 bits. MSB first or LSB first can also be selected. Data is input/output by hand shaking for an external device, and by interrupts, polling or wait function in internal. 2.5.2 Host Interface Outline The PD77018A has 8 bits parallel ports as host interface to input/output data to and from host CPU and DMA controller. When an external device accesses host interface, HA0 and HA1 pins; which are host address input pins; specifies bit 15 to bit 8 and bit 7 to bit 0. The PD77018A includes 3 registers consisting of 16 bits, which are dedicated for input data, output data and status. The PD77018A has three types of interface method for internal and external data; interrupts, polling and wait function. 2.5.3 General Input/output Ports Outline General input/output ports consist of 4 bits. User can set each port as input or output. The PD77018A includes two registers. One is 4 bits register for input/output data, and the other is 16 bits for control. 2.5.4 Wait Cycle Register The wait cycle registers consist of 16 bits. It is used to set wait cycle number when external memory is accessed. When external data memory area (C000H - FFFFH) is accessed, 0, 1, 3, or 7 wait cycle can be set. When external data memory area is accessed, wait cycle can be also set by WAIT pin. 22 PD77018A, 77019 3. INSTRUCTIONS 3.1 Outline All PD77018A instructions are one-word instructions, consisting of 32 bits. And they are executed in 16.6 ns (min.) per instruction. There are following 9 instruction types. (1) Trinomial instructions : specify the Acc operation. 3 of general registers are specified optionally as the operation object. (2) Dyadic operation instructions : specify the Acc, ALU or shifter operation. 2 of general registers are specified optionally as the operation object. Some instructions can specify a general register and immediate data. (3) Monadic operation instructions : specify operations by ALU. 1 general register is specified optionally as the operation object. (4) Load/store instructions : transfer 16 bits data from memory to general registers, from general registers to memory and between general registers. (5) Inter-register transfer instructions : transfer data between general register and other registers. (6) Immediate data set instructions : set immediate data at general registers or each registers of address operation unit. (7) Branch instructions : specify the direction of the program flow. (8) Hardware loop instructions : specify times of instruction repeating. (9) Control Instructions : specify the control program. 23 PD77018A, 77019 3.2 Instruction Set and Operation An operation is written according to the rules for expressing. An expression of instructions having two or more descriptions can have only one selected. (a) Expressions and selectable registers Expression and selectable registers are shown as follows. Expression ro, ro', ro" rl, rl' rh, rh' re reh dp dn dm dpx dpy dpx_mod dpy_mod dp_imm xxx Selectable registers R0 - R7 R0L - R7L R0H - R7H R0E - R7E R0EH - R7EH DP0 - DP7 DN0 - DN7 DMX, DMY DP0 - DP3 DP4 - DP7 DPn, DPn++, DPn- -, DPn##, DPn%%, !DPn## (n = 0 - 3) DPn, DPn++, DPn- -, DPn##, DPn%%, !DPn## (n = 4 - 7) DPn##imm (n = 0 - 7) content of memory address xxx Example When the content of DP0 register is 1000, DP0 shows the content of memory address 1000. 24 PD77018A, 77019 (b) Modifying data pointers Data pointers are modified after memory access. The results are valid immediately after instruction execution. It is impossible to modify without memory access. Description DPn DPn++ DPn- - DPn## Operation No operation: DPn value does not change. DPn DPn+1 DPn DPn-1 DPn DPn + DNn: Adds DN0-DN7 corresponding to DP0-DP7 Example DP0 DP0 + DN0 (n = 0 - 3) (n = 4 - 7) DPn = ((DPL + DNn )mod (DMX + 1)) + DPH DPn = ((DPL + DNn )mod (DMY + 1)) + DPH DPn%% !DPn## Access memory after DPn value is bit-reversed After memory access, DPn DPn + DNn DPn DPn + imm DPn##imm (c) Concurrent processing instructions shows concurrent processing instruction. Instruction names are shown in abbreviation. TRI DYAD TRANS IMM BR LOOP CTR : Trinomial : Dyadic : Inter-register transfer : Immediate data set : Branch : Hardware loop : Control MONAD : Monadic (d) State of Overflow flag (OV) The following marks show the PD77018A overflow flag state. : Not affected : 1 is set when the result of operation is overflow. If overflow does not occur after operation, OV is not reset, and keeps the state before operation. Caution 25 26 PD77018A INSTRUCTION SET Concurrent Writing Processing Name Mnemonic Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. BR. LOOP. Flag CTL. OV Multiply add Multiply sub Sign unsign Multiply add Trinomial Unsign unsign Multiply add ro = ro + rhrh' ro = ro-rhrh' ro = ro + rhrl (rl should be a plus integral number.) ro=ro+rlrl' (rl and rl' should be a plus integral number.) ro=(ro>>1)+rhrh' ro = (ro>>16)+rhrh' ro=rhrh' ro"=ro+ro' ro'=ro+imm ro"=ro-ro' ro'=ro-imm ro'=ro SRA rl ro'=ro SRA imm ro ro+rhrh' ro ro-rhrh' ro ro+rhrl ro ro+rlrl' 1 bit shift Multiply add 16 bits shift Multiply add Multiply Add Immediate add Sub Immediate sub Arithmetic right shift Immediate arithmetic right shift Logic right shift Immediate Logic right shift Logic left shift Immediate logic left shift ro ro +rhrh' 2 ro ro 16 +rhrh' 2 ro rhrh' ro" ro+ro' ro' ro+imm (imm1) ro" ro-ro' ro' ro-imm (imm1) ro' ro >> rl ro' ro >> imm Dyadic ro'=ro SRL rl ro'=ro SRL imm ro'=ro SLL rl ro'=ro SLL imm ro' ro >> rl ro' ro >> imm ro' ro << rl ro' ro << imm PD77018A, 77019 Concurrent Writing Processing Name Mnemonic ro" ro & ro' ro' ro & imm ro" ro | ro' ro' ro | imm ro" ro ^ ro' ro ro ^ imm if(ro Flag CTL. OV And Immediate and Or Immediate or Dyadic Exclusive or Immediate exclusive or Less than ro" = ro & ro' ro' = ro & imm ro" = ro | ro' ro' = ro | imm ro" = ro ^ ro' ro = ro ^ imm ro" = LT(ro, ro') Clear Increment Decrement Absolute CLR(ro) ro' = ro + 1 ro' = ro - 1 ro' = ABS (ro) One's complement Two's complement Monadic Clip ro' = ~ro ro' = -ro ro' = CLIP (ro) PD77018A, 77019 Round ro' = ROUND (ro) Exponent Substitution ro' = EXP (ro) ro' = ro 27 28 Name Mnemonic Operation TRI. Cumulation Degression Monadic Division ro'+ = ro ro'- = ro ro'/ = ro ro' ro'+ro ro' ro'-ro if (sign(ro')==sign(ro)) {ro' (ro'-ro)<<1} else {ro' (ro'+ro)< if (sign(ro')==0 {ro' ro'+1} ro dpx, ro' dpy ro dpx, dpy rh dpx rh, ro dpy dpx rh, dpy rh' dest dpx, dest' dpy dest dpx, dpy source dpx source, dest dpy dpx source, dpy source' Parallel load/store Note 1, Note 2 ro=dpx_mod ro'=dpy_mod ro=dpx_mod dpy_mod=rh dpx_mod=rh ro=dpy_mod dpx_mod=rh dpy_mod=rh' Load/store Section load/store Note 1, Note 2, Note 3 dest=dpx_mod dest'=dpy_mod dest=dpx_mod dpy_mod=source dpx_mod=source dest=dpy_mod dpx_mod=source dpy_mod=source' Concurrent Writing Processing DYAD. MONAD. Load/ store TRANS. IMM. BR. LOOP. Flag CTL. OV Notes 1. 2. 3. One or both of a mnemonic pair can be written. After execution of load/store, data is modified by mod. One of following mnemonic should be selected: dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}. PD77018A, 77019 Concurrent Writing Processing Name Mnemonic Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. BR. LOOP. Flag CTL. OV Direct addressing load/store Note 1 Load/store Immediate index load/store Note 2 dest = addr addr = source dest = dp_imm dp_imm = source dest addr addr source dest dp dp source dest rl rl source rl imm Inter-register transfer Inter-register transfer Note 3 dest = rl rl = source Immediate data set rl = imm (provided imm = 0-0xFFFF) dp = imm (provided imm = 0-0xFFFF) dn = imm (provided imm = 0-0xFFFF) dm = imm (provided imm = 1-0xFFFF) dp imm Immediate data set dn imm dm imm Notes 1. 2. 3. One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, add = One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}. Any register except general registers should be selected as dest or source. 0: X-0xFFFF:X memory 0: Y-0xFFFF:Y memory . PD77018A, 77019 29 30 Name Mnemonic Operation TRI. Jump Inter-register indirect jump Subroutine call JMP imm JMP dp CALL imm PC imm PC dp SP SP + 1 STK PC + 1 PC imm SP SP + 1 STK PC + 1 PC dp PC STK SP SP - 1 PC STK STK SP - 1 Restore the interrupt enable flag start repeat end RC count RF 0 PC PC RC RC - 1 PC PC + 1 RF 1 RC count RF 0 PC PC RC RC - 1 PC PC + 1 RF 1 Branch Inter-register indirect subroutine call CALL dp Return RET Return from interrupt RETI Repeat REP count Loop Hardware loop LOOP count (Mnemonics more than two lines) start repeat end Loop pop LPOP LC LSR3 LE LSR2 LS LSR1 LSP LSP-1 PC PC + 1 CPU stop Note1 Note2 Concurrent Writing Processing DYAD. MONAD. Load/ store TRANS. IMM. BR. LOOP. Flag CTL. OV PD77018A, 77019 No operation Halt Control Stop If Forget interrupt NOP HALT STOP IF (ro cond) FINT CPU, PLL, OSC Stop Conditional judge Forget interrupt requests PD77018A, 77019 Notes 1. The HALT instruction causes all function except for clock and PLL to halt. The system is placed in much less power consumption mode. The contents of internal registers and memories are maintained. HALT is released by interrupt input. It takes several system clock to recover. 2. The STOP instruction causes all function including clock and PLL to stop. The system is placed in a minimum-power consumption mode. The contents of internal registers and memories are not maintained. After the STOP instruction is executed, pin status is maintained. STOP is released by hardware reset. It takes a few ms to recover. 31 PD77018A, 77019 4. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25 C) Parameters Power supply voltage Input voltage Output voltage Storage temperature Operating ambient temperature Symbol VDD VI VO Tstg TA 2.7 V VDD 3.6 V Conditions Ratings -0.5 to +4.6 -0.5 to +4.1 VI < VDD +0.5 V -0.5 to +4.6 -65 to +150 -40 to +85 Unit V V V C C Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. Recommended Operating Conditions Parameters Operating voltage Symbol VDD Conditions MIN. 2.7 3.0 2.7 3.0 0 TYP. 3.0 3.3 3.0 3.3 MAX. 3.6 3.6 3.6 3.6 VDD Unit V V V V V PD77018A tcC 19.0 ns tcC 16.6 ns PD77019 tcC 20.0 ns tcC 16.6 ns Input voltage VI Capacitance (TA = +25 C, VDD = 0 V) Parameters Input capacitance Output capacitance Input/output capacitance Symbol CI CO CIO Conditions f = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. 10 10 10 MAX. Unit pF pF pF 32 PD77018A, 77019 DC Characteristics (TA = -40 to +85 C, VDD = 2.7 to 3.6 V) Parameters High level input voltage High level X1 input voltage Low level input voltage High level output voltage Symbol VIH VIHC VIL VOH IOH = -2.0 mA IOH = -100 A Low level output voltage High level input leak current Low level input leak current Pull-up pin current Power supply current VOL ILIH ILIL IPI IDD IOL = 2.0 mA Except for TDI, TMS, VI = VDD Except for TDI, TMS, VI = 0 V TDI, TMS, 0 V VI VDD Except for X1 X1 input Conditions MIN. 0.7VDD 0.8VDD 0 0.7VDD 0.8VDD 0.2VDD 10 -10 -250 TBD 125Note 1 TYP. MAX. VDD VDD 0.2VDD Unit V V V V V V A A A mA PD77018A PD77019 Active mode, tcC = 25 ns, VIH = VDD, VIL = 0 V, no load Active mode, tcC = 25 ns, VIH = VDD, VIL = 0 V, no load HALT mode, tcC = 200 ns, VIH = VDD, VIL = 0 V, no load HALT mode, tcC = 200 ns, VIH = VDD, VIL = 0 V, no load TBD 150Note 1 mA IDDH PD77018A PD77019 13.5Note2 mA 15Note 2 mA IDDS STOP mode, TA = +60C, VIH = VDD, VIL = 0 V, no load 100 A Notes 1. The MAX. value is measured when a special program that MAX. switching required is executed, and VDD = 3.6 V condition. You can convert by each operation frequency f[MHz] on by each power supply VDD[V]. [PD77018A] Max. current value (TA = +25C) = (1.15 x VDD - 1.21) x f + 8 [mA] [PD77019] Max. current value (TA = +25C) = (1.40 x VDD - 1.74) x f + 18 [mA] 2. This value is measured when VDD = 3.6 V condition. You can convert by each operation frequency f[MHz] on by each power supply VDD[V]. [PD77018A] HALT current value (TA = +25C) = (0.15 x VDD - 0.25) x f + 2 [mA] [PD77019] AC Timing Test Points HALT current value (TA = +25C) = (0.17 x VDD - 0.38) x f + 5.9 [mA] X1 0.8VDD 0.5VDD 0.2VDD Test points 0.8VDD 0.5VDD 0.2VDD Input (except for X1) 0.7VDD 0.45VDD 0.2VDD Test points 0.7VDD 0.45VDD 0.2VDD Output 0.7VDD 0.45VDD 0.2VDD Test points 0.7VDD 0.45VDD 0.2VDD 33 PD77018A, 77019 AC Characteristics (TA = -40 to +85 C, VDD = 2.7 to 3.6 V) Clock Required Timing Condition (VDD = 2.7 V to 3.6 V) Parameters CLKIN cycle time Symbol tcCX Conditions MIN. 19 38 57 76 152 20 40 60 80 160 8 8 TYP. MAX. 40 80 120 160 320 40 80 120 160 320 tcCX - 8 - 2trfCXNote tcCX - 8 - 2trfCXNote 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns PD77018A PLL multiple rate: 1 PLL multiple rate: 2 PLL multiple rate: 3 PLL multiple rate: 4 PLL multiple rate: 8 PD77019 PLL multiple rate: 1 PLL multiple rate: 2 PLL multiple rate: 3 PLL multiple rate: 4 PLL multiple rate: 8 CLKIN high level width CLKIN low level width CLKIN rise/fall time twCXH twCXL trfCX Note 0.5tcCX - trfCX 8 (MIN.) Required Timing Condition (VDD = 3.0 V to 3.6 V) Parameters CLKIN cycle time Symbol tcCX Conditions PLL multiple rate: 1 PLL multiple rate: 2 PLL multiple rate: 3 PLL multiple rate: 4 PLL multiple rate: 8 CLKIN high level width CLKIN low level width CLKIN rise/fall time twCXH twCXL trfCX MIN. 16.6 33.3 50 66.6 133 6.5 6.5 TYP. MAX. 40 80 120 160 320 tcCX - 6.5 - 2trfCXNote tcCX - 6.5 - 2trfCXNote 15 Unit ns ns ns ns ns ns ns ns Note 0.5tcCX - trfCX 6.5 (MIN.) Switching Characteristics Parameters Internal clock cycle time Symbol tcC Active mode HALT mode CLKOUT cycle time CLKOUT level width CLKOUT rise/fall time tcCO twCO trfCO 0.5tcCO - 5 5 Conditions MIN. TYP. tcCX/NNote 8tcCX/NNote tcC MAX. Unit ns ns ns ns ns Note N: PLL multiple rate (N = 1, 2, 3, 4, 8) 34 PD77018A, 77019 Oscillator Circuit Resonator Ceramic or crystal resonator X1 X2 Recommended Circuit C1 C2 External clock X1 X2 External Clock NU Supply NU: Not Use. Leave Open. Cautions 1. When using system clock oscillator, wire the portion enclosed in broken lines in the figure as follows to avoid adverse influences on the wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. * Do not route the wiring in the vicinity of lines through which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as GND. * Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillator. 2. When using ceramic resonator or crystal resonator, frequency multiple rate should be specified to as 1 by mask option. The device does not operate in other frequency multiple rate. Recommended Oscillator Circuit Constants TBD 35 PD77018A, 77019 Reset, Interrupt Required Timing Condition Parameters RESET low level width Symbol tW(RL) Conditions Crystal resonator is input, at power on or STOP mode External clock is input, at power on or STOP mode Active mode or HALT mode RESET recovery time INT1-INT4 low level width INT1-INT4 recovery time trec(R) tW(INTL) trec(INT) MIN. 3 Note 1 100 Note 1 4tcC Note 2 4tcC 3tcC Note 2 3tcC TYP. MAX. Unit ms s ns ns ns ns Notes 1. The tw(RL) indicates a time between crystal resonator or oscillator starts to provide clock and PLL becomes stable. The tw(RL) depends on the rating of crystal resonator or oscillator. At power on, the tw(RL) is measured after the point that power supply voltage reaches to 2.7V. 2. Note that, during HALT mode, tcC is extended to 8 times as long as that of Active mode. 36 PD77018A, 77019 Clock Input/Output Timing tcCX twCXH X1 twCXL trfCX trfCX tcC Internal clock tcCO twCO CLKOUT twCO trfCO trfCO Reset Timing tw(RL) RESET trec(R) Interrupt Timing trec(INT) tw(INTL) INT1 - INT4 37 PD77018A, 77019 External Data Memory Access Required Timing Condition Parameters Read data setup time Read data hold time WAIT setup time WAIT hold time Symbol tsuDDRD thDDRD tsuWA thWA Conditions MIN. 15 0 12 0 TYP. MAX. Unit ns ns ns ns Switching Characteristics Parameters Address output delay time Address output hold time MRD output delay time MRD hold time Write data output valid time Write data output hold time MWR output delay time MWR setup time MWR low level width Symbol tdDA thDA tdDR thDR tvDDWD thDDWD tdDW tsuDW twDWL 0 0.25tcC - 5 0 0.5tcC - 3 + tcDW Note 0.5tcC - 5 0 16 0 8 Conditions MIN. TYP. MAX. 8 Unit ns ns ns ns ns ns ns ns ns MWR high level width twDWH ns Note tcDW: Data wait cycle External Data Memory Access Timing (Read) CLKOUT tdDA thDA DA0 DA13, X/Y tsuDDRD thDDRD D0 - D15 tdDR MRD thDR tsuWA thWA tsuWA thWA WAIT 38 External Data Memory Access Timing (Write) CLKOUT tdDA thDA DA0 - DA13, X/Y tvDDWD Hi-Z tvDDWD thDDWD Hi-Z D0 - D15 tdDW twDWL MWR tsuDW twDWH PD77018A, 77019 tsuWA thWA tsuWA thWA WAIT 39 PD77018A, 77019 Bus Arbitration Required Timing Condition Parameters HOLDRQ setup time HOLDRQ hold time Symbol tsuHRQ thHRQ Conditions MIN. 12 0 TYP. MAX. Unit ns ns Switching Characteristics Parameters BSTB hold time BSTB output delay time HOLDAK output delay time Data hold time when bus arbitration Data valid time after bus arbitration Symbol thBS tdBS tdHAK th(BS-D) tv(BS-D) Conditions MIN. 0 12 12 30 15 TYP. MAX. Unit ns ns ns ns ns 40 Bus Arbitration Timing (Bus idle) CLKOUT (Bus busy) Bus idle Bus release Bus idle (Bus busy) thBS tdBS BSTB tsuHRQ HOLDRQ tdHAK tdHAK thHRQ tsuHRQ thHRQ HOLDAK th(BS-D) X/Y, DA0 - DA13, MRD, MWR Hi-Z tv(BS-D) PD77018A, 77019 41 42 Bus Arbitration Timing (Bus busy) CLKOUT (Bus busy) Bus busy Bus idle Bus release Bus idle (Bus busy) thBS tdBS BSTB tsuHRQ thHRQ HOLDRQ tdHAK tsuHRQ thHRQ tdHAK HOLDAK th(BS-D) X/Y, DA0 - DA13, MRD, MWR Hi-Z tv(BS-D) PD77018A, 77019 PD77018A, 77019 Serial Interface Required Timing Condition Parameters SCK input cycle time SCK input high/low level width SCK input rise/fall time SOEN recovery time SOEN hold time SIEN recovery time SIEN hold time SI setup time SI hold time Symbol tcSC twSC trfSC trecSOE thSOE trecSIE thSIE tsuSI thSI 20 0 20 0 20 0 Conditions MIN. 2tcC 25 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns Switching Characteristics Parameters SORQ output delay time SORQ hold time SO valid time SO hold time SIAK output delay time SIAK hold time Symbol tdSOR thSOR tvSO thSO tdSIA thSIA 0 0 30 0 30 Conditions MIN. TYP. MAX. 30 Unit ns ns ns ns ns ns Notes for Serial Clock Serial clock inputs SCK1 and SCK2 are sensitive to any kind of interfering signals (noise on power supply, induced voltage, etc.). Spurious signals can cause malfunction of the device. Special care for the serial clock design should be taken. Careful grounding, decoupling and short wiring of SCK1 and SCK2 are recommended. Intersection of SCK1 and SCK2 with other serial interface lines or close wiring to lines carrying high frequency signals or large changing currents should be avoided. It considers for the serial clock to make a waveform stable especially about the rising and falling. Example 1. good example Straight rising form and falling form Example 2. no good example It doesn't bound. It doesn't make noise one above another. Example 3. no good example It doesn't make a stair stepping. 43 44 Serial Output Timing 1 tcSC twSC SCK1, SCK2 tdSOR thSOR twSC trfSC trfSC SORQ1 trecSOE trecSOE thSOE thSOE SOEN1, SOEN2 tvSO tvSO thSO SO1, SO2 Hi-Z 1st Last Hi-Z PD77018A, 77019 Serial Output Timing 2 (Continual output) tcSC twSC SCK1, SCK2 tdSOR thSOR twSC trfSC trfSC SORQ1 trecSOE thSOE SOEN1, SOEN2 tvSO thSO Hi-Z SO1, SO2 Last 1st Last PD77018A, 77019 45 46 Serial Input Timing 1 tcSC twSC SCK1, SCK2 tdSIA thSIA twSC trfSC trfSC SIAK1 trecSIE trecSIE thSIE thSIE SIEN1, SIEN2 tsuSI thSI SI1, SI2 1st 2nd 3rd PD77018A, 77019 Serial Input Timing 2 (Continual input) tcSC twSC SCK1, SCK2 tdSIA thSIA twSC trfSC trfSC SIAK1 trecSIE thSIE SIEN1, SIEN2 tsuSI thSI SI1, SI2 Last-1 Last 1st 2nd 3rd PD77018A, 77019 47 PD77018A, 77019 Host Interface Required Timing Condition Parameters HRD delay time HRD width HCS, HA0, HA1 read hold time HCS, HA0, HA1 write hold time HRD, HWR recovery time HWR delay time HWR width HWR hold time HWR setup time Symbol tdHR twHR thHCAR thHCAW trecHS tdHW twHW thHDW tsuHDW Conditions MIN. 0 2tcC 0 0 2tcC 0 2tcC 0 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns Switching Characteristics Parameters HRE, HWE output delay time HRE, HWE hold time HRD valid time HRD hold time Symbol tdHE thHE tvHDR thHDR 0 Conditions MIN. TYP. MAX. 30 30 30 Unit ns ns ns ns 48 Host Interface Timing (Read) CLKOUT HCS, HA0, HA1 thHCAR tdHR twHR trecHS HRD thHDR tvHDR HD0 - HD7 Hi-Z Hi-Z tdHE thHE PD77018A, 77019 HRE 49 50 Host Interface Timing (Write) CLKOUT HCS, HA0, HA1 thHCAW tdHW twHW trecHS HWR thHDW tsuHDW HD0 - HD7 tdHE thHE HWE PD77018A, 77019 PD77018A, 77019 General Input/Output Ports Required Timing Condition Parameters Port input setup time Port input hold time Symbol tsuPI thPI Conditions MIN. 20 10 TYP. MAX. Unit ns ns Switching Characteristics Parameters Port output delay time Symbol tdPO Conditions MIN. 0 TYP. MAX. 30 Unit ns General Input/Output Ports Timing CLKOUT tdPO P0 - P3 (Output) tsuPI thPI P0 - P3 (Input) 51 PD77018A, 77019 Debugging Interface (JTAG) Required Timing Condition Parameters TCK cycle time TCK high/low level width TCK rise/fall time TMS, TDI setup time TMS, TDI hold time Input pin setup time Input pin hold time Symbol tcTCK twTCK trfTCK tsuDI thDI tsuJIN thJIN 10 0 10 0 Conditions MIN. 4tcC 50 20 TYP. MAX. Unit ns ns ns ns ns ns ns Switching Characteristics Parameters TDO output delay time Output pin output delay time Symbol tdDO tdJOUT Conditions MIN. TYP. MAX. 30 30 Unit ns ns Debugging Interface Timing tcTCK twTCK twTCK trfTCK trfTCK TCK tsuDI TMS, TDI thDI Valid Valid Valid tdDO TDO tsuJIN thJIN Capture state Valid tdJOUT Update state Remark For the details of JTAG, refer to "IEEE1149.1." 52 PD77018A, 77019 5. PACKAGE DRAWING 100 PIN PLASTIC TQFP (FINE PITCH) ( A B 14) 75 76 51 50 detail of lead end C D S 100 1 26 25 F G H I M J K P N NOTE L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.00.1 0.10.05 3 +7 -3 1.27 MAX. INCHES 0.6300.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6300.008 0.039 0.039 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.039 +0.005 -0.004 0.0040.002 3 +7 -3 0.050 MAX. S100GC-50-9EU-1 Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. M Q R 53 PD77018A, 77019 6. RECOMMENDED SOLDERING CONDITIONS When soldering these products, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Surface Mount Device PD77018AGC-xxx-9EU: 100-pin plastic TQFP (FINE PITCH) (14 x 14mm) PD77019GC-xxx-9EU: 100-pin plastic TQFP (FINE PITCH) (14 x 14mm) Process Conditions Peak temperature: 235 C or below (Package surface temperature), Reflow time: 30 seconds or less (at 210 C or higher), Maximum number of reflow processes : 2 times, Exposure limit Note : 3 days (10 hours pre-baking is required at 125 C afterwards). Vapor Phase Soldering Peak temperature: 215 C or below (Package surface temperature), Reflow time: 40 seconds or less (at 200 C or higher), Maximum number of reflow processes : 2 times, Exposure limit Note : 3 days (10 hours pre-baking is required at 125 C afterwards). Partial heating method Pin temperature : 300 C or below, Heat time : 3 seconds or less (Per each side of the device) VP15-103-2 Symbol IR35-103-2 Infrared ray reflow Note Maximum allowable time from taking the soldering package out of dry pack to soldering. Storage conditions: 25 C and relative humidity of 65 % or less. Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or the device will be damaged by heat stress. 54 PD77018A, 77019 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 55 PD77018A, 77019 [MEMO] The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 |
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