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LZ93BE0
LZ93BE0
DESCRIPTION
The LZ93BE0 is a CMOS timing generator LSI which provides horizontal transfer pulse, reset pulse, and sample-hold pulse used for separate camera, in combination with single-chip driver LSI (LZ95G55, LZ95G41 ) and timing LSI (LZ93F33, LZ93F50, LZ93N61 or LZ95D37/M).
Timing Pulse Generator LSI for CCD PIN CONNECTIONS
20-PIN MFP
/"
TOP VIEW
1 =o FHIB 2 GND 3
FH I
a Vcc ~ FCDS
18 FS 17
FEATURES
q Switchable between 270 ~0 pixels CCD and
FH2 FH2B
4 5
co
16 c l 15 s o 1 4 SI g CH 12 SLCT 11 MIR
320000 pixels CCD
q Switchable between NTSC (EIA) and PAL
HDI ~ TVMD FR CKI 7 8 9
(CCIR) systems
q Single +5 V power supply q Switchable between normal and mirror-image q Suitable for separate camera q Package : 20-pin MFP(MFP020-P) Designed for A-type and B-type CCD area sensors :
GND 10
A-type CCD area sensor : LZ2314J, LZ2324J, LZ231 32, LZ23232 B-type CCD area sensor : LZ2414J, LZ2424J, LZ2313H5, LZ2323H5, LZ2413, LZ2423
BLOCK DIAGRAM
"in tie ab%nce of con f(nnatlon by device $pectf{cation sheets, SHARP takes no respnslb(l[v for any defecs hat xcur in equipment using any of SHARPs devices, shown In cahlcgs, 256 I data bwks, etc CQntacl SHARP In order to obkln he latest version of tie device wlf!cation*wts betcn'e using any SHARPs device'
LZ93BE0 ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage lnDut voltaae voltage I SYMBOL Vcc VI Vo Topr Tstq I RATING - 0.3 to 7.0 -0,3 to Vcc + 0.3 -0.3 to VCC+O.3 ] UNIT v v v `c "c I
Gt
Operation temperature Storaae temperature
- 2 0 t o +70 -55 to +150
DC CHARACTERISTICS
PRAMETER Input Low voltage Input High voltage Input High threshold voltage Input Low threshold voltage Hysteresis voltage Input Low current Input High current Output High voltage Output Low voltage Output High voltage OutDut LOW voltaae output High voltage Output Low voltage SYMBOL
vlL vlH
(VCC=+5 Vf5% T a = - 2 0 CONDITIONS MIN. TYP. MAX.
1.5
t o +7UC
NOTE 1
UNIT v v
3.5 2.2 Schmitt Buffer 1.0 0.4 Vl=o v Vl=o v
VI= Vcc IoH=- Z
vT + vT vT+ -VTI IIL1 I I I
11L2 IIH I I
3.8 2.4
v v v 2
1.0 8.0 60
1,0
,uA ,uA PA v
3 4 5 6
vOH 1 vOL1
vOH2 v0L2
mA
4.0 0.4 4.0 0.4 4.0 0.4
IOL = 4 mA
IoH=-4
v v
mA
IOL = 8 mA IoH=-6 mA 10.=12 mA
7 v v 8 v
vOH3 vOL3
NOTES : 1. Applled to inputs (IC, ICU).
2. Applied to Input (ICS). 3. Applied to inputs (IC, ICS). 4. Applied to Input (ICU). 5. Applied to inputs (IC, ICU, ICS) 6. Applied to output (0) 7. Applied to output (08M) 8 Applied to output (012M)
257
LZ93BE0
:!.
1
SYMBOL FH I
1/0
012M
POIARITY N
PfN NAME Horizontal transfer pulse 1
FLfNCTION A horizontal transfer pulse for CCD area sensor. tinnect to 4 HI of CCD area sensor. A horizontal transfer pulse for CCD area sensor, Connect to 4 HI E of CCD area sensor. If the CCD area sensor which corresponds to Mirror mode is driven at Normal mode (MIR = L), its drive-pulse is the same phase as the pulse of FHI (pin 1), and it is the same phase as the pulse of FH2 (pin 4) at Mirror mode (MIR = H). A grounding pin. A horizontal transfer pulse for CCD area sensor. ~nfleCt to ~ HZ of CCD area sensor, A horizontal transfer pulse for CCD area sensor. bnnect to 4 H2E of CCD area sensor. If the CCD area sensor which corresponds to Mirror mode is driven at Normal mode (MIR = L), its drive-pulse is the same phase as the pulse of FH2 (pin 4),and it is the same phase as the pulse of FH I (pin 1 ) at Mirror mode (MIR = H). Put in a horizontal reference pulse from SSG-LSI. ~nnect to HD terminal of SSG-LSI. An input-pin to select TV standards, L level : NTSC mode H level or o~n : PAL mode A reset pulse for CCD area sensor, bnnect to ~ R of CCD area sensor through the DC offset circuit. An input pin for reference clock. The frequencies are as follows : At EIA mode : 19.06993 MHz (1212 fH) At CCIR mode : 19.31250 MHz (1 236 fH) A grounding pin. An input pin to select Mirror mode or Normal mode. L level : Normal Drive mode H level or open : Mirror Drive mode An input pin to select the type of CCD area sensw, L level (A type) LZ23t4J, LZ2314Z, LZ23t42, LZ2313A9, LZ23132 LZ2324J, LZ2324Z, LZ23242, LZ2323A9, LZ23232 H level or open (B type) LZ2314BK, LZ2414J, LZ2313B5, LZ2313H5, LZ2413 LZ2324BK, U2424J, LZ2323B5, LZ2323H5, LZ2423
2
FHIB
08M
m
Horizontal transfer pulse 1 B
3 4
GND FH2
- 012M
- m
Ground Horizontal transfer pulse 2
5
FHZB
08M
m
Horizontal transfer pulse 2B
6
HDI
Ics
-
Horizontal reference pulse TV mode select
7
TVMD
Icu
-
8
FR
08M
n
Reset pulse
9
CKI
Ics
nn
Clock input
10 11
GND MIR
- Icu
- --
Ground Mirror mode select
12
SLCT
Icu
--
CCD type select
U93BE0
WN
"~
SYMBOL
1/0
POtARiTY
PIN NAME Phase control terminal for FCDS and FS
FUNCTION An input pin to select the phase of FCDS (pin 19) pulse and FS (pin 18) pulse. L level : adjustable H level or open : fixed An input pin to control the phase of FS (pin 18). SO (pin 15) pulse put in this terminal after make it delay with resistor and capacitor. An output pin to control the phase of FS (pin 18). The output pulse put in S1 (pin 14) after make it delay with resistor and capacitor. An input pin to control the phase of FCDS (pin 19). CD (pin 17) pulse put in this terminal after make it delay with resistor and capacitor. An output pin to control the phase of FCDS (pin 19). The output pulse put in Cl (pin 16) after make it delay with resistor and capacitor. A pulse to sample-hold the signal from CCD area sensor. The phase of FS is fixed if CH (pin 13) equals H level and it can be adjustable if CH (pin 13) equals L level. A pulse to clamp the feed-through level form CCD area sensor. The phase of FCDS is fixed if CH (pin 13) equals H level and it can be adjustable if CH (pin 13) equals L level.
Supply +5 V power.
13
CH
Icu
--
14
SI
Ic
-
Phase-adjust input for FS Phase-adjust output for FS Phase-adjust input for FCDS Phase-adjust output for FCDS
15
so
o
nn
18
cl
Ic
--
17
co
o
nrl
18
FS
o
n
Sample-hold pulse output
19
FCDS
o
n
CDS pulse output
20
Vcc
-
--
Power supply
Ic
Icu Ics
: Input pin (CMOS level input) : Input pin (CMOS level input with pull-up resistor) : Input pin (CMOS scnmiti input )
O, 08M, 012M : Output pin
NOTE : At the input pin, the rising edge of HDI (pin 6) is f 20 ns shorter than that of CKI (pin 9).
259
LZ93BE0 TIMING DIAGRAM
NTSC(EIA) < A-TYPE, NORMAL MODE >
1212,0 49
1 clock = 52.4 ns
114
HDI CBLK CKI FH I FHz FHIB FH2B FR FCDS FS
114 120 166 210
HDI CBLK CKI FH I FH2 FHIB FHZB XX FR FCDS FS Ulnllnnnnnl lnnnnmnnnnlllln ~wnnnnn X X1212345678 101214161 ~202224 26 ~mdw~ 1~ ~~~m
---
nnnnnnnn~nnnnnnnn
NTSC(EIA) < A-TYPE, MIRROR MODE >
1212,0 HDI CBLK CKI FH I FH2 FHIB FH2B
OBIXXX XXX 1111 JIJlnnn Mnn nnnnnn~flflflnnnflfl~flfl nnnnlln
1
clock = 52.4 ns 114
8
FR FCDS FS
Pw~nnnn
flfl
n rd~
m~nnnnL!lnnnnllnnn
nluLJlnnflnnn ~d~w
lnnnnnnn~ nnnrlnnnnnnnn ~~JL
114 116 120 210 T
HDI CBLK CKI FH I FHz FHIe FH2B FR FCDS FS
LZ93BE0
NTSC(EIA) < B-TYPE, NORMAL MODE >
1212,0 HDI CBLK CKI FH 1 FH2 FHIB FH2B FR FCDS FS 14 HDI CBLK CKI FH I FH2 FHiB FHZB FR FCDS FS 120 163 210
!
1
clock= 52.4 ns 174 --
47
1 I
I
NTSC(EIA) < B-TYPE, MIRROR MODE >
1212,0 3 HDI CBLK CKI FH T FH2 FHIB FHZB OBIXX X X FR FCDS FS 114 HDI CBLK CKI FH I FH2 FHIB FH2B XX X X XOB28 FR FCDS FS 0B20 OB1O , 1 120 nnnnnluln nnnluuuulnllnnnn nnluuuuLnnnfl~flflflflfl 210 nnnnruulnnnnnnn~n J
1 clock =52.4 ns 111 114
x nnn~flflnflnflflfl flu
flnflfl~
OBI 512 510 W 5C6 W W2 500 498 496 494 492 4W W nnlLrLn nnnrLnflnnn~ flflfl~ `nnnm
nnnll~nn
Jflflflflflflnflflfl~
261
U93BE0
PAL(CCIR) < A-TYPE, NORMAL MODE >
1236,0 HDI CBLK CKI FH I FH. FHi B FH2B 0B4 FR FCDS FS nnnflnnn OB1O nnllnnn OB20 0B28 nnnnnnn nnnnnn~nnnmnnnnnm 48
1 clock = 51.8 ns 114
--
nnnnnnflnnnnnnnnn~ Mnnnnnnn nnflnnnnnnnn 192
nnflm
nnwflflnnnnJLluLll
nnnnnn
MnnnnnJ nnnnLILIL nnnnfln~ 234
1
mflnnnn nnflnflnnnn~ 114 120 I
nnnnn Mnnnnnn
HDI CBLK CKI FH I FH2 FHIB FH2B FR FCDS FS
UlnMMM~llln J u"mT'-1uJ-LnnrLUuuLrLrI_Ju nUL--11-nruLrLUuuLnr1.XXXX1212345878 nnnnnnn lnnnnll nnnnnJnnnnnMnnnn nmnnnnn nmnnnnnnnnnnnn nllnnllmnnnn~nnnnn nMnnflnnnnunnn nn~llnllnnnnnnn n~nllnnnnll 10 12 14 m~
mm
nllflfl nnnnllll
n~ nmnnnnllnnm r
PAL(CCIR) < A-TYPE, MIRROR MODE >
12%,0 HDI CBLK CKI FH I FH2 FHIB FH2B FR FCDS FS 3
1
clock =51.8 ns 114
m Ju
m lr
JL
OBIXXXXXX nnllnnluLll_n nnnnn~n mnnnlLll 114 i 20 I nnnnnn~ nnnfl Mnnllnn nnnnnnn nnnnnnnnnnnnnnnn nnLILrLJuLILIL nnnnnnn nflnnn Mnnnnflfln~ nnnnnnllnn~ 234
nnnnnMnnnnnllnnn 140
nnnnnlLn_lLn nllflllnllnnnnmfl
HDI CBLK CKI FH I FHz F HIB FH2B FR FCDS FS
Mnnnnnn ruLnnnhnnnnn~ nnnnnnn nnnnnnnnnn~n nnnnnnnnnnnn
nnnnnnn nnnnnnnnnnnnnnnn nnnn Mnnnnnnnnn nnflnnn nnnnnnnnnnnnnnnnn JMnnnnn nnnJnnn nn~nnnnnnnnnufl
m Uul~~ u ULruL-uuLv ~ mnnnn~ nn~ XX X XOB28 OB20 OB1O OB1 512 510 5W 506 504 502 ~
nnnnn~ ~L flflflflfl~
L
262
LZ93BE0
PAL(CCIR) < B-TYPE, NORMAL MODE >
7236,0 HDI CBLK CKI FH I FH. FHIe FH2B OB4 FR FCDS FS OB1O 0 OB~ OB28 m~Lrlnn llnnnnnnllllfln 47
1 clock =51,8 ns 114
Ln nnnnnnn nMnnflnnnnnnnnn~
lnnflnn nnmnnnnnnllnn~ nnnn~ 114 120 187 234
HDI CBLK CKI FH t FH2 FHIB FH2B FR FCDS FS
L
u JuuumJmMmJ-nv. uWm1mmmJnunn~
XXXXXX121234567 8 10 12 14 nnnnnMn nnnnnn Lnnnnflnn nnnnn~ nnnllnn~ nnllnllnrL m~nn nnnnnnnnn~nnnlln~ nnnnr
PAL(CCIR) < B-TYPE, MIRROR MODE >
i236,0 3 HDI CBLK CKI FH I FHz FHIB FH2B OBIX X X X FR FCDS FS 114 HDI CBLK CKI FH I FHz 120 135
1
clock=51.8
ns i14
MUIM~~ mm 7n
rLul 7n
nnnllnlln~
234
L
Hum~
XXXXXXOB28 FR FCDS FS
OBm
OB1O
OBI 512 510 W ~ 504 W2 500 :
mnnnnnnn~ nnnnnnn nnnnflnnnnnnnnnnnn nnnn; nnnnnnn nnnnnnnnnnnnnnnnn nnnnnnn nnnnnnnnnMnnnnnn ruuuuulnllllllllll
lnnnnnn nnnnJnnnnnnnnnn nlLILnnnllnnnllnn~
263
LZ93F33
LZ93F33
DESCRIPTION
The LZ93F33 is a CMOS timing generator LSI which provides timing pulses used to drive a CCD area sensor, in combination with the SSG LSI (LZ93N19 or LZ93B53).
Timing Pulse Generator LSI for CCD
PIN CONNECTIONS
48-PIN QFP
cx$:i~::$ic~ >S>>oa>z+>z 2 TOP VIEW
FEATURES
q Switchable between 270000 pixels CCD and q q q q q q
v3k
37
24 MCDI 23 MFS2 22 MFSI 21 FS 20 FCDS 19 INSL 18 TO 17 SE 16 SINV 15 SESL 14 SP2
V4X $
OFDX 39 FR 40 FHZB 41 FH2 42 GND 43 FH I z FHIB 45 CKI 46 CKO 47 TEST 48
320000 pixels CCD Switchable between NTSC (EIA) and PAL (CCIR) systems Built-in EE (Electronic Exposure) control Flicker-less function Switchable between normal and mirror image Single +5 V power supply Package : 48-pin QFP(QFP048-P-101 O)
0
llf121131141] 511611711811911101111 ]l12 aaogoood>om o r>nzzzz~~~z + ~tiu13 SP1
TO
GND
GND
GND
Vcc
TEST
TSTO
Vlx
VDI
V2X V3X V4X
TVMD MIR ACL
TOSL DO CKI CKO
4
HDI EEST EEUD EENR
i
r
SHU~ER UP/DOWN CONTROL SHUTTER SPEED CONTROL
1 C"NTR"' B
EEMD FLMD
VHIX VH3X OBCP SINV SESL FHI FHIE FH2 FHZB FR FS FCDS SE SP2 SPI MFSI MFS2 MCDI MCD2 MFR I MFR2 INS' OFDX
"In abwnce confinnahon by SHARP takes no rewnmblllv fci any defacta tiat in equipment using 264 I databeWks, etc. ofContact SHARP dev[ce sw[flcahontieaheek,wmlon of the dev!ce Wlfcahon shwts kf~ using cccur SHARPs device" any of WARPs devices, ah~ In ca~lws, uder to obm(n Iateat any
Im

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