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19-3011; Rev 0; 10/03
KIT ATION EVALU E AILABL AV
15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
General Description Features
o 65Msps Minimum Sampling Rate o -79.3dBFS Noise Floor o Excellent Dynamic Performance 76.2dB SNR at fIN=15MHz and AIN = -1dBFS 93.1dBc/95.5dBc Single-Tone SFDR1/SFDR2 at fIN = 15MHz and AIN = -1dBFS -91dBc Multitone SFDR at fIN1 = 10MHz and fIN2 = 15MHz o Less than 0.25ps Sampling Jitter o Fully Differential Analog Input Voltage Range of 2.56VP-P o CMOS-Compatible Two's-Complement Data Output o Separate Data Valid Clock and Overrange Outputs o Flexible-Input Clock Buffer o EV Kit Available for the MAX1419 (Order MAX1427EVKIT)
MAX1419
The MAX1419 is a 5V, high-speed, high-performance analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) and a 15-bit converter core. The MAX1419 is optimized for multichannel, multimode receivers, which require the ADC to meet very stringent dynamic performance requirements. With a noise floor of -79.3dBFS, the MAX1427 allows for the design of receivers with superior sensitivity. The MAX1419 achieves two-tone, spurious-free dynamic range (SFDR) of -91dBc for input tones of 10MHz and 15MHz. Its excellent signal-to-noise ratio (SNR) of 76.2dB and single-tone SFDR performance (SFDR1/SFDR2) of 93.1dBc/95.5dBc at fIN = 15MHz and a sampling rate of 65Msps make this part ideal for high-performance digital receivers. The MAX1419 operates from an analog 5V and a digital 3V supply, features a 2.56VP-P full-scale input range, and allows for a sampling speed of up to 65Msps. The input T/H operates with a -1dB full-power bandwidth of 200MHz. The MAX1419 features parallel, CMOS-compatible outputs in two's-complement format. To enable the interface with a wide range of logic devices, this ADC provides a separate output driver power-supply range of 2.3V to 3.5V. The MAX1419 is manufactured in an 8mm x 8mm, 56-pin QFN package with exposed paddle (EP) for low thermal resistance, and is specified for the extended industrial (-40C to +85C) temperature range. Note that IF parts MAX1418, MAX1428, and MAX1430 (see the Pin-Compatible Higher/Lower Speed Versions Selection table) are recommended for applications that require high dynamic performance for input frequencies greater than fCLK/3. The MAX1419 is optimized for input frequencies of less than fCLK/3.
Ordering Information
PART MAX1419ETN
*EP
TEMP RANGE -40C to +85C
PIN-PACKAGE 56 QFN-EP*
= Exposed paddle.
Applications
Cellular Base-Station Transceiver Systems (BTS) Wireless Local Loop (WLL) Single- and Multicarrier Receivers Multistandard Receivers E911 Location Receivers Power Amplifier Linearity Correction Antenna Array Processing
Pin-Compatible Higher/Lower Speed Versions Selection
PART MAX1418 MAX1419 MAX1427 MAX1428* MAX1429* MAX1430* SPEED GRADE (Msps) 65 65 80 80 100 100 TARGET APPLICATION IF Baseband Baseband IF Baseband IF
Pin Configuration appears at end of data sheet.
*Future
product--contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
ABSOLUTE MAXIMUM RATINGS
AVCC, DVCC, DRVCC to GND.................................. -0.3V to +6V INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AVCC + 0.3V) D0-D14, DAV, DOR to GND..................-0.3V to (DRVCC + 0.3V) Continuous Power Dissipation (TA = +70C) 56-Pin QFN (derate 47.6mW/C above +70C) ......3809.5mW Operating Temperature Range ...........................-40C to +85C Thermal Resistance JA ...................................................21C/W Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVCC = 5V, DVCC = DRVCC = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT (INP, INN) Differential Input Voltage Range Common-Mode Input Voltage Differential Input Resistance Differential Input Capacitance Full-Power Analog Bandwidth CONVERSION RATE Maximum Clock Frequency Minimum Clock Frequency Aperture Jitter CLOCK INPUT (CLKP, CLKN) Full-Scale Differential Input Voltage Common-Mode Input Voltage Differential Input Resistance Differential Input Capacitance DYNAMIC CHARACTERISTICS Thermal + Quantization Noise Floor Signal-to-Noise Ratio (Note 1) NF Analog input <-35dBFS fIN = 5MHz at -1dBFS SNR fIN = 15MHz at -1dBFS fIN = 25MHz at -1dBFS 73.5 -79.3 76.5 76.1 76 dB dBFS VDIFFCLK VCM RINCLK CINCLK Fully differential input drive, VCLKP - VCLKN Self-biased 0.5 to 3.0 2.4 2 15% 1 V V k pF fCLK fCLK tAJ 65 20 0.21 MHz MHz psRMS VDIFF VCM RIN CIN FPBW-1dB -1dB rolloff for a full-scale input Fully differential inputs drive, VDIFF = VINP - VINN Self-biased 2.56 3.38 1 15% 1 200 VP-P V k pF MHz INL DNL fIN = 15MHz fIN = 15MHz, no missing codes guaranteed -12 -4 15 1.5 0.4 +12 +4 Bits LSB LSB mV %FS SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = 5V, DVCC = DRVCC = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization.)
PARAMETER Signal-to-Noise and Distortion (Note 1) Spurious-Free Dynamic Range (HD2 and HD3) (Note 1) Spurious-Free Dynamic Range (HD4 and Higher) (Note 1) Two-Tone Intermodulation Distortion Two-Tone Spurious-Free Dynamic Range Digital Output Voltage Low Digital Output Voltage High SYMBOL CONDITIONS fIN = 5MHz at -1dBFS fIN = 15MHz at -1dBFS fIN = 25MHz at -1dBFS fIN = 5MHz at -1dBFS SFDR1 fIN = 15MHz at -1dBFS fIN = 25MHz at -1dBFS fIN = 5MHz at -1dBFS SFDR2 fIN = 15MHz at -1dBFS fIN = 25MHz at -1dBFS TTIMD SFDRTT fIN1 = 10MHz at -7dBFS; fIN2 = 15MHz at -7dBFS fIN1 = 10MHz at -10dBFS < fIN1 < -100dBFS; fIN2 = 15MHz at -10dBFS < fIN2 < -100dBFS 85.5 84 73 MIN TYP 76.3 75.9 74.3 96.5 93.5 80.5 94.5 94.5 93.2 -91 -105 dBc dBFS dBc dBc dB MAX UNITS
MAX1419
DIGITAL OUTPUTS (D0-D14, DAV, DOR) VOL VOH DVCC 0.5 0.5 V V
TIMING CHARACTERISTICS (DVCC = DRVCC = 2.5V) Figure 4 CLKP/CLKN Duty Cycle Effective Aperture Delay Output Data Delay Data Valid Delay Pipeline Latency CLKP Rising Edge to DATA Not Valid CLKP Rising Edge to DATA Valid (Guaranteed) DATA Setup Time (Before DAV Rising Edge) DATA Hold Time (After DAV Rising Edge) Duty cycle tAD tDAT tDAV tLATENCY tDNV tDGV tSETUP tHOLD (Note 3) (Note 3) (Note 3) (Note 3) 2.6 3.4 tCLKP 0.5 (Note 3) (Note 3) 3 5.3 50 5 230 4.5 6.5 3 3.8 5.2 tCLKP + 1.3 5.7 8.6 tCLKP + 2.4 7.5 8.7 % ps ns ns Clock cycles ns ns ns ns
tCLKN - tCLKN - tCLKN 3.6 2.8 2.0
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = 5V, DVCC = DRVCC = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, unless otherwise noted. +25C guaranteed by production test, <+25C guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS MIN TYP 50 5 230 (Note 3) (Note 3) 2.8 5.3 4.1 6.3 3 (Note 3) (Note 3) (Note 3) (Note 3) 2.5 3.2 tCLKP + 0.2 3.4 4.4 tCLKP + 1.7 5.2 7.4 tCLKP + 2.8 6.5 8.6 MAX UNITS
TIMING CHARACTERISTICS (DVCC = DRVCC = 3.3V) Figure 4 CLKP/CLKN Duty Cycle Effective Aperture Delay Output Data Delay Data Valid Delay Pipeline Latency CLKP Rising Edge to DATA Not Valid CLKP Rising Edge to DATA Valid (Guaranteed) DATA Setup Time (Before DAV Rising Edge) DATA Hold Time (After DAV Rising Edge) POWER REQUIREMENTS Analog Supply Voltage Range Digital Supply Voltage Range Output Supply Voltage Range Analog Supply Current Digital + Output Supply Current Analog Power Dissipation AVCC DVCC DRVCC IAVCC IDVCC + PDISS (Note 2) (Note 2) fCLK = 65MHz, CLOAD = 5pF 5 3% 2.3 to 3.5 2.3 to 3.5 377 35.5 1974 440 42 V V V mA mA mW Duty cycle tAD tDAT tDAV tLATENCY tDNV tDGV tSETUP tHOLD % ps ns ns Clock cycles ns ns ns ns
tCLKN - tCLKN - tCLKN 3.5 2.7 2.0
Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of fSAMPLE = 65.0117120MHz, an input frequency of fIN = fSAMPLE x (7561/32768) = 15.001024MHz, and a frequency bin size of 1984Hz. Close-in (fIN 23.8kHz) and low-frequency (DC to 47.6kHz) bins are excluded from the spectrum analysis. Note 2: Apply the same voltage levels to DVCC and DRVCC. Note 3: Guaranteed by design and characterization.
4
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
Typical Operating Characteristics
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = +25C. All AC data based on a 32k-point FFT record and under coherent sampling conditions.)
FFT PLOT (32,768-POINT DATA RECORD, COHERENT SAMPLING)
MAX1419 toc01
FFT PLOT (32,768-POINT DATA RECORD, COHERENT SAMPLING)
fCLK = 65.0117MHz fIN = 15.0010MHz AIN = -0.98dBFS SNR = 76.5dB SFDR1 = 89.1dBc SFDR2 = 98.1dBc HD2 = 94.8dBc HD3 = 89dBc
MAX1419 toc02
FFT PLOT (32,768-POINT DATA RECORD, COHERENT SAMPLING)
fCLK = 65.0117MHz fIN = 25.0004MHz AIN = -06dBFS SNR = 76.3dB SFDR1 = 77.9dBc SFDR2 = 92.3dBc HD2 = 85.6dBc HD3 = 77.9dBc
MAX1419 toc03
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 0 5 10 15
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
fCLK = 65.0117MHz fIN = 10.0013MHz AIN = -1.02dBFS SNR = 76.8dB SFDR1 = 87.7dBc SFDR2 = 98.3dBc HD2 = 87.7dBc HD3 = 91.5dBc
0 -20 -40 -60 -80 -100 -120
0 -20 -40 -60 -80 -100 -120
20
25
30
0
5
10
15
20
25
30
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SNR vs. ANALOG INPUT FREQUENCY (fCLK = 65.0117MHz, AIN = -1dBFS)
MAX1419 toc04
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY (fCLK = 65.0117MHz, AIN = -1dBFS)
MAX1419 toc05
HD2/HD3 vs. ANALOG INPUT FREQUENCY (fCLK = 65.0117MHz, AIN = -1dBFS)
MAX1419 toc06
78 77 76
100 95
-70 -75 HD2/HD3 (dBc) -80 -85 HD2 -90 -95 -100
SFDR2
SFDR1/SFDR2 (dBc) 90 85 80 75 70 SFDR1
HD3
SNR (dBc)
75 74 73 72 71 70 5 15 25 35 fIN (MHz) 45 55 65
5
15
25
35 fIN (MHz)
45
55
65
5
15
25
35 fIN (MHz)
45
55
65
FULL-SCALE-TO-NOISE RATIO vs. ANALOG INPUT AMPLITUDE (fCLK = 65.011712MHz, fIN = 15.0010MHz)
MAX1419 toc07
SFDR1/SFDR2 vs. ANALOG INPUT AMPLITUDE (fCLK = 65.0117MHz, fIN = 15.0010MHz)
MAX1419 toc08
HD2/HD3 vs. ANALOG INPUT AMPLITUDE (fCLK = 65.0117MHz, fIN = 15.0010MHz)
-80 -90 HD2/HD3 (dBFS) -100 -110 -120 -130 HD2 HD3
MAX1419 toc09
80 FULL-SCALE-TO-NOISE RATIO (dBFS) 79 78 77 76 75 74 73 72 71 70 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS)
130 120 SFDR1/SFDR2 (dBFS) 110 100 90 80 70 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS) SFDR1
-70
SFDR2
-140 -150 -70 -60 -50 -40 -30 -20 -10 0 ANALOG INPUT AMPLITUDE (dBFS)
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
Typical Operating Characteristics (continued)
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = +25C. All AC data based on a 32k-point FFT record and under coherent sampling conditions.)
SNR vs. SAMPLING FREQUENCY (fIN = 15.2MHz, AIN = -1dBFS)
MAX1419 toc10
SFDR1/SFDR2 vs. SAMPLING FREQUENCY (fIN = 15.2MHz, AIN = -1dBFS)
MAX1419 toc11
HD2/HD3 vs. SAMPLING FREQUENCY (fIN = 15.2MHz, AIN = -1dBFS)
-75 -80 -85 HD2/HD3 (dBc) -90 -95 -100 -105 -110 -115 HD2 HD3
MAX1419 toc12
78 77 76
100 SFDR2 95 SFDR1/SFDR2 (dBc) 90 85 80 75 70
-70
SNR (dBc)
75 74 73 72 71 70 20 25 30 35 40 45 50 55 60 65 fCLK (MHz)
SFDR1
-120 20 25 30 35 40 35 50 55 60 65 20 25 30 35 40 45 50 55 60 65 fCLK (MHz) fCLK (MHz)
SNR vs. TEMPERATURE (fCLK = 65.0117MHz, fIN = 15.0010MHz, AIN = -1dBFS)
MAX1419 toc13
SINAD vs. TEMPERATURE (fCLK = 65.0117MHz, fIN = 15.0010MHz, AIN = -1dBFS)
MAX1419 toc14
78
78
77
77
SNR (dB)
76
SINAD (dB) -40 85
76
75
75
74
74
73 -15 10 35 60 TEMPERATURE (C)
73 -40 -15 10 35 60 85 TEMPERATURE (C)
6
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
Typical Operating Characteristics (continued)
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 65MHz, TA = +25C. All AC data based on a 32k-point FFT record and under coherent sampling conditions.)
SFDR1/SFDR2 vs. TEMPERATURE (fCLK = 65.0117MHz, fIN = 15.0010MHz, AIN = -1dBFS)
MAX1419 toc15
MAX1419
HD2/HD3 vs. TEMPERATURE (fCLK = 65.0117MHz, fIN = 15.0010MHz, AIN = -1dBFS)
MAX1419 toc16
POWER DISSIPATION vs. TEMPERATURE (fCLK = 65.0117MHz, fIN = 15.0010MHz, AIN = -1dBFS)
MAX1419 toc17
100 SFDR2 96 SFDR1/SFDR2 (dBc)
-85 HD2 -90 HD2/HD3 (dBc)
1976 1975 POWER DISSIPATION (mW) 1974 1973 1972 1971
92 SFDR1 88
-95
HD3
84
-100
80 -40 -15 10 35 60 85 TEMPERATURE (C)
-105 -40 -15 10 35 60 85 TEMPERATURE (C)
1970 -40 -15 10 35 60 85 TEMPERATURE (C)
POWER DISSIPATION vs. SUPPLY VOLTAGE (fCLK = 65.0117MHz, fIN = 15.0010MHz, AIN = -1dBFS)
MAX1419 toc18
TWO-TONE IMD PLOT (32,768-POINT DATA RECORD, COHERENT SAMPLING)
fCLK = 65.0117MHz fIN1 = 10.0010MHz fIN2 = 15.0010MHz AIN1 = AIN2 = -7dBFS
MAX1419 toc19
2200 2150 POWER DISSIPATION (mW) 2100
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 2fIN1 - fIN2
fIN1
2050 2000 1950 1900 1850 1800 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 SUPPLY VOLTAGE (V)
fIN2
2fIN2 - fIN1
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
Pin Description
PIN 1, 2, 3, 6, 9, 12, 14-17, 20, 23, 26, 27, 30, 52-56, EP 4 5 7, 8, 18, 19, 21, 22, 24, 25, 28 10 11 13 29 31, 41, 42, 51 NAME GND CLKP CLKN AVCC INP INN CM DVCC DRVCC FUNCTION Converter Ground. Analog, digital, and output driver grounds are internally connected to the same potential. Connect the converter's EP to GND. Differential Clock, Positive Input Terminal Differential Clock, Negative Input Terminal Analog Supply Voltage. Provide local bypassing to ground with 0.1F to 0.22F capacitors. Differential Analog Input, Positive Terminal Differential Analog Input, Negative/Complementary Terminal Common-Mode Reference Terminal Digital Supply Voltage. Provide local bypassing to ground with 0.1F to 0.22F capacitors. Digital Output Driver Supply Voltage. Provide local bypassing to ground with 0.1F to 0.22F capacitors. Data Overrange Bit. This control line flags an overrange condition in the ADC. If DOR transitions high, an overrange condition was detected. If DOR remains low, the ADC operates within the allowable full-scale range. Digital CMOS Output Bit 0 (LSB) Digital CMOS Output Bit 1 Digital CMOS Output Bit 2 Digital CMOS Output Bit 3 Digital CMOS Output Bit 4 Digital CMOS Output Bit 5 Digital CMOS Output Bit 6 Digital CMOS Output Bit 7 Digital CMOS Output Bit 8 Digital CMOS Output Bit 9 Digital CMOS Output Bit 10 Digital CMOS Output Bit 11 Digital CMOS Output Bit 12 Digital CMOS Output Bit 13 Digital CMOS Output Bit 14 (MSB) Data Valid Output. This output can be used as a clock control line to drive an external buffer or data-acquisition system. The typical delay time between the falling edge of the converter clock and the rising edge of DAV is 6.5ns.
32 33 34 35 36 37 38 39 40 43 44 45 46 47 48 49 50
DOR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 DAV
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
Detailed Description
Figure 1 provides an overview of the MAX1419 architecture. The MAX1419 employs an input T/H amplifier, which has been optimized for low thermal noise and low distortion. The high-impedance differential inputs to the T/H amplifier (INP and INN) are self-biased at 3.38V, and support a full-scale differential input voltage of 2.56VP-P. The output of the T/H amplifier is fed to a multistage pipelined ADC core, which has also been optimized to achieve a very low thermal noise floor and low distortion. A clock buffer receives a differential input clock waveform and generates a low-jitter clock signal for the input T/H. The signal at the analog inputs is sampled at the rising edge of the differential clock waveform. The differential clock inputs (CLKP and CLKN) are highimpedance inputs, are self-biased at 2.4V, and support differential clock waveforms from 0.5VP-P to 3.0VP-P. The outputs from the multistage pipelined ADC core are delivered to error correction and formatting logicwhich in turn, deliver the 15-bit output code in two'scomplement format to digital output drivers. The output drivers provide CMOS-compatible outputs with levels programmable over a 2.3V to 3.5V range.
INP
MAX1419
AVCC
GND
DVCC
DRVCC
MAX1419
INN CM INTERNAL REFERENCE
T/H
MULTISTAGE PIPELINE ADC CORE
CLKP CLOCK BUFFER CLKN
INTERNAL TIMING
CORRECTION LOGIC + OUTPUT BUFFERS 15
DAV DATA BITS D0 THROUGH D14
Figure 1. Simplified MAX1419 Block Diagram
T/H AMPLIFIER INP TO 1. QUANTIZER STAGE
500 BUFFER
1k CM INTERNAL REFERENCE AND BIASING CIRCUIT
Analog Inputs and Common Mode (INP, INN, CM)
The signal inputs to the MAX1419 (INP and INN) are balanced differential inputs. This differential configuration provides immunity to common-mode noise coupling and rejection of even-order harmonic terms. The differential signal inputs to the MAX1419 should be AC-coupled and carefully balanced in order to achieve the best dynamic performance (see the Applications Information section for more detail). AC-coupling of the input signal is easily accomplished because the MAX1419 inputs are self-biasing as illustrated in Figure 2. Although the T/H inputs are high impedance, the actual differential input impedance is nominally 1k because of the two 500 bias resistors connected from each input to the common-mode reference.
500
INN
T/H AMPLIFIER TO 1. QUANTIZER STAGE
Figure 2. Simplified Analog and Common-Mode Input Architecture
The CM pin provides a monitor of the input commonmode self-bias potential. In most applications, in which the input signal is AC-coupled, this pin is not connected. If DC-coupling of the input signal is required, this pin may be used to construct a DC servo loop to control the input common-mode potential. See the Applications Information section for more details.
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9
15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
On-Chip Reference Circuit
The MAX1419 incorporates an on-chip 2.5V, low-drift bandgap reference. This reference potential establishes the full-scale range for the converter, which is nominally 2.56V P-P differential. The internal reference potential is not accessible to the user, so the full-scale range for the MAX1419 cannot be externally adjusted. Figure 3 shows how the reference is used to generate the common-mode bias potential for the analog inputs. The common-mode input bias is set to one diode potential above the bandgap reference potential, and so varies over temperature.
Clock Inputs (CLKP, CLKN)
The differential clock buffer for the MAX1419 has been designed to accept an AC-coupled clock waveform. Like the signal inputs, the clock inputs are self-biasing. In this case, the common-mode bias potential is 2.4V and each input is connected to the reference potential through a 1k resistor. Consequently, the differential input resistance associated with the clock inputs is 2k. While differential clock signals as low as 0.5VP-P may be used to drive the clock inputs, best dynamic performance is achieved with clock input voltage levels of 2VP-P to 3VP-P. Jitter on the clock signal translates directly to jitter (noise) on the sampled signal. Therefore, the clock source should be a low-jitter (lowphase noise) source. See the Applications Information section for additional details on driving the clock inputs.
500 1mA 2.5V INP/INN COMMON-MODE REFERENCE 1k
500
System Timing Requirements
Figure 4 depicts the timing relationships for the signal input, clock input, data output, and DAV output. The variables shown in the figure correspond to the various timing specifications in the Electrical Characteristics section. These include: * tDAT: Delay from the rising edge of the clock until the 50% point of the output data transition * tDAV: Delay from the falling edge of the clock until the 50% point of the DAV rising edge * tDNV: Time from the rising edge of the clock until data is no longer valid
2mA
Figure 3. Simplified Reference Architecture
INP INN tAD CLKN N CLKP tDAT tDNV N+1 N+2 tDGV N+3 tCLKP tCLKN
D0-D14 DOR tDAV DAV
N-3
N-2 tS
N-1 tH
N
Figure 4. System and Output Timing Diagram 10 ______________________________________________________________________________________
15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
* tDGV: Time from the rising edge of the clock until data is guaranteed to be valid * tSETUP: Time from data guaranteed valid until the rising edge of DAV * tHOLD: Time from the rising edge of DAV until data is no longer valid * tCLKP: Time from the 50% point of the rising edge to the 50% point of the falling edge of the clock signal * tCLKN: Time from 50% point of the falling edge to the 50% point of the rising edge of the clock signal The MAX1419 samples the input signal on the rising edge of the input clock. Output data is valid on the rising edge of the DAV signal, with a data latency of three clock cycles. Note that the clock duty cycle must be 50% 5% for proper operation. (<10pF). Large capacitive loads result in large charging currents during data transitions, which may feed back into the analog section of the ADC and create distortion terms. The loading capacitance is kept low by keeping the output traces short and by driving a single CMOS buffer or latch input (as opposed to multiple CMOS inputs). Inserting small series resistors (220 or less) between the MAX1419 outputs and the digital load, placed as closely as possible to the output pins, is helpful in controlling the size of the charging currents during data transitions and can improve dynamic performance. Keep the trace length from the resistor to the load as short as possible to minimize trace capacitance. The output data is in two's complement format, as illustrated in Table 1. Data is valid at the rising edge of DAV (Figure 4), and DAV may be used as a clock signal to latch the output data. The DAV output provides twice the drive strength of the data outputs, and may therefore be used to drive multiple data latches. The DOR output is used to identify an overrange condition. If the input signal exceeds the positive or negative full-scale range for the MAX1419, then DOR is asserted high. The timing for DOR is identical to the timing for the data outputs, and DOR therefore provides an overrange indication on a sample-by-sample basis.
MAX1419
Digital Outputs (D0-D14, DAV, DOR)
The logic "high" level of the CMOS-compatible digital outputs (D0-D14, DAV, and DOR) may be set in the range of 2.3V to 3.5V. This is accomplished by setting the voltage at the DVCC and DRVCC pins to the desired logic-high level. Note that the DVCC and DRVCC voltages must be the same value. For best performance, the capacitive loading on the digital outputs of the MAX1419 should be kept as low as possible
Table 1. MAX1419 Digital Output Coding
INP ANALOG VOLTAGE LEVEL VREF + 0.64V INN ANALOG VOLTAGE LEVEL VREF - 0.64V D14-D0 TWO'S COMPLEMENT CODE 011111111111111 (positive full scale) 000000000000000 (midscale + ) 111111111111111 (midscale - ) 100000000000000 (negative full scale)
VREF
VREF
VREF - 0.64V
VREF + 0.64V
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11
15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
BACK-TO-BACK DIODE AVCC DVCC DRVCC 0.1F T2-1T-KK81 50 INP 50 INN 0.1F 0.01F 0.1F 0.01F CLKP CLKN GND D0-D14
MAX1419
15
Figure 5. Transformer-Coupled Clock Input Configuration
Applications Information
Differential, AC-Coupled Clock Input
The clock inputs to the MAX1419 are designed to be driven with an AC-coupled differential signal, and best performance is achieved under these conditions. However, it is often the case that the available clock source is single ended. Figure 5 demonstrates one method for converting a single-ended clock signal into a differential signal through a transformer. In this example, the transformer turns ratio from the primary to secondary side is 1:1.414. The impedance ratio from primary to secondary is the square of the turns ratio, or 1:2, so that terminating the secondary side with a 100 differential resistance results in a 50 load looking into the primary side of the transformer. The termination resistor in this example comprises the series combination of two 50 resistors with their common node ACcoupled to ground. Alternatively, a single 100 resistor across the two inputs with no common-mode connection could be employed. In the example of Figure 5, the secondary side of the transformer is coupled directly to the clock inputs. Since the clock inputs are self-biasing, the center tap of the transformer must be AC-coupled to ground or left floating. If the center tap of the secondary were DCcoupled to ground, then it would be necessary to add blocking capacitors in series with the clock inputs. Clock jitter is generally improved if the clock signal has a high slew rate at the time of its zero crossing. Therefore, if a sinusoidal source is used to drive the clock inputs, it is desirable that the clock amplitude be as large as possible to maximize the zero-crossing slew rate. The back-to-back Schottky diodes shown in Figure 5 are not required as long as the input signal is
12
held to 3VP-P differential or less. If a larger amplitude signal is provided (to maximize the zero-crossing slew rate), then the diodes serve to limit the differential signal swing at the clock inputs. Any differential mode noise coupled to the clock inputs translates to clock jitter and degrades the SNR performance of the MAX1419. Any differential mode coupling of the analog input signal into the clock inputs results in harmonic distortion. Consequently, it is important that the clock lines be well isolated from the analog signal input and from the digital outputs. See the PC Board Layout Considerations sections for more discussion on noise coupling.
Differential, AC-Coupled Analog Input
The analog inputs (INP and INN) are designed to be driven with a differential AC-coupled signal. It is extremely important that these inputs be accurately balanced. Any common-mode signal applied to these inputs degrade even-order distortion terms. Therefore, any attempt at driving these inputs in a single-ended fashion results in significant even-order distortion terms. Figure 6 presents one method for converting a singleended signal to a balanced differential signal using a transformer. The primary-to-secondary turns ratio in this example is 1:1.414. The impedance ratio is the square of the turns ratio, so in this example, the impedance ratio is 1:2. In order to achieve a 50 input impedance at the primary side of the transformer, the secondary side is terminated with a 112 differential load. This load, in shunt with the differential input resistance of the MAX1419, results in a 100 differential load on the secondary side. It is reasonable to use a larger transformer turns ratio in order to achieve a larger signal step-up, and this may be desirable in order to relax the drive requirements for the circuitry driving the MAX1419.
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
AVCC DVCC DRVCC
SINGLE-ENDED INPUT TERMINAL
0.1F
T2-1T-KK81
INP 56
D0-D14
MAX1419
56 INN 15
0.1F
0.01F CLKP
GND
CLKN
Figure 6. Transformer-Coupled Analog Input Configuration
AVCC DVCC DRVCC
POSITIVE TERMINAL 0.1F
T2-1T-KK81
T2-1T-KK81
INP 56
D0-D14
MAX1419
56 INN 15
0.1F
0.1F CLKP
GND
CLKN
Figure 7. Transformer-Coupled Analog Input Configuration with Primary-Side Transformer
However, the larger the turns ratio, the larger the effect of the differential input resistance of the MAX1419 on the primary referred input resistance. At a turns ratio of 1:4.47, the 1k differential input resistance of the MAX1419 by itself results in a primary referred input resistance of 50. Although the center tap of the transformer in Figure 6 is shown floating, it may be AC-coupled to ground. However experience has shown that better balance is achieved if the center tap is left floating. As stated previously, the signal inputs to the MAX1419 must be accurately balanced to achieve the best even-
order distortion performance. Figure 7 provides improved balance over the circuit of Figure 6 by adding a balun on the primary side of the transformer, and can yield substantial improvement in even-order distortion terms over the circuit of Figure 6. One note of caution in relation to transformers is important. Any DC current passed through the primary or secondary windings of a transformer may magnetically bias the transformer core. When this happens, the transformer is no longer accurately balanced and a degradation in the distortion of the MAX1419 may be observed. The core must be demagnetized in order to return to balanced operation.
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
POSITIVE INPUT OA1 TO INP
The MAX1427 evaluation board (MAX1427 EV kit) provides an excellent frame of reference for board layout, and the discussion that follows is consistent with the practices incorporated on the evaluation board.
Layer Assignments
RF1 RC1
RG1 OA3 RG2 RF1 RC2 FROM CM
OA2 NEGATIVE INPUT
TO INN
Figure 8. DC-Coupled Analog Input Configuration
DC-Coupled Analog Input
While AC-coupling of the input signal is the proper means for achieving the best dynamic performance, it is possible to DC-couple the inputs by making use of the CM potential. Figure 8 shows one method for accomplishing DC-coupling. The common-mode potentials at the outputs of amplifiers OA1 and OA2 are "servoed" by the action of amplifier OA3 to be equal to the CM potential of the MAX1419. Care must be taken to ensure that the common-mode loop is stable, and the R F /R G ratios of both half circuits must be well matched to ensure balance.
The MAX1427 EV kit is a six-layer board, and the assignment of layers is discussed in this context. It is recommended that the ground plane be on a layer between the signal routing layer and the supply routing layer(s). This practice prevents coupling from the supply lines into the signal lines. The MAX1427 EV kit PC board places the signal lines on the top (component) layer and the ground plane on layer 2. Any region on the top layer not devoted to signal routing is filled with ground plane with vias to layer 2. Layers 3 and 4 are devoted to supply routing, layer 5 is another ground plane, and layer 6 is used for the placement of additional components and for additional signal routing. A four-layer implementation is also feasible using layer 1 for signal lines, layer 2 as a ground plane, layer 3 for supply routing, and layer 4 for additional signal routing. However, care must be taken to make sure that the clock and signal lines are isolated from each other and from the supply lines.
Signal Routing
In order to preserve good even-order distortion, the signal lines (those traces feeding the INP and INN inputs) must be carefully balanced. To accomplish this, the signal traces should be made as symmetric as possible, meaning that each of the two signal traces should be the same length and should see the same parasitic environment. As mentioned previously, the signal lines must be isolated from the supply lines to prevent coupling from the supplies to the inputs. This is accomplished by making the necessary layer assignments as described in the previous section. Additionally, it is crucial that the clock lines be isolated from the signal lines. On the MAX1427 EV kit, this is done by routing the clock lines on the bottom layer (layer 6). The clock lines then connect to the ADC through vias placed in close proximity to the device. The clock lines are isolated from the supply lines, as well as by virtue of the ground plane on layer 5. The digital output traces should be kept as short as possible to minimize capacitive loading. The ground plane on layer 2 beneath these traces should not be removed so that the digital ground return currents have an uninterrupted path back to the bypass capacitors.
PC Board Layout Considerations
The performance of any high-dynamic range, high sample-rate converter may be compromised by poor PC board layout practices. The MAX1419 is no exception to the rule, and careful layout techniques must be observed in order to achieve the specified performance. Layout issues are addressed in the following four categories: 1) Layer assignments 2) Signal routing 3) Grounding 4) Supply routing and bypassing
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
Grounding
The practice of providing a split ground plane in an attempt to confine digital ground return currents has often been recommended in ADC application literature. However, for converters such as the MAX1419, it is strongly recommended to employ a single, uninterrupted ground plane. The MAX1427 EV kit achieves excellent dynamic performance with such a ground plane. The EP of the MAX1419 should be soldered directly to a ground pad on layer 1 with vias to the ground plane on layer 2. This provides excellent electrical and thermal connections to the printed circuit beads are also used on each of the supply lines to enhance supply bypassing (Figure 9). Small value (0.01F to 0.1F) surface-mount capacitors should be placed at each supply pin or each grouping of supply pins to attenuate high-frequency supply noise (Figure 9). It is recommended to place these capacitors on the topside of the board and as close to the device as possible with short connections to the ground plane.
MAX1419
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. However, the static linearity parameters for the MAX1419 are measured using the histogram method with an input frequency of 15MHz.
Supply Bypassing
The MAX1427 EV kit uses 220F capacitors on each supply line (AVCC, DVCC, and DRVCC) to provide lowfrequency bypassing. The loss (series resistance) associated with these capacitors is actually of some benefit in eliminating high-Q supply resonances. Ferrite
BYPASSING--ADC LEVEL AVCC AVCC DVCC
BYPASSING--BOARD LEVEL
FERRITE BEAD
0.1F
0.1F
10F
47F
220F
ANALOG POWER-SUPPLY SOURCE
GND
GND DVCC D0-D14 FERRITE BEAD
MAX1419
15 10F 47F 220F DIGITAL POWER-SUPPLY SOURCE
0.1F
DRVCC
FERRITE BEAD
GND DRVCC 10F 47F 220F OUTPUT DRIVER POWER-SUPPLY SOURCE
Figure 9. Grounding, Bypassing, and Decoupling Recommendations for MAX1419
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
Differential Nonlinearly (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. The MAX1419's DNL specification is measured with the histogram method based on a 15MHz input tone.
Single-Tone Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the ADC's full-scale range.
Dynamic Parameter Definitions
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 4).
Two-Tone Spurious-Free Dynamic Range (SFDRTT)
SFDRTT represents the ratio of the RMS value of either input tone to the RMS value of the peak spurious component in the power spectrum. This peak spur can be an intermodulation product of the two input test tones.
Aperture Jitter
The aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the SNR calculation and should be considered when determining the SNR in ADC. For a near-full-scale analog input signal (-0.5dBFS to -1dBFS), thermal and quantization noise are uniformly distributed across the frequency bins. Error energy caused by transfer function nonlinearities on the other hand is not distributed uniformly, but confined to the first few hundred odd-order harmonics. BTS applications, which are the main target application for the MAX1419 usually do not care about excess noise and error energy in close proximity to the carrier frequency or to DC. These low-frequency and sideband errors are test system artifacts and are of no consequence to the BTS channel sensitivity. They are therefore excluded from the SNR calculation.
Pin Configuration
DRVCC GND GND GND GND GND DAV D14 D13 D12 D11 D10
TOP VIEW
D9 44
56
55
54
53
52
51
50
49
48
47
46
45
43
D8
GND 1 GND 2 GND 3 CLKP 4 CLKN 5 GND 6 AVCC 7 AVCC 8 GND 9 INP 10 INN 11 GND 12 CM 13 GND 14
42 DRVCC 41 DRVCC 40 D7 39 D6 38 D5 37 D4 36 D3
MAX1419
35 D2 34 D1 33 D0 32 DOR 31 DRVCC 30 GND 29 DVCC
15 GND
16 GND
17 GND
18 AVCC
19 AVCC
20 GND
21 AVCC
22 AVCC
23 GND
24 AVCC
25 AVCC
26 GND
27 GND
28 AVCC
QFN
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset.
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15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1419
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17
56L THIN QFN.EPS
15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications MAX1419
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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