View REJ03F0057M61520FP_161749.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M61520FP
6ch Electronic Volume with Tone Control
REJ03F0057-0100Z Rev.1.0 Sep.19.2003
Features
Function names Volume Input selector REC output Gain control Features Six independent high-performance independent volumes on-chip (0 to 87 dB in 1 dB steps, -) L/R ch: 6 inputs with muting and attenuation Two-channel record output (one channel includes a mute switch) Input gain control for FL, FR, C, SL, SR, and SW channels (0/3.6 dB) Record-input gain control (+1/+3/+4.6/+6.6 dB) Output gain control for SL, SR and C channels (0/+6 dB) Output gain control for the SW channel (+6/+10 dB) Output gain control for FL and FR channels (0/+2/+6.5/+10.5 dB) *1 Microphone-mix gain control (0/-2/+6.5/+10.5 dB) *1 On-chip bass-boost circuits for the FL and FR channels Internal balanced outputs for the ADC
Bass boost Balanced output
Note: 1 The microphone mix gain is coupled with output gain control for the FL and FR channels.
Application
Mini-component systems, TVs, etc.
Recommended Operating Conditions
Analog power-supply voltage range: 8.0 V to 10.0 V Digital power-supply voltage range: 3.0 V to 5.5 V
Rev.1.0, Sep.19.2003, page 1 of 15
M61520FP
System Block Diagram
0/-2/-6.5/-10.5dB
ATT
Gain +
Coupled
1 2 3 4 5 6
+
ref
Master VOL. Gain 0/+2/+6.5/+10.5dB
Bass Boost
ATT
-4.4/-9.4/ -8/-13/ -11.6/-16.6dB -
+
0/+3.6dB
FL
Bass Boost
-1
+
REC OUT
-
+
Gain +1/+3/ +4.6/+6.6dB -
Gain 0/+3.6dB
+
ref
Master VOL. Gain 0/+2/+6.5/+10.5dB Master VOL. Gain
FR SL SR C SW
DAC
ADC
DSP
MIC IN
-
Gain 0/+3.6dB
REC OUT
1 2 3 4 5 6
+
Gain +1/+3/ +4.6/+6.6dB
ref Gain + Gain 0/+3.6dB ref 0/+3.6dB ref Master VOL. Master VOL.
0/+6dB
-1 ATT
-4.4/-9.4/ -8/-13/ -11.6/-16.6dB
Gain 0/+6dB
Gain 0/+6dB Master VOL. Gain 0/+3.6dB ref +6/+10dB
MCU I/F
Gain
Rev.1.0, Sep.19.2003, page 2 of 15
PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 LATCH CLOCK DATA
M61520FP
Block Diagram with Pin Connections
AV CC RIN6 RIN5 RIN4 RIN3 RIN2 RIN1 LI N4 LI N3 LI N2 LI N6 NC NC LI N5 LI N1 NC
80
79
60k
78
60k
77
60k
76
60k
75
60k
74
73
60k
72
71
60k
70
60k
69
60k
68
60k
67
60k
66
65
60k
MI CIN LRECIN
1 2
60k
Input selector
+ + 60k 60k -1 ATT -4.4/-9.4/ -8/-13/ -11.6/-16.6dB -1 0/+3.6dB + +1/+3/ +4.6/+6.6dB +1/+3/ +4.6/+6.6dB
Input selector
64 LRECOUT1 63 LRECOUT2
RRECIN 3 ADR+OUT 4 ADR-OUT 5 ADL+OUT 6 ADL-OUT 7 FRIN 8 FLIN 9
+
62 RRECOUT1 61 RRECOUT2
+ C/SW block REF -4.4/-9.4/ -8/-13/ -11.6/-16.6dB SL/SR block REF
60 REFOUTEX2 59 REFOUTEX1
0/-2/-6.5/-10.5dB ATT + -
ATT REF.
58 REFIN 57 REFOUT 56 IVSS
FR 60k 60k 60k 60k 60k 60k
0/+3.6dB 0/+3.6dB
Coupled
L/R/FL/FR block REF
FL
SRIN 10 SL IN 11 CIN 12 SWIN 13 DGND 14 DATA 15
+ -
Internal power supply
55 IVD D 54 AGND
SR
0/+3.6dB
0/+2/+6.5/ +10.5dB
SL
0/+3.6dB
53 FROUT Bass Boost 52 FRBB2 51 FRBB1
C
0/+3.6dB
SW MCU
FR 50 FRVOLIN
CLOCK 16 LA TCH 17 PORT1 18 PORT2 19 PORT3 20 PORT4 21 PORT5 22 PORT6 23 DVDD 24
I/F
0/+2/+6.5/ +10.5dB
49 FRBUF 48 FRREF Bass Boost 47 BBREFOUT 46 FLOUT FL 45 FLBB2 SR 44 FLBB1 43 FLVOLIN 42 FLBUF
SW
C
SL
+6/+10dB
0/+6dB
0/+6dB
0/+6dB
41 FLREF
25
SWREF
26
SWBUF
27
SWVOLIN
28
SWOUT
29
CREF
30
CBUF
31
CVOLIN
32
COUT
33
SLREF
34
SLBUF
35
SLVOLIN
36
SLOUT
37
SRREF
38
SRBUF
39
SRVOLIN
40
SROUT
Rev.1.0, Sep.19.2003, page 3 of 15
M61520FP
Absolute Maximum Ratings
Parameter Max. power-supply voltage Internal power dissipation Ambient operating temperature Storage temperature Symbol AVCC DVDD Pd Topr Tstg Ratings 10.5 6.5 1.4 -20 to +75 -40 to +125 Unit V V W C C Conditions
Thermal derating curve 2.0 Internal power dissipation pd [W]
1.5 1.4 1.0 0.7 0.5
0 0 25 50 75 100 125 150
Ambient temperature Ta [C]
Recommended Operating Condition
Limits Item Power-supply voltage Input voltage (L level) Input voltage (H level) Symbol AVCC DVDD VIL VIH Min. 8.0 3.0 0.0 2.0 Typ. 9.0 5.0 Max. 10.0 5.5 0.8 VDD Unit V V V V Pins 15, 16, and 17 Pins 15, 16, and 17 Condition
Electrical characteristics
Unless otherwise noted, Ta = 25C, AVCC = 9.0 V, DVDD = 5.0 V, f = 1 kHz, and bass boosting is switched off. (1) Power-supply characteristics
Limits Item Analog power-supply circuit current Digital power-supply circuit current Symbol AICC Dldd Min. Typ. 20 0.8 Max. 40 1.5 Unit mA mA Condition Current on pin 73 when AVCC = 5 V, with no signal Current on pin 24 when DVDD = 5 V, with no signal
Rev.1.0, Sep.19.2003, page 4 of 15
M61520FP (2) Input/output characteristics
Limits Item Input impedance Input-selector max. input voltage FL, FR OUT max. output voltage Symbol Rin Vin Vom Min. 30 1.8 1.8 Typ. 60 2.2 2.2 Max. 90 Unit K Vrms Vrms Condition 66pin, 74pin 66pin, 74pin Input on pins 8 and 9, output on pins 46 and 53, RL = 10 k, THD = 1%, bass boost = on, fin = 80 Hz Input on pins 2 and 3, output on pins 62 and 64, RL = 10 k, THD = 1%, fin = 1 kHz Input on pins 10 and 11, output on pins 36 and 40. RL = 10 k, THD = 1%, fin = 1 kHz, gain = 6 dB Gain from pins 4 to 74 and pins 6 to 66. Gain from pins 8 to 53 and pins 9 to 46. Vo = 1 Vrms, on pins 40 and 36, JIS-A filter JIS-A filter, when no signal is present, RG = 10 k, on pins 4 and 6, "normal function" settings JIS-A filter, when no signal is present, RG = 10 k, on pins 62 and 64, "normal function" settings JIS-A filter, when no signal is present, Rg = 10 k, volume setting: 0 dB, "normal function" settings JIS-A filter, when no signal is present, Rg = 10 k, volume setting: - dB, "normal function" setting 46, 53pin 40, 36pin 28pin 46, 53pin 40, 36pin 28pin
REC OUT max. output voltage
Vomrec
1.8
2.2
Vrms
C, SL, SR, SW max. output voltage Bypass gain 1 Bypass gain 2 Max. attenuation ADOUT output noise voltage
Vomvol
1.8
2.2
Vrms
Gv1 Gv2 ATT Vadno
-87
-8.0 0 -92 4.0
12.0
dB dB dB Vrms
RECOUT output noise voltage
Vrecno
7.0
15.0
Vrms
FL, FROUT output noise voltage C, SL, SRVOLOUT output noise voltage SW VOLOUT output noise voltage FL, FROUT output noise voltage C, SL, SRVOLOUT output noise voltage SW VOLOUT output noise voltage Distortion on FL, FROUT Distortion on REC OUT Distortion on C, SL, SR, SWVOLOUT Crosstalk between channels
Vono1 Vvolno1

7.0 6.0 12.0 5.0 4.0 8.0 0.01 0.01 0.01 -70 -70
15.0 12.0 24.0 10.0 8.0 16.0 0.05 0.05 0.05 -55 -55
Vrms Vrms Vrms Vrms Vrms Vrms % % % dB dB
Vvolwno1 Vono2 Vvolno2
Vvolwno2 THD THDrec THDvol CT CTrec
On pins 46 and 53, BW = 400 to 30 kHz, Vo = 300 mVrms, RL = 30 k On pins 62 and 64, BW = 400 to 30 kHz, Vo = 300 mVrms, RL = 51 k On pins 40 and 36, BW = 400 to 30 kHz, Vo = 300 mVrms, RL = 30 k Vo = 0.5 Vrms, RL = 10 k, JIS-A, Rg = 10 k, between pins 46 and 53 Vo = 0.5 Vrms, RL = 30 k, JIS-A, Rg = 10 k, between pins 62 and 64
Normal function settings: * * * * * Input attenuator: -8 dB REC input gain amp: +1 dB FL, FR, C, SL, SR, SW input gain amp: 0 dB SL, SR, C output gain amp: 0 dB SW output gain amp: +6 dB
Rev.1.0, Sep.19.2003, page 5 of 15
M61520FP
Specification of Control Data
Data is fetched on rising edges of SCK; after 16 bits have been fetched, they are internally latched on the rising edge of REQ.
DATA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
SCK
REQ (All data for the ten formats must be initialized each time the power is turned on.)
D0 D1 D2 D3 D4 A 0 0 0 0
D5 (1)
D6
D7
D8 (2)
D9
D10
D11 (3)
D12 (4)
D13 (5)
D14
D15
Input selector
(6) (7) (8) SW Gain
Input ATT
(9) (10)
REC inGain (11) (12)
FL/FR inGain SL/SR/C/SW inGain (13) PORT5 (14) PORT6
B
0
0
0
1
MIC MIX/FL/FR Gain SL/SR/C Gain (15) (16) (17)
PORT1 PORT2 PORT3 PORT4 (19) Lch
C
1
0
0
0
ALL MUTE MIC MUTE REC2 MUTE 0 0 (18) Bass Boost 0
volume
(19)
D
1
0
0
1
Rch
volume
(19)
Chip address 1 1
E
1
0
1
0
0
0
Cch
volume
(19)
F
1
0
1
1
0
0
0
SLch
volume
(19)
G
1
1
0
0
0
0
0
SRch
volume volume
H
1
1
0
1
0
0
0
(19) SWch
Initial internal state of the IC (state just after power is turned on):
(1) Input selector : (2) Input ATT : (3) Record-input gain amp : (4) FL/FRch input gain amp : (5) SL/SR/C/SWch input gain amp : (6) MIC mixing gain, FL/FR output gain amp : (7) SL/SR/Cch output gain amp : (8) SWch output gain amp : MUTE -8dB +1dB 0dB 0dB 0dB 0dB +6dB (9) OUTPUTPORT1 : (10) OUTPUTPORT2 : (11) OUTPUTPORT3 : (12) OUTPUTPORT4 : (13) OUTPUTPORT5 : (14) OUTPUTPORT6 : (15) Mute all : (16) MIC MUTE : (17) REC2 MUTE : PORT1OFF PORT2OFF PORT3OFF PORT4OFF PORT5OFF PORT6OFF No muting MUTE THRU (18) Bass boost: (19) LchVOL : (20) RchVOL : (21) CchVOL : (22) SLchVOL : (23) SRchVOL : (24) SWchVOL : No boost -dB -dB -dB -dB -dB -dB
Note: Do not input values other than those specified above. Operation is not guaranteed with other values.
Rev.1.0, Sep.19.2003, page 6 of 15
M61520FP
Setting just after power is turned on (15) Mute-all setting ALL MUTE 0 1
(1) Input selector setting INPUT SEL. 1 2 3 4 5 6 D4A 0 0 0 0 1 1 1 D5A 0 0 1 1 0 0 1
(7) SL/SR/C ch output gain amp setting D6A 0 1 0 1 0 1 1 (8) SW ch output gain amp setting SW GAIN AMP D7B 0 1 SL/SR/C GAIN AMP D6B
0 +6dB
No MUTE ALL MUTE (16) Microphone mute setting MIC MUTE THRU
+6dB +10dB (9) Output port 1 setting
MUTE (2) Input ATT setting INPUT ATT
MUTE
(17) RECOUT2 mute setting REC2 MUTE 0 1
D7A 0 0 0
D8A 0 0 1
D9A 0 1 0
PORT1
D8B
-8dB -13 dB -4.4 dB
PORT1 OFF PORT1 ON (10) Output port 2 setting PORT2
THRU MUTE (18) Bass-boost setting BASS BOOST
-9.4 dB
-11.6 dB -16.6 dB
0
1 1
1
0 0
1
0 1
D9B 0 1
PORT2 OFF PORT2 ON
No Boost Boost ON
(3) REC input gain amp setting
REC IN GAIN
+1 dB +3 dB +4.6 dB +6.6 dB
D10A
0 0 1 1
D11A
0 1 0 1
(11) Output port 3 setting PORT3 D10B 0 1
PORT3 OFF PORT3 ON (12) Output port 4 setting
(4) FL/FR ch input gain amp setting FL/FR IN GAIN D12A 0 1
PORT4
D11B 0 1
PORT4 OFF PORT4 ON (13) Output port 5 setting
0 dB +3.6 dB
(5) SL/SR/C/SW ch input gain amp setting SL/SR/C/SW IN GAIN D13A 0 1
PORT5
D12B 0 1
PORT5 OFF PORT5 ON (14) Output port 6 setting PORT6
0 dB +3.6 dB
D13B 0 1
PORT6 OFF PORT6 ON
(6) MIC mixing gain, FL/FR ch output gain setting MIC MIX GAIN FL/FR GAIN AMP 0 dB +2 dB +6.5 dB +10.5 dB D4B 0 0 1 1 D5B 0 1 0 1
0 dB -2 dB -6.5 dB -10.5 dB
Rev.1.0, Sep.19.2003, page 7 of 15
M61520FP (19) Volume setting (FLch, FRch, SLch, SRch, SWch)
ATT 0dB -1.0dB -2.0dB -3.0dB -4.0dB -5.0dB -6.0dB -7.0dB -8.0dB -9.0dB -10.0dB -11.0dB -12.0dB -13.0dB -14.0dB -15.0dB -16.0dB -17.0dB -18.0dB -19.0dB -20.0dB -21.0dB -22.0dB -23.0dB -24.0dB -25.0dB -26.0dB -27.0dB -28.0dB -29.0dB -30.0dB -31.0dB -32.0dB -33.0dB -34.0dB -35.0dB -36.0dB -37.0dB -38.0dB -39.0dB -40.0dB -41.0dB -42.0dB -43.0dB -44.0dB ATT -45.0dB -46.0dB -47.0dB -48.0dB -49.0dB -50.0dB -51.0dB -52.0dB -53.0dB -54.0dB -55.0dB -56.0dB -57.0dB -58.0dB -59.0dB -60.0dB -61.0dB -62.0dB -63.0dB -64.0dB -65.0dB -66.0dB -67.0dB -68.0dB -69.0dB -70.0dB -71.0dB -72.0dB -73.0dB -74.0dB -75.0dB -76.0dB -77.0dB -78.0dB -79.0dB -80.0dB -81.0dB -82.0dB -83.0dB -84.0dB -85.0dB -86.0dB -87.0dB Setting just after power is turned on
D10C~H D11C~H D12C~H D13C~H
D7C~H D8C~H D9C~H
D7C~H
D8C~H
D9C~H
D10C~H D11C~H D12C~H D13C~H
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1
1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1
1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
-dB
Note: Do not input values other than those specified above. Operation is not guaranteed with other values. Rev.1.0, Sep.19.2003, page 8 of 15
M61520FP
Control-Data Timing
t1, t2
VDD=5V 2.2V
DATA
0.8V
t6 t1 t4
t7 t2
2.2V
SCK
0.8V
t5 t3 t8 t9
t10
2.2V
REQ
t1 t2
0.8V
Name Time for signal to rise Time for signal to fall SCK clock width SCK high pulse width SCK low pulse width DATA setup time DATA hold time REQ rise hold time REQ high pulse width SCK setup time
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
Min. 1 0.4 0.4 0.4 0.4 0.8 0.4 0.4
Typ.
Max. 0.3 0.3
Unit s s s s s s s s s s
Rev.1.0, Sep.19.2003, page 9 of 15
M61520FP
Functional description
(1) Input selector, input attenuator The IC incorporates a selector for either of two six-input channels and a mute switch. An input level for the selected input is chosen from among -4.4, -8, -9.4, -11.6, -13, and -16.6 dB.
60k
1 2 3 4 5 6
60k 60k 60k 60k 60k
-4.4/-9.4/ -8/-13/ -11.6/-16.6dB + ATT + -
Balanced output for the ADC (positive phase)
+ Balanced output for the ADC (inverse phase)
(2) REC block The REC signal is mixed with the MIC signal and then output. The gain of the signal for mixing with the MIC signal is selected from among +1 dB, +3, +4.6, +6.6 dB. The REC OUT2 side includes a mute switch.
From MIC REC input
60k
0dB
REC OUT1
+ +
REC OUT2 MUTE SW
+1/+3/+4.6/+6.6dB
Rev.1.0, Sep.19.2003, page 10 of 15
M61520FP (3) Microphone mixing In the microphone-input circuit, the input signal is passed through an op-amp buffer to prevent crosstalk between FL and FR and then mixed with FL and FR. The level of the mixed signal changes in accordance with the variable gain of the output gain amplifier (see the table below). A mute switch is incorporated to improve noise characteristics when microphone mixing is not in use.
to REC OUT 60k
Microphone input
MUTE SW
+ -
0/-2/-6.5/-10.5dB ATT
+
Lch/Rch OUT
Main signals FL,FR
The relation between the output gain and mixing gain
FL/FR output gain 0 +2dB +6.5dB +10.5dB Mixing gain 0 -2dB -6.5dB -10.5dB
(4) Master volume (FL ch, FR ch, C ch, SL ch, SR ch, SW ch) This IC incorporates six independently controlled electronic volumes, each of which has low-distortion and lownoise characteristics. Volume: attenuation of 0 dB to -87 dB, settable in 1-dB steps.
FL/FRch
VOL IN
+ Volume: 0 dB to -87 dB in 1-dB steps, -
VOL OUT
0/+2/+6.5/+10.5dB
SL/SR/Cch
VOL IN
SWch
VOL IN
+ Volume: 0 dB to -87 dB in 1-dB steps, -
VOL OUT
Volume: 0 dB to -87 dB in 1-dB steps, -
+ -
VOL OUT
0/+6dB
+6/+10dB
Rev.1.0, Sep.19.2003, page 11 of 15
M61520FP (5) Equivalent Circuit for the Bass-Boost Circuit
Q=4 (G=10dB)
Input
SEL
+ -
Output
G0
0dB Switching-noise reduction circuit f0
Positive-feedback second-order high-pass filter circuit for the bass-boost module
R1
VIN
C1
C2 +K R2
VOUT
Amplitude characteristics of the second-order high-pass filter
Q 1 2 4 5 10 G0 0 to 1dB 6dB 10dB 13dB 20dB
The transfer function is described by the following expressions:
o2 = VOUT = VIN s2 + s Ks2 1 1 1 1 + + (1-K) + R2C2 R1C1 R1R2C1C2 R2C1 Q= R1C1 + R2C2 1 R1R2C1C2 1 R1C2 + (1-K) R2C1 R2C2 R1C1
The bass-boost module includes the above positive-feedback second-order high-pass filter. In the above figure, when R1 = 1.2 k, R2 = 470 k, and C1 = C2 = 0.1 F (K = +1), Fo = 70 Hz (f0 = o/2), Q = 10.
Rev.1.0, Sep.19.2003, page 12 of 15
M61520FP
Gain Level Diagram

SELECTOR INPUT
ATT
-1 AD OUT
Input D range 2.2Vrms(9V Vcc)
MIC INPUT MIC BUF
-4.4/-9.4/ -8/-13/ -11.6/-16.6dB
TOTAL GAIN -4.4/-8/-9.4/-11.6/-13/-16.6dB
MIC MIXING (0dB) REC INPUT
+
REC MIXING (+1/+3/+4.6/+6.6dB) INPUT GAIN (0/+3.6dB)
TOTAL GAIN
REC OUT
+1/+3/+4.6/+6.6dB (Mixed)
Input D range 2.2Vrms (9V Vcc)
FL,FR IN
Output D range 2.2Vrms(9V Vcc)
FL,FR BUF OUT
+
Input D range 1.8Vrms (9V Vcc)
MIC BUF MIC MIXI NG (0/-2/-6.5/-10.5dB) Coupled OUTPUT GAIN (0/+2/+6.5/+10.5dB) Bass Boost FL,FR OUT
Output D range 1.8Vrms (9V Vcc)

FL,FR VOL IN
Input D range 1.8Vrms (9V Vcc)
C to SW IN
Output D range 2.2Vrms (9V Vcc)
C to SW BUFOUT
TOTAL GAIN 0dB or 3.6dB TOTAL GAIN 0dB or 6dB
Input D range
1.8Vrms (9V Vcc) C,SL,SR VOL IN
INPUT GAIN (0/+3.6dB)
Output D range
1.8Vrms (9V Vcc)
C,SL,SR OUT OUTPUT GAIN (0/+6dB)
Input D range
1.8Vrms (9V Vcc) SW VOL IN
Output D range
2.2Vrms (9V Vcc) SW OUT
TOTAL GAIN 6dB or 10dB
Input D range
1.8Vrms (9V Vcc)
OUTPUT GAIN (+6/+10dB)
Output D range
2.2Vrms (9V Vcc)
Caution: Do not input a signal which exceeds the power-supply voltage level.
Rev.1.0, Sep.19.2003, page 13 of 15
M61520FP
Application Example
RIN5 RIN4 RIN2 RIN3 RIN1 RIN6 LI N5 LI N4 LI N6 LI N3
AnalogVCC 9.0V
80
79
60k
78
60k
77
60k
76
60k
75
60k
74
73
60k
72
71
70
60k 60k
69
60k
68
60k
67
60k
LI N2
66
LI N1
65
60k
MICIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
60k Input selector + + 60 k 60k -1 ATT -4.4/-9.4 -8/-13 -11.6/-16.6dB -1 0/+3.6dB + +1/+3 +4.6/+6.6dB + C/SW block REF -4.4/-9.4/ -8/-13/ -11.6/-16.6dB 0/-2/-6.5/-10.5dB ATT REF. + SL/SR block REF +1/+3 +4.6/+6.6dB + Input selector
64 63 62 61 60 59 58 57
100 + 220 + 47
LRECOUT1
LRECIN
LRECOUT2
RRECIN
RRECOUT1
ADR+OUT
RRECOUT2
ADR-OUT
0.01 47 + 0.01
REFOUTEX2
ADL +OUT
REFOUTEX1
ADL -OUT
ATT
0.01 47 + 0.01
REFOUTEX1
FRIN
FR 60k 60k 60k 60k 60k 60k
0/+3.6dB 0/+3.6dB
Coupled
L/R/FL/FR block REF
FLIN
FL
56
+ Internal power supply
100 +
+
SRIN
55 54
0/+2/ +6.5/+10.5dB
SLIN
SR
0/+3.6dB
Analog GND
CIN
SL
0/+3.6dB
53
Bass Boost
Rch OUT
SWIN Digital GND
C
0/+3.6dB
52
0.1 470k
SW MCU
51 FR 50
10 0.1 1.2k
MCU
16 17
I/F
0/+2/ +6.5/+10.5dB
49 48
+
FRVOLREF
PORT1
18 19 20 21 SW C SL FL
Bass Boost
47
BBREFOUT
PORT2
46 45
0.1 470k
Lch OUT
PORT3
PORT4
44 SR 43
10 0.1 1.2k
PORT5
22 23 24
+6/ +10dB 0/ +6dB 0/ +6dB 0/ +6dB
PORT6
42 41
+
Digital VDD
FLVOLREF
25
SWVOLREF
26
+ 10
27
SWOUT
28
CVOLREF
29
30
31
32
SLVOLREF
33
34
+ 10
35
36
SRVOLREF
37
38
39
SROU T
40
SLOUT
COUT
+ 10
10
Rev.1.0, Sep.19.2003, page 14 of 15
M61520FP
80P6N-A
JEDEC Code -- MD
e
MMP
Weight(g) 1.58 Lead Material Alloy 42
Plastic 80pin 1420mm body QFP
Package Dimensions
EIAJ Package Code QFP80-P-1420-0.80 HD D
65 64
E
24 41
25
40
HE
A2
c
x
M
A1
Rev.1.0, Sep.19.2003, page 15 of 15
1
b2
I2 Recommended Mount Pad Symbol
A L1
A A1 A2 b c D E e HD HE L L1 x y L
Detail F
F e
b
y
b2 I2 MD ME
Dimension in Millimeters Min Nom Max 3.05 -- -- 0.1 0.2 0 2.8 -- -- 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.8 -- -- 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 -- -- -- -- 0.2 -- -- 0.1 -- 0 10 -- -- 0.5 1.3 -- -- 14.6 -- -- -- -- 20.6
ME
80
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 1.0

▲Up To Search▲

Price & Availability of REJ03F0057M61520FP

	To Download REJ03F0057M61520FP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .