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128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No. 1.0 1.1 First Version Release 1. Corrected PIN ASSIGNMENT A12 to NC History Draft Date Dec. 2004 Jan. 2005 Remark
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Jan. 2005 1
Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
DESCRIPTION
The Hynix HY57V281620E(L)T(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V281620E(L)T(P) series is organized as 4banks of 2,097,152 x 16. HY57V281620E(L)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)
FEATURES
* * * * * * Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM * Internal four banks operation * Burst Read Single Write operation Programmable CAS Latency; 2, 3 Clocks * * * Auto refresh and self refresh 4096 Refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No. HY57V281620E(L)T(P)-5 HY57V281620E(L)T(P)-6 HY57V281620E(L)T(P)-7 HY57V281620E(L)T(P)-H
Note: 1. 2. 3. 4. HY57V281620ET Series: Normal power, Leaded. HY57V281620ELT Series: Low power, Leaded. HY57V281620ETP Series: Normal power, Lead Free. HY57V281620ELTP Series: Low power, Lead Free.
Clock Frequency 200MHz 166MHz 143MHz 133MHz
Organization
Interface
Package
4Banks x 2Mbits x16
LVTTL
54 Pin TSOPII
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
PIN ASSIGNMENTS
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
54 Pin TSOPII 400mil x 875mil 0.8mm pin pitch
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
PIN DESCRIPTION
SYMBOL TYPE DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE, UDQM and LDQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8 Auto-precharge flag: A10
CLK
Clock
CKE
Clock Enable
CS
Chip Select
BA0, BA1
Bank Address
A0 ~ A11
Address
RAS, CAS, WE
Row Address Strobe, Column Address Strobe, Write Enable
RAS, CAS and WE define the operation Refer function truth table for details
UDQM, LDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers
DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC
Data Input/Output Power Supply/Ground
Data Output Power/Ground Power supply for output buffers No Connection No connection
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic & timer
Internal Row Counter
CLK CKE
State Machine
2Mx16 BANK 3
Row Active
Row Pre Decoder
2Mx16 BANK 2 2Mx16 BANK 1 2Mx16 BANK 0
DQ0
I/O Buffer & Logic Sense AMP & I/O Gate
X-Decoder X-Decoder X-Decoder X-Decoder
CS RAS CAS WE U/LDQM
Refresh
Column Active
Memory Cell Array
Column Pre Decoder
DQ15
Y-Decoder
Bank Select
Column Add Counter
A0 A1
Address Buffers
Address Register
Burst Counter
A11 BA1 BA0
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 0 BA0 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0
OP Code
A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write
Burst Type
A3 0 1 Burst Type Sequential Interleave
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
Burst Length
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
ABSOLUTE MAXIMUM RATING
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature / Time Symbol TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Rating 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 / 10
o
Unit
oC
C V V mA W C / Sec
o
DC OPERATING CONDITION (TA= 0 to 70oC)
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min. 3.0 2.0 -0.3 Typ 3.3 3.0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1, 2 1, 3
-
Note: 1. All voltages are referenced to VSS = 0V 2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration
AC OPERATING TEST CONDITION (TA= 0 to 70 oC, VDD=3.30.3V, VSS=0V)
Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement
Note 1.
Vtt = 1.4V Vtt = 1.4V
Symbol VIH / VIL Vtrip tR / tF Voutref CL
Value 2.4 / 0.4 1.4 1 1.4 50
Unit V V ns V pF
Note
1
RT = 500
RT = 50
Output
Output 50pF
Z0 = 50 50pF
DC Output Load Circuit
AC Output Load Circuit
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
CAPACITANCE (TA= 0 to 70 oC, f=1MHz, VDD=3.3V)
Parameter CLK Input capacitance A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, LDQM, UDQM DQ0 ~ DQ15 Pin Symbol CI1 CI2 CI/O Min 2.0 2.5 3.0 Max 4.0 5.0 5.5 Unit pF pF pF
Data input / output capacitance
DC CHARACTERISTICS I (TA= 0 to 70oC)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Note: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6
Symbol ILI ILO VOH VOL
Min -1 -1 2.4 -
Max 1 1 0.4
Unit uA uA V V
Note 1 2 IOH = -2mA IOL = +2mA
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
DC CHARACTERISTICS II (TA= 0 to 70oC)
Parameter Symbol Speed Test Condition 5 Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRC tRC(min), All banks active
Normal
Unit Note 6 110 2 2 7 100 H 100 mA mA mA 1
Operating Current
IDD1 IDD2P IDD2PS
120
Precharge Standby Current in Power Down Mode
IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS IDD3P IDD3PS
18 mA
15 3 mA 3
Active Standby Current in Power Down Mode
IDD3N Active Standby Current in Non Power Down Mode IDD3NS Burst Mode Operating CurIDD4 rent Auto Refresh Current IDD5
40 mA
35
120 210
110 200 2
100 190
100 190
mA mA mA
1 2
Self Refresh Current
IDD6
CKE 0.2V
Low power
3 800 uA
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY57V281620ET(P) Series: Normal Power HY57V281620ELT(P) Series: Low Power
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter CAS Latency=3 CAS Latency=2 Symbol tCK3 tCK2 tCHW tCLW CAS Latency=3 CAS Latency=2 tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 5 6 7 H Unit Note
Min Max Min Max Min Max Min Max 5.0 1000 10 1.75 1.75 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 4.5 6.0 4.5 6.0 10 2.0 2.0 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 5.4 6.0 5.4 6.0 6.0 1000 10 2.0 2.0 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6.0 5.4 6.0 7.0 1000 10 2.5 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6.0 5.4 6.0 7.5 1000
System Clock Cycle Time
ns
ns ns ns ns 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1
Clock High Pulse Width Clock Low Pulse Width
Access Time From Clock
Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time CAS Latency=3 CAS Latency=2
Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter RAS Cycle Time RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z CAS Latency=3 CAS Latency=2 Power Down Exit Time Self Refresh Exit Time Refresh Time Operation Auto Refresh Symbol tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 5 Min 55 55 15 Max Min 60 60 18 42 18 12 1 0 2 6 Max Min 100K 63 63 20 42 20 14 1 0 2 tDPL + tRP 2 0 2 3 2 1 1 64 2 0 2 3 2 1 1 64 CLK CLK CLK CLK CLK CLK CLK ms 1 7 H Max Min Max 100K 63 63 20 42 20 15 1 0 2 120K Unit Note ns ns ns ns ns ns CLK CLK CLK
38.7 100K 15 10 1 0 2 -
Note: 1. A new command can be given tRRC after self refresh exit.
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
COMMAND TRUTH TABLE
Command Mode Register Set CKEn-1 H CKEn X CS L H No Operation H X L Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-Single-WRITE Entry Self Refresh1 Exit L H L H Entry Precharge power down Exit L H L H Clock Suspend Entry H L L Exit L H V X V V X H X H X H X X X H L L H H X H X H X X X H X H X H X X H H H H H H X L L L L H X L H X L L L X L L L X H L H X X H L X V X X X X X L L H L X X L X X X A9 ball High (Other balls OP code) MRS
Mode
RAS L X H L
CAS L X H H
WE L X
DQM X
ADDR
A10/AP OP code
BA
Note
X H H X RA
X
H
X
L
V L
X
L
H
L
H
X
CA H L
V
X
L
H
L
L
X
CA H H
V
X V
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Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series
PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960)
0.150(0.0059) 0.050(0.0020)
1.194(0.0470) 0.991(0.0390)
0.80(0.0315)BSC
0.400(0.016) 0.300(0.012)
5deg 0deg
0.597(0.0235) 0.406(0.0160)
0.210(0.0083) 0.120(0.0047)
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