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ISL6205
TM
Data Sheet
November 2001
File Number
9047
High Voltage Synchronous Rectified Buck MOSFET Driver
The ISL6205 is a high-voltage, high-frequency, dual MOSFET driver specifically designed to drive two N-Channel power MOSFETs in a synchronous rectified buck converter topology in mobile computing applications. This driver combined with an ISL6223 or other Intersil Multi-Phase Buck PWM controllers forms a complete single-stage core-voltage regulator solution for advanced mobile microprocessors. The ISL6205 allows users to select a gate voltage ranging from 5V to 12V for the lower MOSFET in the synchronous rectified buck converter. Using a 12V gate voltage reduces the RDS(ON) and the conduction loss in the MOSFET. The upper gate is required to run at 5V. The ISL6205 features a three-state PWM input that, working together with any Intersil multiphase PWM controllers, will prevent a negative transient on the output voltage when the output is being shut down. This feature eliminates the schottky diode that is usually seen in a microprocessor power system for protecting the microprocessor from any reversed output voltage damage. The output drivers in the ISL6205 have the capacity to efficiently switch power MOSFETs at frequencies up to 2MHz. Each driver is capable of driving a 3000pF load with a 30ns propagation delay and 50ns transition time. This product implements bootstrapping on the upper gate, reducing implementation complexity and allowing the use of higher performance, cost effective, N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously.
Features
* Drives Two N-Channel MOSFETs * Adaptive Shoot-Through Protection * 25V Operation voltage * Supports High Switching Frequency - Fast Output Rise Time - Propagation Delay 30ns * Small 8 Lead SOIC Package * Dual Gate-Drive Voltages for the Lower MOSFET for Optimal Efficiency * Three-State Input for Output Stage Shutdown * Supply Under Voltage Protection * 5V or 12V Drive for the Lower MOSFET
Applications
* Core Voltage Supplies for Intel Mobile Pentium(R) III, AMD(R) Mobile AthlonTM or DuronTM Microprocessors * High Frequency Low Profile DC-DC Converters * High Current Low Voltage DC-DC Converters * High Input Voltage DC-DC Converters
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Pinout
ISL6205CB, (SOIC) TOP VIEW
Ordering Information
PART NUMBER ISL6205CB ISL6205CB-T TEMP. RANGE (oC) -10 to 85 PACKAGE 8 Ld SOIC PKG. NO. M8.15
UGATE BOOT PWM GND
1 2 3 4
8 PHASE 7 PVCC 6 VCC 5 LGATE
8 Ld SOIC Tape and Reel
ti
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001. All Rights Reserved Pentium(R) is a registered trademark of Intel Corp. AMD(R) is a registered trademark of Advanced Micro Devices, Inc. | AthlonTM and DuronTM are trademarks of Advanced Micro Devices, Inc.
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ISL6205 Block Diagram
PVCC VCC +5V 10K PWM 10K CONTROL LOGIC SHOOTTHROUGH PROTECTION PVCC LGATE GND PHASE BOOT UGATE
Typical Application - Two Phase Converter Using ISL6223 and ISL6205 Gate Drivers
VBAT +5V +5V BOOT FB VCC VSEN PWM1 PGOOD PWM2 LGATE COMP VCC PWM DRIVE ISL6205 PHASE PVCC UGATE +VCORE
+12V
VID
MAIN CONTROL ISL6223 ISEN1 ISEN2 +12V DACOUT GND +5V VBAT
FS
BOOT PVCC VCC PWM DRIVE ISL6205 PHASE UGATE
LGATE
2
ISL6205
Absolute Maximum Ratings
Supply Voltage (VCC, PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .15V Phase Voltage (VPHASE) . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 25V BOOT Voltage (VBOOT - VPHASE) . . . . . . . . . . . . . . . . . . . . . . . .7V Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V UGATE. . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to VPVCC + 0.3V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . 4kV Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .200V
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -10oC to 85oC Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125oC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V 10% Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V Boot Voltage (VBOOT - VPHASE) . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Bias Supply Current
Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVCC
fPWM = 1MHz, VPVCC = 5V fPWM = 1MHz, VPVCC = 12V
-
1.7 1.7 0.8
3.6 3.6 3.3
mA mA mA
Upper Gate Bias Current POWER-ON RESET VCC Rising Threshold VCC Falling Threshold PWM INPUT Input Current PWM Rising Threshold PWM Falling Threshold UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay Shutdown Window Shutdown Holdoff Time OUTPUT Upper Drive Source Impedance Upper Drive Sink Impedance Lower Drive Source Current Lower Drive Sink Impedance
IPVCC
fPWM = 1MHz, VPVCC = 5V
9.6 8.7
9.95 9.1
10.4 9.5
V V
IPWM
VPWM = 0 or 5V (See Block Diagram)
3.45 -
500 3.6 1.45 20 50 20 20 30 20 230
1.55 3.6 -
A V V ns ns ns ns ns ns V ns
tRUGATE tRLGATE tFUGATE tFLGATE tPDLUGATE tPDLLGATE
VPVCC = 5V, 3nF Load VPVCC = 5V, 3nF Load VPVCC = 5V, 3nF Load VPVCC = 5V, 3nF Load VPVCC = 5V, 3nF Load VPVCC = 5V, 3nF Load
1.4 -
RUGATE RUGATE ILGATE RLGATE
500mA Current 500mA Current VPVCC = 5V 500mA Current
600 -
1.6 2.3 850 1.2
3.1 4.0 2.5
mA
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ISL6205 Functional Pin Description
UGATE (Pin 1)
Upper gate drive output. Connect to the gate of high-side power N-Channel MOSFET.
PVCC (Pin 7)
This pin supplies the lower gate drive bias. Connect this pin to either +12V or +5V.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. The PHASE voltage is monitored for adaptive shoot-through protection. This pin also provides a return path for the upper gate drive.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin and a schottky diode between this pin and a 5V supply. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Bootstrap Diode and Capacitor section under DESCRIPTION for guidance in choosing the appropriate capacitor value.
Description
Operation
Designed for versatility and speed, the ISL6205 dual MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal. The upper and lower gates are held low until the driver is initialized. Once the VCC voltage surpasses the VCC Rising Threshold (See Electrical Specifications), the PWM signal takes control of gate transitions. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [tPDLLGATE], the lower gate begins to fall. Typical fall times [tFLGATE] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [tPDHUGATE] based on how quickly the LGATE voltage drops below 0.5V. This prevents both the lower and upper MOSFETs from conducting simultaneously or shoot-through. Once this delay period is complete the upper gate drive begins to rise [tRUGATE] and the upper MOSFET turns on.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation. See the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
VCC (Pin 6)
Connect this pin to a +12V bias supply. Place a high quality bypass capacitor from this pin to GND.
Timing Diagram
PWM
tPDHUGATE tPDLUGATE tRUGATE tFUGATE
UGATE
LGATE
tFLGATE tPDLLGATE tPDHLGATE
tRLGATE
4
ISL6205
Three-State PWM Input
A unique feature of the ISL6205 and other Intersil drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the Electrical Specifications determine when the lower and upper gates are enabled. where Q GATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The VBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose a MOSFET is chosen as the upper MOSFET. Its gate charge, QGATE , from the data sheet is 30nC for a 5V upper gate drive. We will assume a 200mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.15F is required. The next larger standard value capacitance is 0.22F. A good quality ceramic capacitor is recommended.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to rise. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 0.5V threshold, at which time the UGATE is released to rise. Adaptive shoot-through circuitry monitors the PHASE voltage during UGATE turn-off. Once PHASE has dropped below a threshold of 3V, the LGATE is allowed to rise. PHASE continues to be monitored during the lower gate rise time. If PHASE has not dropped below 3V within 250ns of the falling edge of the PWM input, LGATE is taken high to keep the bootstrap capacitor charged. If the PHASE voltage exceeds the 3V threshold during this period and remains high for longer than 2s, the LGATE transitions low. Both upper and lower gates are then held low until the next rising edge of the PWM signal.
Gate Driver Voltage
The ISL6205 provides the user flexibility in choosing the lower gate drive voltage. Simply applying a voltage from 5V up to 12V on PVCC will set the lower driver rail voltage. The upper gate driver rail voltage is set independently by connecting a 5V supply to the anode of the bootstrap diode, as shown in Figure 1.
+12V +5V VBAT
BOOT PVCC VCC PWM DRIVE ISL6205 PHASE UGATE
LGATE
Power-On Reset (POR) Function
During initial startup, the VCC voltage rise is monitored and gate drives are held low until a typical VCC rising threshold of 9.95V is reached. Once the rising VCC threshold is exceeded, the PWM input signal takes control of the gate drives. If VCC drops below a typical VCC falling threshold of 9.1V during operation, then both gate drives are again held low. This condition persists until the VCC voltage exceeds the VCC rising threshold.
FIGURE 1. APPLICATION CIRCUIT TO USE 12V LOWER GATE VOLTAGE AND 5V UPPER GATE VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125oC. The maximum allowable IC power dissipation for the SO-8 package is approximately 800mW. When designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The power dissipated by the driver is approximated as:
P = f sw ( VU Q + VL Q ) + I D DQ V U L CC
Bootstrap Diode and Capacitor
An external bootstrap diode and a bootstrap capacitor are required for the bootstrap circuit. The connection is shown in the typical application schematic. Typically a schottky diode should be employed for its low forward drop. Its voltage rating must be greater than the maximum battery voltage plus 5V. The bootstrap capacitor must have a maximum voltage rating above the maximum battery voltage plus 5V. The bootstrap capacitor can be chosen from the following equation:
Q GATE C BOOT ----------------------V BOOT
where fsw is the switching frequency of the PWM signal. VU and VL represent the upper and lower gate rail voltage. QU and QL is the upper and lower gate charge determined by MOSFET selection and any external capacitance added to the gate pins. The IDDQ VCC product is the quiescent power of the driver and is typically 30mW.
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ISL6205 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C A M BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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