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19-2392; Rev 0; 4/02
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
General Description
The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable. The LVDS input has a fail-safe function. The MAX9160 has a propagation delay that can be adjusted using an external resistor to set the bias current for an internal delay cell. The LVTTL/LVCMOS outputs feature 200ps maximum output-to-output skew and 100ps maximum added peak-to-peak jitter. The MAX9160 is designed to operate with a 3.3V supply voltage over the extended temperature range of -40C to +85C. This device is available in 28-pin exposed- and nonexposed-pad TSSOP and 32-lead 5mm x 5mm QFN packages.
Features
o LVDS or LVTTL/LVCMOS Input Selection o LVDS Input Fail-Safe Sets Outputs High for Open, Undriven Short, or Undriven Parallel Termination o Two Output Banks with Separate Bank Enables o Integrated Output Series Termination for 60 Lines o 200ps (max) Output-to-Output Skew o 100ps (max) Peak-to-Peak Added Output Jitter o 42% to 58% Output Duty Cycle at 125MHz o Guaranteed 125MHz Operating Frequency o LVDS Input Is High Impedance with VCC = 0V or Open (Hot Swappable) o 28-Pin Exposed- and Nonexposed-Pad TSSOP or 32-Lead QFN Packages o -40C to +85C Operating Temperature o 3.0V to 3.6V Supply Voltage
MAX9160
Applications
Cellular Base Stations Servers Add/Drop Multiplexers Digital Cross-Connects DSLAMs Networking Equipment
Ordering Information
Typical Application Circuit and Functional Diagram appear at end of data sheet.
PART MAX9160EUI MAX9160AEUI MAX9160EGJ* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 TSSOP 28 TSSOP-EP** 32 QFN-EP
Pin Configurations
TOP VIEW
OUTA5 1 OUTA6 2 ENA 3 SEL 4 SE_IN 5 VCC 6 GND 7 IN+ 8 IN- 9 GND 10 RSET 11 ENB 12 OUTB0 13 OUTB1 14 28 OUTA4 27 OUTA3 26 GND 25 OUTA2 24 OUTA1
*Future product--contact factory for availability. **Exposed pad.
Function Table
EN_ H H H H SEL H H L or open L or open L or open X SE_IN H L or open X X VID X X +50mV -50mV Open, undriven short, or undriven parallel termination X OUT_ H L H L
MAX9160
23 VCC 22 OUTA0 21 OUTB6 20 GND 19 OUTB5 18 OUTB4 17 VCC 16 OUTB3 15 OUTB2
H L or Open
X
H
X
L
TSSOP
Pin Configurations continued at end of data sheet.
VID = VIN+ - VINH = high logic level
L = low logic level X = don't care
________________________________________________________________ Maxim Integrated Products
1
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver MAX9160
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V to +4V IN+, IN- to GND........................................................-0.3V to +4V SE_IN, EN_, SEL, RSET, OUT_ to GND ........-0.3V to VCC + 0.3V Output Short-Circuit Duration (OUT_) (Note 1) ..........Continuous Continuous Power Dissipation (TA = +70C) 28-Pin TSSOP (derate 12.8mW/C above +70C) .....1024mW 28-Pin TSSOP-EP (derate 23.8mW/C above +70C) ..1904mW 32-Pin QFN (derate 21.2mW/C above +70C) .........1704mW Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C ESD Protection Human Body Model (IN+, IN-) .......................................16kV Human Body Model (SE_IN) ............................................8kV Soldering Temperature (10s) ...........................................+300C
Note 1: Short one output at a time. Do not exceed the absolute maximum junction temperature.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, ENA = ENB = high, RSET = 12k 1%, differential input voltage IVIDI = 0.05V to 1.2V, input common-mode voltage VCM = IVID/2 I to 2.4V - IVID/2 I, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, IVIDI = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 2, 3)
PARAMETER Input High Voltage Input Low Voltage Input Clamp Voltage Input Current SE_IN Capacitance (Note 4) LVDS INPUT (IN+, IN-) Differential Input High Threshold Differential Input Low Threshold Input Current Power-Off Input Current Input Resistor 1 Input Resistor 2 Input Capacitance (Note 4) OUTPUTS (OUT_) Output Short-Circuit Current (Note 1) Output Capacitance (Note 4) IOS CO SEL = high, SE_IN = high, VOUT = 0V SEL = low, VID = 100mV, VOUT = 0V OUT_ to GND IOH = -100A Output High Voltage VOH IOH = -4mA IOH = -8mA SEL = low, inputs open, undriven short, or undriven parallel terminated IOH = -100A IOH = -4mA IOH = -8mA VCC 0.2 2.4 2.1 VCC 0.2 2.4 2.1 V -115 -30 9 mA pF VTH VTL IIN+, IINIIN+(off) IIN-(off) RIN1 RIN2 CIN 0.05V IVIDI 0.6V 0.6V < IVIDI 1.2V 0.05V IVIDI 0.6V, VCC = 0V or open 0.6V < IVIDI 1.2V, VCC = 0V or open VCC = 3.6V or 0V, Figure 1 VCC = 3.6V or 0 V, Figure 1 IN+ or IN- to GND -50 -15 -20 -15 -20 51 200 +15 +20 +15 +20 100 341 6.0 50 mV mV A A k k pF SYMBOL VIH VIL VCL IIN CIN ICL = -18mA VIN = high or low SE_IN to GND CONDITIONS MIN 2.0 GND -1.5 -20 -0.85 +20 6.1 TYP MAX VCC 0.8 UNITS V V V A pF SINGLE-ENDED INPUTS (SE_IN, ENA, ENB, SEL)
Fail-Safe Output High Voltage
VOHFS
V
2
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, ENA = ENB = high, RSET = 12k 1%, differential input voltage IVIDI = 0.05V to 1.2V, input common-mode voltage VCM = IVID/2 I to 2.4V - IVID/2 I, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, IVIDI = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 2, 3)
PARAMETER Output Low Voltage SYMBOL IOL = 100A VOL IOL = 4mA IOL = 8mA Supply Current Output Series Resistance (Note 5) ICC RS SEL = high, SE_IN = high or low, no load SEL = low, VID = -100mV or 100mV, no load Output switched high, VOUT = 1.65V Output switched low, VOUT = 1.65V 7.0 72 61 CONDITIONS MIN TYP MAX 0.2 0.4 0.8 15 10 A mA V UNITS
MAX9160
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, CL = 20pF, ENA = ENB = high, SEL = high or low, RSET = 12k 1%, differential input voltage IVIDI = 0.15V to 1.2V, input common-mode voltage VCM = IVID/2I to 2.4V - IVID/2 I, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, IVIDI = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 6, 7, 8)
PARAMETER Rise Time Fall Time Low-to-High Propagation Delay IN+, IN- to OUT_ High-to-Low Propagation Delay IN+, IN- to OUT_ Low-to-High Propagation Delay SE_IN to OUT_ High-to-Low Propagation Delay SE_IN to OUT_ Added Peak-to-Peak Output Jitter Output Duty Cycle Output-to-Output Skew (Note 9) Part-to-Part Skew (Note 10) Part-to-Part Skew (Note 11) Maximum Switching Frequency (Note 12) SYMBOL tR tF tPLH1 tPHL1 tPLH2 tPHL2 tJ ODC tSKOO tSKPP1 tSKPP2 fMAX SE_IN to OUT_, SEL = high IN+, IN- to OUT_, SEL = low SE_IN to OUT_, SEL = high IN+, IN- to OUT_, SEL = low 125 CONDITIONS Figures 2 and 3 SEL = low SEL = low SEL = high SEL = high 100mV peak-to-peak supply noise at 200kHz, 3.3V supply fIN = 125MHz fIN = 35MHz 42 48.75 RSET = 12k RSET = open RSET = 12k RSET = open MIN 1.4 1.4 5.3 4.9 5.3 4.9 2.2 2.2 2.9 3.1 6.4 6.5 TYP MAX 2.95 2.95 8.0 9.0 8.0 9.0 3.8 3.8 100 58 51.25 200 0.9 2.2 1.6 2.7 UNITS ns ns ns ns ns ns ps % ps ns ns MHz
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, and VID. Note 3: Parameter limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C.
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3
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver MAX9160
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, CL = 20pF, ENA = ENB = high, SEL = high or low, RSET = 12k 1%, differential input voltage IVIDI = 0.15V to 1.2V, input common-mode voltage VCM = IVID/2I to 2.4V - IVID/2 I, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, IVIDI = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 6, 7, 8) Note 4: Note 5: Note 6: Note 7: Note 8: Guaranteed by design and characterization. Total of driver output resistance and integrated series resistor. AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at 6 sigma. CL includes scope probe and test jig capacitance. Pulse generator conditions for SE_IN input: frequency = 125MHz, 50% duty cycle, ZO = 50, tR = 1.2ns, and tF = 1.2ns (20% to 80%), VOH = VCC, VOL = 0V. Pulse generator conditions for IN+, IN- input: frequency = 125MHz, 50% duty cycle, ZO = 50, t R = 1ns, and t F = 1ns (20% to 80%). V ID , V CM as specified in AC Electrical Characteristics general conditions. Measured between outputs with identical loads at VCC/2 for a same-edge transition. tSKPP1 is the greatest difference in propagation delay between different parts operating under identical conditions within rated conditions. tSKPP2 is the greatest difference in propagation delay between different parts operating within rated conditions. All AC specifications met at fMAX.
Note 9: Note 10: Note 11: Note 12:
Typical Operating Characteristics
(MAX9160 with RSET = 12k 1%, VCC = 3.3V, CL = 20pF, ENA = ENB = high, IVIDI = 0.2, VCM = 1.2V, fIN = 125MHz, TA = +25C, unless otherwise noted.)
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
MAX9160 toc01
SINGLE-ENDED PROPAGATION DELAY vs. TEMPERATURE
MAX9160 toc02
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9160 toc03
7.2 DIFFERENTIAL PROPAGATION DEALY (ns) 6.7 tPLH 6.2 tPHL 5.7 5.2 4.7 4.2
4.0 SINGLE-ENDED PROPAGATION DELAY (ns)
8.2 7.7 7.2 6.7 6.2 5.7 5.2 tPLH
3.5 tPHL 3.0
2.5
tPLH
tPHL
2.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
4
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
Typical Operating Characteristics (continued)
(MAX9160 with RSET = 12k 1%, VCC = 3.3V, CL = 20pF, ENA = ENB = high, IVIDI = 0.2, VCM = 1.2V, fIN = 125MHz, TA = +25C, unless otherwise noted.)
SINGLE-ENDED PROPAGATION DELAY vs. SUPPLY VOLTAGE
SINGLE-ENDED PROPAGATION DELAY (ns)
MAX9160 toc04
MAX9160
DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE
MAX9160 toc05
OUTPUT VOLTAGE HIGH vs. TEMPERATURE
ILOAD = -4mA OUTPUT VOLTAGE HIGH (V) 3.15
MAX9160 toc06
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0 3.1 3.2 3.3 3.4 3.5 tPLH tPHL
8.2 DIFFERENTIAL PROPAGATION DELAY (ns) 7.7 7.2 6.7 6.2 5.7 5.2 4.7 4.2 tPHL tPLH
3.20
3.10
3.05
3.00 0.1 0.6 1.1 1.6 2.1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) COMMON-MODE VOLTAGE (V)
3.6
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE LOW vs. TEMPERATURE
MAX9160 toc07
OUTPUT VOLTAGE HIGH vs. SUPPLY VOLTAGE
MAX9160 toc08
OUTPUT VOLTAGE LOW vs. SUPPLY VOLTAGE
MAX9160 toc09
0.30 0.25 OUTPUT VOLTAGE LOW (V) 0.20 0.15 0.10 0.05 ILOAD = 4mA 0
4.0 ILOAD = -4mA 3.5 OUTPUT VOLTAGE HIGH (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0 3.1 3.2 3.3 3.4 3.5
0.25
OUTPUT VOLTAGE LOW (V)
0.24
0.23
0.22
0.21 ILOAD = 4mA 3.6 0.20 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. FREQUENCY
180 160 SUPPLY CURRENT (mA) 140 120 100 80 60 40 20 0 0 15 30 45 60 75 90 105 120 FREQUENCY (MHz) DIFFERENTIAL PROPAGATION DELAY (ns) ALL CHANNELS SWITCHING CL = 18pF SINGLE-ENDED INPUT
MAX9160 toc10
DIFFERENTIAL PROPAGATION DELAY vs. OUTPUT CAPACITANCE
MAX9160 toc11
TRANSITION TIME vs. TEMPERATURE
MAX9160 toc12
200
14 12 10 8 6 4 2 0 15 30 45 60 75 tPHL tPLH
3.0
TRANSITION TIME (ns)
2.5
tR
2.0
tF
1.5
1.0 90 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) OUTPUT CAPACITANCE (pF)
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5
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver MAX9160
Typical Operating Characteristics (continued)
(MAX9160 with RSET = 12k 1%, VCC = 3.3V, CL = 20pF, ENA = ENB = high, IVIDI = 0.2, VCM = 1.2V, fIN = 125MHz, TA = +25C, unless otherwise noted.)
DIFFERENTIAL PROPAGATION DELAY vs. RSET
DIFFERENTIAL PROPAGATION DELAY (ns) 9 8 7 6 5 4 3 2 1 0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 5 10 RSET (k) 15 20 SUPPLY VOLTAGE (V) 0 0 50 100 150 200 250 300 SUPPLY NOISE AMPLITUDE (mVP-P) tPHL tPLH
MAX9160 toc14
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9160 toc13
OUTPUT JITTER vs. 200kHz SUPPLY NOISE AMPLITUDE
MAX9160 toc15
3.0
10
300 250 OUTPUT JITTER (psP-P) DIFFERENTIAL INPUT 200 150 100 50
TRANSITION TIME (ns)
2.5
tR
2.0
tF
1.5
1.0
Pin Description
PIN NAME QFN 1 2 3, 12, 16, 22, 29 4, 7, 13, 19, 25, 28 5 6 8 TSSOP 4 5 6, 17, 23 7, 10, 20, 26 8 9 11 SEL SE_IN VCC GND IN+ INRSET LVCMOS/LVTTL Level Logic Input. SEL = high selects SE_IN. SEL = low or open selects IN+, IN-. SEL is pulled to GND by an internal resistor. LVCMOS/LVTTL Level Input. SE_IN is pulled to GND by an internal resistor. Positive Supply Voltage. Bypass with 0.1F and 0.001F capacitors to ground. Ground Noninverting Input of Differential Input Inverting Input of Differential Input Connect a 12k 1% resistor to ground to decrease the minimum to maximum IN+, IN- to OUT_ propagation delay. LVCMOS/LVTTL Level Logic Input. When ENB = high, outputs OUTB_ are enabled and follow the selected input. When ENB = low or open, outputs OUTB_ are driven low. ENB is pulled to GND by an internal resistor. Bank B LVCMOS/LVTTL Outputs FUNCTION
9 10, 11, 14, 15, 17, 18, 20
12 13-16, 18, 19, 21
ENB
OUTB_
6
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
Pin Description (continued)
PIN NAME QFN 21, 23, 24, 26, 27, 30, 31 32 TSSOP 1, 2, 22, 24, 25, 27, 28 3 OUTA_ Bank A LVCMOS/LVTTL Outputs LVCMOS/LVTTL Level Logic Input. When ENA = high, outputs OUTA_ are enabled and follow the selected input. When ENA = low or open, outputs OUTA_ are driven low. ENA is pulled to GND by an internal resistor. Solder to PC board FUNCTION
MAX9160
ENA Exposed Pad
EP*
*MAX9160EGJ and MAX9160AEUI.
VCC OUT_ RIN2 FAIL-SAFE COMPARATOR TO INPUT MUX VCC - 0.3V IN+ RIN1 CL
Figure 2. Output Load
-40C to +85C. This device is available in 28-pin exposed and nonexposed pad TSSOP and 32-lead 5mm x 5mm QFN packages.
Fail-Safe
A fail-safe circuit on the MAX9160 sets enabled outputs high when the LVDS input is:
RIN1 IN-
Figure 1. Fail-Safe Input Circuit
Detailed Description
The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable. The LVDS input has a fail-safe function. The MAX9160 has a propagation delay that can be adjusted using an external resistor to set the bias current for an internal delay cell. The LVTTL/LVCMOS outputs feature 200ps maximum output-to-output skew and 100ps maximum added peak-to-peak jitter. The MAX9160 is designed to operate with a 3.3V supply voltage over the extended temperature range of
* Open * Undriven and shorted * Undriven and terminated Without a fail-safe circuit, when the LVDS input is selected and undriven, noise may cause the enabled outputs to switch. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when a driver output is in high impedance. A shorted input can occur because of a cable failure. When the MAX9160 LVDS input is driven with a differential signal with a common-mode voltage between IVID/2I and 2.4V - IVID/2I, the fail-safe circuit is not activated. If the input is open, undriven and shorted, or undriven and parallel terminated, an internal resistor in the fail-safe circuit pulls both of the LVDS inputs above VCC - 0.3V, activating the fail-safe circuit and forcing the output high (Figure 1).
_______________________________________________________________________________________
7
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver MAX9160
VCC
VCC/2
VCC/2
SE_IN IN0V DIFFERENTIAL IN+ 0V DIFFERENTIAL
0V
tPLH
tPHL VOH
80% VCC
80% VCC
50% VCC
50% VCC
OUT_
20% VCC
20% VCC VOL tR tF
Figure 3. Transition Time and Propagation Delay Timing Diagram
Propagation Delay and RSET
The MAX9160 delay can be adjusted by connecting a resistor from RSET to ground. See Typical Operating Characteristics for a graph of delay vs. RSET.
Supply Bypassing
Bypass each supply pin with high-frequency surfacemount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller value capacitor closest to the device.
Output Enables
Each bank of seven LVTTL/LVCMOS drivers is controlled by an output enable. Outputs follow the selected input when EN_ is high. Outputs are low (not high impedance) when EN_ = low.
Board Layout
A four-layer PC board that provides separate power, ground, input, and output signals is recommended. Keep input and output signals separated to prevent coupling.
Power Dissipation and Package Type
Power dissipation at high switching frequencies may exceed the power dissipation capacity of the standard TSSOP package (see the Supply Current vs. Frequency graph in the Typical Operating Characteristics). An EP version of the TSSOP package is available that dissipates higher power. Also, a space-saving QFN package with EP is available. The EP must be soldered to the PC board.
Chip Information
TRANSISTOR COUNT: 756 PROCESS: CMOS
8
_______________________________________________________________________________________
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
Functional Diagram
ENA VCC
MAX9160
OUTA[0:6] SEL RSET
IN+ INDELAY MUX VCC
SE_IN
OUTB[0:6]
ENB
_______________________________________________________________________________________
9
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver MAX9160
Typical Application Circuit
CARD 1 ASIC 1 ASIC 14 CARD 2 FPGA 1 1 FPGA 14
1
14
14
MAX9160
LVDS SYSTEM CLOCK
MAX9160
BACKPLANE RT
TEST CLOCK RT SINGLE ENDED
Pin Configurations (continued)
OUTA6
OUTA5 OUTA4
GND
ENA
VCC
32
31
30
29
28
27
26
25 24 23 22 21
GND
TOP VIEW
OUTA3
SEL SE_IN VCC GND IN+ INGND RSET
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16
OUTA2 OUTA1 VCC OUTA0 OUTB6 GND OUTB5 OUTB4
MAX9160
20 19 18 17
9
OUTB1
OUTB2
OUTB0
OUTB3
VCC
QFN
10
______________________________________________________________________________________
GND
ENB
VCC
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9160
______________________________________________________________________________________
11
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver MAX9160
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12
______________________________________________________________________________________
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP, 4.0,EXP PADS.EPS
MAX9160
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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