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SPL10A1
7.5KB LCD CONTROLLER/DRIVER
GENERAL DESCRIPTION The SPL10A1 is a CMOS 8-bit single chip micro-controller which contains LCD drivers, ROM, SRAM, I/O, timer/counter and audio output on a single chip. The SPL10A1 is designed to drive LCD directly and perform efficient controller function as well as arithmetic function. With the on chip crystal oscillator, the clock function is easily realized. For power saving, a software controllable standby switch is also built-in. The SPL10A1 is widely used in electronic products requiring very low power operation, for example, multi-function watch, calendar, calculator, thermometer or LCD game with audio output. FEATURES iCPU: 8-bit SUNPLUS RISC CPU iOperating voltage: 2.4V to 5.5V iMaximum CPU clock: 2 MHz @ 3V iROM capacity: 7.5 K x 8 bits iRAM capacity: 96 x 8 bits iDirect Driver for LCD : 4 Commons X 32 Segments (1/2, 1/3 bias, 1/2, 1/3, 1/4 duty) iInput Port : 6 input pins with key wakeup function with 4 different configurations (mask option) iI/O Port : 2 general I/O pins and 4 special I/O pins that can implement thermometer and.. iTimer/Counter: one 12-bit timer/counter i6 Interrupt sources : External Interrupt Timer Interrupt 2 KHz Interrupt LCD Service Interrupt (in LCD share mode) 128 Hz Interrupt 2 Hz Interrupt iDual Clock System : One built-in RC oscillator (only one resistor is needed) for CPU and one built-in crystal oscillator or RC oscillator ( mask option ) for LCD scanning. iAudio or Tone Output : One 7-bit DA single tone melody or speech that can drive transistor or Tone output that can drive buzzer. iLow Operating Current : Typical current < 3 A @ 3V for timepiece product
(c) Sunplus Technology Co., Ltd.
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Rev. : 1.1
1998.07.19
SPL10A1
BLOCK DIAGRAM ROSC X32I X32O
8 BIT RISC PROCESSOR
ROSC GEN TIME BASE & INTERRUPT LOGIC
12 I/O P O R T
IOAB0-1(I/O) IOCD0-3(I/O) IOEF0-5(INPUT)
7.5K 8 ROM 96 8 SRAM
ONE 12 BITS AUTO RELOAD TIMER DA TONE AUD
32 SEGMENTS 4 COMMONS LCD DRIVER SEG0 - SEG31 COM0 - COM3
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SPL10A1
PIN DESCRIPTION PIN NAME SEG0 - SEG31 COM0 - COM3 IOAB0 - IOAB1 IOEF0 - IOEF5 IOCD0 - IOCD3 ROSC RESET AUD X32I X32O TEST VDD VSS VDD1 VDD2 CUP1 CUP2 FUNCTION DESCRIPTION ROM The SPL10A1 has 7.5K bytes ROM size. The user can has 7K bytes for program and data. The other 0.5K bytes are for SUPLUS internal test use. The ROM address is from $0200 to $1FFF. RAM The SPL10A1 has 96 bytes RAM size. This area is all for data storage. The RAM address is from $00A0 to $00FF. I/O O O I/O I I/O I I O I O I I I I I I I DESCRIPTION LCD driver segment output LCD driver common output I/O port INPUT port (also for key wake input) I/O port R-osc input, connect to VDD through resistor System reset input Current DA output /Tone output 32.768KHz crystal input/R oscillator input (provide LCD frequency) 32.768KHz crystal output Test input Power input Ground input Inputs for setting LCD bias Inputs for setting LCD bias Input for maintaining 1/3 Bias LCD Input for maintaining 1/3 Bias LCD
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SPL10A1
MEMORY and I/O MAP
$0000 H/W REGISTER,I/Os $001F $00A0 USER RAM and STACK $00FF $0100 DUMMY for ICE DEBUG $01FF $0200 $03FF $0400 SUNPLUS TEST PROGRAM $05FF $0600
USER'S PROGRAM DATA AREA ROM
USER'S PROGRAM DATA AREA ROM
$1FFF
OSCILLATORS The SPL10A1 has dual clock system that one is for the CPU and system and the other is for the LCD scanning and interrupt sources. 1. R Oscillator for the CPU and system clock 1.1 Normal case
+VDD
1.2 Noise Environment
+ V DD
Note: Length of the wiring for ROSC pin should be minimized because the oscillator frequency varies due to coupling from other signal lines.
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SPL10A1
2. 32768Hz crystal oscillator or R oscillator (mask option) for LCD scanning and interrupt sources (2 KHz, LCDL for LCD service,128 Hz, 2Hz). It is suggested to enable 32768Hz crystal in strong mode for a few seconds and then switch to weak mode when reset occurs.
C1 X32I 20p 32768Hz C2 X32O 20p
X32I R + V DD
32768Hz Crystal
R Oscillator
Note: Length of the wiring for X32I and X32O should be as short as possible. STOP CLOCK MODE The SPL10A1 supports the power saving mode for those applications needed very low standby current. The user can simply enable the wake-up sources then stop the CPU clock by writing the STOP CLOCK register ($09). The CPU will go to stand-by and the RAM and I/O remains their previous states until wake-up. There are three sources of wake-up in this chip, PORT IOEF wake-up, TIMER 0 wake-up and 2 Hz wake-up. After the chip being waken up, the internal CPU will go to the RESET state the RAM and I/O are not affected by the wake-up reset. The standby current of timepiece product typically is less than 3 A@3V by using this mode and 32768Hz clock source in weak mode. For non-timepiece products, 32768Hz crystal driver or R oscillator (mask option) that generates the 32768Hz clock source also can be turned off, then the whole chip stops. The standby current of the SPL10A1 is less than 1A@3V. In this mode, IOEF port can be used to wake up this chip. TIMER/COUNTER The SPL10A1 contains one 12-bit timer/counter,TM0.In timer mode,TM0 is reloadable up-counter. When timer overflows from 0FFF to 0000, the carry signal will generate the INTERRUPT signal if the corresponding bit is enabled in INT ENABLE register ($0D),and the timer will be auto reloaded to the user`s setup value and upcount again. If TM0 being specified as a counter, the user may reset the counter by loading 0 into register $14 and $1C. After the counter being activated, the count value can also be read from above registers on-the-fly, the read instruction will not affect the counter's value or reset it.
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SPL10A1
The clock source of the timer/counter are selectable as the following: TIMER/COUNTER TM0 12 BIT 12 BIT MODE SELECT TIMER CLOCK TIMER COUNTER ADDR. $0014 $001C $0014 $001C $000B $001C CLOCK SOURCE CPU CLOCK (T) or T/4 T/128, T/256, T/2048 or EXT CLK
REGISTER SELECTOR
Select TM0 timer or counter Select T or T/4
INTERRUPTS The SPL10A1 has six interrupt sources. They are INT0 ( interrupt fromTIMER 0 ), 2 KHz INT, LCDL INT (LCD service in share mode, due to LCD registers is shared with the TIMER/COUNTER ), 128 Hz INT, EXT INT ( external INTERRUPT from IOCD1 ), 2 Hz INT. The 2KHz INT, LCDL INT (256 Hz in 1/3, 1/4 bias;128 Hz in 128 Hz), 128 Hz INT, 2Hz INT, all are divided from 32768 Hz Crystal Oscillator. AUDIO (MELODY/SPEECH) / TONE OUTPUT The SPL10A1 provides both speech and single tone melody output in current DA type that can drive SPEAKER through transistor. Also, the SPL10A1 provides TONE output that can directly drive BUZZER. The two modes, current DA and tone, share the same AUD pin. In current DA mode, it should smoothly switch current DA output current to zero by using speech mode to reduce noise to turn off current DA. The current DA should be turned off when not used due to the current consumption. The TONE output is a full-swing (VDD and VSS) signal and its frequency source is the frequency of TIMER Carry divided by 2.
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SPL10A1
The block diagram is shown as below: Timer Carry 2 TONE DRIVER AUD Melody Tone
PITCH
MIX
DA ENVE LOPE
speech
LIQUID CRYSTAL DISPLAY The SPL10A1 can directly drive the liquid crystal display (LCD) panel of 1/2 duty, 1/3 duty, and 1/4 duty with 1/2 bias or 1/3 bias. It has 4 commons and 32 segments signal pins. In share mode (Timer/Counter is used), the LCD being refresh by LCDL interrupt. The INT routine will read the number of common which is under serving, and send the next common's pattern to LCD port ($10 - $13) from RAM buffer. If the Timer/the Counter is not used, hardware mechanism will auto refresh the LCD after writing OPTION register ($1F). The power connections for LCD (1/2 bias,1/3bias) are shown as below:
1 / 2 Bias
1 / 3 Bias
0.01u VDD2 VDD1 CUP2
0.1u
VDD
VDD2
CUP1
0.01u
0.01u
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SPL10A1
i Output
waveform of the LCD driver
1/2 Bias , 1/2 duty lighting format At the initial clear ( reset )
VDD COM0 ~ COM3 VSS VDD
LCD display ON mode
VSS
Normal operation
COM0 VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS
COM1
COM2
COM3
LCD driver output:All the LCD segments display OFF LCD driver output: COM0 LCD segments display ON LCD driver output: COM1 LCD segments display ON LCD driver output:All the LCD segments display ON
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SPL10A1
1/2 Bias , 1/3 duty lighting format At the initial clear ( reset )
VDD COM0 ~ COM3 VSS VDD
LCD display ON mode
VSS
Normal operation
COM0 VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS
COM1
COM2
COM3
LCD driver output:All the LCD segments display OFF LCD driver output: COM0 LCD segments display ON LCD driver output: COM1 LCD segments display ON LCD driver output: COM2 LCD segments display ON LCD driver output : COM1 and COM1 LCD segments display ON LCD driver output : COM1 and COM2 LCD segments display ON LCD driver output : COM2 and COM2 LCD segments display ON LCD driver output:All the LCD segments display ON
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SPL10A1
1/2 Bias , 1/4 duty lighting format At the initial clear ( reset )
VDD COM0 ~ COM3 VSS VDD
LCD display ON mode
VSS
Normal operation
COM0 VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS VDD VDD2 VSS
COM1
COM2
COM3
LCD driver output:All the LCD segments display OFF LCD driver output: COM0 LCD segments display ON LCD driver output: COM1 LCD segments display ON LCD driver output: COM2 LCD segments display ON LCD driver output: COM3 LCD segments display ON LCD driver output : COM1 and COM1 LCD segments display ON LCD driver output : COM1 and COM2 LCD segments display ON LCD driver output : COM2 and COM2 LCD segments display ON LCD driver output : COM2 and COM3 LCD segments display ON
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SPL10A1
1/3 Bias , 1/2 duty lighting format At the initial clear ( reset )
VDD COM0 ~ COM3 VSS VDD
LCD display ON mode
VSS
Normal operation
VDD COM0 VDD2 VDD1 VSS VDD COM1 VDD2 VDD1 VSS COM2 VDD2 VDD1 VDD2 VDD1 VDD2 VDD1 VDD
LCD driver output: COM0 LCD segments display ON
COM3
LCD driver output:All the LCD segments display OFF
VDD2 VDD1 VSS VDD
LCD driver output: COM1 LCD segments display ON
VDD2 VDD1 VSS VDD
LCD driver output:All the LCD segments display ON
VSS
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SPL10A1
1/3 Bias , 1/3 duty lighting format At the initial clear ( reset )
COM0 ~ COM3 VDD VSS VDD VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD2 VDD1 VDD2 VDD1 VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS
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LCD display ON mode
Normal operation
COM0
COM1
COM2 COM3
LCD driver output:All the LCD segments display OFF
LCD driver output: COM0 LCD segments display ON
LCD driver output: COM1 LCD segments display ON
LCD driver output: COM2 LCD segments display ON
LCD driver output : COM1 and COM1 LCD segments display ON LCD driver output : COM1 and COM2 LCD segments display ON
LCD driver output : COM2 and COM2 LCD segments display ON
SPL10A1
1/3 Bias , 1/4 duty lighting format At the initial clear ( reset )
COM0 ~ COM3
VDD VSS VDD
LCD display ON mode
Normal operation
COM0
COM1
COM2
COM3
LCD driver output:All the LCD segments display OFF LCD driver output: COM0 LCD segments display ON
LCD driver output: COM1 LCD segments display ON
LCD driver output: COM2 LCD segments display ON
LCD driver output: COM3 LCD segments display ON
LCD driver output : COM1 and COM2 LCD segments display ON LCD driver output : COM2 and COM3 LCD segments display ON
VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD2 VDD1 VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS
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SPL10A1
i
RESET FUNCTION
The SPL10A1 can be reset by setting the RESET pin to ground voltage and its operation starts when this pin is set to power voltage. Also an automatic reset function (internal reset function) operates when power is turned on.
iWATCH
DOG FUNCTION
The SPL10A1 provides a watch dog timer. The watch dog timer must be reset when 2 Hz wake-up by writing $0F, otherwise it will reset the system.
i
MASK OPTION
The following type mask option is available. IOEF0 to IOEF5 ............ Select one of A, B, C, D(Refer to INPUT/OUTPUT) A. Without Fixed Pull Low Resistor 200K, with Feedback MOS B. With Fixed Pull Low Resistor 200K, without Feedback MOS C. With Fixed Pull Low Resistor 200K, with Feedback MOS D. Without Fixed Pull Low Resistor 200K, without Feedback MOS 32768 Hz clock source ................ Select one of A, B (Refer to R oscillator) A. 32768 Crystal Oscillator B. R Oscillator I/O PORT CONFIGURATION INPUT IOEF PORT: IOEF0 to IOEF5 There are 4 different configurations in IOEF port.
EF PORT ( MASK OPTION )
TYPE A INPUT
D
They are shown as following:
TYPE C INPUT
D
: EF PORT WRITE
TYPE B INPUT
D
TYPE D INPUT
D
CK
Q
CK
Q
CK
Q
CK
Q
30K
30K
50K
30K
200K 200K
50K
30K
PL
GND GND
PL
GND GND GND
PL GND GND
PL
GND
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SPL10A1
INPUT/OUTPUT IOAB PORT: IOAB0 and IOAB1 These two ports can be programmed to be INPUT or OUTPUT pins. The configurations are shown as below:
AB PORT
input data OUTPUT D CK Q
:
AB PORT WRITE
INPUT
100K
GND
* INPUT/OUTPUT IOCD PORT: IOCD0 to IOCD3 These four IOCD ports can be programmed to be INPUT or OUTPUT pins independently. These pins also can be used to implement a thermometer by sense mode. Their configurations are shown as belows:
CD PORT
input data OUTPUT D CK Q
:
CD PORT WRITE
INPUT
100K
GND
The application circuit for sense mode:
IOCDB1
Thermo-resistor
IOCDB2
IOCDB3
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SPL10A1
ABSOLUTE MAXIMUM RATINGS Characteristics DC supply Voltage Input Voltage Range Operating Temperature Storage Temperature DC CHARACTERISTICS Characteristics Symbol Operating Voltage Operating Current Standby Current Current DA output Input High Level Input Low Level Output High I (I/O) Output Sink I (I/O) LCD Display Voltage LCD Drive Output Voltage VDD IOP ISTBY IOH VIH VIL IOH IOL VLCD VDD VDD2 VDD1 VSS OSC Resistor ROSC Limit Min 2.4 2.0 -300 600 2.8 1.8 0.8 0 Typ 350 -1 50K Max 5.0 1 0.8 VDD 3.0 2.2 1.2 0.2 Unit V A A mA V V A A V V V V V ohm VLCD=3V, IO = 6A VLCD=3V, IO = 3.5A VLCD=3V, IO = 3.5A VLCD=3V, IO = 6A FCPU = 600KHz/3.0V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V
VDD = 3.0 V, VOH = 2.4V VDD = 3.0 V, VOL = 0.8V
Symbol V+ VIN TA TSTO
Ratings < 7V -0.5V to V+ + 0.5V 0 : to +60 : -50 : to +150 :
Test Condition
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SPL10A1
AC CHARACTERISTICS Characteristics OSC frequency CPU clock Frame frequency of the LCD drive Wake-up time Tw Symbol FOSC FCPU Ffm1 Limits Min 0.01 6T1 T1= 1/(Fosc), Tw = 3 x T1, FCPU = FOSC/2 Sleep
T1
Typ 64 85 64 -
Max 4.0 2.0 -
Unit MHz MHz Hz Hz Hz Hz
Test condition VDD = 3.0 V FCPU=FOSC /2@3V 1/2 duty 1/3 duty 1/4 duty
Wake-up
system clock CPU clock
TW
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SPL10A1
The relationship between the Rosc and the FCPU VDD = 3.0V, Ta = 25 :
2.0 FCPU ( MHz ) 1.5 1.0 0.5 0.0 0 200 400 600 800 Rosc ( Kohms )
VDD = 4.5V, Ta = 25 :
2.0 FCPU ( MHz ) 1.5 1.0 0.5 0.0 0 200 400 600 800 Rosc ( Kohms )
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SPL10A1
Frequency vs. Temperature Frequency normalized to 25 : 1.04 F C P U /FCPU(25 :)
Rosc=560Kohms
1.02 1.00
V D D =4.5V
V D D =3.0V
0.98 0.96 0 10 20 30 40 50 60 Temperature ( :) 70
Frequency vs. VDD
1.5 FCPU ( MHz )
Rosc = 100 Kohms
1 0.5 0 2.5
Rosc = 430 Kohms
3.5
4.5
5.5
VDD ( Volts )
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SPL10A1
Operating current vs. Frequency vs. VDD
1000.0 800.0 600.0 400.0 200.0 0.0 0.0
IOP ( A )
VDD = 4.5V
VDD = 3V
0.5
1.0
1.5
2.0
FCPU ( MHz )
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SPL10A1
VDD
VDD
C1 20p 32768Hz
C2 20p
Audio CKT
RESET
Bias option
I/O IO DEVICE Inputs
IOEF1 IOEF2 IOEF3 IOEF4 IOEF5 IOAB0 IOAB1 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 Bias option VDD1 VDD2
0.1uF
IOEF0 TEST ROSC RESET
IOCD3 IOCD2 IOCD1 IOCD0 X32O X32I
AUD CUP2 CUP1
100uF VDD VDD2 VDD1 VSS COM0 COM1 COM2 COM3
C5 0.1uF
1/2 Bias
CUP1 CUP2
SPL10A1
VDD SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8
APPLICATION NOTES i SPL10A1 Application circuit
1/3 Bias VDD1
0.01uF
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 VDD2
0.01uF
Common
C O M O3:0 O
LCD Module
Segment
S E G O31:0 O
CUP1
0.01uF
CUP2
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SPL10A1
i
Audio driver/amplifier for DA mode
*AUD IN CURRENT DA MODE
VDD SPEAKER
AUD 8050 GND
*AUD IN TONE MODE
AUD
BUZZER
GND
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SPL10A1
PAD ASSIGNMENT AND LOCATIONS i Pad assignment
Chip Size: 2100 m x 2380 m This IC substrate should be connected to VSS Ordering Information Product number SPL10A1-nnnnV-C
Package type Chip form
Note: 1.Code number (nnnnV) is assigned for customer. 2.Code number ( nnnn = 0000 ~ 9999 ); version ( V = A ~ Z ).
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SPL10A1
i Pad
locations
Pad Name
Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
X -913 -913 -913 -913 -913 -913 -913 -913 -913 -913 -913 -913 -913 -913 -913 -913 -913 -759 -633 -507 -381 -255 -129 -3 122 248 374 500 626 752
Y 1028 882 756 630 504 378 252 126 0 -125 -251 -377 -503 -629 -755 -881 -1028 -1028 -1028 -1028 -1028 -1028 -1028 -1028 -1028 -1028 -1028 -1028 -1028 -1028
Pad No 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Pad Name
X 912 912 912 912 912 912 912 912 912 912 912 912 912 912 912 912 912 752 626 500 374 248 122 -3 -129 -255 -381 -507 -633 -759
Y -1028 -881 -755 -629 -503 -377 -251 -125 0 125 251 377 503 629 755 881 1028 1028 1028 1028 1028 1028 1028 1028 1028 1028 1028 1028 1028 1028
IOEF1 IOEF2 IOEF3 IOEF4 IOEF5 IOAB0 IOAB1 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VSS VDD1 VDD2 CUP1 CUP2 AUD VDD X32I X32O IOCD0 IOCD1 IOCD2 IOCD3 RESET ROSC TEST IOEF0
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