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| Memory ICs 256k (32k x 8) Bit SRAM BR62256F-70LL The BR62256F-70LL is a 32768 word x 8 bit asynchronous high-speed CMOS static RAM. It runs on a 5V single power supply, and in addition to its low power consumption and high-speed, its low standby current enables its use in battery backup applications. *Applications General-purpose *Featureswith a 32768 word x 8 bit configuration. 1) SRAM 2) High speed read access time of 70ns maximum (Ta = 0 to 70C). 3) Battery backup is possible. Standby current: 50A max. (Ta = 0 to 70C) Data holding current: 3A max. (Ta = 0 to 70C) 4) 5V single power supply voltage with 10% fluctuation tolerance. 5) Input / output TTL compatible. 6) Common input / output pin with three output statuses. 7) No clock is necessary (asynchronous static circuit). 8) Input and output data are in the same phase. 9) Low power consumption. *Block diagram A0 A1 A2 A3 A4 A5 A6 A14 I / O0 INPUT DATA CONTROL I / O7 ADDRESS BUFFER ROW DECODER 262144BIT (512 x 512) MEMORY CELL ARRAY COLUMN SWITCH COLUMN DECODER OUTPUT DATA CONTROL ADDRESS BUFFER A7 A 12 A 13 CS OE WE CONTROL BUFFER 1 Memory ICs BR62256F-70LL *Absolute maximum ratings (Ta = 25C) Parameter Applied voltage Power dissipation Storage temperature Operating temperature I / O voltage Input voltage Symbol VCC Pd Tstg Topr VI / O VIN Limits - 0.51 ~ + 7.0 8502 - 55 ~ + 125 0 ~ + 70 - 0.5 ~ VCC + 0.5 - 0.5 ~ VCC + 0.5 Unit V mW C C V V 1 At pulse width of 50ns: - 3.0V (min.) 2 Reduced by 8.5mW for each increase in Ta of 1C over 25C. *Recommended operating conditions Parameter Power supply voltage Input high level voltage Input low level voltage Ambient temperature Symbol VCC VIH VIL Ta Min. 4.5 2.2 - 0.3 0 Typ. 5.0 -- -- -- Max. 5.5 VCC + 0.5 0.8 70 Unit V V V C *Pin assignments VCC 28 WE 27 A13 26 A8 25 A9 24 A11 23 OE 22 A10 21 CS 20 I / 07 I / 06 I / 05 I / 04 I / 03 19 18 17 16 15 1 A14 2 A12 3 A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 12 13 14 VSS I / 00 I / 01 I / 02 Fig.1 *Pin descriptions Pin name VCC VSS A0 ~ A14 I / 00 ~ I / 07 CS OE WE I/O -- -- I I/O I I I 5V 10% power supply Reference voltage for all input / output, 0V 32k memory address input 8-bit data I / O Chip segment control input Output enable control input Write enable control input Function 2 Memory ICs BR62256F-70LL *Electrical characteristics (unless otherwise noted, Ta = 0 to + 70C, VCC = 5V 10%) Parameter Input low level voltage Input high level voltage Output low level voltage Output high level voltage Input leakage current Output leakage current Average operating current Symbol VIL VIH VOL VOH VOH1 ILI ILO ICCA1 ICCA2 ISB ISB1 Min. - 0.3 2.2 -- 2.4 VCC x 0.8 -1 -1 -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. 0.8 VCC + 0.5 0.4 -- -- +1 +1 45 10 3 50 Unit V V V V V A A mA mA mA A IOL = 2.1mA IOH = - 1.0mA IOH = - 0.1mA VIN = 0 ~ VCC VI / O = 0 ~ VCC CS = VIH or CE = VIH or WE = VIL CS = VIL,I / O: OPEN, Min.cycle time CS VIL 0.2V, f = 1MHz, I / O: OPEN 0.2V, VIH VCC - 0.2V Conditions -- -- Mesurement Circuit -- -- Fig.2 Fig.3 Fig.3 Fig.4 Fig.5 Fig.6 Fig.6 -- Fig.7 Standby current CS = VIH CS VCC - 0.2V 3 Memory ICs BR62256F-70LL *Measurement circuits VCC VIH VIH WE CS OE VCC I / O 0 ~ I / O7 VSS 2.1mA WE CS OE V V0L VIL VCC VCC I / O 0 ~ I / O7 VSS 1.0mA V V0H VIL Data sets all output to LOW (Data 00) Data sets all output to HIGH (Data FF) Fig.2 Fig.3 VCC VCC ILI A VIN = 0 ~ VCC VCC A0 ~ A14 WE, CS, OE VSS VCC I / O 0 ~ I / O7 IL0 A VI / 0 = 0 ~ VCC VSS CS = VIH or WE = VIL or OE = VIH Fig.4 Fig.5 VCC VCC A ICCA1, ICCA2 CS = VCC - 0.2V A ISB1 VCC I / O 0 ~ I / O7 CS VSS VIL A0 ~ A14 SW OPEN VCC I / O 0 ~ I / O7 VIH or VIL (Min. cycle) VIH or VIL (1MHz cycle) CS VSS A0 ~ A14 OPEN VCC or VSS q w Sw q: Average operating current ICCA1 Sw w: Average operating current ICCA2 Fig.6 Fig.7 4 Memory ICs BR62256F-70LL *Operating modes Control pin OE X H L X X: Either VIL or VIH Mode WE X H H L Wait state Output disable Read Write I/O High impedance High impedance Data output Data input Power consumption Standby state Operating state Operating state Operating state CS H L L L *Input / output capacity (Ta = 25C, f = 1MHz) Parameter Input / output capacity Input capacity Symbol CI/O C IN Min. -- -- Typ. -- -- Max. 10 10 Unit pF pF V I / O = 0V V IN = 0V Conditions Note: These parameters are not measurements for all conditions, but are sample values. *Part specification Part number BR62256F-70LL Acces time (ns) 70 max. =0 *AC test conditions (Ta2.4Vto + 70C, VCC = 5V 10%) Input pulse level: 0.8 to Input rise / fall time: 5ns I / O timing level: 1.5V Output load: 1 TTL gate and CL = 100pF *Read cycle Parameter Read cycle time Address access time Chip enable access time (CS) Output enable access time Output hold time CS output set time Output enable and output set time Chip deselect output floating Chip disable output floating Symbol tRC tAA tACS tOE tOH tLZ tOLZ tCHZ tOHZ Min. 70 -- -- -- 10 10 5 -- -- Max. -- 70 70 35 -- -- -- 30 30 Unit ns ns ns ns ns ns ns ns ns 5 Memory ICs BR62256F-70LL *Read cycle timing chart 1 (CS = OE = VIL, CE2 = WE = VIH) tRC Address tAA tOH DOUT Previous Valid Data Valid Data Fig.8 *Read cycle timing chart 2 (WE = VIH) tRC Address tAA CS tACS tCHZ tLZ OE tOHZ tOE tOLZ DOUT High Impedance Valid Data Fig.9 6 Memory ICs BR62256F-70LL *Write cycle Parameter Write cycle time Chip select time Address valid time Address setup time Write pulse width WE output delay time CS output delay time WE output floating time Input data set time Input data hold time WE output set time Symbol tWC tCW tAW tAS tWP tWR tWR1 tWHZ tDW tDH tOW Min. 70 60 60 0 55 0 0 -- 30 0 10 Max. -- -- -- -- -- -- -- 30 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns *Write cycle timing chart 1 (WE control) Address tAW tWC tWR OE CS tCW tAS tWP WE tDW DIN tWHZ Valid Data tDH tOW DOUT High Impedance Fig.10 7 Memory ICs BR62256F-70LL *Write cycle timing chart 2 (CS control) tWC Address tAW tWR1 OE tAS tCW CS tWP WE tDW tDH DIN Valid Data tLZ tWHZ DOUT Fig.11 While the I / O pin is in the output state, input signals should not be applied that are in reverse phase to the output. The contents noted in this document may fall under the jurisdiction of services pertaining to overseas exchange rates and overseas control regulations (services pertaining to design, construction, specifications), and may require special handling. 8 Memory ICs BR62256F-70LL *Data retention characteristics at low power supply voltage (Ta = 0 to + 70C) Parameter Data retention power supply voltage Data retention current CS data retention time Operating recovery time Symbol VDR ICCDR1 tCDR tR Min. 2.0 -- 0 5 Typ. -- 1.0 -- -- Max. 5.5 20 -- -- Unit V A ns ms CS Conditions VCC - 0.2V VCC - 0.2V VCC = 3.0V, CS -- -- 1 3A (max.) when Ta = 0 to 40C *Data retention waveform at low power supply voltage VCC 4.5V Data Retention Mode 4.5V VDR tCDR tR CS 2.2V CS VCC - 0.2V 2.2V Fig.12 *External dimensions (Units: mm) 18.0 0.2 28 11.8 0.3 15 8.4 0.2 2.55 0.10 1 14 0.20 1.27 0.40 0.10 0.5Min. 0.1 SOP-N28 0.15 0.1 9 |
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