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Ordering number : ENN6249A
CMOS IC
LC895299W, 895299L
48x Speed ATAPI (IDE) CD-ROM Decoder with On-Chip Digital Servo System
Overview
The LC895299W and LC895299L are CD-ROM drive digital servo system ICs that integrate all signalprocessing functions after the RF head amplifier on a single chip.
* Bilingual support * Built-in digital audio interface (supports both CLV and CAV) * Built-in digital deemphasis * Built-in 8x oversampling digital filters * Built-in D/A converters CD-ROM Decoder and ATAPI (IDE) Interface Block * Built-in ATAPI (IDE) interface * The user can freely set the CD main channel, C2 flag, and subcode areas in internal DRAM. * Batch transfer function (Function for transferring the CD main channel, C2 flag, or subcode data in a single operation.) * Multiple transfer function (Function for transferring multiple blocks automatically in a single operation.) * CAV audio functions * Intelligent functions (auto buffering, auto decoding, and CD-R functions) * Subcode P to W buffering function (No ECC) and CD-TEXT support * Supports Ultra DMA MODE2, MODE1, and MODE0 * Built in 1-Mbit DRAM
Functions
* Built-in digital servo and ATAPI (IDE) CD-ROM, CD-DSP, CAV audio, and1-Mbit DRAM functions
Features
CD-DSP Block * Supports full CAV operation at 48x speed * Assures stable data readout by performing frame sync signal detection, protection, and interpolation. * Demodulates the EFM signal to produce 8-bit symbol data. * Applies a CRC check to the subcode Q signal and then outputs that signal via parallel I/O to the system microprocessor. * Performs unscrambling and deinterleaving operations to rearrange the demodulated EFM signal in the stipulated order. * Detects and corrects error signals and processes flags (C1: 2 errors, C2: 4 errors) * References the C1 flags and the C2 error check result to set the C2 flags and interpolates or mutes the signal depending on the C2 flags. * Provides two types of muting: zero-cross muting and soft muting. * Independent left and right channel digital attenuators (8-bit resolution) Provides two types of attenuation: direct attenuation and soft attenuation.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
13100TH (OT)/31599HA (OT) No. 6249-1/12
LC895299W, 895299L
Package Dimensions
unit: mm 3230-SQFP176
[LC895299W]
1.25 26.0 24.0 0.5
3244-LQFP176
[LC895299L]
1.25 0.125
22.0 20.0 0.4
132 133 89 88
132 133
1.25
89 88
(1.4)
26.0 24.0
0.5
1.25
(1.4)
1
1.4 1.6max
1
44
(1.4) 1.6max
176
0.2
45 44
22.0 20.0 0.4
176
45
0.15
0.125
0.1
0.5
0.5
SANYO: SQFP176
SANYO: LQFP176
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Maximum supply voltage Symbol VDD5 max VDD3 max VI5, VO5 VI3, VO3 Pd max Topr Tstg 10 seconds II, IO Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta 70C Conditions Ratings -0.3 to +6.0 -0.3 to +4.6 -0.3 to VDD5 + 0.3 -0.3 to VDD3 + 0.3 550 -30 to +70 -55 to +125 235 20 * Unit V V V V mW C C C mA
Input and output voltages Allowable power dissipation Operating temperature Storage temperature Soldering conditions (pins only) Input and output power Note: * Per single input or output basic cell.
Allowable Operating Ranges at Ta = 0 to +70C, VSS = 0 V I/O Cell 5.0-V Power Supply
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 4.5 0 typ 5.0 max 5.5 VDD Unit V V
Note: The input voltage range for speeds of 45x or over is 4.5 to 5.25 V.
Internal Cell 3.3-V Power Supply
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 3.0 0 typ 3.3 max 3.8 VDD Unit V V
Note: The input voltage range differs depending on the drive speed used. Contact your Sanyo representative for details.
0.1
0.5
(0.5)
No. 6249-2/12
LC895299W, 895299L DC Characteristics at Ta = 0 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Analog input voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output low-level voltage Output low-level voltage Output low-level voltage Analog output voltage Input leakage current Output leakage current Pull-up resistance Pull-up resistance Pull-up resistance Pull-down resistance Pull-down resistance Symbol VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VANI VOH VOL VOH VOL VOH VOL VOH VOL VOL VOL VOL VANO IIL IOZ RUP RUP RUP RDN RDN VI = VSS, VDD During high-impedance output IOH = -2 mA IOL = 2 mA IOH = -8 mA IOL = 8 mA IOH = -4 mA IOL = 24 mA IOH = -4 mA IOL = 4 mA IOL = 24 mA IOL = 1 mA IOL = 8 mA Conditions Applicable pins * 1 Ratings min 2.2 0.8 2.2 0.8 2.2 0.8 2.4 0.8 2.4 0.8 0.8 VDD 0.2 VDD 0.7 VDD 0.3 VDD 1/4 VDD VDD - 2.1 0.4 VDD - 2.1 0.4 VDD - 2.1 0.4 VDD - 2.1 0.4 0.4 0.4 0.4 1/4 VDD -10 -10 50 20 7 50 7 100 40 10 100 10 3/4 VDD +10 +10 200 80 13 200 13 3/4 VDD typ max Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V A A k k k k k
TTL level inputs
TTL level inputs with pull-up resistors
7
TTL level inputs with pull-down resistors TTL level inputs Schmitt inputs TTL level inputs Schmitt inputs with pull-up resistors CMOS level inputs Schmitt inputs CMOS level inputs with pull-up resistors
2
3, 9
19, 20
4
5 18 6, 17
7, 8, 14
9, 12, 10, 20
16 11, 21 13 15 22 1, 3, 4, 9 9, 11, 13, 14, 16, 17 5 7, 15 19, 20, 21 2 10
Note: * The applicable pin column entries refer to the following sets. INPUT 1 : ATPINSEL, SUA0 to SUA7 2 : TEST0 to TEST2 3 : DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZHRST, ZCS, ZRD, ZWR 4 : ZRESET, ZDSPRST 5 : FG 18 : AD0, AD1, PH, BH, RREC, FE, TE, VREF, CSS, AD2 19 : ZDMACK, CSEL OUTPUT 6 : FSEQ 8 : HFLO, FSX, EFLG, C2F, WRQ, DIR, PCK, EFMOUT 13 : HINTRQ 11 : ZIOCS16 10 : DMARQ 13 : PDS1 to PDS3 14 : DOUT 15 : ZSWAIT, ZINT0, ZINT1 21 : IORDY 16 : DSLB, EQS, OUTPORT0 to OUTPORT2, MCK 17 : RHLD, TSH, BHH, GHS, LDON 22 : PHC, BHC, FBAL, TBAL, SGC, TOFST, TDO, FDO, SLDO, SPDO INOUT 7 : D0 to D7, TRV, TRV2 9 : DD0 to DD15 20 : ZDASP, ZPDIAG Note: XTAL, XTALCK The above pins are not included in the DC Characteristics.
No. 6249-3/12
LC895299W, 895299L Block Diagram
Driver TDO, FDO SLDO, SPDO FG Data bus[0:7] DRAM Data bus[0:15] Address bus[0:18] CAV-AUDIO Address generator
*11 ZDSPRST *1 LA9238 *12 *2 *14 *3 Audio Circuit
VCEC PLL
CD-DSP
Sub-code SYNC Detector De-scramble & Buffering Address generator ECC & EDC Address generator Each Block Bus control signal Bus Arbiter & DRAM controller
SRAM
ZRESET
CD-DSP I/F & SYNC Detector
HOST
*4 *5 *6 ZINT 1 ZINT 0 WRQ *7 *8 ZSWAIT XTALCK XTAL Each Block Register decoder
ATAPI I/F
Buffer DRAM
Micro controller
Data output input I/F Address generator
PLL Clock generator Each Block *13
Micro controller RAM access Address generator
*9
*1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 *14
*10
A12530
EFMIN, EFMIN2, PH, BH, FE, TE, TES, RREC RHLD, TSH, EQS, BHH, GHS, LDON, FBAL, TBAL, TOFST, SGC LOUT, ROUT, DOUT DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, ZHRST, CSEL DMARQ, HINTRQ, ZIOCS16, IORDY ZRD, ZWR, ZCS, CSCTRL, SUA0 to SUA7 D0 to D7 DIR/FLOCK, HFLO/TLOCK, FSEQ, FSX/LRCK, EFLG/CK2, C2F, EFMOUT, PCK, TRV2/DATA, TRV, PORT OUT0 to OUT2 ATPINSEL, TEST0 to TEST2 RPO, OPP, PCKISTF, PCKISTP, PDO, POS1 to POS3, FR SLCO0 to SLCO3, JITC, DSLB, PHC, BHC PLL1 to PLL3 SLCIT1 to SLCIT2, JITIN, AD0 to AD2, VREF, CSS
No. 6249-4/12
LC895299W, 895299L Pin Functions LC895299 Pin Functions 1 (When pin 95, ATPINSEL, is low)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 SUA7 ZWR ZRD FSEQ DOUT/TESO VDD0 VSS PLL1 PLL2 PLL3 PLL1 VDD PLL1 VSS CSEL ZHRST ZDASP ZCS3FX ZCS1FX VSS1 VDD0 VDDD VDD1 VSS VSSD Pin VSS FLOCK/CRCERR DIR/TLOCK ZSWAIT WRQ/HFLO ZINT0 ZINT1 TEST0 D0 D1 D2 D3 D4 D5 D6 D7 MCK ZCS Type P O O O O O O I B B B B B B B B O I NC NC P P P P NC NC I I I I I I I I I I O O P P I I O P P I I B I I I I I/F ground I/O system power supply: 5 V ATAPI I/F Logic PLL VDD: 3.3 V Logic PLL system ground System Clock PLL Microcontroller write signal Microcontroller read signal Frame synchronization detection Digital output/tes output I/O system power supply: 5 V Logic system ground Microcontroller address bus DRAM VDD: 5 V 3.3 V Logic system ground DRAM ground Clock output to the microcontroller Microcontroller ZCS signal Microcontroller data bus Logic system ground Monitor outputs Wait signal output to the microcontroller Monitor output Microcontroller interrupt Test pin (Must be tied to ground during normal operation.) Type I O INPUT OUTPUT B P Function BIDIRECTION POWER NC NOT CONNECT
Continued on next page.
No. 6249-5/12
LC895299W, 895299L
Continued from preceding page.
Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Pin DA2 DA0 ZPDIAG DA1 ZIOCS16 VSS1 HINTRQ ZDMACK IORDY ZDIOR ZDIOW DMARQ VDD0 VDD1 VSS1 DD15 DD0 DD14 DD1 DD13 VSS1 DD2 DD12 DD3 DD11 DD4 VSS1 DD10 DD5 DD9 DD6 DD8 DD7 VDD0 ROUT AUVDD AUVSS LOUT VSS XTAL XTALCK VDD0 ATPINSEL TEST1 FSX/LRCK EFLG/CK2 TRV2/DATA TRV C2F PCK EFMOUT OUTPORT0 OUTPORT1 OUTPORT2 I/O I I B I O P O I O I I O P P P B B B B B P B B B B B P B B B B B B P O P P O P O I P I I O O B B O O O O O O NC General-purpose output ports I/O system power supply: 5 V D/A converter output D/A converter VDD: 5 V DAC ground D/A converter output Logic system ground XTALCK output XTALCK input (33.8688 MHz) I/O system power supply: 5 V ATAPI pin assignment selection Test pin (Must be tied to ground during normal operation.) Monitor outputs ATAPI I/F I/F ground ATAPI I/F I/F ground ATAPI I/F I/O system power supply: 5 V 3.3 V I/F ground ATAPI I/F I/F ground ATAPI I/F Function
General-purpose I/O ports C2F output PCK output EFM output
Continued on next page. No. 6249-6/12
LC895299W, 895299L
Continued from preceding page.
Pin No. 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 DSLB AVDD SLCIST1 SLCIST2 SLCO0 SLCO1 SLCO2 SLCO3 EFMIN EFMIN2 AVSS JITIN JITC RPO OPP PCKISTF PCKISTP PLL2VDD PLL2VSS PDO PDS1 PDS2 PDS3 FR SVSS AD0 AD1 PH BH RREC FE TE TES VREF CSS AD2 PHC BHC FBAL SVDD SVSS TBAL SGC TOFST TDO FDO SLDO SPDO VSSD VDD1 VSS VDDD Pin I/O NC P P P P NC NC O P I I O O O O I I P I O O I I I P P O O O O I P I I I I I I I I I I I O O O P P O O O O O O O VCO frequency setting Servo system ground A/D converter input 0 A/D converter input 1 Peak hold circuit Bottom hold circuit Optical recognition input FE input TE input TES comparator input VREF input Center servo input A/D converter input 2 PH slice capacitor connection BH slice capacitor connection Focus balance Servo system VDD: 5V Servo system ground Tracking balance Servo gain adjustment Tracking offset adjustment Tracking output Focus output Sled output Spindle output Charge pump selection EFM input Slice level ground Jitter detection input Jitter output P/N balance adjustment Frequency comparator charge pump setting Phase comparator charge pump setting VCEC PLL VDD: 3.3 V VCEC PLL ground Charge pump filter EFM slice level outputs SLC PWM output Slice level VDD: 3.3 V EFM slice level setting DRAM ground 3.3 V Logic GND DRAM VDD: 5 V Function
Continued on next page. No. 6249-7/12
LC895299W, 895299L
Continued from preceding page.
Pin No. 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Pin VDD0 VSS VDD1 RHLD TSH EQS BHH GHS LDON TEST2 FG ZDSPRST ZRESET VDD0 I/O P P P O O O O O O I I I I P A/D and D/A converter VDD: 5 V Logic ground 3.3 V RF AGC hold output TS frequency switching RF equalizer selection BH frequency switching RF and TS signal gain switching Laser control Test pin (Must be tied to ground during normal operation.) FG input DSP RESET CHIP RESET I/O system VDD: 5 V Function
All NC pins must be left open. Pins whose name begin with Z operate with inverted (negative) logic. Applications must supply 5 V to VDD0, 3.3 V to VDD1, the 1-bit D/A converter 5 V to AUVDD, the logic PLL 3.3 V to PLL1VDD, the VCEC PLL 3.3 V to PLL2VDD, the slice level 3.3 V to AVDD, the servo system 5 V to SVDD, and the DRAM 5 V to VDDD. VSS is the logic system ground, AUVSS is the 1-bit D/A converter ground, VSS1 is the IDE interface driver ground, PLL1VSS is the logic PLL ground, PLL2VSS is the VCEC PLL ground, AVSS is the slice level ground, SVSS is the servo system ground, and VSSD is the DRAM ground.
No. 6249-8/12
LC895299W, 895299L Pin Functions LC895299 Pin Functions 2 (When pin 95, ATPINSEL, is high)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 SUA7 ZWR ZRD FSEQ DOUT/TESO VDD0 VSS PLL1 PLL2 PLL3 PLL1 VDD PLL1 VSS CSEL DD7 DD8 DD6 DD9 VSS1 VDD0 VDDD VDD1 VSS VSSD Pin VSS FLOCK/CRCERR DIR/TLOCK ZSWAIT WRQ/HFLO ZINT0 ZINT1 TEST0 D0 D1 D2 D3 D4 D5 D6 D7 MCK ZCS Type P O O O O O O I B B B B B B B B O I NC NC P P P P NC NC I I I I I I I I I I O O P P I I O P P I B B B B P P I/F ground I/O system power supply: 5 V ATAPI I/F Logic PLL VDD: 3.3 V Logic PLL ground System Clock PLL Microcontroller write signal Microcontroller read signal Frame synchronization detection Digital output/tes output I/O system power supply: 5 V Logic system ground Microcontroller address bus DRAM VDD: 5 V 3.3 V Logic system ground DRAM ground Clock output to the microcontroller Microcontroller ZCS signal Microcontroller data bus Logic system ground Monitor outputs Wait signal output to the microcontroller Monitor output Microcontroller interrupt Test pin (Must be tied to ground during normal operation.) Type I O INPUT OUTPUT B P Function BIDIRECTION POWER NC NOT CONNECT
Continued on next page.
No. 6249-9/12
LC895299W, 895299L
Continued from preceding page.
Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Pin DD5 DD10 DD4 DD11 DD3 VSS1 DD12 DD2 DD13 DD1 DD14 DD0 VDD0 VDD1 VSS1 DD15 DMARQ ZDIOW ZDIOR IORDY VSS1 ZDMACK HINTRQ ZIOCS16 DA1 ZPDIAG VSS1 DA0 DA2 ZCS1FX ZCS3FX ZDASP ZHRST VDD0 ROUT AUVDD AUVSS LOUT VSS XTAL XTALCK VDD0 ATPINSEL TEST1 FSX/LRCK EFLG/CK2 TRV2/DATA TRV C2F PCK EFMOUT OUTPORT0 OUTPORT1 OUTPORT2 I/O B B B B B P B B B B B B P P P B O I I O P I O O I B P I I I I B I P O P P O P O I P I I O O B B O O O O O O NC General-purpose output ports I/O system power supply: 5 V D/A converter output D/A converter VDD: 5 V DAC ground D/A converter output Logic system ground XTALCK output XTALCK input (33.8688 MHz) I/O system power supply: 5 V ATAPI pin assignment selection Test pin (Must be tied to ground during normal operation.) Monitor outputs ATAPI I/F I/F GND ATAPI I/F I/F GND ATAPI I/F I/O system power supply: 5 V 3.3 V I/F GND ATAPI I/F I/F GND ATAPI I/F Function
General-purpose I/O ports C2F output PCK output EFM output
Continued on next page. No. 6249-10/12
LC895299W, 895299L
Continued from preceding page.
Pin No. 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 DSLB AVDD SLCIST1 SLCIST2 SLCO0 SLCO1 SLCO2 SLCO3 EFMIN EFMIN2 AVSS JITIN JITC RPO OPP PCKISTF PCKISTP PLL2VDD PLL2VSS PDO PDS1 PDS2 PDS3 FR SVSS AD0 AD1 PH BH RREC FE TE TES VREF CSS AD2 PHC BHC FBAL SVDD SVSS TBAL SGC TOFST TDO FDO SLDO SPDO VSSD VDD1 VSS VDDD Pin I/O NC P P P P NC NC O P I I O O O O I I P I O O I I I P P O O O O I P I I I I I I I I I I I O O O P P O O O O O O O VCO frequency setting Servo system ground A/D converter input 0 A/D converter input 1 Peak hold circuit Bottom hold circuit Optical recognition input FE input TE input TES comparator input VREF input Center servo input A/D converter input 2 PH slice capacitor connection BH slice capacitor connection Focus balance Servo system VDD: 5V Servo system ground Tracking balance Servo gain adjustment Tracking offset adjustment Tracking output Focus output Sled output Spindle output Charge pump selection EFM input Slice level ground Jitter detection input Jitter output P/N balance adjustment Frequency comparator charge pump setting Phase comparator charge pump setting VCEC PLL VDD: 3.3 V VCEC PLL ground Charge pump filter EFM slice level outputs SLC PWM output Slice level VDD: 3.3 V EFM slice level setting DRAM ground 3.3 V Logic system ground DRAM VDD: 5 V Function
Continued on next page. No. 6249-11/12
LC895299W, 895299L
Continued from preceding page.
Pin No. 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Pin VDD0 VSS VDD1 RHLD TSH EQS BHH GHS LDON TEST2 FG ZDSPRST ZRESET VDD0 I/O P P P O O O O O O I I I I P A/D and D/A converter VDD: 5 V Logic system ground 3.3 V RF AGC hold output TS frequency switching RF equalizer selection BH frequency switching RF and TS signal gain switching Laser control Test pin (Must be tied to ground during normal operation.) FG input DSP RESET CHIP RESET I/O system VDD: 5 V Function
All NC pins must be left open. Pins whose name begin with Z operate with inverted (negative) logic. Applications must supply 5 V to VDD0, 3.3 V to VDD1, the 1-bit D/A converter 5 V to AUVDD, the logic PLL 3.3 V to PLL1VDD, the VCEC PLL 3.3 V to PLL2VDD, the slice level 3.3 V to AVDD, the servo system 5 V to SVDD, and the DRAM 5 V to VDDD. VSS is the logic system ground, AUVSS is the 1-bit D/A converter ground, VSS1 is the IDE interface driver ground, PLL1VSS is the logic PLL ground, PLL2VSS is the VCEC PLL ground, AVSS is the slice level ground, SVSS is the servo system ground, and VSSD is the DRAM ground.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of January, 2000. Specifications and information herein are subject to change without notice. PS No. 6249-12/12

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