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M54HC165
RAD-HARD 8 BIT PISO SHIFT REGISTER
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HIGH SPEED: tPD = 15ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 165 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9306-042
DILC-16
FPC-16
ORDER CODES
PACKAGE DILC FPC FM M54HC165D M54HC165K EM M54HC165D1 M54HC165K1
DESCRIPTION The M54HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters PIN CONNECTION
when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
March 2004
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M54HC165
IEC LOGIC SYMBOLS
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN N 1 2 7 9 10 11, 12, 13, 14, 3, 4, 5, 6 15 8 16 SYMBOL NAME AND FUNCTION
SHIFT/LOAD Data Inputs QH Complementary Output QH Serial Output Clock Input (LOW to CLOCK HIGH, Edge Triggered SI Serial Data Inputs A to H Parallel Data Inputs
CLOCK INH Clock Inhibit GND Ground (0V) VCC Positive Supply Voltage
TRUTH TABLE
INPUTS SHIFT / LOAD L H H H H H H X H CLOCK INH X L L L L H X CLOCK X SI X H L H L X X A..........H a..........h X X X X X X INTERNAL OUTPUTS QA a H L H L QB b QAn QAn QAn QAn NO CHANGE NO CHANGE OUTPUTS QH h QGn QGn QGn QGn
a........h : The level of steady input voltage at inputs a through respectively QAn - QGn : The level of QA - QG, respectively. before the most-recent transition of the clock
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M54HC165
LOGIC DIAGRAM
TIMING CHART
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 50 300 -65 to +150 265 Unit V V V mA mA mA mA mW C C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V C ns ns ns
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M54HC165
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 IO=-20 A IO=-20 A IO=-20 A IO=-4.0 mA IO=-5.2 mA IO=20 A IO=20 A IO=20 A IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VCC or GND TA = 25C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 1 40 Typ. Max. Value -40 to 85C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 1 80 A A V V Max. -55 to 125C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
V
VOH
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 20 5 4 TA = 25C Min. Typ. 30 8 7 55 18 15 65 21 18 52 17 14 15 60 71 24 6 5 32 8 7 24 6 5 Max. 75 15 13 150 30 26 165 33 28 135 27 23 6.0 30 35 75 15 13 75 15 13 75 15 13 0 0 0 75 15 13 95 19 16 95 19 16 95 19 16 0 0 0 95 19 16 Value -40 to 85C Min. Max. 95 19 16 190 38 33 205 41 35 170 34 29 4.8 24 28 110 22 19 110 22 19 110 22 19 0 0 0 110 22 19 -55 to 125C Min. Max. 110 22 19 225 45 38 250 50 43 205 41 35 ns ns ns Unit
tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK - QH, QH) tPLH tPHL Propagation Delay Time (SHIFT/LOAD QH, QH) tPLH tPHL Propagation Delay Time (H - QH, QH) fMAX Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (SHIFT/LOAD) Minimum Set-up Time (PI - SHIFT/LOAD) (SI - CLOCK) (SHIFT/LOAD - CK) Minimum Hold Time (PI - SHIFT/LOAD) (SI - CLOCK) (SHIFT/LOAD - CK) Minimum Removal Time (CLOCK - CK INH)
ns
7.4 37 44
MHz
tW(H) tW(L) tW(L)
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ns
ts
ns
th
ns
tREM
ns
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 5.0 TA = 25C Min. Typ. 5 55 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
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M54HC165
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
WAVEFORM 1: SERIAL MODE PROPAGATION DELAY (f=1MHz; 50% duty cycle)
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WAVEFORM 2: PARALLEL MODE PROPAGATION DELAY (f=1MHz; 50% duty cycle)
WAVEFORM 3: MINIMUM PULSE WIDTH (S/L), PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
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WAVEFORM 4: SETUP AND HOLD TIME (PI TO S/L) (f=1MHz; 50% duty cycle)
WAVEFORM 5: MINIMUM REMOVAL TIME (CK INH TO CK) (f=1MHz; 50% duty cycle)
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M54HC165
DILC-16 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 B b b1 D e e1 e2 e3 F I K L 10.90 1.14 17.65 7.62 7.29 2.1 3.00 0.63 1.82 0.40 0.20 20.06 7.36 0.45 0.254 20.32 7.62 2.54 17.78 7.87 7.49 17.90 8.12 7.70 3.83 12.1 1.5 0.429 0.045 0.695 0.300 0.287 0.88 TYP MAX. 2.71 3.70 1.14 2.39 0.50 0.30 20.58 7.87 MIN. 0.083 0.118 0.025 0.072 0.016 0.008 0.790 0.290 0.018 0.010 0.800 0.300 0.100 0.700 0.310 0.295 0.705 0.320 0.303 0.151 0.476 0.059 0.035 TYP. MAX. 0.107 0.146 0.045 0.094 0.020 0.012 0.810 0.310 inch
0056437F
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M54HC165
FPC-16 MECHANICAL DATA
mm. DIM. MIN. A B C D E F G H L M N 0.38 6.0 18.75 0.33 0.38 4.31 22.0 0.43 6.75 9.76 1.49 0.102 8.76 0.127 8.89 1.27 0.43 0.48 0.015 0.237 0.738 0.013 0.015 0.170 0.867 0.017 TYP 6.91 9.94 MAX. 7.06 10.14 1.95 0.152 9.01 MIN. 0.266 0.384 0.059 0.004 0.345 0.005 0.350 0.050 0.017 0.019 TYP. 0.272 0.392 MAX. 0.278 0.399 0.077 0.006 0.355 inch
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0016030E
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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