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19-1981; Rev 0; 5/01
12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference
General Description
The MAX1420, +3.3V, 12-bit analog-to-digital converter (ADC) features a fully-differential input, pipelined, 12stage ADC architecture with wideband track-and-hold (T/H) and digital error correction, incorporating a fullydifferential signal path. The MAX1420 is optimized for low-power, high dynamic performance applications in imaging and digital communications. The converter operates from a single +3.3V supply, and consumes only 221mW. The fully-differential input stage has a small signal -3dB bandwidth of 400MHz and may be operated with single-ended inputs. An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure accommodates an internal reference, or externally applied buffered or unbuffered reference for applications that require increased accuracy and a different input voltage range. In addition to low operating power, the MAX1420 features two power-down modes: reference power-down and shutdown mode. In reference power-down, the internal bandgap reference is deactivated, which results in a typical 2mA supply current reduction. A full shutdown mode is available to maximize power savings during idle periods. The MAX1420 provides parallel, offset binary, CMOScompatible three-state outputs. The MAX1420 is available in a 7mm 7mm, 48-pin TQFP package, and is specified over the commercial (0C to +70C) and the extended industrial (-40C to +85C) temperature range. Pin-compatible lower speed versions of the MAX1420 are also available. Please refer to the MAX1421 data sheet for 40Msps and the MAX1422 data sheet for 20Msps. o +3.3V Single Power Supply o 67dB SNR at fIN = 5MHz o 66dB SNR at fIN = 15MHz o Internal +2.048V Precision Bandgap Reference o Differential, Wideband Input T/H Amplifier o Power-Down Modes: 218mW (Reference Shutdown Mode) 10W (Shutdown Mode) o Space-Saving 48-Pin TQFP Package
Features
MAX1420
Ordering Information
PART MAX1420CCM MAX1420ECM TEMP. RANGE 0C to +70C -40C to +85C PIN-PACKAGE 48 TQFP 48 TQFP
Pin Configuration
AGND AVDD CML REFN REFP REFIN AVDD AGND PD OE D11 D10
48 47 46 45 44 43 42 41 40 39 38 37
________________________Applications
Medical Ultrasound Imaging CCD Pixel Processing IR Focal Plane Arrays Radar IF & Baseband Digitization
AGND AVDD AVDD AGND AGND INP INN AGND AGND AVDD AVDD AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
D9 D8 D7 D6 DVDD DVDD DGND DGND D5 D4 D3 D2
MAX1420
AGND CLK CLK AGND AVDD DVDD
AGND AVDD AVDD
Functional diagram appears at end of data sheet.
48-TQFP
________________________________________________________________ Maxim Integrated Products
DGND D0 D1
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD to AGND..............................................-0.3V to +4V DVDD, AVDD to DGND..............................................-0.3V to +4V DGND to AGND.....................................................-0.3V to +0.3V INP, INN, REFP, REFN, REFIN, CML, CLK, CLK ....................(AGND - 0.3V) to (AVDD + 0.3V) D0-D11, OE, PD .....................(DGND - 0.3V) to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 12.5mW/C above +70C)........1000mW Operating Temperature Ranges MAX1420CCM ....................................................0C to +70C MAX1420ECM .................................................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 62.5MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity Mid-scale Offset Mid-scale Offset Temperature Coefficient RES DNL INL MSO MSOTC Internal reference (Note 1) Gain Error GE External reference applied to REFIN (Note 2) External reference applied to REFP, CML, and REFN (Note 3) Gain Error Temperature Coefficient GETC External reference applied to REFP, CML, and REFN (Note 3) fIN = 5MHz fIN = 15MHz, TA =+25C fIN = 5MHz fIN = 15MHz, TA =+25C fIN = 5MHz fIN = 15MHz, TA =+25C fIN = 5MHz fIN = 15MHz, TA =+25C fIN = 5MHz fIN = 15MHz fIN1 = 11.566036MHz, fIN2 = 13.4119138MHz (Note 4) 58.5 64 62 -5 -5 -1.5 100 x 106 TA = +25C, no missing codes TA = TMIN to TMAX TA = TMIN to TMAX -3 -1 0.5 2 .75 3 x 10-4 0.1 0.2 5 5 1.5 %/C %FSR 3 12 1 Bits LSB LSB %FSR %/C SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (fCLK = 60MHz, 4096-point FFT) Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-Noise and Distortion Effective Number of Bits Two-Tone Intermodulation Distortion SNR SFDR THD SINAD ENOB IMD 67 66 72 72 -70 -69 64.5 63 10.4 10.2 -74 -62 dB dB dB dB Bits dBc
2
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12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 62.5MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Differential Gain Differential Phase ANALOG INPUTS (INP, INN, CML) Input Resistance Input Capacitance Common-Mode Input Level (Note 5) Common-Mode Input Voltage Range (Note 5) Differential Input Range Small-Signal Bandwidth Large-Signal Bandwidth Overvoltage Recovery RIN CIN VCML VCMVR VIN BW-3dB FPBW-3dB OVR VINP - VINN (Note 6) (Note 7) (Note 7) 1.5 FS input Either input to ground Either input to ground 22 4 VAVDD 0.5 VCML 5% VDIFF 400 150 1 k pF V V V MHz MHz Clock Cycle SYMBOL DG DP CONDITIONS MIN TYP 1 0.25 MAX UNITS % degrees
MAX1420
INTERNAL REFERENCE (REFIN bypassed with 0.22F in parallel with 1nF) Common-Mode Reference Voltage Positive Reference Voltage Negative Reference Voltage Differential Reference Voltage Differential Reference Temperature Coefficient REFIN Input Resistance REFIN Input Capacitance REFIN Reference Input Voltage Differential Reference Voltage VCML VREFP VREFN VDIFF REFTC At CML At REFP At REFN VDIFF = VREFP - VREFN VAVDD 0.5 VCML + 0.512 VCML - 0.512 1.024 5% 100 V V V V ppm/C
EXTERNAL REFERENCE (REFIN = +2.048V) RIN CIN VREFIN VDIFF VDIFF = (VREFP - VREFN) 0.95 VREFIN/2 -200 15 (Note 8) 5 10 2.048 10% VREFIN/2 1.05 VREFIN/2 200 k pF V V
EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and CML) REFP, REFN, CML Input Current REFP, REFN, CML Input Capacitance IIN CIN A pF
_______________________________________________________________________________________
3
12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 62.5MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Differential Reference Voltage Range CML Input Voltage Range REFP Input Voltage Range REFN Input Voltage Range DIGITAL INPUTS (CLK, CLK, PD, OE) Input Logic High Input Logic Low VIH VIL CLK, CLK Input Current Input Capacitance DIGITAL OUTPUTS (D0-D11) Output Logic High Output Logic Low Three-State Leakage Three-State Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Analog Supply Current Analog Supply Current with Internal Reference in Shutdown Analog Shutdown Current Digital Supply Current Digital Shutdown Current Power Dissipation Power Dissipation with Internal Reference in Shutdown (Note 8) PDISS PDISS IDVDD PD = VDVDD Analog power dissipation REFIN = AGND 221 218 VAVDD VDVDD IAVDD REFIN = AGND PD = DVDD 3.135 2.7 3.3 3.3 67 66 10 8 20 258 251 3.465 3.63 78 76 20 V V mA mA A mA A mW mW VOH VOL IOH = 200A IOL = -200A VDVDD - 0.5 0 -10 2 VDVDD 0.5 10 V V A pF PD OE -20 -20 10 330 20 20 pF A 0.7 x VDVDD 0.3 x VDVDD V V SYMBOL VDIFF VCML VREFP VREFN CONDITIONS VDIFF = VREFP - VREFN MIN TYP 1.024 10% 1.65 10% VCML + VDIFF/2 VCML VDIFF/2 MAX UNITS V V V V
4
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12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 62.5MHz (50% duty cycle), digital output load CL 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Power Dissipation In Shutdown Power-Supply Rejection Ratio TIMING CHARACTERISTICS Maximum Clock Frequency Clock High Clock Low Pipeline Delay (Latency) Aperture Delay Aperture Jitter Data Output Delay Bus Enable Time Bus Disable Time tAD tAJ tOD tBE tBD fCLK tCH tCL Figure 6, clock period 16.667ns Figure 6, clock period 16.667ns Figure 6 Figure 10 Figure 10 Figure 6 Figure 5 Figure 5 5 60 8.33 8.33 7 2 2 10 5 5 14 MHz ns ns fCLK cycles ns ps ns ns ns SYMBOL PDISS PSRR (Note 9) CONDITIONS PD = VDVDD MIN TYP 10 1 MAX UNITS W mV/V
MAX1420
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Internal reference, REFIN bypassed to AGND with a combination of 0.22F in parallel with 1nF capacitor. External +2.048V reference applied to REFIN. Internal reference disabled. VREFIN = 0, VREFP = +2.162V, VCML = +1.65V, and VREFN = +1.138V. IMD is measured with respect to either of the fundamental tones. Specifies the common-mode range of the differential input signal supplied to the MAX1420. VDIFF = VREFP - VREFN. Input bandwidth is measured at a 3dB level. VREFIN is internally biased to +2.048V through a 10k resistor. Measured as the ratio of the change in mid-scale offset voltage for a 5% change in VAVDD, using the internal reference.
Typical Operating Characteristics
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dB FS, fCLK = 60.006MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
FFT PLOT (8192-POINT DATA RECORD) DIFFERENTIAL INPUT
MAX1420 toc01
FFT PLOT (8192-POINT DATA RECORD) DIFFERENTIAL INPUT
MAX1420 toc02
FFT PLOT (8192-POINT DATA RECORD) DIFFERENTIAL INPUT
fIN = 37.701219MHz -20 AMPLITUDE (dB) -40 HD3 -60 -80 -100 -120 HD2
MAX1420 toc03
0 fIN = 5.5449583MHz -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 0 5 10 15 20 25 HD2
0 fIN = 13.4119138MHz -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 HD2 HD3
0
HD3
30
0
5
10
15
20
25
30
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
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5
12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dB FS, fCLK = 60.006MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
TWO-TONE IMD PLOT (8192-POINT DATA RECORD) DIFFERENTIAL INPUT
MAX1420 toc04
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1420 toc05
SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1420 toc06
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 0 5 10 fIN1 IMD3 IMD2
70
70
fIN1 = 11.566036MHz fIN2 = 13.4119138MHz AIN1 = AIN2 = -6.5dB FS TWO TONE ENVELOPE: -0.5dB FS fIN2 IMD2
66
66 SINAD (dB)
IMD3
SNR (dB)
62
62
58
58
54
54
50 15 20 25 30 1 10 ANALOG INPUT FREQUENCY (MHz) 100 ANALOG INPUT FREQUENCY (MHz)
50 1 10 ANALOG INPUT FREQUENCY (MHz) 100
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1420 toc07
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX1420 toc08
SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 15MHz)
60 50 40 SNR (dB) 30 20 10 0
MAX1420 toc09
-50
85
70
-56
77
-68
SFDR (dB)
THD (dB)
-62
69
61
-74
53
-80 1 10 ANALOG INPUT FREQUENCY (MHz) 100
45 1 10 ANALOG INPUT FREQUENCY (MHz) 100
-10 -70 -60 -50 -40 -30 -20 INPUT POWER (dB FS) -10 0
SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 15MHz)
70 60 50 SINAD (dB) 40 30 20 10 0 -10 -70 -60 -50 -30 -20 INPUT POWER (dB FS) -40 -10 0 -80 -70 THD (dB)
MAX1420 toc10
TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 15MHz)
MAX1420 toc11
SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 15MHz)
MAX1420 toc12
80
-20 -30 -40 -50 -60 -70
80 70 60 SFDR (dB) 50 40 30 20
-60
-50
-30 -20 INPUT POWER (dB FS)
-40
-10
0
-70
-60
-50
-40 -30 -20 INPUT POWER (dB FS)
-10
0
6
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12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dB FS, fCLK = 60.006MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
MAX1420 toc13
SIGNAL-TO-NOISE + DISTORTION vs. TEMPERATURE
MAX1420 toc14
TOTAL HARMONIC DISTORTION vs. TEMPERATURE
fIN = 15MHz -67
MAX1420 toc15
70 fIN = 15MHz 68
66 fIN = 15MHz 65 64
-65
SNR (dB)
63 62
64
THD (dB)
66
SINAD (dB)
-69
-71
62
61 60 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
-73
60
-75 -40 -15 10 35 60 85 TEMPERATURE (C)
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
MAX1420 toc16
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1421 toc17
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1420 toc18
84 fIN = 15MHz 80
2
0.50
1 SFDR (dB) INL (LSB) INL (LSB) 76
0.25
0
0
72
68
-1
-0.25
64 -40 -15 10 35 60 85 TEMPERATURE (C)
-2 0 1024 2048 3072 4096 DIGITAL OUTPUT CODE
-0.50 0 1024 2048 3072 4096 DIGITAL OUTPUT CODE
GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE VREFIN = +2.048V
MAX1420 toc19
OFFSET ERROR vs. TEMPERATURE
MAX1420 toc20
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1420 toc21
0.250 0.125 GAIN ERROR (%FSR) 0 -0.125 -0.250 -0.375 -0.500 -40 -15 10 35 60
0
65
-0.25 OFFSET ERROR (%FSR)
63
-0.50
IAVDD (mA)
61
-0.75
59
-1.00
57
85
-1.25 -40
55 -15 10 35 60 85 3.1 3.2 3.3 AVDD (V) 3.4 3.5 TEMPERATURE (C)
TEMPERATURE (C)
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7
12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +3.3V, AGND = DGND = 0, VIN = 1.024V, differential input voltage at -0.5dB FS, fCLK = 60.006MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX1420 toc22
DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE
MAX1420 toc23
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX1420 toc24
80
14
14 13 12
70 IDVDD (mA) IAVDD (mA)
12 IDVDD (mA) 2.7 2.9 3.0 3.2 DVDD (V) 3.3 3.5 3.6
60
10
11 10
50
8 9
40 -40 -15 10 35 60 85 TEMPERATURE (C)
6
8 -40 -15 10 35 60 85 TEMPERATURE (C)
ANALOG POWER-DOWN CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1420 toc25
DIGITAL POWER-DOWN CURRENT vs. DIGITAL SUPPLY VOLTAGE
MAX1420 toc26
SNR, SINAD, THD, SFDR vs. CLOCK FREQUENCY
60 SFDR, SNR, THD, SINAD (dB) 40 20 fIN = 15MHz 0 -20 -40 -60 THD
MAX1420 toc27
0.20
0.15
80 SFDR
0.16
0.12
SINAD
SNR
IAVDD (A)
IDVDD (A)
0.12
0.09
0.08
0.06
0.04
0.03
0 3.10
0 3.20 3.30 AVDD (V) 3.40 3.50 2.7 2.9 3.0 3.2 DVDD (V) 3.3 3.5 3.6
-80 20 30 40 50 60 70 80 CLOCK FREQUENCY (MHz)
INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX1420 toc28
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1420 toc29
OUTPUT NOISE HISTOGRAM (DC INPUT)
502186 339785 387312 500,000 400,000
MAX1420 toc30
2.075
2.10
600,000
2.063 VREF (dB) VREF (V)
2.08
COUNTS
2.06
2.050
300,000 200,000 115171 153704 53499 6113
2.04 2.038
2.02
2.025 3.1 3.2 3.3 AVDD (V) 3.4 3.5
2.00 -40 -15 10 35 60 85 TEMPERATURE (C)
0
0
2 342
14538
100,000
242 0
N-6 N-5 N-4 N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6
DIGITAL OUTPUT NOISE
8
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12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference
Pin Description
PIN 1, 4, 5, 8, 9, 12, 13, 16, 19, 41, 48 2, 3, 10, 11, 14, 15, 20, 42, 47 6 7 17 18 NAME FUNCTION
MAX1420
AGND
Analog Ground. Connect all return paths for analog signals to AGND.
AVDD INP INN CLK CLK
Analog Supply Voltage. For optimum performance, bypass to the closest AGND with a parallel combination of a 0.1F and a 1nF capacitor. Connect a single 10F and 1F capacitor combination between AVDD and AGND. Positive Analog Signal Input Negative Analog Signal Input Clock Frequency Input. Clock frequency input ranges from 100kHz to 60MHz. Complementary Clock Frequency Input. This input is used for differential clock inputs. If the ADC is driven with a single-ended clock, bypass CLK with a 0.1F capacitor to AGND. Digital Supply Voltage. For optimum performance, bypass to the closest DGND with a parallel combination of a 0.1F and a 1nF capacitor. Connect a single 10F and 1F capacitor combination between DVDD and DGND. Digital Ground Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB. Digital Data Outputs. D6 through D11, where D11 represents the MSB. Output Enable Input. A logic "1" on OE places the outputs D0-D11 into a high-impedance state. A logic "0" allows for the data bits to be read from the outputs. Shutdown Input. A logic "1" on PD places the ADC into shutdown mode. External Reference Input. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To disable the internal reference, connect REFIN to AGND. Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFP should be biased to VCML + VDIFF / 2. Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF. With the internal reference disabled (REFIN = AGND), REFN should be biased to VCML - VDIFF / 2. Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22F in parallel with 1nF.
21, 31, 32 22, 29, 30 23-28 33-38 39 40 43
DVDD DGND D0-D5 D6-D11 OE PD REFIN
44 45 46
REFP REFN CML
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9
12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
Detailed Description
The MAX1420 uses a 12-stage, fully-differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle, including the delay through the output latch. The latency is seven clock cycles. A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held-input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage. This process is repeated until the signal has been processed by all 12 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. ductance amplifier (OTA) input, and open simultaneously with S1, sampling the input waveform. The resulting differential voltage is held on capacitors C2a and C2b. Switches S4a and S4b are then opened before S3a, S3b, S4C are closed. The OTA is used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The wide input bandwidth T/H amplifier allows the MAX1420 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs INP to INN can be driven either differentially or single-ended. Match the impedance of INP and INN and set the common-mode voltage to midsupply (AVDD/2) for optimum performance.
Analog Input and Reference Configuration
The full-scale range of the MAX1420 is determined by the internally generated voltage difference between REFP (AV DD /2 + V REFIN /4) and REFN (AV DD /2 VREFIN/4). The MAX1420's full-scale range is adjustable through REFIN, which provides high input impedance for this purpose. REFP, CML (AVDD/2), and REFN are internally buffered low impedance outputs. An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure accommodates an internal reference, or externally applied buffered or unbuffered reference for appli-
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track-and-hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully-differential circuit passes the input signal to the two capacitors C2a and C2b through switches S4a and S4b. Switches S2a and S2b set the common mode for the operational transcon-
MDAC VIN T/H x2 VOUT
INTERNAL BIAS S2a TO NEXT STAGE C1a
CML S5a S3a
FLASH ADC 2 BITS
DAC S4a OUT C2a S4c S1 OTA OUT STAGE 1 STAGE 2 STAGE 12 S4b C2b C1b S3b S2b S5b CML
VIN
DIGITAL CORRECTION LOGIC 12
MAX1420
D11-D0
MAX1420
INTERNAL BIAS
Figure 1. Pipelined Architecture--Stage Blocks
Figure 2. Internal Track-and-Hold Circuit
10
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12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
AVDD 50 R 0.22F AVDD 2 R
MAX4284
CML 1nF
(AV2DD)
50 REFP R 0.22F 1nF
(AV2DD
0.5V
)
R AVDD 2 AVDD 4
MAX4284
MAX1420
R 50 R REFN AVDD- 0.5V 2 0.22F AVDD 4 R REFIN R AGND 1nF
(
)
0.5V
Figure 3. Unbuffered External Reference Drive--Internal Reference Disabled
cations that require increased accuracy and a different input voltage range. The MAX1420 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, the on-chip +2.048V bandgap reference is active and REFIN, REFP, CML, and REFN are left floating. For stability purposes, bypass REFIN, REFP, REFN and CML with a capacitor network of 0.22F in parallel with a 1nF capacitor to AGND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In unbuffered external reference mode, REFIN is connected to AGND, thereby deactivating the on-chip buffers of REFP, CML, and REFN. With their buffers shut down, these nodes become high impedance and can be driven by external reference sources, as shown in Figure 3.
Clock Inputs (CLK, CLK)
The MAX1420's CLK and CLK inputs accept both differential and single-ended input operation and accept CMOS-compatible clock signals. If CLK is driven with a single-ended clock signal, bypass CLK with a 0.1F capacitor to AGND. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). Sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the ADC according to the following relationship: SNRdB = 20 x log10 1 2 x fIN x t AJ
where fIN represents the analog input frequency and tAJ is the aperture jitter. Clock jitter is especially critical for high input frequency applications. The clock input should always be considered as an analog signal and routed away from any analog or digital signal lines. The MAX1420 clock input operates with a voltage threshold set to AVDD/2. Clock inputs must meet the specifications for high and low periods as stated in the Electrical Characteristics.
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12-Bit, 60Msps, +3.3V, Low-Power ADC MAX1420
OE
INP ADC INN AVDD D11-D0
tBE OUTPUT DATA D11-D0 HIGH-Z
tBD HIGH-Z
VALID DATA
10k CLK 10k CLK AGND
10k
Figure 5. Output Enable Timing
10k
MAX1420
Figure 4. Simplified Clock Input Circuit
ternal bandgap reference is deactivated, which results in a typical 2mA supply current reduction. A full shutdown mode is available to maximize power savings during idle periods. The MAX1420 provides parallel, offset binary, CMOScompatible three-state outputs. With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last digital output code prior to the power-down. All data outputs, D0 (LSB) through D11 (MSB), are TTL/CMOS logic-compatible. There is a seven clock-cycle latency between any particular sample and its valid output data. The output coding is in offset binary format (Table 1). The capacitive load on the digital outputs D0 through D11 should be kept as low as possible (10pF), to avoid large digital currents that could feed back into the analog portion of the MAX1420, thereby degrading its performance. The use of buffers (e.g., 74LVCH16244) on the digital outputs of the ADC can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1420, add small-series resistors of 100 to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output.
Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10k resistors to bias the common-mode level of each input. This circuit may be used to AC-couple the system clock signal to the MAX1420 clock input.
Output Enable (OE), Power-Down (PD) and Output Data (D0-D11)
In addition to low operating power, the MAX1420 features two power-down modes: reference power-down and shutdown mode. In reference power-down, the in-
Table 1. MAX1420 Output Code for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF x 2047/2048 VREF x 2046/2048 VREF x 1/2048 0 -VREF x 1/2048 -VREF x 2046/2048 -VREF x 2047/2048 DIFFERENTIAL INPUT +FULL SCALE 1LSB +FULL SCALE 2LSB + 1 LSB Bipolar Zero - 1 LSB -FULL SCALE + 1 LSB -FULL SCALE OFFSET BINARY 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
System Timing Requirements
Figure 6 depicts the relationship between the clock input, analog input, and valid data output. The MAX1420 samples the analog input signal on the rising edge of CLK (falling edge of CLK) and output data is valid seven clock cycles (latency) later.
Applications Information
Figure 7 depicts a typical application circuit containing a single-ended to differential converter. The internal reference provides an AVDD/2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter at the input suppresses some of the wideband noise associated
* VREF = VREFP - VREFN
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12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
7 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6
ANALOG INPUT
CLK CLK tOD N-7 N-6 N-5 tCH N-4 tCL N-3 N-2 N-1 N
DATA OUTPUT
Figure 6. System and Output Timing Diagram
+5V
0.1F LOWPASS FILTER MAX4108 300 0.1F RISO 50 0.1F *CIN 22pF INP
-5V
MAX1420
600 300 600 CML 0.1F +5V +5V 0.1F INPUT 0.1F MAX4108 300 0.1F MAX4108 INN RISO 50 0.1F *CIN 22pF LOWPASS FILTER 600 0.22F 1nF 0.1F 44pF*
-5V
300 -5V
300 300 600 *TWO CIN (22pF) CAPS MAY BE REPLACED BY ONE 44pF CAP, TO IMPROVE PERFORMANCE.
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion ______________________________________________________________________________________ 13
12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
25 22pF * 0.1F VIN 1 N.C. 2 3 T1 6 5 4 0.22F 1nF 44pF * INP
MAX1420
CML
MINICIRCUITS T1-1T-KK81 25 22pF * INN
*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.
Figure 8. Using a Transformer for AC-Coupling
with high-speed op amps. Select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 7, an isolation resistor (RISO) of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor. Connecting CIN from INN to INP may further improve dynamic performance.
Grounding, Bypassing and Board Layout
The MAX1420 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass REFP, REFN, REFIN, and CML with a parallel network of 0.22F capacitors and 1nF to AGND. AVDD should be bypassed with a similar network of a 10F bipolar capacitor in parallel with two ceramic capacitors of 1nF and 0.1F. Follow the same rules to bypass the digital supply DV DD to DGND. Multilayer boards with separate ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arrangement to match the physical location of the analog ground (AGND) and the digital ground (DGND) on the ADCs package. Join the two ground planes at a single point, such that the noisy digital ground currents do not interfere with the analog ground plane. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces and remove digital ground and power planes from underneath digital outputs. Keep all signal lines short and free of 90 degree turns.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1420 for optimum performance. Connecting the center tap of the transformer to CML provides an AVDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements. In general, the MAX1420 provides better SFDR and THD with fully differential input signals over single-ended input signals, especially for very high input frequencies. In differential input mode, even-order harmonics are suppressed and each input requires only half the signal swing compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
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12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
VIN MAX4108 100 1k 0.1F RISO 50 INP CIN 22pF
MAX1420
CML
0.22F
1nF RISO 50
100
INN CIN 22pF
Figure 9. Single-Ended AC-Coupled Input Signal
CLK CLK
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 10). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-bits): SNRMAX = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise, e.g., thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB is computed from: ENOB = SINADdB -1.76dB 6.02dB
T/H
TRACK
HOLD
TRACK
Figure 10. T/H Aperture Timing
Static Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight-line. This straightline can be either a best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. The static linearity parameters for the MAX1420 are measured using the best straight-line fit method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes.
Dynamic Parameter Definitions
Aperture Jitter Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
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15
12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + V5 THDdB = 20 x log10 V1
Functional Diagram
CLK CLK INTERFACE MAX1420 AVDD AGND
INP T/H INN PIPELINE ADC
OUTPUT DRIVERS
D11-D0
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale.
PD
BANDGAP REFERENCE
REF SYSTEM + BIAS
DVDD DGND
REFIN REFP CML REFN
OE
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12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference MAX1420
Package Information
32L/48L,TQFP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
17 ____________________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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