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QL5064 QuickPCI Data Sheet
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66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM
Device Highlights
High Performance PCI Controller
* 64-bit/66 MHz Master/Target PCI Controller (automatically backwards compatible to 33 MHz or/and 32-bits) * 75 MHz PCI Interface supported for embedded systems * PCI Specification v2.2 compliance * Programmable back-end interface with three 64-bit busses/100 MHz * Provides full 533 MB/s PCI data transfer rates (600 MB/s at 75 MHz)
Extremely Flexible and Configurable
* Supports processor-less systems, as well as 0 wait-state burst connections to all known 8/16/32/64 bit processors * Includes non-volatile on-chip configuration data for total customization * Independent PCI bus (66 MHz) and local bus (100 MHz) clocks * All local interface, control, and glue-logic can be implemented on chip * "PCI friendly" pinout simplifies board layout, supports 4-layer PCI boards
Advanced Master DMA Features Advanced PCI Features
* DMA Chaining mode for queued DMA transactions * Four-channel DMA mastering, plus a SPCI (Single PCI Access) mode * Unlimited bursts supported in Master and Target mode * Two Master Write FIFOs and two Master Read FIFOs, each 64-deep and 64 bits wide * Target Read and Write FIFOs for pre-fetched reads and multipleposted writes * Programmable interrupt controller * I2O compliant under microprocessor control * 16 Mailbox registers for message passing and semaphores * Extended configuration space allowing Messaged Interrupts, power management, and future PCI enhancement support * Programmable DMA Channel Arbitration Scheme * SPCI (Single PCI Access) mode may initiate any PCI Master command * DMA controller configurable via PCI or back-end * DMA Chaining mode allows a linked list of DMA transfers to occur without user intervention
High Performance PCI Target
* Write posting FIFO increases performance with queued transactions (up to 16 queued writes) * Any BAR can be defined as pre-fetchable * Six base address registers supported, configurable as memory or IO * Unique "Target Blast Mode" enables highperformance and very low overhead streaming data to/from PCI
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QL5064 QuickPCI Data Sheet Rev. G
Expanded PCI Functionality
* Support for Configuration Space from 0x40 to 0x3FF * PCI expanded capabilities support * Expansion ROM supported with back-end memory * Power management support * Compact PCI hot-swap/hot-plug compliant * Messaged Interrupts * Configuration specified with anti-fuses on board, external EEPROM not needed
Programmable Logic
* 192 Programmable I/O pins in a 456 pin or 484 pin PBGA package * 74K gates with 11 blocks (total of 12,672 bits) of dual-port RAM * 250 MHz 16-bit counters, 275 MHz Datapaths, 160 MHz FIFOS * All back-end interface and glue-logic can be implemented on chip Figure 1: QL5064 Block Diagram
PCI Bus - 33/66/75 MHz 32/64 Bits (Data and Address)
PCI CONTROLLER 3 RECV FIFOs 64 deep 4 Channel DMA Ctrl 3 XMIT FIFOs 64 deep Interrupts Messaging Config.
64
64
64
100 MHz INTERFACE
192 User I/O
High Speed Logic Cells 74K Gates PROGRAMMABLE LOGIC
12k bits Dual Port RAM
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QL5064 QuickPCI Data Sheet Rev. G
Architecture Overview
The QL5064 device in the QuickLogic QuickPCI ESP (Embedded Standard Products) family provides a complete and customizable PCI interface solution combined with 74,000 system gates of programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum possible PCI bus bandwidth. The programmable logic portion of the device is built from 792 QuickLogic Logic Cells, and 11 QuickLogic Dual-Port RAM Blocks. The configurable RAM blocks can each operate in 64x18, 128x9, 256x4, or 512x2 mode. These dual-port RAM blocks can be cascaded to achieve deeper or wider configurations. They can also be combined with logic cells to form FIFOs. See RAM Module Features on page 13 for more information. The QL5064 device includes a complete pre-designed PCI Initiator/Target interface offering full burst mode transfers at 32 or 64 bits per clock cycle. At 66 MHz, this device offers support for 533 Mbytes/sec data transfer rates (66.6 MHz * 8 bytes per transfer). At the maximum speed of 75 MHz (exceeding the current maximum speed specification for PCI), the QL5064 device can achieve 600 Mbytes/sec data transfer rates. The PCI interface is configured via internal programmable configuration bits, so no external EEPROM or memory is needed. The QL5064 device meets PCI 2.2 electrical and timing specifications and has been fully hardware-tested. The QL5064 device features 3.3-volt operation with multi-volt compatible I/Os. Thus it can easily operate in 3.3-volt only systems, as well as mixed 3.3 volt/5 volt system. It can be placed on a universal signaling PCI board. A wide range of additional features complements the QL5064 device. The FPGA side of the device is 5 volt and 3.3-volt PCI-compliant and is capable of implementing FIFOs at 160 MHz, and counters at over 250 MHz. I/O pins provide individually controlled output enables, dedicated input/feedback registers, and full JTAG capability for boundary scan and test. In addition, the QL5064 device provides the benefits of non-volatility, high design security, immediate functionality on power-up, and a self-contained single chip solution.
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DQ
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*
Target Interface Controller
Address Latch/ Decode/ Increment
1152 bits 1152 bits 1152 bits 1152 bits 1152 bits 1152 bits
Configuration
Lane Steering
64
QL5064 QuickPCI Data Sheet Rev. G
Embedded Memory
data_in Interface
5 DMA Controllers
xmit0 xmit1 rcv0 rcv1
72x32 Target Write/ Post FIFO 72x64 DMA/ Chain Rcv0 FIFO
Chain Control Single PCI Access
control Interface
72x64 DMA Rcv1 FIFO 64
DQ
User I/O (192)
Global Clk's (4)
FPGA
(792 Logic Modules)
Internal Bus Arbiter
Registers
64
Array Clk's (2)
Control Bus Decode
Figure 2: QL5064 Device Block Diagram
PCI Interface Buffers & Logic
PCI/FPGA Interrupt Controller
64x16 Target Read/ Prefetch FIFO 72x64 DMA/ Chain Xmit0 FIFO data_out Interface 72x64 DMA Xmit1 FIFO
Data Construction Lane Steering
1152 bits 1152 bits 1152 bits
64
33/66/75 MHz PCI 32/64 bits (data and address)
Embedded Memory
PCI to FPGA Mailbox (8x8) FPGA to PCI Mailbox (8x8)
1152 bits 1152 bits
I2O Messaging
User Clock (0-100MHz) PCI Clock
Antifuse Configuration
(c) 2003 QuickLogic Corporation
User_clk (global clock)
QL5064 QuickPCI Data Sheet Rev. G
Applications
The QL5064 device supports maximum PCI transfer rates, so many applications exist which are ideally suited to the device's high performance. High speed data communications, telecommunications, and computing systems are just a few of the broad range of applications areas that can benefit from the high speed PCI interface and programmable logic. The PCI Interface can also act as a PCI Host Controller. This can be accomplished by glue-less interface to most popular 8/16/32/64-bit microprocessors.
Six FIFOs for Increased Performance
The PCI interface includes the following six FIFO buffers: * Two 64x64 PCI Master Transmit Buffers * Two 64x64 PCI Master Receive Buffers * One 16x64 PCI Target Read/Pre-Fetch Buffer * One 32x64 PCI Target Write/Post Buffer All FIFO buffers are 72 bits wide (64 data bits + 8-bit byte enables). PCI Initiator-mode buffers are 64 deep and support sustained burst transfers. PCI Target mode buffers are provided for both Read and Write operations to the PCI Target, supporting pre-fetched reads with configurable registers. All FIFOs can operate with independent read and write clocks, so that the programmable logic design can interface to the FIFOs at up to 100 MHz (a clock asynchronous to the 33/66 MHz PCI clock). All data synchronization is accomplished in the PCI core. The transmit FIFOs have full flags and the receive FIFOs have empty flags. Both types of FIFOs have programmable status flags that may be used to determine if either of the transmit FIFOs are almost full or if either of the receive FIFOs are almost empty.
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QL5064 QuickPCI Data Sheet Rev. G
DMA Feature Overview
Each Master-mode FIFO has its own DMA controller to support maximum data throughput. Combining one Initiator-Mode Transmit FIFO with one Initiator-Mode Receive FIFO also supports DMA Chaining. This unique and flexible DMA chaining mode permits a 'linked-list' of transfers to be completed by the DMA controller without software or processor intervention. DMA Registers are accessible by the FPGA (back-end interface), as well as the PCI bus. DMA Chaining descriptors are made of four 64-bit Quad-Words, or 32 bytes of data per descriptor. Each descriptor defines a DMA transaction (memory start location, size, read/write) as well as 88 bits of user-defined information (such as a descriptor identifier, or back-end address). DMA Chaining is a powerful DMA feature, allowing the QL5064 device to drive continuous pre-defined DMA transactions with no processor or software interaction. Single PCI Access (SPCI) reads and writes are supported for single quad-word transfers that do not require FIFOs. SPCI supports IO reads and writes, configuration reads and writes, special cycles, interrupt acknowledge cycles, as well as standard memory read/write transactions. Figure 3: DMA Chaining Descriptor
63 0 Offset
First PCI Address User Defined (63:0) (local address) Transfer Count (bytes) User Defined (31:0) (23:0) Next Descriptor Pointer Address (63:0)
0 x 00 0 x 08
7
R
I W
0 E O C
0 x 10 0 x 18
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QL5064 QuickPCI Data Sheet Rev. G
Mailbox Registers and I2O
The PCI interface contains 16 bytes of mailbox registers to support message/semaphore passing between the programmable logic design and the PCI bus. These mailbox registers are memory mapped to a dedicated register bank within the first 256 bytes of BAR 0. Eight bytes are provided for the FPGA to PCI direction, and eight bytes are also provided for the PCI to FPGA direction. Status flags and interrupts are available for each direction as well. Figure 4 shows the mailbox structure within the QL5064 device. Hardware controlled queues allow full I2O messaging support with a processor and local I2O drivers. Figure 4: Mailbox Structure
PCI Outgoing Mailboxes
mailbox 7 mailbox 6 mailbox 5 mailbox 4 mailbox 3 mailbox 2 mailbox 1 mailbox 0
63
0
byte 7
outgoing decode control
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0
STATUS REGISTER
status
interrupt configuration register
status
INTERRUPT CONTROL
8
full interrupt
empty interrupt
empty interrupt
full interrupt
INTERRUPT CONTROL
interrupt configuration register
status
status
STATUS REGISTER incoming decode control
63 0
byte 7
byte 6
byte 5
byte 4
8 byte 3
byte 2
byte 1
byte 0
mailbox 7
mailbox 6
mailbox 5
mailbox 4
mailbox 3
mailbox 2
mailbox 1
mailbox 0
PCI BUS
User Outgoing mailboxes
CNTL BUS
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QL5064 QuickPCI Data Sheet Rev. G
Internal Bus Structure
The internal interface between the PCI Controller and the FPGA logic cells is both simple and flexible. The interface is configurable, based on the needs of the FPGA design. Configuration is accomplished at the time of programming the FPGA. The FPGA/PCI interface supports very high bandwidth data transfers via three 64-bit busses. The interface is fully synchronous, and supports a separate clock from the PCI clock. The Interface clock can run at up to 100 MHz. The interface has three busses: DataIN, DataOUT, and Control_DATA. The DataIN bus moves the data from the PCI bus to the back-end. The DataOUT bus moves data from the back-end to the PCI bus. The Control_DATA bus moves the data from the PCI bus to the back-end and from the back-end to the PCI bus. It also accesses the internal control registers. All three busses can operate simultaneously at zero wait states.
Clocking
All bus accesses to the QL5064 from the FPGA (back-end) interface are synchronous to the back-end user clock - called user_clk. The user_clk is supplied on a dedicated external pin. The PCI clock may be routed out to a pin, and then back into the device to be used as the user_clk if desired. The user_clk signal may be asynchronous to the pci_clk signal, and may run at up to 100 MHz with no PLL requirements. All busses on the back-end of the QL5064 device can sustain data movement on every cycle of user_clk. Figure 5: FPGA to PCI Synchronization
PCI pci_clk FPGA PCI user_clk or FPGA user_clk osc
user_clk
DataIN Bus Description
The DataIN bus transfers data from the PCI bus to the back-end interface. This data can come from three different data paths: either one of the two DMA receive FIFOs, or the Target Write/Post FIFO. For proper data management, empty and almost empty flags from the two DMA receive FIFOs are accessible to the backend design. The almost empty flags are configured through the Control_DATA bus interface or the PCI bus. Interface to the Target Write/Post FIFO is accomplished through the Target interface signals. A block diagram of the DataIN and Target control connections is shown in Figure 6. Data is transferred to the DataIN bus in the same byte lane in which is was transferred over the PCI bus. To assist with re-aligning or compacting data in the back-end interface, a byte-lane barrel shifter provides the means to manipulate byte lane positioning. This is accomplished with the byte_select[2:0] input. See the DataIN Bus section of the internal signal descriptions for more information.
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QL5064 QuickPCI Data Sheet Rev. G
Figure 6: DataIN Bus Description
PCI Core
pci data pci cbe [7:0]
64
Target/ Write Post FIFO (32 Deep)
Byte lane [7:0]
FPGA
0 1 2 3
0 1 2
Decode
DataOUT Bus Description
The DataOUT bus is used to transfer data from the back-end interface to the PCI bus. This bus is connected to three destinations within the QL5064 device: either one of the two DMA transmit FIFOs, or the Target Read/Pre-Fetch FIFO. For proper data management and high data throughput, full and almost full flags are available for each of the two DMA transmit FIFOs. The almost full flags are fully configurable via the Control_DATA bus interface or the PCI bus. Interface to the Target Read/Pre-Fetch FIFO is accomplished through the Target interface signals. A block diagram of the DataOUT connections is shown in Figure 7. The data_outDES[1:0] signals select a particular FIFO to be connected to the DataOUT bus. A block diagram of the DataOUT bus and its connections is shown in Figure 7. Data written to the DMA transmit FIFOs or the Target Read/Pre-fetch FIFO must be set up in the same byte lanes in which the data will be transferred in the PCI bus. To aid with aligning, re-aligning, or compacting data that is to be written to the FIFOs via the DataOUT bus, a byte-lane barrel shifter is present, controlled by the data_out_shift[2:0] signals. See the DataOUT bus section of Table 2 for more information.
(c) 2003 QuickLogic Corporation
PCI Bus
8
64
Lane Barrel Shifter
D
Q
64
dataIN [63:0]
64
DMA Rcv 0 FIFO (64 deep)
8
Byte lane [7:0] Chain Descriptor Tags 0 1
rcv0_fifo_program_empty_flag rcv0_fifo_ef
3 2
dataIN_bytesel [2:0]
8
64
2
Shifter
D
Q
dataIN_BE[7:0]
DMA Rcv 1 or Target Write Post FIFO (64 Deep)
8
Byte lane [7:0]
3
2
D
Q
dataIN_byteID [1:0] rcv1_fifo_program_empty_flag rcv1_fifo_ef
2
dataIN_src_sel[1:0] dataIN_cs user_clk
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QL5064 QuickPCI Data Sheet Rev. G
Figure 7: DataOUT and Control Bus Description
cntl_data_in [63:0] cntl_data_out [63:0] cntl_wrt_nrd cntl_be[7:0] cntl_addr [7:3] cntl_cs
(cntl_addr == 0xc0 ) * ctrl_cs
cntl_data[63:0] byte_lane [7:0]
0 1
0 1
Control Bus Interface
(cntl_addr == 0xc8 ) * ctrl_cs (cntl_addr == 0xf8) * ctrl_cs
Fifo 0 Transmit
0 1
WR
0 1
data_out [63:0] data_out_BE[7:0] data_out_h [63:0] data_out_BEh[7:0]
To Master Controller
data_out_byte_sel[2:0] fpga_reset user_clk
data_out Lane Shifter and Construction
0 1
Fifo 1 Transmit
0 1
WR
0 1
0 1
2
data_outDES[1:0]
Target Read Fifo
0 1
To Target Controller
WR
data_outCS user_clk
FPGA
PCI Core
Control_DATA Bus Description
The Control_DATA bus is the heart of the control circuitry for the PCI interface. The intent of this bus is to provide access to all of the control structures necessary for a microprocessor interfaced to the QL5064 device to be able to marshal all PCI operations. The Control_DATA bus, like the DataIN and DataOUT buses, is synchronous to user_clk, and can be written or read on every clock. This is a bi-directional bus that offers read and write access at 64-bits. In addition to all control structures, this bus is designed to access all of the six FIFOs.
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QL5064 QuickPCI Data Sheet Rev. G
PCI Master Arbitration
Five possible masters could be driving PCI master transactions on the PCI bus, and as a result, a flexible arbitration controller has been included in the QL5064 device. The five sources for PCI master transactions include: Transmit FIFO 0, Transmit FIFO 1, Receive FIFO 0, Receive FIFO 1, and SPCI (Single PCI Access). (SPCI is a means for the back-end design to initiate single quad-word transfers directly on the PCI bus for master transactions, bypassing the DMA FIFOs). SPCI Mastering is controlled through the Control_DATA bus. Three arbitration modes have been defined for the QL5064 device. These modes are round robin, prioritized, and customized. In all modes, the SPCI Mastering always has highest priority. The arbitration scheme is selected by setting the proper values in the Arbitration Mode bits of configuration registers (offset 0xD0, bits 49:48). The selection is: 00b - round robin, 01b - prioritized, 10b - customized, 11b - reserved. Round robin arbitration simply cycles through the four Master FIFOs in the following order: Transmit 0 (T0), Transmit 1 (T1), Receive 0 (R0), Receive 1 (R1). Prioritized mode uses values assigned to DMA_arbitration_priority bits in the configuration memory (offset 0xD0). Masters set to equal priority are arbitrated (high to low): T0, T1, R0, R1. Customized arbitration mode uses two buses and back-end logic. The fpga_bus_req[3:0] signals (1 bit per FIFO) indicate to the programmable logic design which master is requesting the bus. The fpga_bus_req bits are assigned: [0]-R1, [1]-R0, [2]-T1, [3]-T0. The back-end design should set fpga_arb_sel[1:0] according to which master should be granted the bus. The fpga_arb_sel bus uses the enumeration: 00-R1, 01-R0, 10-T1, 11-T0.
Control Registers
DMA Control and QL5064 registers can be accessed from the PCI bus or the back-end Control_DATA bus. On the PCI side, these registers are accessed through BAR 0, with offsets 0x00 to 0xFF (below 0x100). The breakdown of this memory space can be seen in Table 1.
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QL5064 QuickPCI Data Sheet Rev. G
Table 1: User Memory Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Master Write Address 0[63:0] (r/w)
Master Write Count Status0[31:0] (r only) Master Write Count Status1[31:0] (r only) 00 strt
32 bit
00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78
Master Write Transfer Count0[31:0] (r/w) Master Write Transfer Count1[31:0] (r/w)
Receive FIFO 0 Byte Lane[7:0]
Target FIFO Threshold MSB's[3:0]
Master Write Address 1[63:0] (r/w)
Single PCI Access cmd[3:0] byte lanes[7:0]
en16 /8
Pipeline Bus Request Not Empty tag0 Receive FIFO 1 XMT XMT RCV RCV XMT XMT Byte Lane[7:0] [1:0] 0 1 0 1 0 1 Target BAR Configuration (r only)
Chip Revision ID [7:0] User ID [7:0] (r only) (r only) antifuse
RO RO
0000
wrt wwt
BAR Enable (r only)
rom
XM f XM a f XM f XM a f RC e RC a e RC e RC a e
Target FIFO Control -- Emptyness Threshold BAR5 BAR4 BAR3 BAR2 BAR1 BAR0
543210
BAR5
BAR4
BAR3
BAR2
BAR1
BAR0
0
Target Prefetch Cntl BAR[5:0]
0
Target Burst Request BAR[5:0]
I2O Interrupt Mask Bit [3]
I2O Interrupt Service Request Bit [3]
Reserved
I2O Outbound Queue Pointer Master Read Count Status0[31:0] (r only) Master Read Count Status1[31:0] (r only) 00
XMIT FIFO 1 Almost Full[5:0] (r/w)
I2O Inbound Queue Pointer Master Read Transfer Count0[31:0] (r/w) Master Read Transfer Count1[31:0] (r/w) 00
Receive FIFO1 Almost Full[5:0] (r/w)
Master Read Address 0[63:0] (r/w) / Chain Descriptor Start Address [63:0] (r/w) Master Read Address 1[63:0] (r/w)
00
XMIT FIFO 0 Almost Full[5:0] (r/w)
00
XMIT FIFO 1 Almost Empty[5:0] (r/w)
00
XMIT FIFO 0 Almost Empty[5:0] (r/w)
00
Receive FIFO0 Almost Full[5:0] (r/w)
00
Receive FIFO1 Almost Empty[5:0] (r/w)
00
Receive FIFO0 Almost Empty[5:0] (r/w)
User Incoming Mail 7 User Incoming Mail 6 User Incoming Mail 5 User Incoming Mail 4 User Incoming Mail 3 User Incoming Mail 2 User Incoming Mail 1 User Incoming Mail 0 User Outgoing Mail 7 User Outgoing Mail 6 User Outgoing Mail 5 User Outgoing Mail 4 User Outgoing Mail 3 User Outgoing Mail 2 User Outgoing Mail 1 User Outgoing Mail 0
0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 Error 0000 0
PCI Incoming MB Empty PCI Outgoing MB Empty Interrupt Mask[7:0] Interrupt Mask[7:0]
User region [2:0]
TUM TUR W TUR TAV
I2O Interrupt
I
oflf ople iplf ifle
DMA Interrupt
SP
BI St
CE chn rcv1 rcv0 xmt1 xmt0
User Outgoing MB Empty [7:0] Interrupt Mask[7:0] User Outgoing MB Status [7:0]
User Incoming MB Full [7:0] User Incoming MB Full Interrupt Mask[7:0] User Incoming MB Status [7:0]
BI Ms SP Ma
MRT
PED
RTA
MA
SPCI Chn rcv1 rcv0 xmt1 xmt0
BI St
user_be_req[7:0]
Single PCI Access Address Register[63:0] (r/w) Single PCI Access Data Register[63:0] (r/w) Reserved Receive FIFO0[63:0] (r only) Receive FIFO1[63:0] (r only) Transmit FIFO0[63:0] (w only) Transmit FIFO1[63:0] (w only)
0000_0000 0000_00
Arb Mode [1:0]
DMA Arbitration Priority
rcv1[1:0] rcv0[1:0] xmt1[1:0] xmt0[1:0]
0000
DMA 32/64#
rcv1 rcv0 xmt1 xmt0
rcv1 rcv0 xmt1xmt0
xmt1xmt0 Chn rcv1 rcv0 xmt1 xmt0
Reserved Reserved Reserved Target Control Address[63:0] (r only) Target Control Data[63:0] (r/w)
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
BI Do
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0000 0000 0000
0000
80 88 90 98 a0 a8 b0 b8 c0
I2O Int Mask
oflf ople iplf ifle
DMA Interrupt Mask User Outgoing MB Empty
CE chn rcv1 rcv0 xmt1 xmt0
Chain Ptr Fetch End
I2O Status
oflf ople iplf ifle
0
DMA Start/Done#
chn rcv1 rcv0 xmt1 xmt0
00
DMA SPC
0
FIFO Flush
DMA Cancel
000
BIST Code[3:0]
0
BE En [1:0]
Max Retry [1:0]
FIFO Thresh TO[1:0]
lat en
c8 d0 d8 e0
e8 000 f0 f8
2 1 0
(c) 2003 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. G
RAM Module Features
Figure 8: RAM Module
RAM Module
MODE[1:0] WA[a:0] WD[w:0] ASYNCRD RA[a:0] RD[w:0]
WE WCLK
RE RCLK
Mode: Address Busses [a:0] Data Busses [w:0]
64x18 [5:0] [17:0]
128x9 [6:0] [8:0]
256x4 [7:0] [3:0]
512x2 [8:0] [1:0]
The RAM modules are "dual-ported," with independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 9 address lines, allowing word lengths of up to 18 bits and address spaces of up to 512 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. This approach allows up to 512 words deep configurations as large as 22 bits wide in the QL5064 device. A similar technique can be used to create depths greater than 512 words. In this case address signals higher than the eighth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
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QL5064 QuickPCI Data Sheet Rev. G
Figure 9: QuickWorks Tool Suite
QuickWorks Design Software
Third Party Design Entry & Synthesis
Schematic
SCS Schematic Tools
VHDL/ Verilog
Turbo Writer HDL Editor
Mixed-Mode Design
Synplify-Lite HDL Synthesis
Third Party Simulation
QuickTools/QuickChip: Optimize, Place, & Route
Silos & Simulators
JTAG Support
JTAG pins support IEEE standard 1149.1a to provide boundary scan capability for QL5064 devices. Six pins are dedicated to JTAG and programming functions on each QL5064 device, and are unavailable for general design input and output signals. These pins are: TDI, TDO, TCK, TMS, and TRSTB are JTAG. The sixth pin, STM, is used only for programming.
Development Tool Support
Software support for the QL5064 device is available through the QuickWorks development package. This turnkey PC-based QuickWorks package, shown in Figure 9, provides a complete ESP software solution with design entry, logic synthesis, place and route, and simulation. QuickWorks includes VHDL, Verilog, schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the integrated Synplicity Synplify Lite tool, specially tuned to take advantage of the QL5064 architecture. QuickWorks also provides functional and timing simulation for guaranteed timing and source-level debugging. The UNIX-based QuickTools and PC-based QuickWorks-Lite packages are a subset of QuickWorks and provide a solution for designers who use schematic-only design flow third-party tools for design entry, synthesis, or simulation. QuickTools and QuickWorks-Lite read EDIF netlists and provide support for all QuickLogic devices. QuickTools and QuickWorks-Lite also support a wide range of third-party modeling and simulation tools. In addition, the PC-based package combines all the features of QuickWorks-Lite with the SCS schematic capture environment, providing a low-cost design entry and compilation solution.
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QL5064 QuickPCI Data Sheet Rev. G
PCI to Programmable Logic Interface
The QL5064 device is designed to be highly customizable. Figure 10 illustrates the interface signals present between the configurable PCI core, and the programmable logic region of the QL5064 device. Detailed descriptions of each of these interface signals follow in the next section. Figure 10: PCI to Programmable Logic Interface Block Diagram
pci_clk_2fpga user_clk fpga_reset AD[63:0] C/BE[7:0] PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL dataIN_bytesel[2:0] PERR# SERR# REQ# GNT# CLK RST# dataIN[63:0] dataIN_BE[7:0] dataIN_src_sel[1:0] dataIN_cs dataIN_byteID[1:0] rcv0_fifo_ef rcv0_fifo_prog_empty_flag rcv1_fifo_ef rcv1_fifo_prog_empty_flag xmt0_fifo_ff PAR64 REQ64# ACK64# INTA# xmt0_fifo_prog_full_flag xmt1_fifo_ff xmt1_fifo_prog_full_flag spci_done user_region[2:0] user_stop user_be_req[7:0] user_rdwr user_addr_valid user_req user_mult user_addr_output[32:0] addr_select user_clk gclk (4) aclk (2) user I/O (192)
cntl_data_in[63:0] cntl_data_out[63:0] cntl_wrt_nrd cntl_addr[7:3] cntl_be[7:0] cntl_cs data_out_byte_sel[2:0] data_outCS
TDI TDO TCK TMS TRST#
data_outDES[1:0] data_outBE[7:0] data_out[63:0] interrupt_o interrupt_i
fpga_loc_sel[1:0] fpga_bus_req[3:0]
Programmable Logic and Dual-Port RAM
PCI Block
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QL5064 QuickPCI Data Sheet Rev. G
PCI Back-End Interface Signals
The PCI back-end internal signals can interface directly to pins or to internal logic cells or RAM blocks in the programmable logic region of the device. These signals are used to customize the device so that it can connect to other devices on the board directly, without any glue-logic required. Table 2: PCI Back-End Interface Signals
Symbol Clocks pci_clk_2fpga user_clk I O Buffered version of the PCI clock. For use in the FPGA. FPGA supplied clock used for all interface to the embedded PCI core. This signal is required and all communication between the embedded PCI core and the FPGA is synchronous to this clock with the exception of the DMA arbitrary signals. Active High. Global reset signal from the PCI core. Active High. This signal should be used as the global reset for the FPGA and all other supporting circuitry. When target_addr_valid is active, these signals indicate which of the following regions are being accessed. 3'b000 BAR0 3'b001 BAR1 3'b010 BAR2 3'b011 BAR3 3'b100 BAR4 3'b101 BAR5 3'b110 Expansion ROM 3'b111 Configuration Space 0x40-0xff Active High. Stops prefetch after the current cycle. Active High. Byte lanes requested by PCI for all target accesses. When target_addr_valid is active, a logic `1' indicates that the requested transaction is a read. When `0' the present transaction is a write. Active High. Indicates that PCI is requesting a sequentially continuing target access. Active High. When active, PCI is requesting at least one piece of data to be transferred. Deasserted after an advance generated by a read or write from the target FIFOs or after `target_user_stop' is asserted. Active High. PCI is requesting at least 2+ pieces of data to be transferred. The current address of the PCI target transaction. Incremented automatically by a quad word when a 64-bit piece of target data is written or read. Selects which half of the 64-bit PCI address for a target transaction is placed on the user_addr [32:0] bus. addr_select O 0 - [35:3] 1 - 00000. [63:36] I/O
a
Description
fpga_reset Target Interface
I
user_region [2:0]
I
user_stop user_be_req [7:0] user_rdwr user_addr_valid
O I I I
user_req user_mult user_addr_output [32:0]
I I I
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QL5064 QuickPCI Data Sheet Rev. G
Table 2: PCI Back-End Interface Signals (Continued)
Symbol DataIN Bus - (PCI - FPGA) dataIN [63:0] I Active High. A 64-bit bus connecting to the FIFOs. Used by the FPGA to obtain data being transferred from the PCI bus to the FPGA. Active High. Data source select signals determines which FIFO is connected to the dataIN bus: dataIN_src_sel[1:0] O 00 Receive FIFO0 01 Receive FIFO1 10 Target Write post FIFO 11 Not defined (returns 0) Active High. Chip select for read operations on the dataIN bus. When active, advances the pointer for the FIFO selected by dataIN_src_sel[1:0] Active High. Indicates which byte lane is active for the current transfer occurring on dataIN[63:0]. dataIN_BE[7] dataIN_BE[6] dataIN_BE[5] dataIN_BE[4] dataIN_BE[3] dataIN_BE[2] dataIN_BE[1] dataIN_BE[0] dataIN[63:56] dataIN[55:48] dataIN[47:40] dataIN[39:32] dataIN[31:24] dataIN[23:16] dataIN[15:08] dataIN[07:00] I/Oa Description
dataIN_cs
O
dataIN_BE[7:0]
I
dataIN_BE[7:0] are shifted along with the data. dataIN_bytesel[2:0] I Sets the number of bytes to barrel shift the 64-bit dataIN bus and the dataIN_BE bus. Active High. Tag bits for the DMA chain descriptor pointer. When active, indicates that chain descriptor information is available at the output of Receive FIFO0. dataIN_byteID[1:0] I dataIN_byteID[1:0] 00 Normal data 01 Descriptor dword 0 (PCI starting address) 10 Descriptor dword 1 (user defined) 11 Descriptor dword 2 (transfer count, et al.) Active High. Receive FIFO0 is empty. Active High. Receive FIFO0 contains a number of entries less than or equal to the threshold set in register 0x68, bits 37:32. Active High. Receive FIFO1 is empty. Active High. Receive FIFO1 contains a number of entries less than or equal to the threshold set in register 0x68, bits 45:40. Active High. Transmit FIFO0 is full. Active High. Transmit FIFO0 contains a number of entries greater than or equal to the threshold set in register 0x68, bits 53:48. Active High. Transmit FIFO1 is full.
FIFO Status Signals rcv0_fifo_ef rcv0_fifo_prog_empty_flag rcv1_fifo_ef rcv1_fifo_prog_empty_flag xmt0_fifo_ff xmt0_fifo_prog_full_flag xmt1_fifo_ff I I I I I I I
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QL5064 QuickPCI Data Sheet Rev. G
Table 2: PCI Back-End Interface Signals (Continued)
Symbol xmt1_fifo_prog_full_flag I/Oa I Description Active High. Transmit FIFO1 contains a number of entries greater than or equal to the threshold set in register 0x68, bits 61:56. Active High. Single PCI Access done. Active High. A 64-bit bus used to read to the various memory mapped registers of the QL5064. Control bus write/not read. When `1' current access to the control bus is a write. When `0' current access to the control bus is a read. Active High. Control bus address bits 7:3. Selects which of the 64-bit registers the control bus is accessing. cntl_be[7] cntl_be[6] cntl_be[5] cntl_be[4] cntl_be[3] cntl_be[2] cntl_be[1] cntl_be[0] cntl_data[63:56] cntl_data[55:48] cntl_data[47:40] cntl_data[39:32] cntl_data[31:24] cntl_data[23:16] cntl_data[15:08] cntl_data[07:00]
Miscellaneous Interface Signals SPCI_done I Control Bus Interface Signals cntl_data_in[63:0] cntl_wrt_nrd cntl_addr[7:3] I O O
cntl_be[7:0]
O
cntl_data_out[63:0] cntl_cs
O O
Active High. A 64-bit bus used to write to the various QL5064 memory mapped registers. Active High. Control bus chip select. A 64-bit bus connecting to the FIFOs. Used by the FPGA to write data from the FPGA to the PCI bus via the three output FIFOs. Active High. Chip select for the data_out bus. Destination select for the data_out bus.
Data OUT Bus Interface Signals data_out[63:0] data_outCS O O
data_outDES[1:0]
O
00 Transmit FIFO0 01 Transmit FIFO1 10 Target/Read Post FIFO 11 No destination (parked) Lane shifting selection for the construction registers before the FIFOs data_out_BE[7:0] are also shifted accordingly. Sets the number of bytes to barrel shift the 64-bit data_out bus and the 8-bit data_outBE bus. Active High. Indicates which byte lane is active for the current transfer occurring on data_out[63:0]. data_outBE[7] data_outBE[6] data_outBE[5] data_outBE[4] data_outBE[3] data_outBE[2] data_outBE[1] data_outBE[0] data_out[63:56] data_out[55:48] data_out[47:40] data_out[39:32] data_out[31:24] data_out[23:16] data_out[15:08] data_out[07:00]
data_out_byte_sel[2:0]
O
data_outBE[7:0]
O
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QL5064 QuickPCI Data Sheet Rev. G
Table 2: PCI Back-End Interface Signals (Continued)
Symbol Interrupt Control interrupt_i interrupt_o Master Arbitration Control FPGA arbitration select. If the FPGA has control of the master-modeling arbitration, these bits determine which DMA channel should initiate a DMA transfer after the next arbitration cycle. Has relationship to pci_clk. fpga_loc_sel[1:0] O 00 => Receive channel 1 has access to the bus 01 => Receive channel 0 has access to the bus 10 => Transmit channel 1 has access to the bus 11 => Transmit channel 0 has access to the bus Active High. Master request status. Indicates that the respective master has need to access the PCI bus. Has relationship to pci_clk. fpga_bus_req[3:0] I fpga_bus_req[0] = receive channel 1 fpga_bus_req[1] = receive channel 0 fpga_bus_req[2] = transmit channel 1 fpga_bus_req[3] = transmit channel 0 O I Active High and level sensitive. When active and not masked, asserts a PCI interrupt. Active High. Indicates an interrupt is pending for the FPGA to service. I/Oa Description
a. I = Input from PCI to FPGA O = Output from FPGA to PCI
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QL5064 QuickPCI Data Sheet Rev. G
Configuration Space
Defaults for most configuration space parameters can be programmed into the Via-Link antifuse-based configuration region in the device. Also, by fully supporting the extended configuration space region beyond the 40(hex), the full enhanced feature set of the PCI bus is available to the user. Figure 11: Configuration Space Block Diagram
31
Device ID Status
R M
16 15
AF
0
Vendor ID Command
R
AF RW
R
AF
00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h
AF
M
AF
Class Code BIST
RW
Revision ID R AF Cashe Line Size
RW
Header R AF Type
M M M
AF
Latency Timer
AF
AF
Base Address Registers
M M M
AF
AF
AF
Cardbus CIS Pointer Subsystem ID
R
AF
R
AF
28h
R
AF
Subsystem Vendor ID
M
AF
2Ch 30h 34h 38h
Expansion ROM Base Address Reserved
R
AF
Cap. Ptr R AF
R
AF
Reserved Max_Lat R AF Min_Gnt R AF
Interrupt R AF Pin
Interrupt Line
RW
3Ch 40h
FPGA Controlled using BARCS[7]
FF
R
Legend
AF
Read only antifuse program Read / Write masked by antifuses Read / Write
M
AF
RW
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QL5064 QuickPCI Data Sheet Rev. G
AC Characteristics
The AC characteristics are calculated at VCC = 3.3 V, TA = 25C (K=1.00). To calculate delays, multiply the appropriate K factor in Table 15 by the numbers presented in Table 3 through Table 10. Logic cell diagrams and waveforms are provided from Figure 12 through Figure 20. Figure 12: QuickPCI Logic Cell Configuration
Programmable Logic Cell
5 Independent Functions (Optimized for Synthesis) OR
F1
Single Large Function
Table 3: Logic Cells
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delayb Setup Timeb Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width Propagation Delays (ns) Fanouta 1 1.4 1.8 0.0 0.8 1.6 1.6 1.4 1.2 1.9 1.8 2 1.7 1.8 0.0 1.1 1.6 1.6 1.7 1.5 1.9 1.8 3 2.0 1.8 0.0 1.4 1.6 1.6 2.0 1.8 1.9 1.8 4 2.3 1.8 0.0 1.7 1.6 1.6 2.3 2.1 1.9 1.8 8 3.5 1.8 0.0 2.9 1.6 1.6 3.5 3.3 1.9 1.8
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. b. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
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QL5064 QuickPCI Data Sheet Rev. G
Table 4: RAM Cell Synchronous Write Timing
Symbol tSWA tHWA tSWD tHWD tSWE tHWE tWCRD Parameter WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA)
a
Propagation Delays (ns) Fanout 1 1.0 0.0 1.0 0.0 1.0 0.0 5.0 2 1.0 0.0 1.0 0.0 1.0 0.0 5.3 3 1.0 0.0 1.0 0.0 1.0 0.0 5.6 4 1.0 0.0 1.0 0.0 1.0 0.0 5.9 8 1.0 0.0 1.0 0.0 1.0 0.0 7.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
Table 5: RAM Cell Synchronous Read Timing
Symbol tSRA tHRA tSRE tHRE tRCRD Parameter RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RD ]
b
Propagation Delays (ns) Fanouta 1 1.0 0.0 1.0 0.0 4.0 2 1.0 0.0 1.0 0.0 4.3 3 1.0 0.0 1.0 0.0 4.6 4 1.0 0.0 1.0 0.0 4.9 8 1.0 0.0 1.0 0.0 6.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. b. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
Table 6: RAM Cell Asynchronous Read Timing
Symbol RPDRD Parameter RA to RDa Propagation Delays (ns) Fanout 1 3.0 2 3.3 3 3.6 4 3.9 8 5.1
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
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QL5064 QuickPCI Data Sheet Rev. G
Table 7: Input-Only Cells
Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time Propagation Delays (ns) Fanouta 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 2 1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0 3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0 4 1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0 8 2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0 12 2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
Table 8: Clock Cells
Symbols tACK tGCKP tGCKB Parameter 1 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1.2 0.7 0.8 2 1.2 0.7 0.8 3 1.3 0.7 0.9 Propagation Delays (ns) Loads per Half Columna 4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 .16 0.7 1.2 12 1.7 0.7 1.3 14 1.8 0.7 1.4 16 1.9 0.7 1.5 18 2 0.7 1.6 20 2.1 0.7 1.7
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column.
Table 9: I/O Cell Input Delays
Symbol tI/O tISU tIH tlOCLK tlORST tlESU tlEH Parameter Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Set-Up Time Input Register Clock Enable Hold Time Propagation Delays (ns) Fanouta 1 1.3 3.1 0.0 0.7 0.6 2.3 0.0 2 1.6 3.1 0.0 1.0 0.9 2.3 0.0 3 1.8 3.1 0.0 1.2 1.1 2.3 0.0 4 2.1 3.1 0.0 1.5 1.4 2.3 0.0 8 3.1 3.1 0.0 2.5 2.4 2.3 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
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QL5064 QuickPCI Data Sheet Rev. G
Table 10: I/O Cell Output Delays
Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter 30 Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [a] Output Delay Low to Tri-State [a ] 2.1 2.2 1.2 1.6 2.0 1.2 Propagation Delays (ns) Output Load Capacitance (pF) 50 2.5 2.6 1.7 2.0 75 3.1 3.2 2.2 2.6 100 3.6 3.7 2.8 3.1 150 4.7 4.8 3.9 4.2
a. Loads are used for tPXZ.
The loads presented in Figure 13 are used for tPXZ. Figure 13: Loads used for tPXZ
tPHZ 1K 5 pF 1K tPLZ 5 pF
Table 11: PCI DC Specifications for 3.3 V Signaling
Symbol Vcc Vcc Vih Vil Vipu Iil Voh Vol Cin Cclk CIDSEL Lpin Ioff Parameter Supply Voltage Supply Voltage (for 75MHz only) Input High Voltage Input Low Voltage Input Pull-up Voltage Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance PME# Input Leakage Vo3.6VVcc off or floating 5 024 * www.quicklogic.com *
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QL5064 QuickPCI Data Sheet Rev. G
Table 12: PCI DC Specifications for 5 V Signaling
Symbol Vcc Vih Vil Iih Iil Voh Vol Cin Cclk CIDSEL Lpin Ioff Parameter Supply Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance PME# input leakage Vo5.25VVcc off or floating 5 Vin=2.7 Vin=0.5 Iout=-2mA Iout=3mA, 6mA 2.4 0.55 10 12 8 20 1 Condition Min. 4.75 2.0 -0.5 Max. 5.25 Vcc+0.5 0.8 70 -70 Units V V V mA mA V V pF pF PF nH mA
Table 13: PCI Timing Parameters
Symbol Tval Ton Toff Tsu Th Trst Trst-clk Trst-off trrsu trrh Trhfa Trhff Parameter CLK to Signal Valid Delay -bused signals Float to Active Delay Active to Float Delay Input Setup Time to CLK - bused signals Input Hold Time from CLK Reset Active Time after power stable Reset Active Time after CLK stable Reset Active to output float delay REQ64# to RST# setup time RST# to REQ64# hold time RST# high to first Configuration access RST# high to first FRAME# assertion 75 MHz Min. 2 2 2 2.67 4.45 0 1 100 10Tcyc 0 225 5 Max. 5.34 5.34 12.45 40 50 66 MHz Min. 2 2 2 3 5 0 1 100 10Tcyc 0 225 5 Max. 6 6 14 40 50 33 MHz Min. 2 2 2 7 10, 12 0 1 100 10Tcyc 0 225 5 Max. 11 12 28 40 50 Units ns ns ns ns ns ns ns ms ms ns ns ns clocks clocks
Tval (ptp) CLK to Signal Valid Delay - point to point signals
Tsu(ptp) Input Setup Time to CLK - point to point signals
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QL5064 QuickPCI Data Sheet Rev. G
Timing Diagrams
Figure 14: FPGA to PCI Core Signal Timing
user_clk user_stop addr_select dataIN_bytesel[2:0] dataIN_src_sel[1:0] dataIN_cs cntl_data_out[63:0] cntl_wrt_nrd cntl_addr[7:3] cntl_be[7:0] cntl_cs data_out_byte_sel[2:0] data_outCS data_outDES[1:0] data_outBE[7:0] data_out[63:0] interrupt_i
T su_I
T hd_I T su_I T hd_I
For Signals: data_out[*], data_outBE[*], dataIN_bytesel[*], cntl_data_out[*], cntl_be[*], addr_select, user_stop, interrupt_i Symbol Parameter Best T su_l T hd_l 1.425 0.5 33A/66A Nominal Worst 1.890
--
Best 1.425 0.5
33B/66B Nominal Worst 1.828
--
Best 1.425 0.5
75C Nominal Worst 1.673
--
Unit
2.850
--
2.726
--
2.416
--
ns ns
For Signals: data_outCS, data_outDES[*], data_out_byte_sel[*], dataIN_src_sel[*], dataIN_cs, cntl_wrt_nrd, cntl_addr[*], cntl_cs Symbol Parameter Best T su_l T hd_l 2.015 0.5 33A/66A Nominal Worst 2.672
--
Best 2.015 0.5
33B/66B Nominal Worst 2.584
--
Best 2.015 0.5
75C Nominal Worst 2.365
--
Unit
4.030
--
3.854
--
3.416
--
ns ns
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QL5064 QuickPCI Data Sheet Rev. G
Figure 15: PCI Clock Signal AC Parameters
T cyc_pci
T pci_clk
high_pci
T
low_pci
Symbol T cyc_pci T high_pci T low_pci
Parameter pci_clk cycle time pci_clk high time pci_clk low time pci_clk slew rate 1
33A/66A Min. Max. 30/15 11 11 1 -- -- -- 4
33B/66B Min. Max. 30/15 6 6 1.5 -- -- -- 4
75C Min. 13.33 5.3 5.3 1.5 Max. -- -- -- 4
Unit ns ns ns V/ns
1 0.2 V cc to 0.6 V cc
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QL5064 QuickPCI Data Sheet Rev. G
Figure 16: PCI Core to FPGA Signal Timing
T cyc_user
user_clk at core interface user_region[2:0] user_be_req[7:0] user_rdwr user_addr_valid user_req user_mult user_addr_output[32:0] dataIN[63:0] dataIN_BE[7:0] dataIN_byteID[1:0] rcv0_fifo_ef rcv0_fifo_prog_empty_flag rcv1_fifo_ef rcv1_fifo_prog_empty_flag xmt0_fifo_ff xmt0_fifo_prog_full_flag xmt1_fifo_ff xmt1_fifo_prog_full_flag spci_done cntl_data_in[63:0] interrupt_o
T co
Symbol
T T
Parameter
user_clk cycle time
33A/66A Best Nominal Worst 10 3.071
-- --
Best 10 3.071
33B/66B Nominal Worst
-- --
Best 10 3.071
75C Nominal Worst
-- --
Unit ns ns
cyc_user co
4.072
6.141
3.939
5.874
3.605
5.207
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QL5064 QuickPCI Data Sheet Rev. G
Figure 17: PCI Signal Timing Specifications
pci_clk Output
V test T val T inval
Valid
T on T off
Input
T su
Valid
Th
Note: V test --1.5V for 5-V signals; 0.4 V cc for 3.3-V signals
Symbol T val T val(ptp) T on T off T su T su(ptp) Th
Parameter pci_clk to signal valid delay--bussed signals pci_clk to signal valid delay--point-to-point Reset float to active delay Reset active to float delay Input setup time to pci_clk--bussed signals Input setup time to pci_clk--point-to-point Input signal hold time from pci_clk
33A/66A Min. Max. 2 2 2 -- 7 11 12 -- 28 --
33B/66B Min. Max. 2 2 2 -- 3 6 6 -- 14 --
Min. 2 2 2 -- 2.66
75C Max. 5.33 5.33 -- 12 --
Unit ns ns ns ns ns
10
--
5
--
4.44
--
ns
0
--
0
--
0
--
ns
Note:
All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized to s_clk.
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QL5064 QuickPCI Data Sheet Rev. G
Figure 18: PCI Clock Related Interface Timing
T
pci_clk
valclk
pci_clk_2fpga
T su T hold T su T hold
fpga_loc_sel
VALID
T valdata
xxxxx
VALID
T valdata
xxxxx
fpga_bus_req
Symbol
Parameter
33A/66A Best Nominal Worst 2.040 1.831 0 3.946 2.705 2.404 -- 5.232 4.080 3.625 -- 7.891
Best 2.040 1.813 0 3.946
33B/66B Nominal Worst 2.617 2.325 -- 5.061 3.903 3.467 -- 7.548
Best 2.040 1.813 0 3.946
75C Nominal Worst 2.395 2.128 -- 4.632 3.459 3.073 -- 6.691
Unit
T valclk T su T hold T valdata
ns ns ns ns
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QL5064 QuickPCI Data Sheet Rev. G
Figure 19: PCI Reset Signal AC Parameter
T
su_r T hold_r
REQ64#
VALID
T
cyc_pci
pci_clk RST#
T
rst_min
T
cyc_user
user_clk
Symbol T cyc_user T cyc_pci T su_r T hold_r T rst_min
1 1
Parameter user_clk cycle time pci_clk cycle time
33A/66A Min. Max. 10 30/15 300 0 -- -- -- --
33B/66B Min. Max. 10 30/15 150 0 -- -- -- --
75C Min. 10 13.33 133 0 Max. -- -- -- --
Unit ns ns ns ns clk periods
4 pci_clk followed by 4 user_clk
User_clk must be running for proper reset function to complete.
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QL5064 QuickPCI Data Sheet Rev. G
Figure 20: User Clock Signal AC Parameter
T cyc_user
T user_clk
high_user
T
low_user
Symbol T cyc_user T high_user T low_user
Parameter user_clk cycle time user_clk high time user_clk low time
33A/66A Min. Max. 10 2 2 -- -- --
33B/66B Min. Max. 10 2 2 -- -- --
75C Min. 10 2 2 Max. -- -- --
Unit ns ns ns
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QL5064 QuickPCI Data Sheet Rev. G
DC Characteristics
The DC Specifications are provided in the Table 14 through Table 16. Table 14: Absolute Maximum Ratings
Parameter VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity Value -0.5 to 4.6V -0.5 to 7.0V -0.5V to VCCIO +0.5V 200 mA Parameter DC Input Current ESD Pad Protection Storage Temperature Max Lead Temperature Value 20 mA 2000V -65C to +150C 300C
Table 15: Operating Range
Symbol VCC VCCIO TA TJ Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Junction Temperature -33A Speed Grade -33B Speed Grade K Delay Factor -66A Speed Grade -66B Speed Grade -75C Speed Grade a. At VCC minimum of 3.15 V.
a
Parameter
Military Min. 3.15 3.15 -55 125 0.42 0.42 0.42 0.42 NA 1.04 0.92 1.04 0.92 NA Max. 3.6 5.5
Industrial Min. 3.0 3.0 -40 0.43 0.43 0.43 0.43 0.43 Max. 3.6 5.5 85 1.02 0.90 1.02 0.90 0.81
Commercial Min. 3.0 3.0 0 0.46 0.46 0.46 0.46 0.46 Max. 3.6 5.25 70 0.99 0.88 0.99 0.88 0.79
Unit V V C
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QL5064 QuickPCI Data Sheet Rev. G
Table 16: DC Input and Output Levels
Symbol VIH VIL VOH VOL II IOZ CI IOS ICC ICCIO Idd Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [ ] Output Short Circuit Current [b] Quiescent Current [ ] Quiescent Current on VCCIO Static Idd Current See Figure 21
c a
Conditions
Min. 0.5 VCC -0.5
Max. VCCIO+0.5 0.3VCC
Unit V V V V
IOH = -12 mA IOH = -500 mA IOL = 16 mA IOL = 1.5 mA VI = VCCIO or GND VI = VCCIO or GND VO = GND VO = VCC VI, VIO = VCCIO or GND
2.4 0.9VCC 0.45 0.1VCC -10 -10 -15 40 0.50 (typ.) 0 10 10 10 -180 210 4 100
V V mA mA pF mA mA mA mA
a. Capacitance is sample tested only. b. Only one output at a time. Duration should not exceed 30 seconds. c. For commercial grade devices only. Maximum ICC is 5 mA for all industrial grade devices. For AC conditions, contact QuickLogic Customer Engineering.
Figure 21: Static Idd of the QL5064
3.0 2.5
S ta tic Idd o f the Q L 5 0 6 4
Static Idd (mA)
2.0 1.5
1.0
0.5
0.0 -5 5 0 25 70 85 125
T e m p (C )
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QL5064 QuickPCI Data Sheet Rev. G
Power-up Sequencing
Figure 22: Power-up Sequencing
VCCIO
Voltage
VCC (VCCIO -VCC)MAX VCC
400 us
Time
When powering up a device, the VCC/VCCIO rails must take 400 s or longer to reach the maximum value (refer to Figure 22). NOTE: Ramping VCC/VCCIO to the maximum voltage faster than 400 s can cause the device to behave improperly. For users with a limited power budget, keep (VCCIO -VCC)MAX 500 mV when ramping up the power supply.
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35
QL5064 QuickPCI Data Sheet Rev. G
QL5064 Pin Type Descriptions
The QL5064 device pins are indicated in the Table 17. These are pins on the device, some of which connect to the PCI bus, and others that are programmable as user I/O. Table 17: Pin Type Descriptions
Type IN OUT T/S S/T/S O/D Input. A standard input-only signal. Totem Pole Output. A standard active output driver. Tri-state. A bi-directional, tri-state input/output pin. Sustained Tri-State. An active low tri-state signal driven by one PCI agent at a time. It must be driven high for at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the PCI system central resource to sustain the inactive state once the active driver has released the signal. Open Drain. Allows multiple devices to share this pin as a wired-or. Description
Table 18: Pin / Bus Names and Functions
Pin/Bus Name VCC VCCIO GND T/GND I/O I/GCLK I/ACLK TDI TDO TCL TMS TRSTB STM FLOAT Type IN IN IN IN T/S IN IN IN OUT IN IN IN IN OUT Supply Pin. Tie to 3.3 V supply. Supply Pin for I/O. Set to 3.3 V for 3.3 V I/O, 5 V for 5.0 V compliant I/O. Ground Pin. Tie to GND on the PCB. Thermal Ground. Used to dissipate heat from the device. Tie to GND on the PCB. Programmable Input/Output/Tri-State/Bi-directional Pin. Programmable Input-Only or Global Clock Pin. Tie to VCC or GND if unused. Programmable Input-Only or Array Clock Pin. Tie to VCC or GND if unused. JTAG Data In. Tie to VCC if unused. JTAG Data Out. Leave unconnected if unused. JTAG Clock. Tie to GND if unused. JTAG Test Mode Select. Tie to VCC if unused. JTAG Reset. Tie to GND if unused. QuickLogic Reserved Pin. Tie to GND on the PCB. Test Data Out Pin for QuickLogic Use Only. Must be isolated and floating at all times Function
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QL5064 QuickPCI Data Sheet Rev. G
QL5064 External Device Pins
Table 19: QL5064 External Device Pins
Pin/Bus Name AD[63:0] CBEN[7:0] Type T/S T/S Function PCI Address and Data. 32-bit multiplexed address/data bus. PCI Bus Command and Byte Enables. Multiplexed bus which contains byte enables for AD[31:0] or the Bus Command during the address phase of a PCI transaction. PCI Parity. Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven one clock after address or data phases. Master drives PAR on address cycles and PCI writes. The Target drives PAR on PCI reads. PCI Parity Upper DWORD. Even Parity across AD[63:32] and C/BEN[7:4] busses. PCI Cycle Frame. Driven active by current PCI Master during a PCI transaction. Driven low to indicate the address cycle, driven high at the end of the transaction. PCI Request 64-bit transfer. Driven by the PCI Master to request a 64-bit transfer. Same signal timing as FRAMEN. PCI Device Select. Driven by a Target that has decoded a valid base address. PCI Acknowledge 64-bit Transfer. Driven by a Target which has decoded a valid base address for a 64-bit data transfer. Same timing as DEVSELN. PCI System Clock Input. PCI System Reset Input. PCI Request. Indicates to the Arbiter that this PCI Agent (Initiator) wishes to use the bus. A point to point signal between the PCI Device and the System Arbiter. PCI Grant. Indicates to a PCI Agent (Initiator) that it has been granted access to the PCI bus by the Arbiter. A point to point signal between the PCI device and the System Arbiter. PCI Data Parity Error. Driven active by the initiator or target two clock cycles after a data parity error is detected on the AD and C/BEN busses. PCI System Error. Driven active when an address cycle parity error, data parity error during a special cycle, or other catastrophic error is detected. PCI Initialization Device Select. Use to select a specific PCI Agent during System Initialization. PCI Initiator Ready. Indicates the Initiator's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. PCI Target Ready. Indicates the Target's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. PCI Stop. Used by a PCI Target to end a burst transaction. Interrupt A. Asynchronous Active-Low Interrupt Request.
PAR PAR64 FRAMEN REQ64N DEVSELN ACK64N CLK RSTN REQN
T/S T/S S/T/S S/T/S S/T/S S/T/S IN IN T/S
GNTN
IN
PERRN SERRN IDSEL
S/T/S O/D IN
IRDYN
S/T/S
TRDYN STOPN INTAN
S/T/S S/T/S O/D
NOTE: Signal names that end in the character `N" are active-low (for example, Mst_IRDYN).
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37
QL5064 QuickPCI Data Sheet Rev. G
456 Pin PBGA Pinout Diagram
TOP View TOP View
QuickPCI QuickPCI QL5064-66-BPB456C QL5064-66BPB456C
BOTTOM View BOTTOM View
22 25 24 23 22 2117 16 18 17 16 1512 11 12 1191089 8 6 6 54 4 33 2 1 7 75 26 21 20 19 18 20 19 15 14 13 14 13 10 21
AA BB C C D ED FE GF HG J H K LJ MK NL PM R N T P U VR WT YU AA V AB W AC Y AD AA AE AF AB
PIN A1 PIN A1 CORNER CORNER
Figure 23: 456 Pin PBGA Pinout Diagram
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QL5064 QuickPCI Data Sheet Rev. G
456 Pin PBGA Pinout Table
Table 20: 456 PBGA Pinout Table
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 Function NC NC AD[29] REQN GNTN AD[22] AD[28] RSTN FLOAT NC NC VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC AD[31] AD[30] AD[20] AD[26] INTAN FLOAT NC VCC T/GND T/GND T/GND T/GND T/GND T/GND GND I/O I/O I/O I/O Pin B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 Function NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O STM CBEN[3] AD[25] NC TDO AD[27] AD[18] AD[24] NC VCCIO NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GCLK/I (USER CLK) AD[3] AD[1] CBEN[7] CBEN[5] VCC T/GND T/GND T/GND Pin C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Function I/O I/O I/O I/O TCK I/O AD[21] AD[23] NC GND AD[16] NC IDSEL NC GND FLOAT NC GND I/O I/O GND I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O AD[17] AD[19] NC NC AD[61] AD[59] AD[58] AD[56] NC I/O I/O I/O I/O I/O AD[57] AD[55] Pin E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Function GND VCC GND NC GND NC GND GND VCC GND GND GND I/O GND I/O GND VCC GND I/O I/O I/O I/O DEVSELN CBEN[2] PAR NC VCC VCC I/O I/O I/O I/O SERRN PERRN AD[15] NC GND I/O I/O GND VCC I/O I/O VCC GND I/O VCC GND Pin G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 Function NC GND I/O I/O I/O I/O AD[14] CBEN[1] AD[13] NC NC I/O I/O I/O I/O I/O AD[10] AD[12] AD[11] NC GND I/O I/O I/O I/O I/O FRAMEN NC AD[9] NC VCC GND I/O I/O I/O I/O I/O I/O NC NC AD[45] AD[46] AD[44] AD[38] NC FLOAT NC NC Pin L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 Function STOPN TRDYN IRDYN CBEN[0] NC T/GND T/GND T/GND T/GND T/GND T/GND I/O I/O I/O I/O I/O AD[6] GCLK ACK64N NC GND T/GND T/GND T/GND T/GND T/GND T/GND I/O I/O I/O I/O I/O GCLK NC PCI CLK GCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS
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QL5064 QuickPCI Data Sheet Rev. G
Table 20: 456 PBGA Pinout Table (Continued)
Pin P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 Function AD[4] AD[8] AD[2] AD[0] NC T/GND T/GND T/GND T/GND T/GND T/GND I/O GCLK/I ACLK/I I/O ACLK/I AD[7] AD[5] REQ64N NC NC T/GND T/GND T/GND T/GND T/GND T/GND VCC Pin T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 Function T/GND T/GND T/GND GND I/O I/O I/O I/O NC CBEN[6] PAR64 AD[62] GND I/O I/O I/O I/O I/O CBEN[4] AD[63] AD[60] NC NC GND I/O I/O I/O I/O Pin Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 Function AD[54] AD[52] NC GND I/O I/O I/O I/O AD[53] AD[51] AD[50] NC VCC VCC NC I/O I/O I/O AD[49] AD[47] NC NC GND VCC NC NC NC VCC Pin AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 Function I/O I/O I/O I/O NC NC NC GND AD[48] NC NC VCCIO NC NC I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O Pin AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O I/O NC TDI AD[41] AD[37] AD[42] AD[40] AD[36] NC FLOAT NC NC I/O I/O Pin AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Function NC I/O AD[43] AD[39] AD[35] AD[33] AD[32] AD[34] FLOAT NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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QL5064 QuickPCI Data Sheet Rev. G
484 Pin PBGA Pinout Diagram
TOP View TOP View
QuickPCI QuickPCI QL5064-66-BPB456C QL5064-66BPS484C
BOTTOM View BOTTOM View
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U V V W W Y Y AA AA AB AB
PIN A1 PIN A1 CORNER CORNER
Figure 24: 484 Pin PBGA Pinout Diagram
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41
QL5064 QuickPCI Data Sheet Rev. G
484 Pin PBGA Pinout Table
Table 21: 484 PBGA Pinout Table
Pin A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 Function NC NC AD[29] AD[27] AD[30] IDSEL AD[26] FLOAT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC TDO AD[16] REQN AD[18] AD[22] RSTN VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 Function I/O TCK NC NC AD[21] NC NC NC AD[31] GNTN NC VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CBEN[2] PAR AD[19] CBEN[3] NC NC AD[24] NC FLOAT NC I/O I/O NC I/O Pin D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Function I/O I/O NC NC STM I/O I/O I/O PERRN AD[15] AD[25] AD[23] NC VCC AD[20] AD[28] FLOAT I/O VCC I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O DEVSELN NC AD[17] NC NC GND VCC GND GND GND Pin F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 Function I/O I/O GND I/O GND VCC I/O I/O I/O I/O I/O I/O CBEN[1] AD[13] NC SERRN GND VCC GND INTAN GND I/O GND NC I/O GND GND GND I/O I/O I/O I/O I/O I/O AD[12] NC AD[11] NC VCC AD[14] Pin H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 Function VCC GND VCC VCC I/O GND NC VCC GND I/O I/O I/O NC I/O I/O I/O AD[9] CBEN[0] NC AD[10] GND GND GND VCC GND GND GND GND GND GND VCC GND I/O I/O NC I/O I/O I/O TRDYN NC Pin K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 Function FRAMEN STOPN IRDYN VCC VCC GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O AD[6] GCLK GCLK NC GCLK ACK64N GND VCC GND GND GND GND GND GND VCC GND I/O I/O I/O I/O
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QL5064 QuickPCI Data Sheet Rev. G
Table 21: 484 PBGA Pinout Table (Continued)
Pin L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 Function I/O I/O AD[4] NC AD[2] AD[0] PCI CLK GND GND VCC GND GND GND GND GND GND VCC GND ACLK/I ACLK/I NC GCLK/I (USER CLK) GCLK/I I/O AD[8] NC AD[7] AD[5] VCC REQ64N VCC GND GND GND GND GND GND GND GND I/O I/O Pin N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 Function I/O NC I/O I/O I/O AD[1] AD[3] NC CBEN[6] GND VCC GND GND GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O CBEN[7] NC CBEN[5] NC AD[63] PAR64 NC GND VCC I/O NC GND I/O VCC Pin R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 Function GND VCC VCC I/O I/O I/O I/O I/O CBEN[4] AD[60] NC AD[59] GND AD[62] GND GND GND I/O GND I/O I/O I/O I/O GND I/O I/O NC I/O I/O I/O AD[61] AD[58] AD[53] NC AD[57] GND VCC VCC I/O I/O I/O Pin U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 Function I/O I/O I/O GND I/O GND VCC I/O I/O I/O I/O AD[55] AD[56] NC AD[47] VCC AD[40] AD[36] FLOAT I/O I/O VCCIO I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O AD[54] AD[51] AD[50] NC NC AD[44] NC NC Pin W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 Function I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O AD[52] AD[49] NC NC AD[41] AD[37] AD[38] AD[34] FLOAT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O NC NC AD[45] AD[39] AD[35] Pin AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Function AD[48] NC NC FLOAT I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O NC NC NC NC TDI AD[43] AD[46] AD[42] AD[33] AD[32] VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB I/O NC NC
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QL5064 QuickPCI Data Sheet Rev. G
Ordering Information
QL 5064 - 66B PB456 C QuickLogic device Operating Range C = Commercial I = Industrial M = Military Package Code PB456 = 456-pin PBGA PS484 = 484-pin PBGA
QuickPCI device part number Speed Grade 33A = Quick 33B = Fast 66A = Faster 66B = Super Fast 75C = Fastest
Contact Information
Telephone: (408) 990 4000 (US) (416) 497 8884 (Canada) +(44) 1932 57 9011 (Rest of Europe) +(49) 89 930 86 170 (Germany & Benelux) +(8621) 6867 0273 (Asia) +(81) 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com http://www.quicklogic.com/support http://www.quicklogic.com/
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(c) 2003 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. G
Revision History
Revision A B C D E F G Date Sept 1999 March 2001 Dec 2001 Jan 2002 August 2003 November 2003 November 2003 Comments First release. Updated electrical specs. Re-formatted and re-organized for better clarity. Updated 484 pin table & added ordering info. Updated Delay Factor information in Operating Range table. Jason Lew and Kathleen Murchek Updated 484 pinout table. Bernhard Andretzky and Kathleen Murchek Updated format and edited document.
Copyright and Trademark Information
Copyright (c) 2003 QuickLogic Corporation. All Rights Reserved. The information contained in this document and the accompanying software programs is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, QuickRAM, QuickPCI and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, EclipsePlus, Eclipse II, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation. Verilog is a registered trademark of Cadence Design Systems, Inc.
(c) 2003 QuickLogic Corporation
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