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| DATA SHEET MOS INTEGRATED CIRCUIT ELECTRON DEVICE PD75238 4 BIT SINGLE-CHIP MICROCOMPUTER The PD75238 is a single-chip microcomputer which contains a CPU capable of 1-, 4-, and 8-bit data processing, ROM, RAM, and I/O ports. In addition, it contains a fluorescent display tube (FIP;) controller/driver, A/D converter, clock timer, timer/pulse generator capable of 14-bit PWM output, serial interface, and vectored interrupt function. In comparison with the PD75217, the PD75238 has larger ROM and RAM capacity and has been enhanced in such peripheral facilities as the display function of the FIP controller/driver, I/O ports, A/D converter, serial interface. The PD75238 finds best use in such applications as timer/tuner of VCRs from advanced type to common type, configuration of one-chip system control microcomputer, advanced CD player, advanced microwave ovens, etc. With the PD75238, the PD75P238, which is a PROM product, and various development tools including IE-75001-R and assemblers are available. They can be used for evaluation during system development and small-volume production. FEATURES * Mass-storage built-in ROM and RAM * Program memory (ROM) : 32K x 8 * Data memory (RAM) to FIP) : 1K x 4 * I/O port: 64 lines (excluding pins dedicated * Minimum instruction execution time: 0.67 s (at 6.0 MHz) * * * * * 8-bit A/D converter: 8 channels Enhanced timer/counter function: 5 channels 8-bit serial interface: 2 channels Application-oriented interrupt functions PROM version device: PD75P238 * Instruction execution time specification function to allow a wide range of operating voltages * Programmable FIP controller/driver contained * Number of segments : 9 to 24 segments * Number of digits : 9 to 16 digits ORDERING INFORMATION Part number Package 94-pin plastic QFP (20 x 20 mm) Quality grade Standard PD75238GJ-xxx-5BG Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. (O.D. No. Date Published Printed in Japan IC-2777A IC-8177A) February 1993 P Major changes in this revision are indicated by stars (5) in the margins. (c) NEC Corporation 1992 PD75238 FUNCTIONS Item On-chip memory I/O lines (Excluding pins dedicated to FIP) Function ROM: 32640 x 8 bits, RAM: 1024 x 4 bits * 64 lines * * * * * * * * * * Input : 16 lines I/O : 24 lines Output : 24 lines Instruction cycle 0.67 s/1.33 s/2.67 s/10.7 s (at 6.0 MHz) 0.95 s/1.91 s/3.82 s/15.3 s (at 4.19 MHz) 122 s (at 32.768 kHz) Number of segments : 9 to 24 segments Number of digits : 9 to 16 digits Dimmer function : 8 levels Pull-down resistors provided by mask option Key scan interrupt generator * Basic interval timer : Usable as watchdog timer Fluorescent display tube (FIP) controller/driver Timer/counter 5 channels * * * * * * Timer/event counter Clock timer : With buzzer output function Timer/pulse generator : With 14-bit PWM output function Event counter SBI or 3-wire mode 3-wire mode Serial interface 2 channels Interrupt * * * * * System clock oscillator Allows multiple hardware interrupts. * Detection of both edges External interrupts : 3 * Detection edge programmable (with noise elimination) * Detection edge programmable External test input : 1 * Rising edge detection * Timer/pulse generator * Timer/event counter Internal interrupts : 5 * Basic interval timer * Serial interface #0 * For key scanning Internal test inputs: 2 * Clock timer * Serial interface #1 Main system clock : 6.0 MHz, 4.19 MHz Subsystem clock : 32.768 kHz, standard High-voltage port : Pull-down resistor or open-drain output Ports 4 and 5 : Pull-up resistor Port 7 : Pull-down resistor * * * * * Mask option Operating temperature Operating voltage Package -40 to +85 C 2.7 to 6.0 V (Data held in standby mode: 2.0 to 6.0 V) 94-pin plastic QFP (20 x 20 mm) 2 PD75238 PIN CONFIGURATION AN0 AVREF AVDD VDD VDD X2 X1 IC XT2 XT1 VSS S16/P100 S17/P101 S18/P102 S19/P103 S20/P110 S21/P111 S22/P112 S23/P113 S0/P120 S1/P121 S2/P122 S3/P123 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 1 70 2 69 3 68 4 67 66 5 65 6 64 7 63 8 62 9 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 AN1 AN2 AN3 AN4/P90 AN5/P91 AN6/P92 AN7/P93 AVSS RESET P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30 P31 P32 P33 P40 P41 P42 P43 VSS P50 P51 P52 P53 P60 P61 P62 P63 P70 P71 P72 P73 P80/PPO P81/SCK1 P82/SO1 P83/SI1 VDD Caution Be sure to supply power to the AVDD, VDD, VSS, and AVSS pins (pins 3, 4, 5, 11, 30, 48, 65, and 87). Remark IC: Internally connected pin (to be grounded) S4/P130 S5/P131 S6/P132 S7/P133 S8/P140 S9/P141 VDD VLOAD T15/S10/P142 T14/S11/P143 PH0/T13/S12/P150 PH1/T12/S13/P151 PH2/T11/S14/P152 PH3/T10/S15/P153 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 PD75238GJ-xxx-5BG 3 4 TI0 TI0/P13 PTO0/P20 BUZ/P23 PPO/P80 SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 SI1/P83 SO1/P82 SCK1/P81 INT0/P10 INT1/P11 INT2/P12 INT4/P00 TI0 AN0-AN3 AN4/P90-AN7/P93 AVDD AVREF AVSS 8 BLOCK DIAGRAM Basic interval timer INTBT Timer/event counter #0 INTT0 Watch timer Bank Program counter (15) CY ALU SBS (2) SP (8) Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 ROM program memory 32640 x 8 Port 8 Decode and control RAM data memory 1024 x 4 Port 9 4 4 4 4 4 4 4 4 4 4 10 P00-P03 P10-P13 P20-P23 P30-P33 P40-P43Note P50-P53Note P60-P63 P70-P73 P80-P83 P90-P93 T0-T9 INTW Timer/pulse generator INTTPG Serial interface 0 INTCSI0 General register 4 Serial interface 1 FIP controller/ driver fX/2 Interrupt control Clock output control N T10/S15/PH3/P153T13/S12/PH0/P150 T14/S11/P143 and T15/S10/P142 S0/P120-S9/P141 S16/P100-S23/P113 VLOAD 2 10 8 Clock divider Clock generator Sub Main Stand by control CPU clock Port 10-15 24 P100-P153 Event counter PCL/P22 XT1XT2 X1 X2 RESET VDD VSS VDD A/D converter PD75238 Bit sequential buffer (16) Note Port 4 and port 5 are N-ch open-drain I/O ports with a medium withstand voltage of 10 V. PD75238 CONTENTS 1. PIN FUNCTIONS ........................................................................................................................ 1.1 1.2 1.3 1.4 PORT PINS ...................................................................................................................................... NON-PORT PINS ............................................................................................................................ PIN INPUT/OUTPUT CIRCUITS .................................................................................................... CONNECTION OF UNUSED PD75238 PINS .............................................................................. 7 7 9 11 15 2. ARCHITECTURE AND MEMORY MAP OF THE PD75238 ................................................... 2.1 2.2 2.3 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ................................ GENERAL REGISTER BANK CONFIGURATION .......................................................................... MEMORY-MAPPED I/O ................................................................................................................. 16 16 19 22 3. INTERNAL CPU FUNCTIONS .................................................................................................... 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 PROGRAM COUNTER (PC) ........................................................................................................... PROGRAM MEMORY (ROM) ........................................................................................................ DATA MEMORY (RAM) ................................................................................................................. GENERAL REGISTERS ................................................................................................................... ACCUMULATORS .......................................................................................................................... STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ..................................... PROGRAM STATUS WORD (PSW) .............................................................................................. BANK SELECT REGISTER (BS) ..................................................................................................... 27 27 27 29 31 32 32 35 39 4. PERIPHERAL HARDWARE FUNCTIONS .................................................................................. 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 DIGITAL I/O PORTS ....................................................................................................................... CLOCK GENERATOR ...................................................................................................................... CLOCK OUTPUT CIRCUIT ............................................................................................................. BASIC INTERVAL TIMER ............................................................................................................... TIMER/EVENT COUNTER ............................................................................................................. CLOCK TIMER ................................................................................................................................. TIMER/PULSE GENERATOR ......................................................................................................... EVENT COUNTER .......................................................................................................................... SERIAL INTERFACE ....................................................................................................................... A/D CONVERTER ........................................................................................................................... BIT SEQUENTIAL BUFFER ............................................................................................................ FIP CONTROLLER/DRIVER ............................................................................................................ 40 40 49 58 61 63 69 71 77 79 113 119 119 5. INTERRUPT FUNCTION ............................................................................................................ 131 5.1 5.2 5.3 5.4 5.5 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT .................................................... HARDWARE OF THE INTERRUPT CONTROL CIRCUIT .............................................................. MULTIPLE INTERRUPT PROCESSING CONTROL ...................................................................... VECTOR ADDRESS SHARE INTERRUPT PROCESSING ............................................................ 131 133 139 141 INTERRUPT SEQUENCE ................................................................................................................ 138 5 PD75238 6. STANDBY FUNCTION ............................................................................................................... 142 6.1 6.2 6.3 SETTING OF STANDBY MODES AND OPERATION STATUSES ............................................. OPERATION AFTER A STANDBY MODE IS RELEASED ............................................................ 142 146 RELEASE OF THE STANDBY MODES ......................................................................................... 144 7. 8. RESET FUNCTION ..................................................................................................................... 147 INSTRUCTION SET .................................................................................................................... 150 8.1 8.2 8.3 PD75238 INSTRUCTIONS ............................................................................................................ 150 INSTRUCTION SET AND ITS OPERATION .................................................................................. 153 INSTRUCTION CODES OF EACH INSTRUCTION ....................................................................... 162 9. SPECIFICATION OF MASK OPTIONS ...................................................................................... 168 10. APPLICATION BLOCK DIAGRAM ............................................................................................. 169 11. ELECTRICAL CHARACTERISTICS ............................................................................................. 170 5 12. CHARACTERISTIC CURVES (FOR REFERENCE) ..................................................................... 181 13. PACKAGE DIMENSIONS ........................................................................................................... 183 14. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 184 APPENDIX A APPENDIX B PD75238 SERIES PRODUCT FUNCTION LIST .................................................. 185 DEVELOPMENT TOOLS ......................................................................................... 186 6 PD75238 1. PIN FUNCTIONS 1.1 PORT PINS (1/2) I/ONote 1 circuit type Pin name I/O Also used as INT4 SCK0 SO0/SB0 SI0/SB1 Function 8-bit I/O x When reset P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30Note 2 P31Note 2 P32Note 2 P33Note 2 P40-P43Note 2 I 4-bit input port (port 0). For P01 to P03, pull-up resistors can be provided by software in units of 3 bits. Input B F-A F-B M-C I INT0 INT1 INT2 TI0 With noise elimination function 4-bit input port (port 1). Pull-up resistors can be provided by software in units of 4 bits. 4-bit I/O port (port 2). Pull-up resistors can be provided by software in units of 4 bits. x Input B-C I/O PTO0 - PCL BUZ x Input E-B I/O - - - - Programmable 4-bit I/O port (port 3). Input/output can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. x Input E-C I/O - N-ch open-drain 4-bit I/O port (port 4). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 10 V in open-drain mode. r High level (when a pull-up resistor is provided) or high impedance High level (when a pull-up resistor is provided) or high impedance M P50-P53Note 2 I/O - N-ch open-drain 4-bit I/O port (port 5). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 10 V in open-drain mode. M P60 P61 P62 P63 P70 P71 P72 P73 I/O - - - - Programmable 4-bit I/O port (port 6). Input/output can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. r Input E-C I/O - - - - 4-bit I/O port (port 7). A pull-down resistor can be provided bit by bit (mask option). VSS level (when a pull-down resistor is provided) or high impedance V Notes 1. The circuits enclosed in circles have a Schmitt-triggered input. 2. An LED can be driven directly. 7 PD75238 1.1 PORT PINS (2/2) I/ONote circuit type A Pin name P80 P81 P82 P83 P90 P91 P92 P93 P100 P101 P102 P103 P110 P111 P112 P113 P120 P121 P122 P123 P130 P131 P132 P133 P140 P141 P142 P143 P150 P151 P152 P153 PH0 PH1 PH2 PH3 I/O I/O I/O I/O I I Also used as PPO SCK1 SO1 SI1 AN4 AN5 AN6 AN7 Function 8-bit I/O x When reset 4-bit input port (port 8). Input F E B 4-bit input port (port 9) x Input Y-A O S16 S17 S18 S19 P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors can be provided (mask option). r VLOAD level I-F (when pulldown resistor to VLOAD is provided), VSS level (when pulldown resistor to VSS is pro- O S20 S21 S22 S23 P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors can be provided (mask option). vided), or highimpedance P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors can be provided (mask option). r VLOAD level (when pulldown resistor to VLOAD is provided) or highimpedance I-C O S0 S1 S2 S3 O S4 S5 S6 S7 P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors can be provided (mask option). O S8 S9 S10/T15 S11/T14 P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors can be provided (mask option). P142 and P143 can drive LED directly. r O S12/T13/PH0 P-ch open-drain, 4-bit high-voltage output port. S13/T12/PH1 Pull-down resistors can be provided (mask S14/T11/PH2 S15/T10/PH3 option). LED can be driven directly. x O S12/T13/P150 P-ch open-drain, 4-bit high-voltage output port. S13/T12/P151 Pull-down resistors can be provided (mask option). S14/T11/P152 S15/T10/P153 Note The circuits enclosed in circles have a Schmitt-triggered input. 8 PD75238 1.2 NON-PORT PINS (1/2) I/O circuit type I-C Pin name I/O Also used as Output pins for FIP controller/ PH3/P153driver. PH0/P150 Allows pulldown resistor to P143 be provided (mask P142 option). - P120-P123 P130-P133 P140 P141 P100-P103 Function When reset T0-T9 O High-voltage, large-current output for digit output High-voltage, large-current output usable for digit/segment output as well. Any unused pins can be used for port H. Usable for port 15 in static mode. High-voltage, large-current output usable for digit/segment output as well. Usable for port 14 in static mode. High-voltage output for segment output. Usable for port 12 to port 14 in static mode. T10/S15T13/S12 T14/S11 T15/S10 S0-S3 S4-S7 S8 S9 S16-S19 VLOAD level (when pull-down resistor to VLOAD is provided) or highimpedance High-voltage output for segment output. Usable for port 10 and port 11 in static mode. S20-S23 P110-P113 VLOAD level (when pull-down resistor to VLOAD is provided), VSS level (when pull-down resistor to VSS is provided), or highimpedance I-F 9 PD75238 1.2 NON-PORT PINS (2/2) I/ONote When reset circuit type - Pin name I/O Also used as P13 Function TI0 I External event pulse input for timer/event counter #0 and event counter #1. Timer/event counter output Clock output Fixed frequency output (for buzzer or system clock trimming) Serial clock I/O Serial data output or serial bus I/O Serial data input or serial bus I/O Edge detection vectored interrupt input (Either a rising or falling edge is detected.) Edge detection vectored interrupt input (The edge to be detected is selectable.) Edge detection testable input (An rising edge is detected.) Serial clock I/O Serial data output Serial data input Analog input to A/D converter Synchronous Asynchronous Asynchronous B-C E-B E-B E-B PTO0 PCL BUZ SCK0 SO0/SB0 SI0/SB1 INT4 O O O I/O I/O I/O I P20 P22 P23 P01 P02 P03 P00 Input Input Input Input Input Input - F-A F-B M-C B B-C INT0 INT1 INT2 I P10 P11 - I P12 - B-C F E SCK1 SO1 SI1 AN0-AN3 AN4-AN7 AVDD AVREF AVSS X1, X2 I/O O I I P81 P82 P83 - P90-P93 Input Input Input - B Y Y-A - I - I - - - - Power supply for A/D converter A/D converter reference voltage input A/D converter reference GND Connection to a crystal/ceramic resonator for main system clock generation. When external clock is used, it is input to X1, and its inverted signal is input to X2. Connection to a crystal resonator for subsystem clock generation. When external clock is used, it is input to XT1, and XT2 is left open. System reset input Timer/pulse generator pulse output Positive power supply GND potential Pull-down resistor connection for the FIP controller/driver, or power supply - - - - - Z - - XT1 XT2 RESET PPO VDD (3 pins) VSS (2 pins) VLOAD I - I O - - - - - - - P80 - - - - Input - - - B - - - - Note The circuits enclosed in circles have a Schmitt-triggered input. 10 PD75238 1.3 PIN INPUT/OUTPUT CIRCUITS (1/4) Type A VDD Type D VDD Data P-ch IN Output disable P-ch OUT N-ch N-ch CMOS input buffer Type B Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E Data Type D IN Output disable IN/OUT Type A Schmitt trigger input with hysteresis Type B - C I/O circuit consisting of a push-pull output of type D and an input buffer of type A Type E - B VDD VDD P.U.R. P.U.R. enable Data Type D Output disable IN Output disable P.U.R. P-ch P-ch IN/OUT Type A P.U.R.: Pull-Up Resistor Schmitt trigger input with hysteresis P.U.R.: Pull-Up Resistor 11 PD75238 1.3 PIN INPUT/OUTPUT CIRCUITS (2/4) Type E - C VDD P.U.R. P.U.R. enable Data Type D Output disable P-ch Type F - B VDD P.U.R. P.U.R. enable Output disable (P-ch) P-ch VDD P-ch IN/OUT IN/OUT Data Output disable Type A N-ch Output disable (N-ch) Type B P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor Type F Type F - C VDD P.U.R. P.U.R. enable Data Type D Output disable Output disable Data Type D P-ch IN/OUT IN/OUT Type B Type B I/O circuit consisting of a push-pull output of type D and a Schmitt-triggered input of type B Type F - A Type I - C P.U.R.: Pull-Up Resistor VDD P.U.R. P.U.R. enable Data Type D Output disable VDD P-ch VDD IN/OUT Data P-ch P-ch OUT N-ch Type B P.D.R. (Mask option) VLOAD P.U.R.: Pull-Up Resistor P.D.R.: Pull-Down Resistor 12 PD75238 1.3 PIN INPUT/OUTPUT CIRCUITS (3/4) Type I - F Type V VDD VDD Data Type D IN/OUT Data P-ch P-ch OUT Output disable N-ch P.D.R. (Mask option) VLOAD Type A P.D.R. (Mask option) P.D.R.: Pull-Down Resistor P.D.R.: Pull-Down Resistor Type M VDD P.U.R. (Mask option) Type Y AVDD IN/OUT P-ch IN + AVDD N-ch AVSS AVSS AVSS Reference voltage (from voltage tap of serial resistor string) Middle-voltage input buffer P.U.R.: Pull-Up Resistor Sampling C - Data Output disable N-ch Type M - C VDD P.U.R. P.U.R. enable P-ch IN IN/OUT Data Output disable N-ch Type Y - A AVDD P-ch + AVDD N-ch Sampling C AVSS AVSS AVSS Reference voltage (from voltage tap of serial resistor string) - Type B P.U.R.: Pull-Up Resistor 13 PD75238 1.3 PIN INPUT/OUTPUT CIRCUITS (4/4) Type Z AVSS 14 PD75238 1.4 CONNECTION OF UNUSED PD75238 PINS Pin name P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI1/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80/PPO P81/SCK1 P82/SO1 P83/SI1 P90/AN4-P93/AN7 P100/S16-P103/S19 P110/S20-P113/S23 P120-P123 P130-P133 P140-P143 P150-P153 AN0-AN3 AVREF AVDD AVSS XT1 XT2 VLOAD Recommended connection To be connected to VSS To be connected to VSS or VDD To be connected to VSS Input state : To be connected to VSS or VDD Output state : To be left open To be connected to VSS To be left open To be connected to VSS To be connected to VDD To be connected to VSS To be connected to VSS or VDD To be left open To be connected to VSS 15 PD75238 2. ARCHITECTURE AND MEMORY MAP OF THE PD75238 The PD75238 has three architectural features: (a) Data memory bank configuration (b) General register bank configuration (c) Memory-mapped I/O Each of these features is explained below. 2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES As shown in Fig. 2-1, the data memory space of the PD75238 contains a static RAM (928 words x 4 bits) at addresses 000H to 19FH and 200H to 3FFH, a display data memory (96 words x 4 bits) at addresses 1A0H to 1FFH, and peripheral hardware (such as I/O ports and timers) at addresses F80H to FFFH. To address a 12bit address in this data memory space, the PD75238 uses such a memory bank configuration that the loworder eight bits are specified with an instruction directly or indirectly, and the high-order four bits are used to specify a memory bank (MB). To specify a memory bank (MB), a memory bank enable flag (MBE) and memory bank select register (MBS) are contained, allowing the addressing indicated in Fig. 2-1 and Table 2-1. (The MBS is a register used to select a memory bank, and can be set to 0, 1, 2, 3, or 15. The MBE is a flag used to determine whether a memory bank selected using the MBS register is to be enabled. The MBE is automatically saved or restored at the time of interrupt processing or subroutine processing, so that it can be freely set in interrupt processing and subroutine processing.) In addressing data memory space, the MBE is usually set to 1 (MBE = 1), and the static RAM in the memory bank specified by the MBS is operated. However, the MBE = 0 mode or the MBE = 1 mode can be selected for each step of program processing for more efficient programming. Applicable program processing MBE = 0 mode * Interrupt processing * Processing that repeats internal hardware and static RAM operations * Subroutine processing * Usual program processing MBE = 1 mode 16 PD75238 Fig. 2-1 Data Memory Organization and Addressing Range of Each Addressing Mode mem mem.bit MBE =0 MBE =1 @HL @H + mem.bit MBE =0 MBE =1 @DE @DL - Stack pmem. address- fmem.bit @L ing - - - Addressing mode Memory bank enable flag 000H 01FH 020H 07FH Data area Static RAM (memory bank 0) General resister area MBS =0 MBS =0 SBS =0 0FFH 100H Data area Static RAM (memory bank 1) 19FH 1A0H Display data memory area 1FFH 200H Stack area Data area Static RAM (memory bank 2) MBS =2 MBS =2 SBS =2 MBS =1 MBS =1 SBS =1 2FFH 300H Data area Static RAM (memory bank 3) MBS =3 MBS =3 SBS =3 3FFH Not contained F80H Peripheral hardware area (memory bank 15) FC0H MBS = 15 MBS = 15 FFFH Remark -- : Don't care 17 PD75238 Table 2-1 Addressing Modes Addressing mode 1-bit direct addressing Representation format mem.bit Specified address Bit specified by bit at the address specified by MB and mem. In this case: When MBE = 0 and mem = 00H-7FH, MB = 0 When MBE = 0 and mem = 80H-FFH, MB = 15 When MBE = 1, MB = MBS Address specified by MB and mem. In this case: When MBE = 0 and mem = 00H-7FH, MB = 0 When MBE = 0 and mem = 80H-FFH, MB = 15 When MBE = 1, MB = MBS Address specified by MB and mem (mem: even address). In this case: When MBE = 0 and mem = 00H-7FH, MB = 0 When MBE = 0 and mem = 80H-FFH, MB = 15 When MBE = 1, MB = MBS 4-bit direct addressing mem 8-bit direct addressing 4-bit register indirect addressing @HL @HL+ @HL- Address specified by MB and HL. In this case, MB = MBE* MBS Address specified by MB and HL. In this case, MB = MBE* MBS. HL+ automatically increments the L register after addressing. HL- automatically decrements the L register after addressing. Address specified by DE in memory bank 0 Address specified by DL in memory bank 0 Address specified by MB and HL. In this case, MB = MBE* MBS. Bit 0 of the L resister is ignored. Bit specified by bit at the address specified by fmem. In this case: fmem = FB0H-FBFH (interrupt-related hardware) fmem = FF0H-FFFH (I/O port) Bit specified by the low-order 2 bits of the L register at the address specified by the high-order 10 bits of pmem and the high-order 2 bits of the L register. In this case, pmem = FC0H-FFFH @DE @DL 8-bit register indirect addressing Bit manipulation addressing @HL fmem.bit pmem.@L @H+mem.bit Bit specified by bit at the address specified by MB, H, and the low-order 4 bits of mem. In this case, MB = MBE* MBS Stack addressing - Address specified by SP in memory bank 0, 1, 2, and 3 selected by SBS As summarized in Table 2-1, the PD75238 allows both direct and indirect addressing in data memory manipulation for 1-bit data, 4-bit data, and 8-bit data, so that very efficient and simple programming can be performed. 18 PD75238 2.2 GENERAL REGISTER BANK CONFIGURATION The PD75238 contains four register banks, each consisting of eight general registers: X, A, B, C, D, E, H, and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory. (See Fig. 2-2.) To specify a general register bank, a register bank enable flag (RBE) and a register bank select register (RBS) are contained. The RBS is a register used to select a register bank, and the RBE is a flag used to determine whether a register bank selected using the RBS is to be enabled. The register bank (RB) enabled at instruction execution is determined as RB = RBE* RBS As indicated in Table 2-2, the PD75238 enables the user to create programs in a very efficient manner by selecting a register bank from the four register banks, depending on whether the processing is normal processing or interrupt processing. (The RBE is automatically saved and set at the time of interrupt processing, and is automatically restored upon completion of interrupt processing.) Table 2-2 Recommended Use of Register Banks with Normal Routines and Interrupt Routines Use register banks 2 and 3 with RBE = 1. Use register bank 0 with RBE = 0. Use register bank 1 with RBE = 1. (In this case, the RBS needs to be saved and restored.) Save and restore the registers with PUSH or POP. Normal processing Single interrupt processing Dual interrupt processing Multiple (triple or more) interrupt processing The general registers allow transfers, comparisons, arithmetic/logical operations, and increments and decrements not only on a 4-bit basis, but also on an 8-bit basis with the XA, HL, DE, and BC register pairs. In this case, the register pairs of the register bank that has the inverted value of bit 0 of a register bank specified by RBE* RBS can be specified as XA', HL', DE', and BC', thus providing eight 8-bit registers. (See Fig. 2-3.) 19 PD75238 Fig. 2-2 General Register Configuration (4-Bit Processing) X 01H H 03H D 05H B 07H X 09H H 0BH D 0DH B 0FH X 11H H 13H D 15H B 17H X 19H H 1BH D 1DH B 1FH A 00H L 02H E 04H C 06H A 08H L 0AH E 0CH C 0EH A 10H L 12H E 14H C 16H A 18H L 1AH E 1CH C 1EH Register bank 3 (RBE*RBS = 3) Register bank 2 (RBE*RBS = 2) Register bank 1 (RBE*RBS = 1) Register bank 0 (RBE*RBS = 0) 20 PD75238 Fig. 2-3 General Register Configuration (8-Bit Processing) XA 00H HL 02H DE 04H BC 06H XA' 08H HL' 0AH DE' 0CH BC' 0EH When RBE*RBS =0 XA' 00H HL' 02H DE' 04H BC' 06H XA 08H HL 0AH DE 0CH BC 0EH When RBE*RBS =1 XA 10H HL 12H DE 14H BC 16H XA' 18H HL' 1AH DE' 1CH BC' 1EH When RBE*RBS =2 XA' 10H HL' 12H DE' 14H BC' 16H XA 18H HL 1AH DE 1CH BC 1EH When RBE*RBS =3 21 PD75238 2.3 MEMORY-MAPPED I/O The PD75238 employs memory-mapped I/O, which maps peripheral hardware such as timers and I/O ports to addresses F80H to FFFH in the data memory space as shown in Fig. 2-1. This means that there is no particular instruction to control peripheral hardware, but all peripheral hardware is controlled using memory manipulation instructions. (Some mnemonics for hardware control are available to make programs readable.) To manipulate peripheral hardware, the addressing modes listed in Table 2-3 can be used. The display data memory, key scan registers, and port H mapped to addresses 1A0H to 1FFH are to be manipulated by specifying memory bank 1. Table 2-3 Addressing Modes Applicable to Peripheral Hardware Mapped to Addresses F80H to FFFH Applicable addressing mode Bit manipulation Direct addressing mode specifying mem.bit with MBE = 0 or (MBE = 1, MBS = 15) Direct addressing mode specifying fmem.bit regardless of MBE and MBS setting Indirect addressing mode specifying pmem.@L regardless of MBE and MBS setting 4-bit manipulation Direct addressing mode specifying mem with MBE = 0 or (MBE = 1, MBS = 15) Register indirect addressing mode specifying @HL with (MBE = 1, MBS = 15) 8-bit manipulation Direct addressing mode specifying mem (even address) with MBE = 0 or (MBE = 1, MBS = 15) Register indirect addressing mode specifying @HL (with the L register containing an even number) with (MBE = 1, MBS = 15) Applicable hardware All hardware allowing bit manipulation IST0, IST1, MBE, RBE, IExxx, IRQxxx, PORTn.0-3 PORTn. All hardware allowing 4-bit manipulation All hardware allowing 8-bit manipulation addressing Table 2-4 summarizes the I/O map of the PD75238. The items in Table 2-4 have the following meanings: * Symbol: * R/W : Name representing the address of incorporated hardware, which can be coded in the operand field of an instruction Indicates whether the hardware allows read/write operation. R/W: Both read and write operations possible R W : Read only : Write only * Number of manipulatable bits: Indicates the number of bits that can be processed in hardware manipulation * Bit manipulation addressing: Bit manipulation addressing applicable in hardware bit manipulation 22 PD75238 Table 2-4 PD75238 I/O Map (1/4) Bit manipulation ad1 bit 4 bits 8 bits dressing - - Number of manipulatable bits Address b3 F80H Hardware name (symbol) b2 b1 b0 R/W Remarks Bit 0 is always set to 0. Stack pointer (SP) R/W F82H F83H F84H Resister bank select register (RBS) Memory bank select register (MBS) Stack bank select register (SBS) RNote 1 - Note 2 5 - R/W - - mem.bit Bits 2 and 3 are always set to 0. Only bit 3 allows bit manipulation. F85H Basic interval timer mode register (BTM) W - - - F86H Basic interval timer (BT) R F88H F89H F8AH Display mode register (DSPM) Dimmer select register (DIMS) KSF Digit select register (DIGS) W W R/W - - - - - mem.bit Only bit 3 allows a bit test. Only bit 3 allows bit manipulation. - F90H Timer pulse generator mode register (TPGM) W - mem.bit F94H Timer pulse generator modulo register L (MODL) R/W F96H Timer pulse generator modulo register H (MODH) R/W - - F98H Clock mode register (WM) W - - FA0H Timer/event counter 0 mode register (TM0) W - - - - - Only bit 3 allows bit manipulation. FA2H FA4H TOE0 Timer/event counter 0 count register (T0) W R - - FA6H Timer/event counter 0 modulo register (TMOD0) W - - FA8H Event counter mode register (TM1) W - - - - - Only bit 3 allows bit manipulation. FABH FACH Gate control register (GATEC) Count register (T1) W R - - Notes 1. 2. For the SEL instruction, these registers are both readable and writable. Can be operated separately as the RBS and MBS during 4-bit manipulation. Can also be operated as the BS during 8-bit manipulation. 23 PD75238 Table 2-4 PD75238 I/O Map (2/4) Number of manipulatable bits Address b3 FB0H IST1 Hardware name (symbol) b2 IST0 b1 MBE b0 RBE R/W Bit manipulation ad1 bit 4 bits 8 bits dressing fmem.bit - - - Remarks R/W Program status word (PSW) 5 FB2H FB3H FB4H FB5H Interrupt priority select register (IPS) Processor clock control register (PCC) INT0 mode register (IM0) INT1 mode register (IM1) W W W W - - - Bit 2 is always set to 0. Bits 1, 2, and 3 are always set to 0. 5 FB7H System clock control register (SCC) W - - Only bits 0 and 3 allow bit manipulation. fmem.bit FB8H FB9H FBAH FBBH FBCH FBDH FBEH FBFH FC0H FC1H FC2H FC3H FC8H IE4 IRQ4 IEBT IRQBT EOT R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - IEW IEKS IRQKS IRQT1 IETPG IET0 IECSI0 IE1 IRQ1 IE0 IE2 Bit sequential buffer 0 (BSB0) Bit sequential buffer 1 (BSB1) Bit sequential buffer 2 (BSB2) Bit sequential buffer 3 (BSB3) CSIM11 CSIE1 Serial I/O shift register 1 (SIO1) IRQW IRQTPG IRQT0 IRQCSI0 IRQ0 IRQ2 - - - CSIM10 W W R/W - - - 5 FC9H FCCH - - 24 PD75238 Table 2-4 PD75238 I/O Map (3/4) Number of manipulatable bits Address b3 FD0H FD4H Hardware name (symbol) b2 b1 b0 R/W Bit manipulation ad1 bit 4 bits 8 bits dressing - - - - Remarks Clock output mode register (CLOM) Static mode register B (STATB) W W FD6H Static mode register A (STATA) W - - FD8H SOC EOC R/W - - - - - A/D conversion mode register (ADM) FDAH SA register (SA) R ADM is write only during 8-bit manipulation. 5 FDCH Pull-up resistor specification register group A (POGA) W - - FE0H Serial operation mode register (CSIM0) CSIE0 COI RELD WUP CMDT RELT W R/W R/W - - mem.bit - - mem.bit CSIM0 is write only during 8-bit manipulation. FE2H CMDD SBI control register (SBIC) BSYE FE4H ACKD ACKE ACKT R/W - - Serial I/O shift register 0 (SIO0) FE6H Slave address register (SVA) W - - FE8H PM33 PM32 PM31 PM30 W - - Port mode register group A (PMGA) PM63 FECH - PM62 PM2 PM61 - PM60 - W - - Port mode register group B (PMGB) PM7 - PM5 PM4 25 PD75238 Table 2-4 PD75238 I/O Map (4/4) Number of manipulatable bits Address b3 FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH Hardware name (symbol) b2 b1 b0 R/W Bit manipulation ad1 bit 4 bits 8 bits dressing - fmem.bit pmem.@L Remarks Port 0 (PORT0) Port 1 (PORT1) Port 2 (PORT2) Port 3 (PORT3) Port 4 (PORT4) Port 5 (PORT5) Port 6 (PORT6) Port 7 (PORT7) Port 8 (PORT8) Port 9 (PORT9) Port 10 (PORT10) Port 11 (PORT11) Port 12 (PORT12) Port 13 (PORT13) Port 14 (PORT14) Port 15 (PORT15) R R R/W R/W R/W R/W R/W R/W R R W W W W W W R/W R/W - - 1A0H+4n Display data memory: S16-S23 (n = 0 to 15) 1A1H+4n 1BEH 1BFH 1C0H+4n Display data memory: S0-S7 (n = 0 to 15) 1C1H+4n 1C2H+4n Display data memory: S8-S15 (n = 0 to 15) 1C3H+4n 1FCH 1FDH 1FEH 1FFH Key scan register (KS1) Port H (PORTH) Key scan register (KS0) Key scan register (KS2) mem.bit R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 26 PD75238 3. INTERNAL CPU FUNCTIONS 3.1 PROGRAM COUNTER (PC): 15 BITS The program counter is a 15-bit binary counter for holding program memory address information. Fig. 3-1 Program Counter Format PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Note that the reset start address must be set within a space of 16K bytes (0000H to 3FFFH). This is because a RESET input sets the low-order six bits of program memory address 0000H in PC13 to PC8, and the contents of address 0001H in PC7 to PC0 for initialization. 3.2 PROGRAM MEMORY (ROM): 32640 WORDS x 8 BITS The program memory is a mask-programmable ROM with a configuration of 32640 words x 8 bits for storing programs, table data, and so forth. Program memory is addressed by the program counter. Table data can be referenced using the table reference instruction (MOVT). Fig. 3-2 shows the allowable branch address ranges for the branch instructions and subroutine call instructions. The whole-space branch instruction (BRA !addr1) and the whole-space call instruction (CALLA !addr1) allow a direct branch throughout the whole space 0000H to 7F7FH. The relative branch instruction (BR $addr) allows a branch to addresses (PC - 15 to PC - 1 and PC + 2 to PC + 16) regardless of block boundaries. The program memory is located at addresses 0000H to 7F7FH containing the following specially assigned addresses. (All areas excluding 0000H and 0001H can be used as normal program memory.) * 0000H to 0001H Vector table for holding the RBE and MBE setting values and program start address at the time of a RESET input. A reset start can be performed at an arbitrary address within a 16K-byte space (0000H to 3FFFH). * 0002H to 000FH Vector address table for holding the RBE and MBE setting values and program start address at the time of each vectored interrupt occurrence. Interrupt processing can be started at an arbitrary address within a 16K-byte space (0000H to 3FFFH). * 0020H to 007FH Table area referenced by the GETI instructionNote Note The GETI instruction can represent an arbitrary 2-byte or 3-byte instruction or two 1-byte instructions in 1 byte, thus reducing the number of program bytes. (See Section 8.1.) 27 PD75238 Fig. 3-2 Program Memory Map 0000H MBE RBE Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) 0002H MBE RBE INTBT/INT4 start address INTBT/INT4 start address 0004H MBE RBE INT0 start address INT0 start address 0006H MBE RBE INT1 start address INT1 start address 0008H MBE RBE INTSO start address INTSO start address 000AH MBE RBE INTT0 start address INTT0 start address 000CH MBE RBE INTTPG start address INTTPG start address 000EH MBE RBE INTKS start address INTKS start address (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) BR !addr instruction branch address 0020H GETI instruction reference table 007FH 0080H CALL !addr instruction branch address Branch/call address specified in GETI instruction BRCB !caddr instruction branch address CALLA !addr instruction branch address BR $addr1 instruction relative branch address (-15 to -1, +2 to +16) BRA !addr instruction branch address CALLF !faddr instruction entry address 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address 3FFFH 4000H 4FFFH 5000H 5FFFH 6000H 6FFFH 7000H 7F7FH Caution The start address of an interrupt vector shown above consists of 14 bits. So, the start address must be set within a 16K-byte space (0000H to 3FFFH). Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the low-order 8 bits of the PC changed. 28 PD75238 3.3 DATA MEMORY (RAM) The data memory consists of a static RAM and peripheral hardware. The static RAM consists of an area of 768 words x 4 bits in memory banks 0, 2, and 3, an area of 160 words x 4 bits in memory bank 1, and an area of 96 words x 4 bits in memory bank 1, which is used also as display data memory. The RAM is used for storing processing data, and is also used as stack memory for subroutine and interrupt execution. To particular memory addresses, general registers, display data memory, and peripheral hardware (various registers) are mapped. Data in these areas are manipulated using general register manipulation instructions and memory manipulation instructions (See Fig. 2-1). As a stack area, all addresses in memory banks 0, 1, 2, and 3 (000H to 3FFH) can be used. The data memory has a configuration of 4 bits per address, but allows 8-bit memory manipulation instructions to be used for 8-bit oriented manipulation, and also allows bit manipulation instructions to be used for bit-by-bit manipulation. Even addresses are to be specified for 8-bit manipulation instructions. Fig. 3-4 shows the organization of the display data memory area (1A0H to 1FFH). Fig. 3-3 Data Memory Map Data memory General register area 000H (32 x 4) 01FH 020H 256 x 4 0FFH 100H Stack area Display data memory, etc. 19FH 1A0H (96 x 4) 1FFH 200H 256 x 4 Memory bank 0 1 Data area Static RAM (1024 x 4) 256 x 4 2 2FFH 300H 256 x 4 3 3 FFH Not contained F80H Peripheral hardware area FFFH 128 x 4 15 29 PD75238 Fig. 3-4 Display Data Memory Configuration 1A1H 1A3H 1A5H 1A7H 1A9H 1ABH 1ADH 1AFH 1B1H 1B3H 1B5H 1B7H 1B9H 1BBH 1BDH 1BFH Number of manipulatable bits 1A0H 1A2H 1A4H 1A6H 1A8H 1AAH 1ACH 1AEH 1B0H 1B2H 1B4H 1B6H 1B8H 1BAH 1BCH 1BEH(KS2) 1C3H 1C7H 1CBH 1CFH 1D3H 1D7H 1DBH 1DFH 1E3H 1E7H 1EBH 1EFH 1F3H 1F7H 1FBH 1FFH(PORTH) 1C2H 1C6H 1CAH 1CEH 1D2H 1D6H 1DAH 1DEH 1E2H 1E6H 1EAH 1EEH 1F2H 1F6H 1FAH 1FEH(KS1) 1C1H 1C5H 1C9H 1CDH 1D1H 1D5H 1D9H 1DDH 1E1H 1E5H 1E9H 1EDH 1F1H 1F5H 1F9H 1FDH 1C0H 1C4H 1C8H 1CCH 1D0H 1D4H 1D8H 1DCH 1E0H 1E4H 1E8H 1ECH 1F0H 1F4H 1F8H 1FCH(KS0) 1 bit 4 bits 8 bits Remarks 1. KS0, KS1, and KS2 are key scan registers. 2. PORTH is the high-voltage, high-current output port, and is also used for digit output. 30 PD75238 3.4 GENERAL REGISTERS: 8 x 4 BITS x 4 BANKS The general registers are mapped to particular addresses in data memory. Four banks of registers are provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, A). The register bank (RB) to be enabled at the time of instruction execution is determined by RB = RBE* RBS: (RBS = 0 to 3) Each general register allows 4-bit manipulation. In addition, BC, DE, HL, or XA serves as a register pair for 8-bit manipulation. DL also makes a register pair as well as DE and HL; these three register pairs can be used as data pointers. A general register area can be addressed and accessed as normal RAM, regardless of whether it is used as a register. Fig. 3-5 Address 000H 001H 002H 003H 004H 005H 006H 007H 008H General Register Format 3 Fig. 3-6 0 B 3 D 3 0 H 3 X 0 0 Register Pair Format 3 C 3 E 3 L 3 A 0 0 0 0 3 Data memory A register X register L register H register 0 Register bank 0 E register D register C register B register *********** Same as bank 0 Register bank 1 00FH 010H *********** Same as bank 0 Register bank 2 017H 018H *********** Same as bank 0 Register bank 3 01FH 31 1 bank PD75238 3.5 ACCUMULATORS In the PD75238, the A register and the XA register pair function as accumulators. The A register is mainly used for 4-bit data processing instructions, and the XA register pair is mainly used for 8-bit data processing instructions. For a bit manipulation instruction, the carry flag (CY) functions as a bit accumulator. Fig. 3-7 Accumulators CY Bit accumulator A 4-bit accumulator X A 8-bit accumulator 3.6 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) The PD75238 uses static RAM as stack memory (LIFO scheme), and the 8-bit register holding the start address of the stack area is the stack pointer (SP). The stack area is located at addresses 000H to 3FFH in memory banks 0, 1, 2, and 3. Either of the memory banks is selected according to the value of the 4-bit SBS. The SP is decremented before a write (save) operation to stack memory, and is incremented after a read (restoration) operation from stack memory. The SBS is set with a 4-bit memory manipulation instruction. Note that the high-order two bits are always set to 00. Fig. 3-9 and 3-10 show data saved to and restored from stack memory in these stack operations. To place the stack area at a given location, the SP can be initialized with an 8-bit memory manipulation instruction, and the SBS can be initialized with a 4-bit memory manipulation instruction. Both can be read from as well. Table 3-1 Stack Area to Be Selected by the SBS SBS SBS1 0 0 1 1 -------------------- SBS2 0 1 0 1 Stack area Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3 When the SP is initialized to 00H, a stack operation starts at the high-order address (nFFH) of memory bank (n: n = 0, 1, 2, or 3) specified with the SBS. A stack area must be within the memory bank specified with the SBS. If a stack operation exceeds address n00H, the operation returns to address nFFH of the same bank. Stacking beyond memory bank boundaries is enabled only by resetting the SBS. A RESET signal occurrence causes the contents of the SP and the SBS to be undefined, so that the SP must always be initialized to a desired value at the start of the program. 32 PD75238 Fig. 3-8 Address F80H F84H SP7 SP6 SP5 SP4 SP3 SP2 SP1 SBS1 Always 0 SBS0 Stack Bank Select Register Format Symbol SP SBS 000H SBS 0FFH 100H Memory bank 1 1FFH 200H Memory bank 2 2FFH 300H Memory bank 3 3FFH SP SP SP Memory bank 0 SP 33 PD75238 Fig. 3-9 PUSH instruction Data Saved to Stack Memory CALL, CALLA, or CALLF instruction Interrupt Stack SP - 6 SP - 5 SP - 2 SP - 1 SP Lower bits of pair register Upper bits of pair register Stack PC11 - PC8 0 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 * * * * MBE RBE Note Stack SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 IST1 IST0 MBE RBE PSW CY SK2 SK1 SK0 SP - 4 SP - 3 SP - 2 SP - 1 SP * * Fig. 3-10 Data Restored from Stack Memory POP instruction RET or RETS instruction RETI instruction Stack SP SP + 1 SP + 2 Lower bits of pair register Upper bits of pair register Stack SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 * * 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 * * MBE RBE Note Stack SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 IST1 IST0 MBE RBE PSW CY SK2 SK1 SK0 * * Note A PSW other than the MBE or RBE is not saved/restored. Remark Data marked with * is undefined. 34 PD75238 3.7 PROGRAM STATUS WORD (PSW): 8 BITS The program status word (PSW) consists of various flags closely associated with processor operations. The PSW is mapped to addresses FB0H and FB1H in the data memory space. The four bits at address FB0H can be manipulated with a memory manipulation instruction. Address FB1H cannot be manipulated with a normal data memory manipulation instruction. Fig. 3-11 Address FB1H Program Status Word Format FB0H Symbol PSW CY SK2 SK1 SK0 IST1 IST0 MBE RBE Cannot be manipulated Can be manipulated by an instruction specifically provided for controlling this flag Can be manipulated Table 3-2 PSW Flags Saved/Restored in Stack Operation Saved/restored flag Save When CALL, CALLA, or CALLF instruction is executed When hardware interrupt occurs MBE and RBE are saved. All PSW bits are saved. MBE and RBE are restored. All PSW bits are restored. Restore When RET or RETS instruction is executed When RETI is executed 35 PD75238 (1) Carry flag (CY) The carry flag is a 1-bit flag used to store overflow or underflow occurrence information when an arithmetic operation with a carry (ADDC, SUBC) is executed. The carry flag also has the function of a bit accumulator, and therefore can be used to store the result of a Boolean operation performed on the CY and bit at a specified data memory bit address. The carry flag is manipulated using special instructions, independently of the other PSW bits. A RESET signal occurrence causes the carry flag to be undefined. Table 3-3 Carry Flag Manipulation Instructions Instruction (mnemonic) Instruction dedicated to carry flag manipulation SET1 CY CLR1 CY NOT1 CY SKT CY MOV1 mem*.bit CY MOV1 CY,mem*.bit AND1 CY,mem*.bit OR1 CY,mem*.bit XOR1 CY,mem*.bit Carry flag operation/processing Sets CY to 1. Clears CY to 0. Inverts the contents of CY. Skips if CY is set to 1. Transfers the contents of CY to a specified bit. Transfers the contents of a specified bit to CY. ANDs, ORs, or XORs CY with the contents of a specified bit, then sets the result in CY. Bit transfer instruction Bit Boolean instruction Interrupt handling Saves CY and all other PSW bits to stack memory in parallel. Interrupt execution ------------------------------------------------------------------Restores CY together with the other PSW bits from stack memory. RETI Remark mem*.bit represents the following three addressing modes: * fmem.bit * pmem.@L * @H+mem.bit (2) Skip flags (SK2, SK1, SK0) The skip flags are used to store skip status, and are automatically set or reset when the CPU executes an instruction. The user cannot directly manipulate these flags as operands. 36 PD75238 (3) Interrupt status flag (IST1, IST0) The interrupt status flag is a 2-bit flag used to store the status of processing being performed. (For detailed information, see Table 5-3.) Table 3-4 Information Indicated by the Interrupt Status Flag IST1 0 IST0 0 Status of processing being performed Status 0 Processing and interrupt control Normal program processing is being performed. Any interrupts are acceptable. A lower- or higher-priority interrupt is being serviced. Higher-priority interrupts are acceptable. A higher-priority interrupt is being serviced. No interrupts are acceptable. Not to be set 0 1 Status 1 1 0 Status 2 1 1 -- The interrupt priority control circuit (see Fig. 5-1) checks this flag to control multiple interrupts. The contents of the IST1 and IST0 are saved as part of the PSW to stack memory if an interrupt is accepted, then are automatically set to a one-step higher status. The RETI instruction restores the contents present before an interrupt occurs. The interrupt status flag can be manipulated using a memory manipulation instruction, and the status of processing being performed can be changed by program control. Caution The user must always disable interrupts with the DI instruction before manipulating this flag, and must enable interrupts with the EI instruction after manipulating this flag. 37 PD75238 (4) Memory bank enable flag (MBE) The memory bank enable flag is a 1-bit flag used to specify the address information generation mode for the high-order four bits of a 12-bit data memory address. When the MBE is set to 1, the data memory address space is expanded, allowing all data memory space to be addressed. When the MBE is reset to 0, the data memory address space is fixed, regardless of MBS setting. (See Fig. 2-1.) A RESET input automatically initializes the MBE by setting the MBE to the content of bit 7 at program memory address 0. In vectored interrupt processing, the MBE is automatically set to the content of bit 7 in the vector address table for servicing the interrupt. Usually, the MBE is set to 0 in interrupt processing, and static RAM in memory bank 0 is used. (5) Register bank enable flag (RBE) The register bank enable flag is a 1-bit flag used to determine whether to expand the general register bank configuration. When the RBE is set to 1, a set of general registers can be selected from register banks 0 to 3, depending on the setting of the register bank select register (RBS). When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting of the RBS. A RESET input automatically initializes the RBE by setting the RBE to the content of bit 6 at program memory address 0. When a vectored interrupt occurs, the RBE is automatically set to the content of bit 6 in the vector address table for servicing the interrupt. Usually, the RBE is set to 0 in interrupt processing. Register bank 0 is used for 4-bit processing, and register banks 0 and 1 are used for 8-bit processing. 38 PD75238 3.8 BANK SELECT REGISTER (BS) The bank select register consists of a register bank select register (RBS) and memory bank select register (MBS), which specify a register bank and memory bank to be used, respectively. The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction, respectively. The contents of BS can be saved to or restored from a stack area eight bits at a time by using the PUSH BS/POP BS instruction. Fig. 3-12 Address Bank Select Register Format MBS RBS Symbol RBS0 BS F82H MBS3 MBS2 MBS1 MBS0 0 0 RBS1 (1) Memory bank select register (MBS) The memory bank select register is a 4-bit register used to store the high-order four bits of a 12-bit data memory address. The contents of this register specify a memory bank to be accessed. Memory banks 0, 1, 2, 3, and 15 can be specified. The MBS is set with the SEL MBn instruction (n = 0, 1, 2, 3, 15) Fig. 2-1 shows the range of addressing using MBE and MBS settings. A RESET input initializes the MBS to 0. (2) Register bank select register (RBS) The register bank select register specifies a register bank to be used as general registers; a register bank can be selected from register banks 0 to 3. The RBS is set with the SEL RBn instruction (n = 0 to 3). A RESET input initializes the RBS to 0. Table 3-5 Register Bank to Be Selected with the RBE and RBS RBS RBE 0 3 0 2 0 1 x 0 0 1 0 0 1 1 0 1 Bank 2 is selected. Bank 3 is selected. 0 x 0 1 Register bank Bank 0 is always selected. Bank 0 is selected. Bank 1 is selected. Always 0 Remark x: Don't care 39 PD75238 4. PERIPHERAL HARDWARE FUNCTIONS 4.1 DIGITAL I/O PORTS The PD75238 employs memory-mapped I/O, enabling all I/O ports to be mapped to data memory space. Fig. 4-1 Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH Data Memory Address Assigned to Digital Port 3 P03 P13 P23 P33 P43 P53 P63 P73 P83 P93 P103 P113 P123 P133 P143 P153 2 P02 P12 P22 P32 P42 P52 P62 P72 P82 P92 P102 P112 P122 P132 P142 P152 1 P01 P11 P21 P31 P41 P51 P61 P71 P81 P91 P101 P111 P121 P131 P141 P151 0 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 P100 P110 P120 P130 P140 P150 Symbol PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 8 PORT 9 PORT 10 PORT 11 PORT 12 PORT 13 PORT 14 PORT 15 40 PD75238 (1) Configurations of digital I/O ports Fig. 4-2 to Fig. 4-11 show the configurations of the ports. (2) I/O mode setting The I/O mode of each I/O port is set by the port mode register as shown in Fig. 4-12. Each port functions as an input port when the corresponding bit of the port mode register is set to 0, and functions as an output port when the same corresponding bit is set to 1. An 8-bit memory manipulation instruction is used to set port mode register group A or B. A RESET input clears all bits of each port mode register to 0. This means that the output buffers are set off, and all ports are placed in the input mode. (3) Operation of digital I/O ports When an instruction is executed, the operation of the port and pins depends on the I/O mode setting, as listed in Table 4-1. Table 4-1 I/O Port Operations by I/O Instructions Input mode (corresponding bit in the mode register is 0) [Output buffer is off] When a 1-bit test instruction, 1-bit input instruction, or 4-/8-bit input instruction is executed When a 4-/8-bit output instruction is executed When a 1-bit output instructionNote is executed Receives data on certain pins. Output mode (corresponding bit in the mode register is 1) [Output buffer is on] Receives the contents of the output latch. Transfers data in the accumulator to the output latch. The contents of the output latch are undefined. Outputs data in the accumulator to output pins. Changes the output pin state according to the instruction. Note Instructions such as SET1/CLR1/MOV1 PORTn.bit, CY 41 PD75238 Fig. 4-2 SI0 SCK0 Configuration of Ports 0, 1, and 8 INT4 SO0 P01 output latch Internal SCK0 VDD Selector 8 CSIM0 Selector Pull-up resistor P-ch Bit 0 of POGA P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 Input buffer Output buffer which can be switched to either push-pull output or N-ch open-drain output Pull-up resistor VDD Internal bus P-ch Bit 1 of POGA Input buffer or fX/64 Noise elimination circuit P10/INT0 P11/INT1 P12/INT2 P13/ TI0 TI0 INT2 INT1 INT0 Input buffer with hysteresis SI1 SO1 SCK1 Internal SCK1 PPO 8 CSIM1 P80/PPO P81/SCK1 P82/SO1 P83/PI1 Input buffer 42 PD75238 Fig. 4-3 Configuration of Ports 3n and 6n (n = 0 to 3) VDD Input buffer MPX PMmn = 1 Bit m of POGA P-ch PMmn = 0 Pull-up resistor Internal bus Output buffer Output latch Pmn PMmn Bit of port mode register group A m = 3, 6 n = 0 to 3 Fig. 4-4 Configuration of Port 2 VDD Pull-up resistor P-ch Bit m of POGA Input buffer PMm = 0 MPX PMm = 1 Internal bus Pm0 Pm1 Pm2 Pm3 Output buffer PMm Bit of port mode register group B (m = 2) Output latch 43 PD75238 Fig. 4-5 Configuration of Ports 4 and 5 VDD Pull-up resistor Input buffer PMm = 0 Mask option MPX PMm = 1 Internal bus Pm0 Pm1 Pm2 Pm3 N-ch open-drain output buffer PMm Output latch Bit of port mode register group B (m = 4, 5) 44 PD75238 Fig. 4-6 Input buffer PMm = 0 Configuration of Port 7 MPX PMm = 1 Internal bus Pm0 Pm1 Pm2 Pm3 Output buffer PMm Bit of port mode register group B (m = 7) Mask option Pull-down resistor Output latch Fig. 4-7 Configuration of Port 9 Input instruction Input buffer P90/AN4 Internal bus P91/AN5 P92/AN6 P93/AN7 To A /D converter 45 PD75238 Fig. 4-8 SK P-ch open-drain output buffer SK+1/Pm1 Configuration of Ports 10 and 11 SK/Pm0 SK+1 SK+2 SK+2/Pm2 SK+3 Internal bus SK+3/Pm3 Mask option Pull-down resistor 4 DSPM Mask option VLOAD (Specified for S16 to S23 at a time) 8 STATB Remarks 1. Port 10: K = 16, m = 10 2. Port 11: K = 20, m = 11 Fig. 4-9 SK P-ch open-drain output buffer SK+1/Pm1 Configuration of Ports 12 and 13 SK/Pm0 SK+1 SK+2 SK+2/Pm2 SK+3 Internal bus SK+3/Pm3 Mask option Pull-down resistor 4 DSPM VLOAD 8 STATA Remarks 1. Port 12: K = 0, m = 12 2. Port 13: K = 4, m = 13 46 PD75238 Fig. 4-10 Configuration of Port 14 P-ch open-drain output buffer Output buffer S8/P140 M S8 P X Note S9/P141 Internal bus S9 S10 S11 S10/T15/P142 Note S11/T14/P143 4 DSPM. 3 T15 T14 Mask option (each pin) Pull-down resistor DIGS VLOAD 8 4 STATA Note Selector Fig. 4-11 Configuration of Ports 15 and H Output buffer P-ch open-drain output buffer Note S12/T13/P150/PH0 M S12 Note S13/T12/P151/PH1 Internal bus Note Note Note Note P X Note S13 S14 S15 S14/T11/P152/PH2 Note S15/T10/P153/PH3 PH1 PH3 PH0 PH2 4 DSPM. 3 T12 T10 T13 T11 Mask option (each pin) Pull-down resistor 8 4 STATA DIGS VLOAD Note Selector 47 PD75238 Fig. 4-12 Formats of the Port Mode Registers Port mode register group A Address FE8H 7 PM63 6 PM62 5 PM61 4 PM60 3 PM33 2 PM32 1 PM31 0 PM30 Symbol PMGA Symbol PM3n, PM6n PMGA 0 1 P3n and P6n pin I/O specification (n = 0-3) Input mode (output buffers set off) Output mode (output buffers set on) Port mode register group B Address FECH 7 PM7 6 5 PM5 4 PM4 3 2 PM2 1 0 Symbol PMGB Symbol PMn PMGB 0 1 Port n I/O specification (n = 2, 4, 5, and 7) Input mode (output buffers set off) Output mode (output buffers set on) Remark ----: Don't care (4) Pull-up resistor register group A (POGA) Pull-up resistor register group A is a register to specify an internal pull-up register to each port pin of ports 0 to 3 and port 6 (excluding P00). Fig. 4-13 shows the format of this register. When a pull-up resistor is to be contained, set 1 to an associated bit, and when a pull-up resistor is not to be contained, set 0. Fig. 4-13 Format of the Register Group A Specifying the Use of Pull-Up Resistors Address FDCH 7 -- 6 PO6 5 -- 4 -- 3 PO3 2 PO2 1 PO1 0 PO0 Symbol POGA Port 0 (P01 - P03) Port 1 (P10 - P13) Port 2 (P20 - P23) Port 3 (P30 - P33) Port 6 (P60 - P63) Caution For mask option, ports 4 and 5 can contain pull-up resistors, and port 7 and ports 10 to 15 can contain pull-down resistors bit by bit. Remark ----: Don't care 48 PD75238 4.2 CLOCK GENERATOR (1) Configuration of the clock generator The clock generator supplies various clock signals to the CPU and peripheral hardware. Fig. 4-14 shows the configuration of the clock generator. Fig. 4-14 XT1 Subsystem clock generator fXT Clock timer Timer/pulse generator Block Diagram of the Clock Generator * * * * * * * XT2 X1 FIP controller/driver Basic interval timer (BT) Timer/event counter Serial interface Clock timer Clock output circuit INT0 voice eliminator X2 Main system clock generator fX 1/2 1/4 1/16 1/8 to 1/4096 Frequency divider SCC SCC3 Oscillator disable signal Selector Frequency divider Selector 1/4 * CPU * INT0 noise SCC0 Internal bus PCC PCC0 eliminator * Clock output circuit PCC1 4 HALT Note STOP Note PCC2 HALT F/F S PCC3 R Q PCC2, PCC3 clear signal STOP F/F Q S Wait release signal from BT RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. fX : Main system clock frequency 2. fXT: Subsystem clock frequency 3. = CPU clock 4. PCC : Processor clock control register 5. SCC: System clock control register 6. One clock cycle (tCY) of the CPU clock () is equal to one machine cycle of an instruction. See Chapter 11 for details of tCY. 5 49 PD75238 (2) Functions of the clock generator The clock generator generates the clock signals listed below, and controls the standby mode and other CPU operation modes. * Main system clock: fX * Subsystem clock: fXT * CPU clock: * Clocks for peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). The clock generator functions and operates as described below. (a) A RESET input selects the lowest-speed mode (10.7 s at 6.0 MHz)Note 1 for the main system clock. (PCC = 0, SCC = 0) (b) When the main system clock is selected, the PCC can be set to select one of four CPU clocks (0.67 s, 1.33 s, 2.67 s, and 10.7 s at 6.0 MHz)Note 2 . (c) When the main system clock is selected, the two standby modes, STOP mode and HALT mode, are available. (d) The SCC can be set to select the subsystem clock for very low-speed, low-current operation (122 s at 32.768 kHz). (e) When the subsystem clock is selected, main system clock generation can be stopped with the SCC. In addition, the HALT mode can be used, but the STOP mode cannot be used. (Subsystem clock generation cannot be stopped.) (f) Clocks for peripheral hardware are produced by dividing the main system clock signal. Only to the watch timer, the subsystem clock can be directly supplied to continue the clock function. (g) When the subsystem clock is selected, the watch timer can operate normally, but other hardware cannot be used because they operate with the main system clock. Notes 1. 15.3 s at 4.19 MHz 2. 0.95 s, 1.91 s, 3.82 s, 15.3 s at 4.19 MHz 50 PD75238 (3) Processor clock control register (PCC) The PCC is a 4-bit register for selecting CPU clock with the low-order two bits and for selecting a CPU operation mode with the high-order two bits. (See Fig. 4-15.) When bit 3 or bit 2 is set to 1, the standby mode is set. When this is released by the standby release signal, these bits are automatically cleared to return to the normal operation mode. (See Chapter 6 for detailed information.) A 4-bit memory manipulation instruction is used to set the low-order two bits of the PCC. (The high-order two bits are set to 0.) Bit 3 and bit 2 are set to 1 using the STOP instruction and HALT instruction, respectively. The STOP instruction and HALT instruction can be executed regardless of MBE setting. A CPU clock can be selected only when the main system clock is used for operation. When the subsystem clock is selected for operation, the low-order two bits of the PCC are invalidated, and fXT/4 is automatically set. The STOP instruction can be executed only when the main system clock is used for operation. The generation of a RESET signal clears the PCC to 0. 51 PD75238 Fig. 4-15 Format of the Processor Clock Control Register Address FB3H 3 PCC3 2 1 0 PCC0 Symbol PCC PCC2 PCC1 CPU clock selection bit (Operation with fX = 6.0 MHz) SCC = 0 ( ) indicates fX = 6.0 MHz CPU clock frequency 0 0 1 1 0 1 0 1 = fX/64 (93.7 kHz) = fX/16 (375 kHz) = fX/8 (750 kHz) = fX/4 (1.5 MHz) 1 machine cycle SCC = 1 ( ) indicates f XT = 32.768 kHz CPU clock frequency = fXT/4 (8.192 kHz) Not to be set = fXT/4 (8.192 kHz) 122 s s 1 machine cycle 122 s s s 10.7 s s 2.67 s s 1.33 s 0.67 s s (Operation with fX = 4.19 MHz) SCC = 0 ( ) indicates fX = 4.19 MHz CPU clock frequency 0 0 1 1 0 1 0 1 = fX/64 (65.5 kHz) = fX/16 (262 kHz) = fX/8 (524 kHz) = fX/4 (1.05 MHz) 1 machine cycle 15.3 s s 3.82 s s 1.91 s s 0.95 s s SCC = 1 ( ) indicates f XT = 32.768 kHz CPU clock frequency = fXT/4 (8.192 kHz) Not to be set = fXT/4 (8.192 kHz) 1 machine cycle 122 s s s 122 s Remarks 1. fX : Output frequency from the main syem clock oscillator 2. fXT: Output frequency from the subsyem clock oscillator CPU operation mode control bits 0 0 1 1 0 1 0 1 Normal operation mode HALT mode STOP mode Not to be set 52 PD75238 (4) System clock control register (SCC) The SCC is a 4-bit register for selecting CPU clock with the least significant bit and for controlling the termination of main system clock generation with the most significant bit. (See Fig. 4-16.) SCC.0 and SCC.3 are located at the same data memory address, but both bits cannot be changed at the same time. Accordingly, SCC.0 and SCC.3 are set using bit manipulation instructions. SCC.0 and SCC.3 can be manipulated regardless of MBE setting. Main system clock generation can be terminated by setting SCC.3 only when the subsystem clock is used for operation. The STOP instruction must be used for generation termination when the main system clock is used for operation. A RESET input clears the SCC to 0. Fig. 4-16 Address FB7H SCC3 -- -- SCC0 Format of the System Clock Control Register Symbol SCC SCC3 SCC0 0 0 1 1 0 1 0 1 System clock selection Main system clock Subsystem clock Not to be set Subsystem clock Main system clock operation Can oscillate Oscillation stopped Cautions 1. A time period of up to 1/fXT is needed to change the system clock. This means that to terminate main system clock generation, SCC.3 must be set when the machine cycles indicated in Table 4-2 or more have elapsed after the clock is switched from the main system clock to the subsystem clock. 2. When the main system clock is used for operation, setting SCC.3 to stop clock generation does not enter the normal STOP mode. 3. When SCC.3 is set to 1, the X1 input pin is connected to VSS (GND electric potential) to prevent leakage in the crystal oscillator. When an external clock is used as the main system clock, never set SCC.3 to 1. 4. When the four bits of PCC are set to 0001B ( = fX/16), do not set SCC.0 to 1. Before switching the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other than 0001B is set. When the system operates on the subsystem clock, the PCC bits must also be other than 0001B. 53 PD75238 (5) System clock oscillator The main system clock oscillator operates with a crystal (6.0 MHz standard) or ceramic resonator connected to the X1 and X2 pins. An external clock can also be input. Fig. 4-17 External Circuitry for the Main System Clock Oscillator (b) External clock (a) Crystal/ceramic oscillation PD75238 X1 External clock X1 PD75238 X2 Crystal oscillator or ceramic oscillator X2 Caution When an external clock is used, the STOP mode cannot be set. This is because the X1 pin is connected to VSS in the STOP mode. 54 PD75238 The subsystem clock oscillator operates with a crystal resonator (32.768 kHz standard) connected to the XT1 and XT2 pins. An external clock can also be input. Fig. 4-18 (a) Crystal oscillation External Circuitry for the Subsystem Clock Oscillator (b) External clock PD75238 XT1 32.768 kHz External clock PD75238 XT1 XT2 Open XT2 Caution When the main system clock or subsystem clock oscillator is used, conform to the following guidelines when wiring at the shaded portions of Fig. 4-17 and 4-18 to eliminate the influence of the wiring capacity. * The wiring must be as short as possible. * Other signal lines must not run in these areas. Any line carrying a high fluctuating current must be kept away as far as possible. * The grounding point of the capacitor of the oscillator must have the same potential as that of VSS. It must not be grounded to ground patterns carrying a large current. * No signal must be taken from the oscillator. When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator. 55 PD75238 (6) Time required to change the system clock and CPU clock The system clock and CPU clock can be changed by using the least significant bit of the SCC and the loworder two bits of the PCC. This switching is not performed immediately after the contents of the registers are rewritten, but the system operates with the previous clock for some machine cycles. Accordingly, after this time period, the STOP instruction must be executed or SCC.3 must be set to 1 to terminate main system clock generation. Table 4-2 Setting before switching SCC PCC PCC 0 0 1 0 0 Maximum Time Required to Change the System Clock and CPU Clock Setting after switching SCC0 PCC1 PCC0 0 0 0 SCC0 PCC1 PCC0 0 0 1 1 machine cycle SCC0 PCC1 PCC0 0 1 0 1 machine cycle SCC0 PCC1 PCC0 0 1 1 1 machine cycle SCC0 PCC1 PCC0 1 x x fX /64fXT machine cycles (3 machine cycles) 0 0 1 1 4 machine cycles 4 machine cycles 4 machine cycles Not to be set 0 8 machine cycles 8 machine cycles 8 machine cycles fX/8fXT machine cycles (23 machine cycles) fX/4fXT machine cycles (46 machine cycles) 1 1 16 machine cycles 16 machine cycles 16 machine cycles 1 x x 1 machine cycle Not to be set 1 machine cycle 1 machine cycle Remarks 1. CPU clock is supplied to the CPU in the PD75238. The reciprocal of this frequency is a minimum instruction time (defined as one machine cycle in this manual). 2. Time enclosed in parentheses is required when fX = 6.0 MHz and fXT = 32.768 kHz. Caution When the four bits of PCC are set to 0001B ( = fX/16), do not set SCC.0 to 1. Before switching the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other than 0001B is set. When the system operates on the subsystem clock, the PCC bits must also be other than 0001B. 56 PD75238 (7) Procedure for changing the system clock and CPU clock The procedure for changing the system clock and CPU clock is explained using Fig. 4-19. Fig. 4-19 Changing the System Clock and CPU Clock Commercial power line voltage ON OFF VDD pin voltage RESET signal Wait 21.8 ms [31.3 ms] System clock CPU clock fX 10.7 s [15.3 s] Internal reset operation fX 0.67 s [0.95 s] f XT 122 s fX 0.67 s [0.95 s] Remark The values not enclosed in square brackets are for fX = 6.0 MHz and fXT = 32.768 kHz; the values enclosed in square brackets for fX = 4.19 MHz. 1 2 3 A RESET input starts CPU operation at the lowest speed of the main system clock (10.7 s at 6.0 MHz) Note 1 after a wait time (21.8 ms at 6.0 MHz) Note 2 for stable oscillation. The PCC is rewritten for highest-speed operation after a time elapse which is sufficient for the voltage on the VDD pin to be high enough for highest-speed operation. The removal of commercial power is detected using, for example, an interrupt input (INT4 is useful), then SCC.0 is set to operate with the subsystem clock. (In this case, the start of subsystem clock generation must be confirmed beforehand.) After a time (32 machine cycles) required to switch to the subsystem clock elapses, SCC.3 is set to terminate main system clock generation. 4 After detecting the input of commercial power by using an interrupt, SCC.3 is cleared to start main system clock generation. After a time required for stable generation, SCC.0 is cleared to operate at highest speed. Notes 1. 15.3 s at 4.19 MHz 2. 31.3 ms at 4.19 MHz 57 PD75238 4.3 CLOCK OUTPUT CIRCUIT (1) Configuration of the clock output circuit Fig. 4-20 shows the configuration of the clock output circuit. (2) Functions of the clock output circuit The clock output circuit outputs a clock pulse signal on the P22/PCL pin for remote control or for supplying clock pulses to a peripheral LSI device. The procedure for outputting a clock pulse signal is as follows: (a) Select a clock output frequency, and disable clock output. (b) Write a 0 in the P22 output latch. (c) Set the output mode for port 2. (d) Enable clock output. Fig. 4-20 From the clock generator f X/23 Selector f X/24 f X/2 6 Configuration of the Clock Output Circuit Output buffer PCL/P22 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output. 58 PD75238 (3) Clock output mode register (CLOM) The CLOM is a 4-bit register to control clock output. The CLOM is set with a 4-bit memory manipulation instruction. No read operation is allowed on this register. CPU clock is output on the PCL/P22 pin. SEL MB15 ; Or CLR1 MBE MOV A, #1000B MOV CLOM, A Example A RESET input clears the CLOM to 0, disabling clock output. Fig. 4-21 Address FD0H Format of the Clock Output Mode Register Symbol CLOM 3 CLOM3 2 0 1 0 CLOM1 CLOM0 Clock output frequency selection bit (Frequency when fX = 6.0 MHz) 0 0 1 1 0 1 0 1 Output Note 3 (1.50 MHz, 750 kHz, 375 kHz, 93.7 kHz) Output fX/2 (750 kHz) Output fX/24 (375 kHz) Output fX/26 (93.7 kHz) (Frequency when fX = 4.19 MHz) 0 0 1 1 0 1 0 1 Output Note (1.05 MHz, 524 kHz, 262 kHz, 65.5 kHz) Output fX/23 (524 kHz) Output fX/24 (262 kHz) Output fX/2 (65.5 kHz) 6 Note is the CPU clock supply selected by PCC. Clock output enable/disable bit 0 1 Output disable Output enable Caution Be sure to write a 0 in bit 2 of the CLOM. 59 PD75238 (4) Application to remote control output The clock output function of the PD75238 is applicable to remote control output. The frequency of the carrier for remote control output is selected by the clock frequency select bit of the clock output mode register. Pulse output is enabled or disabled by controlling the clock output enable/disable bit by software. The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output. Fig. 4-22 Application to Remote Control Output CLOM. 3 PCL pin output 60 PD75238 4.4 BASIC INTERVAL TIMER (1) Configuration of the basic interval timer Fig. 4-23 shows the configuration of the basic interval timer. (2) Basic interval timer functions The basic interval timer provides the following four functions: (a) Reference time generation (four time intervals) (b) Application of watchdog timer for detecting program crashes (c) Selection of a wait time for releasing the standby mode, and counting (d) Reading the count value Fig. 4-23 From the clock generator fX/25 fX/27 MPX fX/29 fX/212 Configuration of the Basic Interval Timer Clear Clear Set Basic interval timer (8-bit frequency divider circuit) BT interrupt request flag Vector interrupt request signal BT IRQBT 3 Wait release signal for standby release BTM0 BTM 8 Internal bus BTM3 SET1 Note BTM2 BTM1 4 Note Instruction execution 61 PD75238 (3) Basic interval timer mode register (BTM) BTM is a 4-bit register that controls operation of the basic interval timer. The BTM contents are set by using a 4-bit memory manipulation instruction. Bit 3 can be independently set using a bit manipulation instruction. When bit 3 is set to 1, the contents of the basic interval timer are cleared, and the basic interval timer interrupt request flag (IRQBT) is also cleared (to start the basic interval timer). A RESET input clears the contents to 0, and the longest interrupt request signal generation interval time is set. Fig. 4-24 Address F85H 3 BTM3 2 BTM2 1 BTM1 Format of the Basic Interval Timer Mode Register 0 Symbol BTM BTM0 (Frequency when fX = 6.0 MHz) Input clock specification 0 0 1 1 0 1 0 1 0 1 1 1 fX/212 (1.46 kHz) fX/29 (11.7 kHz) fX/2 (46.9 kHz) fX/2 (188 kHz) Not to be set 5 7 Interrupt interval time (wait time for releasing standby) 20 2 /fX (175 ms) 217/fX (21.8 ms) 2 /fX (5.46 ms) 2 /fX (1.37 ms) - 13 15 Other setting (Frequency when fX = 4.19 MHz) Input clock specification 0 0 1 1 0 1 0 1 0 1 1 1 fX/2 12 Interrupt interval time (wait time for releasing standby) 2 /fX (250 ms) 17 2 /fX (31.3 ms) 20 (1.02 kHz) 9 fX/2 (8.18 kHz) fX/27 (32.768 kHz) fX/25 (131 kHz) Not to be set 215/fX (7.82 ms) 13 2 /fX (1.95 ms) Other setting - Basic interval timer start control bit When "1" is written to this bit, the basic interval timer operation starts (the counter and the interrupt request flag are cleared). When the operation starts, this bit is automatically reset to 0. 62 PD75238 (4) Operation of the basic interval timer The basic interval timer (BT) is always incremented by the clock supplied from the clock generator, and when it overflows, the interrupt request flag (IRQBT) is set. The count operation of BT cannot be stopped. One of four interrupt generation intervals can be selected by setting BTM. (See Fig. 4-24.) The basic interval timer and the interrupt request flag can be cleared by setting bit 3 of BTM to 1 (instruction for starting as an interval timer). The count status can be read by using an 8-bit manipulation instruction. No data can be loaded to the timer. Caution When reading the count value of the basic interval timer, execute a read instruction twice so that unstable data which has been counted will not be read. If the two read values are reasonable, use the second one as the result. If the two read values are far apart, retry from the beginning. To allow the system clock to stabilize after releasing the STOP mode, a wait function is available which stops the operation of the CPU until the basic interval timer overflows. The wait time after a RESET input is fixed. On the other hand, a wait time can be selected by setting BTM when releasing the STOP mode with an interrupt occurrence. In this case, the wait times are the same as the interval times shown in Fig. 4-24. BTM must be set before the STOP mode is set. (For details, see Chapter 6.) 4.5 TIMER/EVENT COUNTER (1) Functions of the timer/event counter The timer/event counter has the following functions. (a) Programmable interval timer operation (b) Output of a square wave at a given frequency to the PTO0 pin (c) Event counter operation (d) Frequency divider operation that divides TI0 pin input by N and outputs the result to the PTO0 pin (e) Supply of serial shift clock signal to a serial interface circuit (f) Function of reading the state of counting 63 64 8 PORT1.3 P13/ TI0Note 2 Input buffer From the clock generator Event counter #1 Fig. 4-25 Block Diagram of the Timer/Event Counter Internal bus SET1 Note 1 TM0 8 8 TMOD0 Modulo register (8) TOE0 TO enable flag PORT2.0 P20 output latch Bit 2 of PGMB TM07 TM06 TM05 TM04 TM03 TM02 Port 2 input/ output mode 8 Match To serial interface TOUT F/F Reset T0 INTT0 Output buffer P20/PTO0 Comparator (8) 8 Count register (8) MPX CP Clear IRQT0 set signal Timer operation start signal RESET (See Fig. 4-26.) IRQT0 clear signal Notes 1. Instruction execution 2. The P13/TI0 pin is an external event pulse input pin shared between timer/event counter and event counter. PD75238 PD75238 (2) Timer/event counter mode register (TM0) and timer/event counter output enable flag (TOE0) The timer/event counter mode register (TM0) is an 8-bit register for controlling the timer/event counter. It is set by an 8-bit memory manipulation instruction. Fig. 4-27 shows the format of the timer/event counter mode register. Bit 3 is the timer start bit, and can be set independently of the other bits. Bit 3 is automatically reset to 0 when the timer starts operation. A RESET input clears all the bits of the TM0 to 0. The timer/event counter output enable flag (TOE0) enables or disables output of the timer out F/F (TOUT F/F) status to the PTO0 pin. Fig. 4-26 shows the format of the timer/event counter output enable flag. The timer out F/F (TOUT F/F) can be inverted by a match signal sent out from the comparator. The timer out F/F is reset when an instruction sets bit 3 of the TM0. A RESET input clears the TOE0 and TOUT F/F to 0. Fig. 4-26 Address FA2H Format of the Timer/Event Counter Output Enable Flag 3 TOE0 Timer/event counter output enable flag 0 1 Disables Enables 65 PD75238 Fig. 4-27 Address FA0H Format of the Timer/Event Counter Mode Register Symbol TM0 7 -- 6 TM06 5 4 3 2 1 -- 0 -- TM05 TM04 TM03 TM02 Operation mode Count operation Halts (retains the contents of counting) Count operation 0 1 Timer start specification bit When "1" is written to this bit, the counter and the IRQT0 flag are cleared. Count operation starts if bit 2 has been set to 1. Count pulse (CP) select bit (Frequency when fX = 6.0 MHz) TM06 TM05 0 0 1 1 1 1 0 0 0 0 1 1 TM04 0 1 0 1 0 1 Count pulse (CP) TI0 input rising edge TI0 input falling edge fX/210 (5.86 kHz) fX/28 (23.4 kHz) fX/26 (93.8 kHz) fX/24 (375 kHz) Not to be set Other setting (Frequency when fX = 4.19 MHz) TM06 TM05 0 0 1 1 1 1 0 0 0 0 1 1 TM04 0 1 0 1 0 1 Count pulse (CP) TI0 input rising edge TI0 input falling edge fX/210 (4.09 kHz) fX/28 (16.4 kHz) fX/26 (65.5 kHz) 4 fX/2 (262 kHz) Other setting Not to be set 66 PD75238 (3) Operation mode of the timer/event counter The timer/event counter operates in the count operation disable mode or in the count operation mode, depending on the setting of the mode register. The following operations are possible, regardless of the setting of the mode register: (i) P13/TI0 pin signal input and test (ii) Output of the timer out F/F status to the PTO0 (iii) Setting of the modulo register (TMOD0) (iv) Reading from the count register (T0) (v) Setting, clearing, and testing of the interrupt request flag (IRQT0) (a) Count operation disable mode This mode is set when bit 2 of TM0 is set to 0. In this mode, count operation is not performed because count pulse (CP) supply to the count register is stopped. (b) Count operation mode This mode is set when bit 2 of TM0 is set to 1. In this mode, a count pulse signal selected with bits 4 to 6 is supplied to the count register for count operation as shown in Fig. 4-28. Timer operation is usually started in the following steps: 1 2 A count value is set in the modulo register (TMOD0). An operation mode, count clock, and start instruction are set in the mode register (TM0). An 8-bit data transfer instruction is used to set the modulo register. Fig. 4-28 Operation in the Count Operation Mode TI0 INTT0 (IRQT0 set signal) Internal clock MPX CP Count register (T0) Clear Comparator Match TOUT F/F PTO0 Modulo register (TMOD0) To serial interface (channel 0) 67 PD75238 (4) Time setting in the timer/event counter [Timer set time] (period) is [value of the modulo register + 1] divided by [count pulse frequency] selected by the timer mode register. (n + 1) fCP T(sec) : Timer set time (seconds) fCP (Hz) : Count pulse frequency (Hz) n : Value in the modulo register (n = 0) T(sec) = = (n + 1) * (resolution) Once the timer is set, the interrupt request signal (IRQT0) is generated at set time intervals. Table 4-3 indicates the resolution and maximum set time (set when FFH is set in the modulo register) of the timer/ event counter for each count pulse signal. Table 4-3 (When fX = 6.0 MHz) Mode register TM06 TM05 TM04 1 1 1 1 0 0 1 1 0 1 0 1 Resolution 171 s 42.7 s 10.7 s 2.67 s Timer channel 0 Maximum set time 43.7 ms 10.9 ms 2.73 ms 683 s Resolution and Maximum Set Time (When fX = 4.19 MHz) Mode register TM06 TM05 TM04 1 1 1 1 0 0 1 1 0 1 0 1 Resolution 244 s 61.1 s 15.3 s 3.81 s Timer channel 0 Maximum set time 62.5 ms 15.6 ms 3.91 ms 977 s 68 PD75238 4.6 CLOCK TIMER (1) Clock timer The PD75238 contains one channel for a clock timer. Fig. 4-29 shows the configuration of the timer. (2) Clock timer functions (a) The clock timer sets the test flag (IRQW) every 0.5 seconds. The standby mode can be released with IRQW. (b) Either the main system clock (4.19 MHz) or subsystem clock (32.768 kHz) can produce 0.5-second intervals. (c) The fast-forward mode produces an interval 128 times faster (3.91 ms), which is useful for program debugging and testing. (d) A fixed frequency (2.048, 4.096, or 32.768 kHz) can be output to the P23/BUZ pin, so that it can be used for sounding the buzzer and system clock frequency trimming. (e) The frequency divider can be cleared, so the clock can start from zero seconds. Fig. 4-29 Block Diagram of the Clock Timer fW 2 7 (256 Hz: 3.91 ms) From the clock generator fX 128 (32.768 kHz) fXT (32.768 kHz) fW (32.768 kHz) Selector fW 8 fW 16 fW 2 Frequency divider (4.096 kHz) Clear 2 Hz 0.5 sec 14 Selector INTW IRQW set signal Selector Output buffer P23/BUZ WM WM7 0 WM5 WM4 0 WM2 WM1 WM0 PORT2.3 P23 output latch Bit 2 of PMGB Port 2 input/ output mode 8 Internal bus Remark Caution The values in parentheses are for fX = 4.194304 MHz and fXT = 32.768 kHz When the main system clock operates at 6.0 MHz, a time interval of 0.5 s cannot be produced. Before producing this time interval, the main system clock must be changed to the subsystem clock. 69 PD75238 (3) Watch mode register (WM) The watch mode register (WM) is an 8-bit register that controls the clock timer, and that is set with an 8-bit memory manipulation instruction. Fig. 4-30 shows the format. An 8-bit memory manipulation instruction is used to set the watch mode register. A RESET input clears all bits to 0. Fig. 4-30 Address F98H 7 WM7 6 0 5 WM5 4 WM4 Format of the Clock Mode Register 3 0 2 WM2 1 WM1 0 WM0 Symbol WM Count clock (fW) selection bit 0 WM0 1 Selects subsystem clock: fXT Selects divided system clock output: fX 128 Operation mode selection bit 0 WM1 1 Normal clock mode ( fW : sets IRQW at 0.5 s) 214 fW : sets IRQW at 3.91 ms) 7 2 Advanced clock mode ( Clock operation enable/disable bit 0 WM2 1 Enables clock operation Disables clock operation (clears the frequency dividing circuit) BUZ output frequency selection bit WM5 WM4 0 0 BUZ output frequency fW/24 (2.048 kHz) fW/23 (4.096 kHz)Note 0 1 1 0 Not to be set fW (32.768 kHz)Note 1 1 Note Not supported by the IE-75000-R. BUZ output enable/disable bit 0 WM7 1 Enables BUZ output Disables BUZ output 70 PD75238 4.7 TIMER/PULSE GENERATOR (1) Timer/pulse generator functions The PD75238 contains one channel for a timer/pulse generator that can be used as a timer or a pulse generator. It has the following functions: (a) Functions available when the timer/pulse generator is used in the timer mode * 8-bit interval timer operation using one of five clock sources (occurrence of IRQTPG) * Square wave output to the PPO pin (b) Functions available when the timer/pulse generator is used in the PWM pulse generation mode * PWM pulse output to the PPO pin with an accuracy of 14 bits (applicable for electronic tuning when used as an D/A converter) * Generation of interrupts at regular intervals (215/fX = 5.46 ms at 6.0 MHz)Note Note 7.81 ms at 4.19 MHz If pulse output is unnecessary, the PPO pin can be used as a 1-bit output port. Caution If the timer/pulse generator is operating when the STOP mode is set, it may malfunction. So the timer/pulse generator must be disabled with the mode register in advance. 71 PD75238 (2) Timer/pulse generator mode register (TPGM) The timer/pulse generator mode register (TPGM) is an 8-bit register that controls operation of the timer/ pulse generator. Fig. 4-31 shows the format of the register. TPGM is set with an 8-bit memory manipulation instruction. Bit 3 enables or disables the transfer (reloading) of the timer/pulse generator modulo register (MODH and MODL) contents to the modulo latch. Bit 3 can be manipulated independently of the other bits. By setting TPGM1 to 0, timer/pulse generator operation can be stopped to decrease current consumption. A RESET input clears all bits to 0. Fig. 4-31 Address F90H Format of Timer/Pulse Generator Mode Register Symbol TPGM 7 TPGM7 6 -- 5 4 3 2 0 1 0 TPGM5 TPGM4 TPGM3 TPGM1 TPGM0 Timer/pulse generator operation mode selection bit TPGM0 0 1 Select PWM pulse generation mode Select timer mode Timer/pulse generator operation enable/disable bit TPGM1 0 1 Disable timer/pulse generator operation Enable timer/pulse generator operation Modulo register reload enable/disable bit TPGM3 0 1 Disable reloading of modulo register Enable reloading of modulo register PPO output latch data TPGM4 0 1 Output 0 to PPO output latch Output 1 to PPO output latch PPO pin output selection bit static/pulse TPGM5 0 1 Static output on PPO pin Pulse output (square wave/PWM) on PPO pin PPO pin output enable/disable bit TPGM7 0 1 Disable output on PPO pin (high-impedance) Enable output on PPO pin 72 PD75238 (3) Configuration and operation when the timer/pulse generator is used in the timer mode Fig. 4-32 shows the configuration when the timer/pulse generator is used in the timer mode. The timer mode is selected by setting bit 0 of TPGM to 1. In the timer mode, TPGM3 must be set to 1, allowing a modulo register to be reloaded at any time. In the timer mode, a prescaler is selected with the modulo register L (MODL), and a frequency or interrupt interval value is set in the modulo register H (MODH). The timer starts when the TPGM1 is set to 1. Fig. 4-33 shows the operation timing for the MODH setting, and Table 4-4 shows the setting of a frequency or interrupt interval. The output to the PPO pin can be switched between the square wave output and static output. To output a square wave, set TPGM5 and TPGM7 to 1. Fig. 4-32 Block Diagram of the Timer/Pulse Generator (Timer Mode) Internal bus 8 MODL Modulo register L (8) TPGM3 (Set to 1) 8 MODH Modulo register H (8) Modulo latch H (8) 8 Match Comparator (8) Frequency divider fX 1/2 TPGM1 Clear Clear Prescaler select latch (5) T F/F Set Selector INTTPG IRQTPG set signal Output buffer PPO CP 8 Count register (8) TPGM4 TPGM5 TPGM7 Caution When the timer operating in the timer operation mode is stopped, IRQTPG may be set because T F/F is set. So, the timer must be stopped with an interrupt being disabled, then IRQTPG must be cleared. 73 PD75238 Fig. 4-33 CP Timer Mode Operation Timing MODH Count register T F/F (PPO) N 0 1 2 N-1 N 0 N 0 N 0 Set TPGM1. Generate IRQTPG. Table 4-4 (When fX = 6.0 MHz) MODL bits 2-6 6 0 0 0 0 1 5 0 0 0 1 0 4 0 0 1 0 0 3 0 1 0 0 0 2 1 0 0 0 0 Modulo Register Settings Interrupt generation interval (fX = 6.0 MHz) 256 (N+1)/fX = 85.3 s - 10.9 ms 128 (N+1)/fX = 42.7 s - 5.45 ms 64 (N+1)/fX = 21.3 s - 2.73 ms 32 (N+1)/fX = 10.7 s - 1.37 ms 16 (N+1)/fX = 5.33 s - 683 s Square wave output frequency (fX = 6.0 MHz) fX/256 (N+1) = 91.6 Hz - 11.7 kHz fX/128 (N+1) = 183 Hz - 23.4 kHz fX/64 (N+1) = 366 Hz - 46.9 kHz fX/32 (N+1) = 732 Hz - 93.8 kHz fX/16 (N+1) = 1465 Hz - 188 kHz (When fX = 4.19 MHz) MODL bits 2-6 6 0 0 0 0 1 5 0 0 0 1 0 4 0 0 1 0 0 3 0 1 0 0 0 2 1 0 0 0 0 Interrupt generation interval (fX = 4.19 MHz) 256 (N+1)/fX = 122 s - 15.6 ms 128 (N+1)/fX = 61.0 s - 7.81 ms 64 (N+1)/fX = 30.5 s - 3.91 ms 32 (N+1)/fX = 15.3 s - 1.95 ms 16 (N+1)/fX = 7.63 s - 977 s Square wave output frequency (fX = 4.19 MHz) fX/256 (N+1) =64 Hz - 8 kHz fX/128 (N+1) = 128 Hz - 16 kHz fX/64 (N+1) = 256 Hz - 32 kHz fX/32 (N+1) = 512 Hz - 65 kHz fX/16 (N+1) = 1024 Hz - 131 kHz Cautions 1. A value other than the above cannot be set in MODL. Bits 0, 1, and 7 must be set to 0. 2. N is the set value of MODH. 0 must not be set for N. Be sure to set a value from 1 to 255 for N. 74 PD75238 (4) Configuration and operation when the timer/pulse generator is used in the PWM pulse generation mode Fig. 4-34 shows the configuration when the timer/pulse generator is used in the PWM pulse generation mode. The PWM pulse generation mode is selected by setting TPGM0 to 0. TPGM5 and TPGM7 are set to 1 to enable pulse output. In the PWM mode, the PWM pulse signal can be output on the PPO pin, and IRQTPG can be set at intervals of a fixed time period (215 /fX = 5.46 ms at 6.0 MHz)Note 1. PWM pulses output by the PD75238 are active-low and have an accuracy of 14 bits. This pulse signal is applicable for electronic tuning and control of a DC motor when it is integrated by an external low-pass filter and is converted to analog voltage. (See Fig. 4-35.) The PWM pulse signal is generated by combining the basic period determined by 2 10 /fX (171 s at 6.0 MHz) Note 2 and the secondary period by 215 /fX (5.46 ms at 6.0 MHz) Note 1 so that the time constant of the external low-pass filter can be decreased. The low-level width of a PWM pulse depends on the 14-bit modulo latch value. The upper 8 bits of the modulo latch are sent from the 8 bits of MODH, and the lower 6 bits of the latch are sent from the upper 6 bits of MODL. When the PWM pulse signal is converted to analog form, the voltage level of the analog output is obtained as follows: VAN = Vref x Value of modulo latch 2 14 Vref: Reference voltage of external switching circuitry To prevent an incorrect PWM pulse from being output by unstable modulo latch data being rewritten, the PD75238 allows correct data to be written in MODH and MODL beforehand with 8-bit manipulation instructions, then in the 14-bit data which is to be transferred to the modulo latch at one time. This transfer operation is referred to as reloading, and it is controlled by TPGM3. Cautions 1. If the modulo register H (MODH) is set to 0, the PWM pulse generator cannot function normally. So be sure to set MODH to a value from 1 to 255. 2. If the lower 2 bits of the modulo register L (MODL) are read, the read result is unpredictable. 3. If the modulo latch is changed in a shorter period than the PWM pulse basic period 210/fX (171 s at 6.0 MHz)Note 2, PWM pulses do not change. Notes 1. 2. 7.81 ms at 4.19 MHz 244 s at 4.19 MHz (5) Static output to the PPO pin When pulse output is unnecessary, the PPO pin can be used as normal static output. In this case, the output data is set in TPGM4 with TPGM5 being set to 0 and TPGM7 to 1. 75 PD75238 Fig. 4-34 Block Diagram of the Timer/Pulse Generator (PWM Pulse Generation Mode) Internal bus 8 MODH Modulo register H (8) 8 MODL Modulo register L (6) (2) TPGM3 MODH (8) Modulo latch (14) TPGM1 fX 1/2 Frequency divider MODL7-2 (6) Output buffer Selector PPO PWM pulse generator INTTPG (IRQTPG set signal) (215/fX = 5.46 ms: 6.0 MHz) Note TPGM5 TPGM7 Note 7.81 ms at 4.19 MHz Fig. 4-35 Sample Configuration of D/A Conversion Using PD75238 Vref PD75238 PPO PWM signal Switching circuit Low-pass filter VAN (analog voltage) 76 PD75238 4.8 EVENT COUNTER (1) Configuration of the event counter The event counter of the PD75238 has a noise eliminator. Fig. 4-36 shows the configuration of the counter. Fig. 4-36 Block Diagram of the Event Counter Timer/counter #0 GATEC.0 TM1.4 Selector Noise eliminator fx 4 TM1.2 8-bit counter Overflow flag T1 IRQT1 Internal bus Caution The TI0/P13 pin is an external event pulse input pin shared between timer/event counter #0 and event counter #1. (2) Event counter functions The event counter provides the following functions: (a) Event counter operation (b) Function of reading the state of counting (c) Count pulse edge specification (d) Noise elimination function Selector TI0/P13 77 PD75238 (3) Event counter mode register The event counter mode register (TM1) is an 8-bit register that controls the event counter. Fig. 4-37 shows the format of the register. The TM1 is set with an 8-bit memory manipulation instruction. Bit 3 is an event counter start bit, and can be set independently of the other bits. Bit 3 is automatically reset to 0 when the timer starts operation. Fig. 4-37 Format of the Event Counter Mode Register Address FA8H 7 0 6 0 5 0 4 TM14 3 TM13 2 TM12 1 0 0 0 Symbol TM1 Event count operation enable/disable bit 0 TM12 1 Enables count operation Disables count operation (count value retained) Event count start instruction bit When 1 is written, the counter and the IRQ1 flag are cleared. IF TM12 is set to 1, count opertaion starts. TM13 Count pulse edge specification 0 TM14 1 TI0 input falling edge TI0 input rising edge (4) Overflow flag (IRQT1) The overflow flag is set to 1 when the event counter (IRQT1) overflows. The flag is cleared to 0 by a count operation start instruction. (5) Event counter control register (GATEC) This register specifies sampling by sampling clock (fX/4). A noise eliminator eliminates pulses narrower than two sampling clock cycles (8/fX) as noise and accepts pulses wider than as interrupt signals. Fig. 4-38 shows the format of the GATEC. Fig. 4-38 Address FABH 3 0 Format of the Event Counter Control Register 2 0 1 0 0 GATEC0 Symbol GATEC 0 1 No sampling Sampling at fX/4 78 PD75238 4.9 SERIAL INTERFACE The PD75238 has two channels of clock synchronous 8-bit serial interface: Channel 0 and channel 1. Table 4-5 lists the differences between channel 0 and channel 1. Table 4-5 Serial transfer mode, function 3-wire serial I/O Clock selection Transfer method Transfer end flag Differences between Channel 0 and Channel 1 Channel 0 fX/24 , fX/23, TOUT F/F, external clock Start bit switchable: MSB/LSB Serial transfer end interrupt request flag (IRQCSI0) Available Channel 1 fX/24 , fX/23, external clock Start bit: MSB Serial transfer end flag (EOT) 2-wire serial I/O Serial bus interface Not available 79 PD75238 (1) Serial interface (channel 0) functions The serial interface (channel 0) of the PD75238 has following four different modes. The functions of the four modes are outlined below. * Operation halt mode This mode is used when serial transfer is not performed. This mode reduces power consumption. * Three-wire serial I/O mode In this mode, 8-bit data is transferred through three lines: Serial clock (SCK0), serial output (SO0), and serial input (SI0). The three-wire serial I/O mode allows full-duplex transmission, so data transfer can be performed at higher speed. The user can choose 8-bit data transfer starting with the MSB or LSB, so devices starting with either the MSB or LSB can be connected. The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many other types of peripheral I/O devices. * Two-wire serial I/O mode In this mode, 8-bit data is transferred through two lines: Serial clock (SCK0) and serial data bus (SB0 or SB1). By controlling output levels on the two lines by software, communication with multiple devices is enabled. The output levels of SCK0 and SB0 (or SB1) can be controlled by software, so the user can match an arbitrary transfer format. This means that a line that has been required for handshaking to connect multiple lines can be eliminated for more efficient I/O port utilization. * Serial bus interface (SBI) mode In this mode, communication with multiple devices can be performed using two lines: Serial clock (SCK0) and serial data bus (SB0 or SB1). This mode conforms to the NEC serial bus format. In this mode, the sender can output, on the serial data bus, an address for selecting a device subject to serial communication, commands directed to the remote device, and data. The receiver can identify an address, commands, and data from received data by hardware. This function enables more efficient I/O port utilization as in the case of the two-wire serial I/O mode. In addition, this function can simplify the serial interface control portion of an application program. (2) Configuration of serial interface (channel 0) Fig. 4-39 shows the block diagram of the serial interface (channel 0). 80 Fig. 4-39 Block Diagram of the Serial Interface (Channel 0) Internal bus 8/4 CSIM0 Bit test 8 8 8 Slave address register (SVA) (8) Coincidence RELT signal Address comparator P03/SI0/SB1 SET CLR SO0 latch Selector Shift register (SIO0) (8) D Q (8) CMDT SBIC Bit manipulation Bit test ACKE ACKT P02/SO0/SB0 Selector Bus release/ command/ acknowledge detection circuit P01/SCK0 RELD CMDD ACKD Busy/ acknowledge output circuit BSYE Serial clock counter INTCSI0 control circuit INTCSI0 RQCSI0 set signal 3 P01 output latch Serial clock control circuit Serial clock selector fX/2 4 fX/2 6 fX/2 TOUT F/F (from timer/event counter) External SCK0 PD75238 81 PD75238 (3) Functions of serial interface (channel 0) registers (a) Serial operation mode register 0 (CSIM0) Fig. 4-40 shows the format of serial operation mode register 0 (CSIM0). CSIM0 is an 8-bit register which specifies a serial interface (channel 0) operation mode, serial clock, wake-up function, and so forth. CSIM0 is manipulated using an 8-bit memory manipulation instruction. The higher three bits can be manipulated bit by bit. Each bit can be manipulated using its name. Each bit may or may not allow read and/or write operation. (See Fig. 4-40.) Bit 6 allows bit test operation only; any data written to this bit is invalid. A RESET input clears all bits to 0. Fig. 4-40 Address 7 FE0H CSIE0 6 COI Format of Serial Operation Mode Register 0 (CSIM0) (1/3) Symbol 5 4 3 2 1 0 CSIM0 WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Serial clock selection bit (W) Serial interface operation mode selection bit (W) Wake-up function specification bit (W) Signal from address comparator (R) Serial interface operation enable/disable specification bit (W) Remark (R) : Read only (W) : Write only 82 PD75238 Fig. 4-40 Serial clock selection bit (W) Serial clock CSIM01 0 0 1 1 CSIM00 3-wire serial I/O mode 0 1 0 1 fX/24 SBI mode 2-wire serial I/O mode Input Output fX/26 (65.5 kHz or 93.8 kHz) Note External clock applied to SCK0 pin Time/event counter output (T0) (262 kHz or 375 kHz)Note SCK0 pin mode Format of Serial Operation Mode Register 0 (CSIM0) (2/3) fX/23 (524 kHz or 750 kHz)Note Note The values in parentheses are for fX = 4.19 MHz or 6.0 MHz. Serial interface operation mode selection bit (W) Bit sequence for shift register 0 SIO07-0 XA (Transfer starting with MSB) SIO00-7 XA (Transfer starting with LSB) SIO07-0 XA (Transfer starting with MSB) CSIM04 x CSIM03 0 CSIM02 0 Operation mode 3-wire serial I/O mode SO0 pin function SO0/P02 (CMOS output) SI0 pin function SI0/P03 (Input) 1 0 1 0 SBI mode SB0/P02 (N-ch open-drain input/output) P02 input P03 input 1 SB1/P03 (N-ch open-drain input/output) P03 input 0 1 1 2-wire serial I/O mode SIO07-0 XA (Transfer starting with MSB) SB0/P02 (N-ch open-drain input/output) P02 input 1 SB1/P03 (N-ch open-drain input/output) Remark x: Don't care Wake-up function specification bit (W) WUP 0 1 Sets IRQCSI0 each time serial transfer is completed in each mode. Used in the SBI mode only to set IRQCSI0 only when an address received after bus release matches the data in the slave address register (wake-up state). SB0/SB1 goes to high-impedance state. Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode, the BUSY signal is output until the next falling edge of the serial clock (SCK0) appears after release of BUSY is directed. Before setting WUP = 1, be sure to confirm that the SB0 (or SB1) pin is high after releasing BUSY. 83 PD75238 Fig. 4-40 Format of Serial Operation Mode Register 0 (CSIM0) (3/3) Signal from address comparator (R) COINote Condition for being cleared (COI = 0) When the slave address register (SVA) does not match the data of the shift register Condition for being set (COI = 1) When the slave address register (SVA) matches the data of the shift register Note COI can be read only before serial transfer is started or after serial transfer is completed. An undefined value may be read during transfer. COI data written by an 8-bit manipulation instruction is ignored. Serial interface operation enable/disable specification bit (W) Shift register 0 operation CSIE0 0 1 Shift operation disabled Shift operation enabled Serial clock counter Cleared Count operation IRQCSI0 flag Held Can be set. SO0/SB0, SI0/SB1 pin Used only for port 0 Used in each mode as well as for port 0 Remarks 1. Each mode can be selected by setting CSIE0, CSIM03, and CSIM02. CSIE0 0 1 1 1 CSIM03 CSIM02 x 0 1 1 x x 0 1 Operation mode Operation halt mode Three-wire serial I/O mode SBI mode Two-wire serial I/O mode 2. The P01/SCK0 pin assumes the following state according to the setting of CSIE0, CSIM01, and CSIM00: CSIE0 0 1 0 0 0 1 1 1 CSIM01 CSIM00 0 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 Serial clock output (High level output) Input port High impedance High level output P01/SCK0 pin state 84 PD75238 Remarks 3. When clearing CSIE0 during serial transfer, use the following procedure: 1 2 3 Disable interrupts by clearing the interrupt enable flag. Clear CSIE0. Clear the interrupt request flag. Examples 1. fX/2 4 is selected as the serial clock, serial interrupt IRQCSI0, is generated each time serial transfer is completed, and serial transfer is performed in the SBI mode with the SB0 pin used as the serial data bus. SEL MOV MOV MB15 XA, #10001010B CSIM0, XA ; CSIM0 10001010B ; or CLR1 MBE 2. Serial transfer dependent on the contents of CSIM0 is enabled. SEL SET1 MB15 CSIE0 ; or CLR1 MBE 85 PD75238 (b) Serial bus interface control register (SBIC) Fig. 4-41 shows the format of the serial bus interface control register (SBIC). SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus. SBIC is used mainly in the SBI mode. SBIC is manipulated using a bit manipulation instruction. SBIC cannot be manipulated using a 4-bit or 8-bit memory manipulation instruction. Each bit may or may not allow read and/or write operation. (See Fig. 4-41.) A RESET input clears all bits to 0. Caution Only the following bits can be used in the three-wire and two-wire serial I/O modes: * Bus release trigger bit (RELT): Sets the SO0 latch. * Command trigger bit (CMDT): Clears the SO0 latch. Fig. 4-41 Format of Serial Bus Interface Control Register (SBIC) (1/3) Address 7 FE2H BSYE 6 ACKD 5 ACKE 4 ACKT 3 CMDD 2 RELD 1 CMDT 0 RELT Symbol SBIC Bus release trigger bit (W) Command trigger bit (W) Bus release detection flag (R) Command detection flag (R) Acknowledge trigger bit (W) Acknowledge enable bit (R/ W) Acknowledge detection flag (R) Busy enable bit (R/ W) Remarks 1. 2. 3. (R) : Read only (W) : Write only (R/W): Read/write 86 PD75238 Fig. 4-41 Bus release trigger bit (W) RELT Control bit for bus release signal (REL) trigger output. By setting RELT = 1, the SO0 latch is set to 1. Then the RELT bit is automatically cleared to 0. Format of Serial Bus Interface Control Register (SBIC) (2/3) Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial transfer. Command trigger bit (W) CMDT Control bit for command signal (CMD) trigger output. By setting CMDT = 1, the SO0 latch is cleared to 0. Then the CMDT bit is automatically cleared to 0. Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial transfer. Bus release detection flag (R) RELD 1 2 3 4 Condition for being cleared (RELD = 0) The transfer start instruction is executed. The RESET signal is entered. CSIE0 = 0 (See Fig. 4-40.) SVA does not match SIO0 when an address is received. Condition for being set (RELD = 1) The bus release signal (REL) is detected. Command detection flag (R) CMDD 1 2 3 4 Condition for being cleared (CMDD = 0) The transfer start instruction is executed. The bus release signal (REL) is detected. The RESET signal is entered. CSIE0 = 0 (See Fig. 4-40.) Condition for being set (CMDD = 1) The command signal (CMD) is detected. Acknowledge trigger bit (W) ACKT When set after transfer, ACK is output in phase with the next SCK0. After ACK signal output, this bit is automatically cleared to 0. Cautions 1. 2. 3. Never set ACKT before or during serial transfer. ACKT cannot be cleared by software. Before setting ACKT, set ACKE = 0. Acknowledge enable bit (R/W) ACKE 0 1 Disables automatic output of the acknowledge signal (ACK). (Output by ACKT is possible.) When set before transfer When set after transfer ACK is output in phase with the 9th clock of SCK0. ACK is output in phase with SCK0 immediately following set instruction execution. 87 PD75238 Fig. 4-41 Format of Serial Bus Interface Control Register (SBIC) (3/3) Acknowledge detection flag (R) ACKD 1 2 Condition for being cleared (ACKD = 0) The transfer start instruction is executed. The RESET signal is entered. Condition for being set (ACKD = 1) The acknowledge signal (ACK) is detected (in phase with the rising edge of SCK0). Busy enable bit (R/W) 1 2 The busy signal is automatically disabled. Busy signal output is stopped in phase with the falling edge of SCK0 immediately after clear instruction execution. BSYE 0 1 The busy signal is output after the acknowledge signal in phase with the falling edge of SCK0. Examples 1. A command signal is output. SEL SET1 accordingly. By setting WUP = 1, this interrupt routine is processed only when an address match is found. SEL SKF BR SKT BR CMD : DATA : ADRS : MB15 RELD !ADRS CMDD !DATA ; Command analysis ; Data processing ; Address decode ; CMDD test ; RELD test MB15 CMDT ; or CLR1 MBE 2. RELD and CMDD are tested to identify the types of received data and the types of processing **************** **************** **************** 88 PD75238 (c) Shift register (SIO0) Fig. 4-42 shows the configuration of peripheral hardware of shift register 0. SIO0 is an 8-bit register which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock. Serial transfer is started by writing data to SIO0. In send operation, data written to SIO0 is output on the serial output (SO0) or serial data bus (SB0/ SB1). In receive operation, data is read from the serial input (SI0) or SB0/SB1 into SIO0. Data can be read from or written to SIO0 by using an 8-bit manipulation instruction. When the RESET signal is entered during operation, the value of SIO0 is undefined. When the RESET signal is entered in the standby mode, the value of SIO0 is preserved. Shift operation is stopped after 8-bit send or receive operation is completed. Fig. 4-42 Peripheral Hardware of Shift Register 0 Internal bus Address comparator RELT CMDT Shift register 0 SET D CLK CSIM0 Shift clock CLR Q SO0 latch BUSY/ACK N-ch open-drain output The timing for reading SIO0 and start of serial transfer (writing to SIO0) is as follows: * When the serial interface operation enable/disable bit (CSIE0) = 1. However, the case where CSIE0 is set to 1 after data is written to the shift register is excluded. * When the serial clock is masked after 8-bit serial transfer * SCK0 is high. When reading from or writing to SIO0, make sure that SCK0 is high. In the two-wire serial I/O mode and SBI mode, the pins specified for the data bus are used for both input and output. Because the configuration of output pins is N-ch open-drain, write FFH in SIO0 for devices that are to receive data. 89 PD75238 (d) Slave address register (SVA) The slave address register (SVA) has the two functions described below. SVA is manipulated using an 8-bit manipulation instruction. SVA allows only write operation. When a RESET is entered, the value of SVA is undefined. However, the value of SVA is preserved when the RESET is entered in the standby mode. * Slave address detection [In the SBI mode] SVA is used when the PD75238 is connected as a slave device to the serial bus. SVA is an 8-bit register for a slave to set its slave address (number assigned to it). The master outputs a slave address to the connected slaves to select a particular slave. Two data values (a slave address output from the master and the value of SVA) are compared with each other by the address comparator. If a match is found, the slave is selected. At this time, bit 6 (COI) of serial operation mode register 0 (CSIM0) is set to 1. Cautions 1. Slave selection or nonselection state is detected by detecting a match for a slave address received after bus release (in the state of RELD = 1). For this match detection, an address match interrupt (IRQCSI0) generated when WUP is set to 1 is usually used. So detect selection/nonselection state by slave address when WUP is set to 1. 2. When detecting selection/nonselection state without using an interrupt when WUP is 0, do not use the address match detection method. Instead, use transfer of commands set in advance in a program. * Error detection [In the two-wire serial I/O mode or SBI mode] SVA detects an error in either of the following cases: * When addresses, commands, or data is transferred with the PD75238 operating as the master * When data is transferred with the PD75238 operating as a slave (4) Signals Table 4-6 lists signals. Fig. 4-43 to 4-48 show operations of signals and flags. 90 Table 4-6 Various Signals Used in the SBI Mode (1/2) Signal name Output device Master Definition Timing chart Condition for output * RELT is set. Flag operation * RELD is set. * CMDD is cleared. Meaning of signal Indicates that CMD signal follows and data sent is address data. Bus release signal (REL) Rising edge of SB0/SB1 when SCK0 = 1 SCK0 SB0/SB1 "H" Command signal (CMD) Master Falling edge of SB0/SB1 when SCK0 = 1 SCK0 SB0/SB1 "H" * CMDT is set. * CMDD is set. i) Data sent after REL signal output is address. ii) Data sent, with REL signal not being output, is command. Indicates completion of receive operation. Acknowledge signal (ACK) Master/ slave Low level signal output on SB0/SB1 during one SCK0 clock cycle after serial receive operation is completed [Synchronous busy signal] Low level signal output on SB0/SB1 after acknowledge signal High level signal output on SB0/SB1 before serial transfer is started or after serial transfer is completed # ACKE = 1 $ ACKT is set. * ACKD is set. [Synchronous busy signal output] Busy signal (BUSY) Slave * BSYE = 1 SCK0 SB0/ SB1 SB0/ SB1 9 - D0 ACK BUSY READY BUSY D0 ACK READY # BSYE = 0 $ Execution of instruction to write data to SIO0 (direction to start transfer) Indicates that serial receive operation is disabled because processing is in progress. Indicates that serial receive operation is enabled. Ready signal (READY) Slave - PD75238 91 92 Signal name Output device Master Definition Serial clock (SCK0) clock cycles. Address (A7 - A0) Master Command (C7 - C0) Master Data (D7 - D0) Master/ slave Table 4-6 Various Signals Used in the SBI Mode (2/2) Timing chart Condition for output Execution of instruction to write data to SIO0 when CSIE0 = 1 (direction to start serial transfer)Note 2 Flag operation IRQCSI0 is set (on rising edge of Note 1 ninth clock) Meaning of signal Timing of signal output on serial data bus Synchronous clock for outputting address/ command/data, ACK SCK0 signal, synchronous BUSY signal, and so on. SB0/ Address/command/data SB1 is output during first 8 1 2 7 8 9 10 8-bit data transferred in phase with SCK0 after REL signal and CMD signal output 8-bit data transferred in phase with SCK0 after only CMD signal is output, with REL signal not being output 8-bit data transferred in phase with SCK0, with neither REL signal nor CMD signal being output SCK0 SB0/ SB1 REL 1 2 7 8 Address of slave device on serial bus CMD Directions and messages to slave device SCK0 SB0/ SB1 CMD 1 2 7 8 SCK0 SB0/ SB1 1 2 7 8 Value processed by slave or master device Notes 1. When WUP = 0, IRQCSI0 is always set on the ninth rising edge of SCK0. When WUP = 1, IRQCSI0 is set on the ninth rising edge of SCK0 only if a received address matches the value of the slave address register (SVA). 2. If the BUSY state is present, data transfer is started after the READY state is set. PD75238 PD75238 Fig. 4-43 Operations of RELT, CMDT, RELD, and CMDD (Master) Transfer operation start specification SIO0 SCK0 "H" SO0 latch RELT CMDT RELD CMDD Fig. 4-44 Operations of RELT, CMDT, RELD, and CMDD (Slave) Write to SIO0 Transfer operation start specification SIO0 SCK0 1 2 7 8 SO0 latch D7 D6 D1 D0 RELT (Master) CMDT (Master) When address match is found RELD When address mismatch is found CMDD Fig. 4-45 Set after transfer completion. Operation of ACKT SCK0 6 7 8 9 ACK signal is output during first clock cycle immediately after ACKT is set. SB0/SB1 D2 D1 D0 ACK ACKT When set during this period Caution Do not set the ACKT until the transfer is completed. 93 PD75238 Fig. 4-46 Operation of ACKE (a) When ACKE = 1 at time of transfer operation completion SCK0 1 2 7 8 9 The ACK signal is output during the ninth clock cycle SB0/SB1 D7 D6 D2 D1 D0 ACK ACKE When ACKE = 1 at this point (b) When ACKE is set after transfer operation completion SCK0 6 7 8 9 The ACK signal is output during the first clock cycle immediately after ACKT is set. SB0/SB1 D2 D1 D0 ACK ACKE When ACKE is set during this period and ACKE = 1 at the falling edge of the next SCK0 (c) When ACKE = 0 at time of transfer operation completion SCK0 1 2 7 8 9 The ACK signal is not output SB0/SB1 D7 D6 D2 D1 D0 ACKE When ACKE = 0 at this point (d) When ACKE = 1 period is too short SCK0 The ACK signal is not output SB0/SB1 ACKE When ACKE is set or cleared during this period, and ACKE = 0 at the falling edge of SCK0 94 PD75238 Fig. 4-47 Operation of ACKD (a) When ACK signal is output during ninth SCK0 clock Transfer operation start specification SIO0 Transfer operation start SCK0 6 7 8 9 SB0/SB1 D2 D1 D0 ACK ACKD (b) When ACK signal is output after ninth SCK0 clock Transfer operation start specification SIO0 Transfer operation start SCK0 6 7 8 9 SB0/SB1 D2 D1 D0 ACK ACKD (c) Clear timing for case where start of transfer is directed during BUSY Transfer operation start specification SIO0 SCK0 6 7 8 9 SB0/SB1 D2 D1 D0 ACK BUSY D7 D6 ACKD Fig. 4-48 SCK0 Operation of BSYE 6 7 8 9 SB0/SB1 ACK BUSY BSYE When BSYE = 1 at this point When reset operation is executed during this period and BSYE = 0 at the falling edge of SCK0. 95 PD75238 (5) Serial interface (channel 0) operation (a) Operation halt mode The operation halt mode is used when serial transfer is not performed. This mode reduces power consumption. The shift register 0 does not perform shift operation in this mode, so the shift register can be used as a normal 8-bit register. A RESET input sets the operation halt mode. The P02/SO0/SB0 pin and P03/SI0/SB1 pin function as input-only port pins. The P01/SCK0 pin can be used as an input port pin by setting the serial operation mode register 0. (b) Three-wire serial I/O mode operations The three-wire serial I/O mode is compatible with other modes used in the 75X series and 78K series. Communication is performed using three lines: Serial clock (SCK0), serial output (SO0), and serial input (SI0). (i) Communication operation The three-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by bit in phase with the serial clock. The shift register performs shift operation on the falling edge of the serial clock (SCK0). Send data is latched on the SO0 latch, and is output on the SO0 pin. Receive data applied to the SI0 pin is latched in the shift register 0 on the rising edge of SCK0. When eight bits have been transferred, shift register 0 operation automatically terminates setting the interrupt request flag (IRQCSI0). Fig. 4-49 Timing of Three-Wire Serial I/O Mode SCK0 1 2 3 4 5 6 7 8 SI0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 IRQCSI0 Completion of transfer Transfer operation is started in phase with falling edge of SCK0. Execution of instruction that writes data to SIO0 (Transfer operation start specification) 96 PD75238 The SO0 pin becomes a CMOS output and outputs the state of the SO0 latch. So the output state of the SO0 pin can be manipulated by setting the RELT bit and CMDT bit. However, this manipulation must not be performed during serial transfer operation. The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the output mode (internal system clock mode). (See (7) in Section 4.9.) (ii) Switching between MSB and LSB as the first transfer bit The three-wire serial I/O mode has a function that can switch between the MSB and LSB as the first bit of transfer. Fig. 4-50 shows the configuration of shift register 0 (SIO0) and internal bus. As shown in Fig. 4-50, read or write operation can be performed by switching between the MSB and LSB. This switching can be specified using bit 2 of serial operation mode register 0 (CSIM0). Fig. 4-50 Transfer Bit Switching Circuit 7 6 Internal bus 1 0 LSB first MSB first Read/write gate Read/write gate SO0 latch SI0 Shift resister 0 (SIO0) D Q SO0 SCK0 The first bit is switched by changing the order of data bits written to shift register 0 (SIO0). The shift operation order of SIO0 is always the same. Accordingly, the first bit must be switched between the MSB and LSB before writing data to the shift register 0. 97 PD75238 (c) Two-wire serial I/O mode The two-wire serial I/O mode can be made compatible with any communication format by programming. In this mode, communication is basically performed using two lines: Serial clock (SCK0) and serial data input/output (SB0 or SB1). (i) Communication operation The two-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by bit in phase with the serial clock. The shift register 0 performs shift operation on the falling edge of the serial clock (SCK0). Send data is latched on the SO0 latch, and is output on the SB0/P02 pin or SB1/P03 pin starting with the MSB. Receive data applied to the SB0 pin or SB1 pin is latched in the shift register 0 on the rising edge of SCK0. When eight bits have been transferred, shift register 0 operation automatically terminates setting the interrupt request flag (IRQCSI0). Fig. 4-51 Timing of Two-Wire Serial I/O Mode SCK0 1 2 3 4 5 6 7 8 SB0/SB1 D7 D6 D5 D4 D3 D2 D1 D0 IRQCSI0 Completion of transfer Transfer operation is started in phase with falling edge of SCK0. Execution of instruction that writes date to SIO0 (Transfer operation start spcification) The SB0 or SB1 pin becomes an N-ch open-drain I/O when specified as the serial data bus, so the voltage level on that pin must be pulled up externally. The state of the SO0 latch is output on the SB0 or SB1 pin, so the SB0 or SB1 pin output states can be controlled by setting the RELT or CMDT bit. However, this operation must not be performed during serial transfer operation. The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the output mode (internal system clock mode). (See (7) in Section 4.9.) 98 PD75238 (d) SBI mode operation The SBI (serial bus interface) is a high-speed serial interface that conforms to the NEC serial bus format. To allow communication with multiple devices on a single-master and high-speed serial bus using two signal lines, the SBI has a bus configuration function added to the clock synchronous serial I/O method. So the SBI can reduce ports and wires on boards when multiple microcomputers and peripheral ICs are used to configure a serial bus. Fig. 4-52 is an example of the SBI system configuration. Fig. 4-52 Example of SBI System Configuration Master CPU PD75238 Slave CPU PD75238 SB0 (SB1) SCK0 SB0 (SB1) Address 1 SCK0 Slave CPU SB0 (SB1) Address 2 SCK0 Slave IC SB0 (SB1) Address N SCK0 Cautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. So the serial data bus line is placed in the wired OR state. A pull-up resistor is required for the serial data bus line. 2. To switch between the master and slave, a pull-up resistor is required also for the serial clock line (SCK0), because SCK0 input/output switching is performed between the master and slave asynchronously. 99 PD75238 (i) SBI functions * Address/command/data identification function Serial data is classified into three types: Address, command, and data. * Address-based chip select function The master selects a chip by address transfer. * Wake-up function A slave can easily check address reception (for chip select identification) with the wake-up function. This function can be set or released by software. When the wake-up function is set, an interrupt (IRQCSI0) is generated when a match address is received. For this reason, in communication with multiple devices, a CPU other than a selected slave can operate independently of serial communication. * Acknowledge signal (ACK) control function The acknowledge signal, which is used to confirm the reception of serial data, can be controlled. * Busy signal (BUSY) control function The busy signal, which is used to post the busy state of a slave, can be controlled. Fig. 4-53 Address transfer SCK0 8 9 Timing of SBI Transfer SB0/SB1 Bus release signal A7 A0 ACK BUSY Command transfer SCK0 Command signal 9 SB0/SB1 C7 C0 ACK BUSY READY Data transfer SCK0 8 9 SB0/SB1 D7 D0 ACK BUSY READY 100 PD75238 (ii) Communication operation In the SBI mode, the master usually selects a slave device to communicate with from multiple devices by outputting the address of the slave in the serial bus. After selecting a device to communicate with, the master exchanges commands and data with the slave device, thus establishing serial communication. Fig. 4-54 to 4-57 show the timing charts of data communication operations. In the SBI mode, the shift register 0 performs shift operation on the falling edge of the serial clock (SCK0). Send data is held on the SO0 latch, and is output on the SB0/P02 or SB1/P03 pin starting with the MSB. Receive data applied to the SB0 (or SB1) pin is latched in the shift register 0 on the rising edge of SCK0. 101 102 Program processing Hardware operation Transfer line SCK0 pin SB0 pin Slave device processing (receiver) Program processing Hardware operation Fig. 4-54 Address Transfer Operation from Master Device to Slave Device (WUP = 1) Master device processing (transmitter) Write to SIO0 Set CMDT Set Set RELT CMDT Interrupt handling (preparation for next serial transfer) Serial send operation Generate IRQCSI0 Set ACKD Stop SCK0 1 2 3 4 5 6 7 8 9 A7 A6 A5 A4 Address A3 A2 A1 A0 ACK BUSY READY WUP0 Set ACKT Clear BUSY Set Clear Set CMDD CMDD CMDD Set RELD Serial receive operation Generate IRQCSI0 Output Output ACK BUSY Clear BUSY (When SVA = SIO0) PD75238 Fig. 4-55 Command Transfer Operation from Master Device to Slave Device Master device processing (transmitter) Set CMDT Program processing Write to SIO0 Interrupt handling (preparation for next serial transfer) Hardware operation Serial send operation Generate IRQCSI0 Set ACKD Stop SCK0 Transfer line SCK0 pin 1 2 3 4 5 6 7 8 9 SB0 pin C7 C6 C5 C4 C3 C2 C1 C0 ACK BUSY READY Command Slave device processing (receiver) Read SIO0 Analyze command Program processing Set ACKT Clear BUSY Hardware operation Set CMDD Serial receive operation Generate IRQCSI0 Output Output BUSY ACK Clear BUSY PD75238 103 104 Master device processing (transmitter) Program processing Hardware operation Transfer line SCK0 pin SB0 pin Slave device processing (receiver) Program processing Hardware operation Fig. 4-56 Data Transfer Operation from Master Device to Slave Device Write to SIO0 Interrupt handling (preparation for next serial transfer) Serial send operation Generate IRQCSI0 Set ACKD Stop SCK0 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 Data D3 D2 D1 D0 ACK BUSY READY Read SIO0 Set ACKT Clear BUSY Serial receive operation Generate IRQCSI0 Output Output BUSY ACK Clear BUSY PD75238 Fig. 4-57 Data Transfer Operation from Master Device to Slave Device 5 Master device processing (receiver) Write FFH to SIO0 Program processing Read SIO0 Set Write FFH ACKT to SIO0 Receive data processing Hardware operation Stop SCK0 Serial receive operation Generate IRQCSI0 Output ACK Serial reception Transfer line SCK0 pin 1 2 3 4 5 6 7 8 9 1 2 SB0 pin BUSY READY D7 D6 D5 D4 Data D3 D2 D1 D0 ACK BUSY READY D7 D6 Slave device processing (transmitter) Write to SIO0 Write to SIO0 Program processing Hardware operation Clear BUSY Serial send operation Generate IRQCSI0 Set ACKD Output BUSY Clear BUSY PD75238 105 PD75238 (6) Transfer start in each mode In each of the three-wire serial I/O, two-wire serial I/O, and SBI modes, serial transfer is started by writing transfer data in shift register 0 (SIO0). However, the following two conditions must be satisfied: * The serial interface operation enable/disable bit (CSIE0) is set to 1. * The internal serial clock is not operating after 8-bit serial transfer, or SCK0 is high. Caution Transfer operation cannot be started by setting CSIE0 to 1 after writing data to the shift register 0. When eight bits have been transferred, serial transfer automatically terminates setting the interrupt request flag (IRQCSI0). [In the two-wire serial I/O mode] Caution The N-ch transistor needs to be turned off when data is received. So FFH must be written to SIO0 beforehand. [In the SBI mode] Cautions 1. The N-ch transistor needs to be turned off when data is received. So FFH must be written to SIO0 beforehand. However, when the wake-up function specification bit (WUP) is set to 1, the N-ch transistor is always off. So FFH need not be written to SIO0 beforehand for reception. 2. If data is written to SIO0 when the slave is busy, the data is not lost. Transfer operation is started when the busy state is released and input to SB0 (or SB1) goes high. Example When RAM data specified by the HL register is transferred to SIO0, SIO0 data is loaded into the accumulator at the same time, and serial transfer is started. MOV SEL XCH XA, @HL MB15 XA, SIO0 ; Extracts send data from RAM ; Or CLR1 MBE ; Exchanges send data with receive data and starts transfer 106 PD75238 (7) Manipulation of SCK0 pin output The SCK0/P01 pin has a built-in output latch, so that this pin allows static output by software manipulation in addition to normal serial clock output. The number of SCK0s can be software-set arbitrarily by manipulating the P01 output latch. (The SO0/ SB0/SB1 pin is controlled by manipulating the RELT and CMDT bits of SBIC.) The procedure for manipulating SCK0/P01 pin output is explained below. 1 2 Set serial operation mode register 0 (CSIM0) (SCK0 pin: output mode, serial operation: enabled). When serial transfer operation is halted, SCK0 from the serial clock control circuit is set to 1. Manipulate the P01 output latch by using a bit manipulation instruction. Example To output one clock cycle on the SCK0/P01 pin by software SEL MOV MOV CLR1 SET1 MB15 ; or CLR1 MBE XA, #10000011B ; SCK0 (fX/2 3), output mode CSIM0, XA 0FF0H.1 0FF0H.1 ; SCK0/P01 0 ; SCK0/P01 1 Fig. 4-58 SCK0/P01 Pin Circuit Configuration P01/SCK0 To internal circuit Address FF0H.1 P01 output latch From the serial clock control circuit SCK0 When CSIE0=1 and CSIM01 and CSIM00 are not 00 The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to 1. Cautions 1. 2. During normal serial transfer operation, the P01 output latch must be set to 1. The P01 output latch cannot be addressed by specifying PORT0.1 (as described below). The address of the latch (0FF0H.1) must be coded in the operand of an instruction directly. However, MBE = 0 (or MBE = 1, MBS = 15) must be specified before the instruction is executed. CLR1 PORT0.1 SET1 PORT0.1 CLR1 0FF0H.1 SET1 0FF0H.1 Allowed Not allowed 107 PD75238 (8) Serial interface (channel 1) functions The serial interface (channel 1) of the PD75238 has following two modes. The functions of the two modes are outlined below. * Operation halt mode This mode is used when serial transfer is not performed. This mode reduces power consumption. * Three-wire serial I/O mode 8-bit data transfer is performed using three lines: Serial clock (SCK1), serial output (SO1), and serial input (SI1). The three-wire serial I/O mode allows full-duplex transmission, so data transfer can be performed at higher speed. 5 Eight-bit data transfer always starts the MSB. The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many other types of peripheral I/O devices. (9) Serial interface (channel 1) configuration Fig. 4-59 shows the block diagram of the serial interface (channel 1). 108 Fig. 4-59 Block Diagram of the Serial Interface (Channel 1) Internal bus Bit manipulation 8 bit 0 P83/SI1 Shift register 1 (8) SIO1 write signal (serial start signal) 7 SIO1 bit 7 8 0 Serial operation mode register (8) CSIM1 Bit manipulation P82/SO1 Clear Serial clock counter (3) Overflow Set Serial transfer end flag (EOT) Clear P81/SCK1 R Q S fX/23 Serial clock selector fX/24 PD75238 109 PD75238 (10) Functions of serial interface (channel 1) registers (a) Serial operation mode register 1 (CSIM1) Fig. 4-60 shows the format of serial operation mode register 1 (CSIM1). CSIM1 is an 8-bit register which specifies a serial interface (channel 1) operation mode and serial clock. CSIM1 is manipulated using an 8-bit memory manipulation instruction. Only the high-order one bit can be manipulated independently. Each bit can be manipulated using its name. A RESET input clears all bits to 0. Fig. 4-60 Format of Serial Operation Mode Register 1 Address FC8H 7 CSIE1 6 0 5 0 4 0 3 0 2 0 1 0 Symbol CSIM1 CSIM11 CSIM10 Serial clock selection bit (W) CSIM11 0 0 1 1 CSIM10 0 1 0 1 Serial clock (3-wire serial I/O mode) External clock applied to SCK1 pin Not to be set fX/24 (262 kHz or 375 kHz)Note fX/23 (524 kHz or 750 kHz)Note Output SCK1 pin mode Input Note The values in parentheses are for fX = 4.19 MHz or 6.0 MHz. Serial interface operation enable/disable specification bit (W) Shift register 1 Serial clock counter Cleared Count operation IRQCSI flag Held Can be set. SO1, SI1 pin Used only for port 8 Port 8 is shared with serial function 5 5 CSIE1 0 1 Shift operation disabled Shift operation enabled Caution Be sure to write 0 in bits 2 to 6 of the serial operation mode register. 110 PD75238 (b) Shift register 1 (SIO1) SIO1 is an 8-bit register which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock. Serial transfer is started by writing data to SIO1. In send operation, data written to SIO1 is output on the serial output (SO1). In receive operation, data is read from the serial input (SI1) into SIO1. Data can be read from or written to SIO1 using an 8-bit manipulation instruction. When the RESET signal is entered during operation, the value of SIO1 is undefined. When the RESET signal is entered in the standby mode, the value of SIO1 is preserved. Shift operation is stopped after 8-bit send or receive operation is completed. The timing for reading SIO1 and start of serial transfer (writing to SIO1) is as follows: * When the serial interface operation enable/disable bit (CSIE1) is set to 1. However, the case where CSIE1 is set to 1 after data is written to the shift register is excluded. * When the serial clock is masked after 8-bit serial transfer * When SCK1 is high 111 PD75238 (11) Serial interface (channel 1) operation (a) Operation halt mode The operation halt mode is used when serial transfer is not performed. This mode reduces power consumption. Shift register 1 does not perform shift operation in this mode, so the shift register can be used as a normal 8-bit register. A RESET input sets the operation halt mode. The P82/SO1 pin and P83/SI1 pin are fixed to function for input ports. The P81/SCK1 pin can be used as an input port pin by setting serial operation mode register 1. (b) Three-wire serial I/O mode operations The three-wire serial I/O mode is compatible with other modes used in the 75X series and 78K series. Communication is performed using three lines: Serial clock (SCK1), serial output (SO1), and serial input (SI1). The three-wire serial I/O mode transfers data with eight bits as one block. Data is transferred bit by bit in phase with the serial clock. Shift register 1 performs shift operation on the falling edge of the serial clock (SCK1). Send data is latched on the SO1 latch, and is output on the SO1 pin. Receive data applied to the SI1 pin is latched in the shift register 1 on the rising edge of SCK1. When eight bits have been transferred, operation of shift register 1 automatically terminates setting the serial transfer end flag (EOT). Fig. 4-61 Timing of the Three-Wire Serial I/O Mode SCK1 1 2 3 4 5 6 7 8 SI1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 EOT Completion of transfer Transfer operation is started in phase with falling edge of SCK1. Execution of instruction that writes data to SIO1 (Transfer operation start specification) 112 PD75238 4.10 A/D CONVERTER The PD75238 contains an 8-bit analog/digital (A/D) converter that has eight analog input channels (AN0 to AN7). The A/D converter employs the successive-approximation method. (1) Configuration of the A/D converter Fig. 4-62 shows the configuration of the A/D converter. Fig. 4-62 Block Diagram of the A/D Converter Internal bus 8 0 ADM6 ADM5 ADM4 SOC EOC 0 0 8 AN0 AN1 AN2 Control circuit Sample and hold circuit + AN3 AN4 AN5 AN6 Multiplexer - Comparator SA register (8) 8 AN7 Tap decoder AVREF R/2 R R R R/2 AVSS 113 PD75238 (2) Pins of the A/D converter (a) AN0 to AN7 AN0 to AN7 are the input pins for eight analog signal channels. Analog signals subject to A/D conversion are applied to these pins. The A/D converter contains a sample-and-hold circuit, and analog input voltages are internally maintained during A/D conversion. (b) AVREF, AVSS A reference voltage for the A/D converter is applied to these pins. By using an applied voltage across AVREF and AVSS, signals applied to AN0 to AN7 are converted to digital signals. AVSS must be always VSS. 5 (c) AVDD This is the supply voltage pin for the A/D converter. When the A/D converter is not used or is in the standby mode, the potential of the AVDD pin must be equal to that of the VDD pin. (3) A/D conversion mode register The A/D conversion mode register (ADM) is an 8-bit register used to select analog input channels, direct the start of conversion, and detect the completion of conversion. (See Fig. 4-63.) ADM is set with an 8-bit manipulation instruction. The conversion completion detection flag (EOC) in bit 2 and the conversion start direction bit (SOC) in bit 3 can be manipulated individually. A RESET input initializes ADM to 04H. That is, only EOC is set to 1, with all bits cleared to 0. 114 PD75238 Fig. 4-63 Address 7 FD8H 0 6 ADM6 5 ADM5 4 ADM4 3 SOC 2 EOC 1 0 0 0 ADM Format of the A/D Conversion Mode Register Symbol End of conversion flag 0 EOC 1 Conversion completed Conversion under way Start of conversion bit Setting this bit starts conversion. After conversion is started, the bit is reset automatically. SOC Analog channel selection bit ADM6 0 0 0 0 1 1 1 1 ADM5 0 0 1 1 0 0 1 1 ADM4 0 1 0 1 0 1 0 1 Analog channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Caution A/D conversion is started a maximum of 24/fX seconds (2.67 s at 6.0 MHz)Note after SOC is set. (See (5) in Section 4.10.) Note 3.81 s at 4.19 MHz 115 PD75238 (4) SA register (SA) The SA register (successive approximation register) is an 8-bit register to hold the result of A/D conversion in successive approximation. SA is read with an 8-bit manipulation instruction. No data can be written to SA by software. A RESET input sets SA to 7FH. (5) A/D converter operation Analog input signals subject to A/D conversion are specified by setting bits 6, 5, and 4 in the A/D conversion mode register (ADM6, ADM5, and ADM4). A/D conversion is started by setting bit 3 (SOC) of ADM to 1. After that, SOC is automatically cleared to 0. A/D conversion is performed by hardware using the successive-approximation method. The resultant 8-bit data is loaded into the SA register. Upon completion of A/D conversion, bit 2 (EOC) of ADM is set to 1. Fig. 4-64 shows the timing chart of A/D conversion. The A/D converter is used as follows: 1 2 3 4 Select analog input channels (by setting ADM6, ADM5 and ADM4). Direct the start of A/D conversion (by setting SOC)3 Wait for the completion of A4D conversion (wait for EOC to be set or wait using a software timer). Read the result of A/D conversion (read the SA register). Cautions 1. 1 and 2 above can be performed at the same time. 2. There is a delay of up to 24/fX seconds (2.67 s at 6.0 MHz)Note from the setting of SOC to the clearing of EOC after A/D conversion is started. EOC must be tested when a time indicated in Table 4-7 has elapsed after the setting of SOC. Table 4-7 also indicates A/D conversion times. Note 3.81 s at 4.19 MHz Table 4-7 Setting values of SCC, PCC A/D conversion time SCC3 SCC0 PCC1 PCC0 0 0 0 1 1 0 1 1 x x x 0 0 1 x x Conversion stopped 168/fX (28.0 s at 6.0 MHz)Note Setting of SCC and PCC Wait time from SOC setting Wait time from SOC setting to A/D conversion completo EOC test tion Waiting not required 2 machine cycles 4 machine cycles Waiting not required -- 3 machine cycles 21 machine cycles 42 machine cycles Waiting not required -- Note 40.1 s at 4.19 MHz x: Don't care Remark 116 PD75238 Fig. 4-64 Timing Chart of A/D Conversion SOC EOC SA register Previous data Undefined Result of conversion Time elapsed before A/D conversion starts (Maximum of 24/fX s) Sampling time A/D conversion 168/fX s (28 s at 6.0 MHz) Note Note 40.1 s at 4.19 MHz (6) Notes on the standby mode The A/D converter operates with the main system clock. So its operation stops in the STOP mode, or when the subsystem clock is used, in the HALT mode. A current flows through the AVREF pin even when the A/D converter is stopped, so that the current must be stopped to reduce overall system power consumption. Since the P21 pin has a higher drive capability than the other ports, it can supply voltage to the AVREF pin directly. In this case, however, the actual AVREF voltage does not provide precision. This means that the value resulting from conversion does not provide precision and can be used only for relative comparison. In the standby mode, outputting a low on the P21 can reduce power consumption. In the standby mode, the potential of the AVDD pin must be equal to that of the VDD pin. Fig. 4-65 Reducing Power Consumption in the Standby Mode VDD P-ch Note P21 AVREF .. AVREF = VDD PD75238 AVSS Note The drive capability of P-ch is higher than that of other ports. 117 PD75238 (7) Other notes on use (a) AN0 to AN7 input range Specified voltages must be applied to AN0 to AN7 inputs. If a voltage higher than VDD or lower than VSS is applied even when the maximum absolute rating is not exceeded, the conversion result for an associated channel becomes unpredictable. In addition, the conversion results for other channels may be affected. 5 (b) Noise protection To maintain 8-bit resolution, the user should pay attention to noise that may be applied to the AVREF, and AN0 to AN7 pins. Noise adversely affects operation to a greater extent when the analog input source has a higher output impedance. As shown in Fig. 4-66, a capacitor should be externally connected. Fig. 4-66 Analog Input Pin Connection If it is anticipated that noise voltages do not fall in the range of VDD to VSS, clamp this point using a diode with a low VF (not higher than 0.3 V). VDD C = 100 - 1000 pF C AVREF, AN0 to AN7 PD75238 VDD VDD AVDD AVSS VSS (c) AN4/P90 to AN7/P93 pins The analog input pins (AN4 to AN7) are also used for an input port (port 9). When any of AN4 to AN7 is selected for A/D conversion, no input instruction must be executed for port 9 during A/D conversion. Otherwise, the accuracy of conversion may deteriorate. If a digital pulse signal is applied to a pin adjacent to a pin being used for A/D conversion, an expected A/D conversion value may not be obtained because of coupling noise. So no digital pulse signal should be applied to the adjacent pin being used for A/D conversion. 5 (d) AVDD pins When the A/D converter is not used or is in the standby mode, the potential of the AVDD pin must be equal to that of the VDD pin. 118 PD75238 4.11 BIT SEQUENTIAL BUFFER: 16 BITS The bit sequential buffer (BSB0 to BSB3) is special data memory for bit manipulations. The buffer allows bit manipulations to be performed very easily by sequentially changing address and bit specifications. So the buffer is particularly useful in processing long data bit by bit. This data memory consists of 16 bits, and allows pmem.@L addressing with a bit manipulation instruction and also allows indirect bit specification using the L register. continued processing. Fig. 4-67 Format of the Bit Sequential Buffer In this case, only by incrementing or decrementing the L register in a program loop, the bit to be manipulated can be sequentially shifted for Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0 BSB3 BSB2 BSB1 BSB0 L register L=F L=C L=B L=8 L=7 L=4 L=3 DECS L L=0 INCS L Remark In pmem.@L addressing, bit specification is shifted according to the L register. With pmem.@L addressing, bit sequential buffer can be manipulated at any time regardless of MBE/MBS specification. Data can also be manipulated using direct addressing. The buffer can be used for applications such as continuous 1-bit data input or output operations by combining direct 1-bit, 4-bit, and 8-bit addressing with pmem.@L addressing. In 8-bit manipulation, the higher eight bits or lower eight bits can be manipulated by specifying BSB0 or BSB2. 4.12 FIP CONTROLLER/DRIVER (1) Configuration of the FIP controller/driver The PD75238 contains a display controller that reads the contents of display data memory by DMA operation and generates digit and segment signals automatically. It also contains a high-voltage output buffer that can directly drive a fluorescent indicator lamp (FIP). Fig. 4-68 shows the configuration of the FIP controller/driver. Caution The FIP controller/driver can operate only when the high-speed or medium-speed (PCC = 0011B or 0010B) is set for the main system clock (SCC.0 = 0). With the other clocks or in the standby mode, the FIP controller/driver may malfunction. Disable FIP controller operation (DSPM.3 = 0) before entering into the standby mode. 119 120 8 Static mode register B 4/8 Display data memory (32 x 4 bits) Key scan register (KS2) 8 Segment data latch (8) 8 High-voltage output buffer 8 S16/P100S23/P113 Fig. 4-68 Block Diagram of the FIP Controller/Driver Internal bus 4 Display mode register 4 Digit select register 4 Dimmer select register Key scan flag (KSF) 8 Static mode register A 4/8 Display data memory (64 x 4 bits) Key scan registers (KS0 and KS1) 12 Port H 4 Digit signal generator 4 4 Key scan flag (KSF) Segment data latch (16) INTKS IRQKS set signal Selector 10 2 2 4 4 Selector 2 4 10 Hige-voltage output buffer 10 S0/P120S9/P141 2 4 10 T0-T9 VLOAD S10/T15/P142 S12/T13/P150/PH0and S11/T14/P143 S15/T10/P153/PH3 PD75238 PD75238 (2) FIP controller/driver functions The FIP controller/driver contained in the PD75238 has the following functions: (a) The FIP controller/driver automatically reads display data and generates a segment signal (DMA operation) and a digit signal. (b) An FIP having 9 to 24 segments and 9 to 16 digits can be controlled with the display mode register (DSPM), digit select register (DIGS), static mode register A (STATA), and static mode register B (STATB). (Up to 34 display outputs are allowed.) (c) Any outputs not used for dynamic display can be used as static outputs or output ports. (d) The dimmer function provides eight levels of intensity. (e) Hardware that makes key scan application possible * An interrupt (IRQKS) is caused for key scanning (detection of key scan timing). * Key scan data can be output on a segment output with key scan buffers (KS0, KS1, and KS2). (f) A high-voltage output pin (40 V) is provided which can directly drive the FIP. * Segment output pins (S0 to S9, S16 to S23): VOD = 40 V, IOD = 3 mA * Digit output pins (T0 to T15): VOD = 40 V, IOD = 15 mA (g) Mask options for display output pins * A pull-down resistor to VLOAD can be incorporated bit by bit for T0 to T9 and S0 to S15. * A pull-down resistor to VLOAD or VSS can be incorporated bit by bit for S16 to S23. VLOAD or VSS must be selected in 8-bit units. (3) Difference of the display output function between the PD75238, PD75216A, and PD75217 Table 4-8 shows the difference of the display output function between the PD75238, PD75216A, and PD75217. Table 4-8 Difference of the Display Output Function between the PD75238, PD75216A, and PD75217 PD75238 High-voltage output display FIP output total : 34 Segment output : 9 - 24 Digit output : 9 - 16 1A0H-1FFH S0-S23 (Port 10-port 15) KS0-KS2 PD75216A, PD75217 FIP output total : 26 Segment output : 9 - 16 Digit output : 9 - 16 1C0H-1FFH S12-S15 (Port H) KS0, KS1 Display data area Output dual-function pin Key scan register 121 PD75238 Fig. 4-69 TCYT TDSP T0 TKS FIP Controller Operation Timing T1 T2 TDIG TN Key scan flag (KSF) Changeable at any time Segment data 1 display cycle Key scan timing IRQKS generation N : Value set in the digit select register TDSP: One display cycle (1024/fX: 171 s at 6.0 MHzNote 1 or 2048/fX: 341 s at 6.0 MHzNote 2) TCYT : Display cycle (TCYT = TDSP x (N + 2)) TDIG : Digit signal pulse width, which can be selected from eight levels with the dimmer select register Notes 1. 244 s at 4.19 MHz 2. 489 s at 4.19 MHz 122 PD75238 (4) Display mode register (DSPM) The display mode register (DSPM) is a 4-bit register for enable/disable setting for the display operation and for specifying the number of display segments. Fig. 4-70 shows the format of the register. The display mode register is set with a 4-bit memory manipulation instruction. Before a standby mode (STOP mode or HALT mode) can be set or the subsystem clock (fXT) can be used for operation, display must be disabled by setting DSPM.3 to 0. A RESET input clears all bits to 0. Fig. 4-70 Address F88H 3 DSPM3 2 DSPM2 1 DSPM1 0 DSPM0 Display Mode Register Format Symbol DSPM Bit for specifying the number of display segments DSPM2 0 0 0 0 1 1 1 1 DSPM1 0 0 1 1 0 0 1 1 DSPM0 0 1 0 1 0 1 0 1 Number of display segments 9 segments (+ 8 segments) 10 segments (+ 8 segments) 11 segments (+ 8 segments) 12 segments (+ 8 segments) 13 segments (+ 8 segments) 14 segments (+ 8 segments) 15 segments (+ 8 segments) 16 segments (+ 8 segments) Remark Segments in parentheses are added when pins S16 to S23 are specified as dynamic mode in STATB. Display operation enable/disable bit 0 DSPM3 1 Display enabled Display disabled (5) Digit select register (DIGS) The digit select register (DIGS) is a 4-bit register that specifies the number of display digits. Fig. 4-71 shows the format of the register. DIGS is set with a 4-bit memory manipulation instruction. This register enables the number of display digits to be selected from 9 to 16 digits. No other values can be selected. A RESET input initializes the register to 1000B so that 9-digit display is selected. Fig. 4-71 Digit Select Register Format Address F8AH 3 DIGS3 2 DIGS2 1 DIGS1 0 DIGS0 Symbol DIGS Caution Do not set a value from 0 to 7 for N. DIGS0-3 set value N (= 8 to 15) Number of display digits N+1 123 PD75238 (6) Dimmer select register (DIMS) The dimmer select register (DIMS) is a 4-bit register for specifying a digit signal cut width to prevent display light leakage and to use the dimmer function (for intensity control). In addition, the register is used to select a display cycle (TDSP). Fig. 4-72 shows the format of DIMS. DIMS is set with a 4-bit memory manipulation instruction. A display cycle of 341 s at 6.0 MHzNote 1 is usually selected by setting 1 in DIMS.0 for reduced light leakage. However, as the number of display digits increases, the display cycle becomes closer to the frequency of commercial power, causing the display to fricker. In this case, a display cycle of 171 s at 6.0 MHzNote 2 should be selected. If light leakage occurs in this case, adjust cutting width of the digit single by setting DIMS.1, DIMS.2, and DIMS.3. A RESET input clears all bits to 0. Notes 1. 489 s at 4.19 MHz 2. 244 s at 4.19 MHz Fig. 4-72 Address F89H DIMS3 DIMS2 DIMS1 DIMS0 Dimmer Select Register Format Symbol DIMS Display cycle specification bit 0 DIMS0 1 A display cycle is 2048 . (One cycle = 341 s/6.0 MHz) Note 2 fX A display cycle is 1024 . (One cycle = 171 s/6.0 MHz) Note 1 fX Digit signal cut width specification bit DIMS3 0 0 0 0 1 1 1 1 DIMS2 0 0 1 1 0 0 1 1 DIMS1 0 1 0 1 0 1 0 1 Digit signal cut width 1/16 2/16 4/16 6/16 8/16 10/16 12/16 14/16 Notes 1. 244 s at 4.19 MHz 2. 489 s at 4.19 MHz 124 PD75238 (7) Static mode registers A static mode registers are registers used to specify static output/dynamic output of the segment output pins. There are two static mode registers: static mode register A and static mode register B. Fig. 4-73 and Fig. 4-74 show their formats. These registers are set with an 8-bit manipulation instruction. A RESET input clears all bits to 0. (a) Static mode register A (STATA) Static mode register A (STATA) is a register to specify static output/dynamic output of the S0/P120 to S15/P153/T10/PH3 pins. Fig. 4-73 Static Mode Register A (STATA) Address FD6H 7 0 6 0 5 0 4 0 3 2 1 0 Symbol STATA STATA3 STATA2 STATA1 STATA0 S0 to S15 pins Static output/dynamic output selection bit STATA3 STATA2 STATA1 STATA0 0 0 0 0 Output status of S0 to S15 pins S0 to S15 become dynamic outputs. The number of segments and the number of digits are set by DSPM and DIGS. S0 to S15 become static outputs. Static data is output by issuing an output instruction for ports 12 to 15. The outputs are independent of the value of DSPM.3. 1 1 1 1 Caution Part of the S0 to S15 pins cannot be set as dynamic outputs while the other pins are set as static outputs. 125 PD75238 (b) Static mode register B (STATB) Static mode register B (STATB) is a register to specify static output/dynamic output of the S16/P100 to S23/P113 pins. Fig. 4-74 Static Mode Register B (STATB) Address FD4H 7 0 6 0 5 4 3 0 2 0 1 0 0 0 Symbol STATB STATB5 STATB4 S16 to S23 pins Static output/dynamic output selection bit STATB5 0 STATB4 0 Output status of S16 to S23 pins S16 to S23 become dynamic outputs. Output depends on the contents of 1A0H to 1BDH. S16 to S23 become static outputs. Static data is output by issuing an output instruction for ports 10 and 11. The outputs are independent of the value of DSPM.3. 1 1 Caution Part of the S16 to S23 pins cannot be set as dynamic outputs while the other pins are set as static outputs. 126 PD75238 (8) Selection of display mode The number of segments and number of digits which can be displayed by the internal FIP controller/driver are determined by display modes. Fig. 4-75 shows the selection of display mode. Fig. 4-75 Selection of Display Mode Number of digits 0 9 10 11 12 13 14 15 16 9-segment mode 9 10-segment mode 10 11-segment mode 11 12-segment mode 12 13-segment mode 13 14-segment mode 14 15-segment mode Number of segments 15 16-segment mode 16 17-segment mode 17 18-segment mode 18 19-segment mode 19 20-segment mode 20 21-segment mode 21 22-segment mode 22 23-segment mode 23 24-segment mode 24 Remark The shaded circles indicate extended modes derived from the PD75216A and PD75217. 127 PD75238 (9) Display data memory Display data memory stores segment data for display. It is mapped to addresses 1A0H to 1FFH in data memory. The display controller automatically reads display data (DMA operation). Area not used for display can be used as normal data memory. Display data is manipulated with data memory manipulation instructions in 1-, 4-, and 8-bit units. With 8-bit manipulation instructions, only even-numbered addresses can be specified. Display data memory locations at 1FCH to 1FFH, 1BEH, and 1BFH are also used as key scan registers KS0, KS1, and KS2. Table 4-9 Data Memory Locations Also Used as Key Scan Registers Key scan register KS0 KS1 KS2 Data memory locations 1FCH, 1FDH 1FEH, 1FFH 1BEH, 1BFH Caution Special care must be paid when a program developed for the PD75238 is transported to the PD75216A or the PD75217. This is because the PD75216A and the PD75217 allow up to 16 display segments, and do not contain data memory at the addresses (1A0H + 4n, 1A1H + 4n). 128 PD75238 Fig. 4-76 Correspondence between Display Data Memory and Segment Output 24-segment mode 23-segment mode 22-segment mode 21-segment mode 20-segment mode 19-segment mode 18-segment mode 17-segment mode 16-segment mode 15-segment mode 14-segment mode 13-segment mode 12-segment mode 11-segment mode 10-segment mode 9-segment mode Bit 3 1A1H 1A3H 1A5H 1A7H 1A9H 1ABH Display data memory 03 1A0H 1A2H 1A4H 1A6H 1A8H 1AAH 1ACH 1AEH 1B0H 1B2H 1B4H 1B6H 1B8H 1BAH 1BCH 1BEH(KS2) 03 1C3H 1C7H 1CBH 1CFH 1D3H 1D7H 1DBH 1DFH 1E3H 1E7H 1EBH 1EFH 1F3H 1F7H 1FBH 1FFH 03 1C2H 1C6H 1CAH 1CEH 1D2H 1D6H 1DAH 1DEH 1E2H 1E6H 1EAH 1EEH 1F2H 1F6H 1FAH 1FEH(KS1) 03 1C1H 1C5H 1C9H 1CDH 1D1H 1D5H 1D9H 1DDH 1E1H 1E5H 1E9H 1EDH 1F1H 1F5H 1F9H 1FDH 03 1C0H 1C4H 1C8H 1CCH 1D0H 1D4H 1D8H 1DCH 1E0H 1E4H 1E8H 1ECH 1F0H 1F4H 1F8H 1FCH(KS0) 0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 Timing output 1ADH 1AFH 1B1H 1B3H 1B5H 1B7H 1B9H 1BBH 1BDH 1BFH Key scan data KS2 KS1 KS0 Tks Segment S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 output Timing output Port H output T10 T11 T12 T13 T14 T15 (When specified by digit select register) PH3 PH2 PH1 PH0 (When neither segment output nor timing output is required) 129 PD75238 (10) Key scan registers (KS0, KS1, and KS2) The key scan registers (KS0, KS1, and KS2) set segment output data on the key scan timing that is mapped to display data memory locations (1FCH, 1FDH, 1FEH, 1FFH, 1BEH, and 1BFH). KS0, KS1, and KS2 are 8-bit registers, which are usually manipulated with an 8-bit manipulation instruction. (One-bit or 4-bit manipulation is also possible for the lower 4 bits.) The data set in KS0, KS1, and KS2 is output on the segment output pins on the key scan timing. During the key scan timing, the rewriting of KS0, KS1, and KS2 is immediately reflected in segment output data, which can be used for key scanning. (11) Key scan flag (KSF) The key scan flag (KSF) is set to 1 on the key scan timing, and is automatically reset to 0 on any other timing. KSF is mapped to bit 3 at address F8AH, and can be tested on a single-bit basis. KSF cannot be written to. Testing this flag can determine whether the key scan timing is present, so that the validity of key input data can be determined. 130 PD75238 5. INTERRUPT FUNCTION The PD75238 has eight interrupt sources and can handle multiple interrupts with a priority. The PD75238 is also provided with two test sources. One test source, INT2, is set by edge detection testable input. Table 5-1 Interrupt Sources Interrupt source INTBT (Reference time interval signal from basic interval timer) (Detection of rising or falling edge) (Rising/falling edge detection specification) In/out In PriorityNote 1 Vector interrupt request signal (vector table address) VRQ1 (0002H) 1 INT4 INT0 INT1 INTCSI0 INTT0 INTTPG INTKS INT2Note 2 INTWNote 2 Out Out Out 2 3 4 5 6 7 VRQ2 (0004H) VRQ3 (0006H) VRQ4 (0008H) VRQ5 (000AH) VRQ6 (000CH) VRQ7 (000EH) (Serial data transfer completion signal) (Match signal from timer enter/counter 0) (Match signal from timer/pulse generator) (Key scan timing signal from display controller) (Detection of rising edge ) (Signal from clock timer) In In In In Out In Testable input signal (Sets IRQ2 and IRQW.) Notes 1. The priority is used when two or more interrupt requests are issued at a time. 2. INT2 and INTW are test sources. Like interrupt sources, these test sources are controlled by an interrupt enable flag. But, they do not cause vector interrupts. The following functions are provided for the interrupt control circuit of the PD75238. (a) Vector interrupt function under hardware control which can determine whether to accept an interrupt by an interrupt enable flag (IExxx) and the interrupt master enable flag (IME) (b) Any interrupt start address can be set. (c) Multiple interrupt function which can specify the priority by the interrupt priority specification register (IPS) (d) Test function of an interrupt request flag (IRQxxx) (The software can confirm that an interrupt occurred.) (e) Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.) 5.1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT The interrupt control circuit of the PD75238 is configured as shown in Fig. 5-1. Each hardware item is mapped in the data memory space. 131 132 2 IM1 2 IM0 Noise eliminator INT4 /P00 INT0 /P10 INT1 /P11 INT BT Both-edge detection circuit Edge detection circuit Edge detection circuit INTCSI0 IRQBT IRQ4 IRQ0 IRQ1 IRQCSI0 INTT0 IRQT0 INTTPG IRQTPG INTKS IPQKS INTW INT2 /P12 Rising edge detection circuit IRQW IRQ2 Fig. 5-1 Block Diagram of Interrupt Control Circuit Internal bus 4 (IME) Interrupt enable flag (IExxx) IPS 2 IST Decoder VRQn Priority control circuit Vector table address generator Standby release signal PD75238 PD75238 5.2 HARDWARE OF THE INTERRUPT CONTROL CIRCUIT (1) Interrupt request flag and interrupt enable flag There are ten interrupt request flags (IRQxxx), listed below, each corresponding to a particular interrupt or test source; there are 8 interrupt and 2 test sources. INT0 interrupt request flag (IRQ0) INT1 interrupt request flag (IRQ1) INT2 interrupt request flag (IRQ2) INT4 interrupt request flag (IRQ4) BT interrupt request flag (IRQBT) Serial interface interrupt request flag (IRQCSI0) Timer/event counter interrupt request flag (IRQT0) Timer/pulse generator interrupt request flag (IRQTPG) Key scan interrupt request flag (IRQKS) Clock timer interrupt request flag (IRQW) 5 The interrupt request flag is set to 1 when an interrupt request is issued, and is automatically cleared to 0 when the CPU is interrupted. Since the IRQBT and IRQ4 share the vector address, the clear operation varies. (See Section 5.5.) There are ten interrupt enable flags (IExxx), listed below, each corresponding to a particular interrupt request flag. INT0 interrupt enable flag (IE0) INT1 interrupt enable flag (IE1) INT2 interrupt enable flag (IE2) INT4 interrupt enable flag (IE4) BT interrupt enable flag (IEBT) Serial interface interrupt enable flag (IECSI0) Timer/event counter interrupt enable flag (IET0) Timer/pulse generator interrupt enable flag (IETPG) Key scan interrupt enable flag (IEKS) Clock timer interrupt enable flag (IEW) 5 When an interrupt request flag is set, the interrupt enable flag corresponding to that interrupt request flag enables the request interrupt. When an interrupt request flag is cleared, the interrupt enable flag corresponding to that interrupt request flag disables the interrupt. When an interrupt request flag is set and its corresponding interrupt enable flag enables the requested interrupt, a vector interrupt request (VRQn) is issued. This signal is also used for releasing the standby mode. The interrupt request flags and interrupt enable flags are manipulated with bit manipulating instructions and 4-bit memory manipulation instructions. When a bit manipulation instruction is used, the flags can always be manipulated directly irrespective of the MBE setting. The interrupt enable flags are manipulated with EI IExxx and DI IExxx instructions. An SKTCLR instruction is normally used to test an interrupt request flag. When an interrupt request flag is set with an instruction, a vector interrupt is executed irrespective of whether an interrupt occurs. A RESET input clears an interrupt request flag and its corresponding interrupt enable flag to 0 and all interrupts are disabled. 133 PD75238 Table 5-2 Set Signals of Interrupt Request Flags Interrupt request flag IRQBT IRQ4 IRQ0 Set signal of interrupt request flag Set by a reference time interval signal from the basic interval timer. Set by a detected rising or falling edge of an INT4/P00 pin input signal. Set by a detected edge of an INT0/P10 pin input signal. The detection edge is specified by the INT0 mode register (IM0). Set by a detected edge of an INT1/P11 pin input signal. by the INT1 mode register (IM1). The detection edge is specified Interrupt enable flag IEBT IE4 IE0 IRQ1 IE1 IRQCSI0 IRQT0 IRQTPG IRQKS IRQW IRQ2 Set by a serial data transfer completion signal for the serial interface. Set by a match signal from timer/event counter 0. Set by a match signal from the timer/pulse generator. Set by a key scan timing signal from the display controller. Set by a signal from the clock timer. Set by a detected rising edge of an INT2/P12 pin input signal. IECSI0 IET0 IETPG IEKS IEW IE2 5 (2) Noise eliminator and edge detection mode register As shown in Fig. 5-2 and Fig. 5-3, the INT0, INT1, and INT2 pins are configured as external interrupt input pins that enable detection edge selection. In addition, INT0 is provided with a noise elimination function based on a sampling clock. Basically, the noise eliminator eliminates pulses narrower than two sampling clock cyclesNote as noise. However, it may accept pulses wider than one sampling clock cycle as interrupt signals depending on the sampling timing. It surely accepts pulses wider than two sampling clock cycles as interrupt signals. INT0 has two sampling clocks and fX/64, either of which can be selected according to bit 3 (IM03) of the edge detection mode register (see Fig. 5-4). The IRQ2 is set by detecting a rising edge of the INT2 pin input. The edge detection mode registers (IM0 and IM1) used to select a detection edge have the format shown in Fig. 5-4. A 4-bit memory manipulation instruction is used to set IM0 or IM1. A RESET input clears all bits to 0, and a rising edge is selected for INT0, INT1, and INT2. Note When a sampling clock is , two sampling clock cycles are 2tCY. When a sampling clock is fX/64, two sampling clock cycles are 128/fX. Cautions 1. Since the INT0 pin input is sampled with a clock, INT0 does not operate in a standby mode. 2. When INT0/P10 is used as a port, pulses input from INT0/P10 go through the noise eliminator. So the input pulses must be wider than two sampling clock cycles. 134 PD75238 Fig. 5-2 Configuration of INT0 and INT1 INT0/P10 Noise eliminator Edge detection circuit IM01, IM00 INT0 IRQ0 set signal Selector INT1/P11 fX 64 IM03 2 Edge detection circuit IM10 IM1 IM0 INT1 IRQ1 set signal Input buffer 4 Internal bus 4 Fig. 5-3 Configuration of INT2 INT2/P12 Rising edge detection circuit INT2 IRQ2 set signal Input buffer Internal bus 135 PD75238 Fig. 5-4 Format of Edge Detection Mode Registers Address FB4H 3 IM03 2 0 1 IM01 0 IM00 Symbol IM0 Detection edge specification 0 0 1 1 0 1 0 1 Specifies rising edge. Specifies falling edge. Specifies both rising and falling edges. Ignored (interrupt request flag is not set.) 5 Sampling clock 0 1 (0.67s, 1.33s, 2.67 s, or 10.7 s at 6.0 MHz) Note 1 fX/64 (10.7 s at 6.0 MHz) Note 2 FB5 0 0 0 IM10 IM1 0 1 Specifies rising edge. Specifies falling edge. Notes 1. 0.95 s, 1.91 s, 3.82 s, or 15.3 s at 4.19 MHz 2. 15.3 s at 4.19 MHz Caution Since changing the edge detection mode register may set an interrupt request flag, disable the interrupts before changing the edge detection mode register. Then clear the interrupt request flag with a CLR1 instruction and enable the interrupts. When fX/64 is selected as a sampling clock pulse in changing IM0, wait for 16 machine cycles after changing the mode register and clear the interrupt request flag. 136 PD75238 (3) Interrupt priority specification register (IPS) The interrupt priority specification register specifies an interrupt with a higher priority from multiple interrupts using the low-order three bits. Bit 3, interrupt master enable flag (IME), specifies whether to disable all interrupts. The IPS is set with a 4-bit memory manipulation instruction. Bit 3 is set with an EI instruction and reset with a DI instruction. When changing the low-order three bits of the IPS, interrupts must be disabled (IME = 0) beforehand. A RESET input clears all bits to 0. Fig. 5-5 Interrupt Priority Specification Register Address 3 FB2H IPS3 2 IPS2 1 IPS1 0 IPS0 Symbol IPS High-order interrupt selection 0 0 0 0 0 1 All low-order interrupt VRQ1 (INTBT/INT4) The listed vector interrupts are treated as high-order interrupts. 0 0 1 1 0 1 VRQ2 (INT0) VRQ3 (INT1) 1 0 0 VRQ4 (INTCSI0) 1 0 1 VRQ5 (INTT0) 1 1 1 1 0 1 VRQ6 (INTTPG) VRQ7 (INTKS) Interrupt master enable flag (IME) 0 All interrupts are disabled and no vector interrupt is activated. The interrupt enable flag corresponding to an interrupt request flag controls interrupt enabling/disabling. 1 137 PD75238 5.3 INTERRUPT SEQUENCE The following flowchart shows the sequence of an interrupt. Interrupt (INTxxx) occurrence IRQxxx setting NO IExxx set? YES Corresponding VRQn occurrence Hold until IExxx is set. IME = 1 YES Depending on the instrucrtion being executed when IRQn is set Is VRQn high-order interrupt? YES Note 1 NO Hold until IME is set. Hold until processing being executed is finished NO NO Note 1 NO IST1, 0 = 00 or 01 YES IST1, 0 = 00 YES If two or more VRQns occur, select one VRQn according to Table 5-1. Selected VRQn Remaining VRQns Save contents of PC and PSW in stack memory and set dataNote 2 in vector table corresponding to activated VRQn to PC, RBE, and MBE. Change contents of IST0 and IST1 from 00 to 01 or from 01 to 10. 2 machine cycles Reset accepted IRQxxx. See Section 5.5 when those interrupt sources share vector address. Start processing the interrupt service program. Notes 1. IST1 and IST0: Interrupt status flags (Bits 3 and 2 of PSW. See Table 5-3.) 2. Each vector table must store the start address of the interrupt service program and the set values of the MBE and RBE at the start of an interrupt. 138 PD75238 5.4 MULTIPLE INTERRUPT PROCESSING CONTROL The PD75238 can handle multiple interrupts by either of the following methods. (1) Multiple interrupt processing by a high-order interrupt In this method, the PD75238 selects an interrupt source among multiple interrupt sources, enabling double interrupt processing. That is, the high-order interrupt specified by the interrupt priority specification register (IPS) is enabled when the processing status is 0 or 1. Other interrupts (interrupts lower than the specified high-order interrupt) are enabled only when the status is 0. (See Fig. 5-6 and Table 5-3.) Fig. 5-6 Multiple Interrupt Processing by a High-Order Interrupt Normal processing (Status 0) Interrupt is disabled. IPS setting Interrupt is enabled. Low- or high-order interrupt processing (Status 1) High-order interrupt processing (Status 2) Low- or high-order interrupt occurrence High-order interrupt occurrence Table 5-3 Interrupt Processing Statuses of IST1 and IST0 IST1 0 IST0 0 Processing status Status 0 After acceptance CPU operation Is processing the normal program. Is processing a low- or highorder interrupt. Is processing a high-order interrupt. Interrupts that can be accepted IST1 All 0 IST0 1 0 1 Status 1 Only high-order interrupts 1 0 1 0 Status 2 None - - 1 1 This status is disabled. IST1 and IST0 are saved with the remaining PSW in the stack memory when an interrupt is accepted and the status of IST0 and IST1 changes to a status one level higher. When an RETI instruction is executed, the former values of IST0 and IST1 are returned. 139 PD75238 (2) Multiple interrupt processing by changing the interrupt status flags As shown in Table 5-3, changing the interrupt status flags with the program causes multiple interrupts to be enabled. That is, when the interrupt processing program changes both IST1 and IST0 to 0 (status 0), multiple interrupt processing is enabled. This method is used when two or more interrupts are to be enabled at a time or when the processing of three or more interrupts is to be performed. When changing IST1 and IST0, interrupts must be disabled beforehand with a DI instruction. Fig. 5-7 Multiple Interrupt Processing by Changing the Interrupt Status Flags Normal processing (status 0) Single interrupt Dual interrupts Triple interrupts Interrupt is disabled. IPS setting Interrupt is enabled. Interrupt is disabled. Modification of IST Interrupt is enabled. Low- or high-order interrupt occurrence Status 1 Low- or high-order interrupt occurrence Status 0 Status 1 High-order interrupt occurrence Status 0 Status 2 140 PD75238 5.5 VECTOR ADDRESS SHARE INTERRUPT PROCESSING Since interrupt sources INTBT and INT4 share the vector table, the following two cases must be considered. (1) When using only one interrupt source The interrupt enable flag corresponding to the required interrupt source of the two interrupt sources sharing the vector table is set and the other interrupt enable flag is cleared. In this case, the enabled interrupt source (IExxx = 1) issues an interrupt request. If this request is accepted, the corresponding interrupt request flag is reset. (The same operation as that of interrupts not sharing a vector address) (2) When using both interrupt sources The interrupt enable flags corresponding to the two interrupt sources are set. In this case, the logical and of the interrupt request flags corresponding to the two interrupt sources is an interrupt request. Even if one or both of the interrupt request flags are set and an interrupt request is accepted, neither of the interrupt request flags is reset. The interrupt service routine must therefore judge which interrupt source caused an interrupt. This is done by executing a DI instruction at the beginning of the interrupt service routine and checking the interrupt request flags with an SKTCLR instruction. 141 PD75238 6. STANDBY FUNCTION To reduce the power consumption when the program is in the wait state, the PD75238 has two standby modes, STOP and HALT. 6.1 SETTING OF STANDBY MODES AND OPERATION STATUSES Table 6-1 Operation Statuses in the Standby Mode STOP mode Instruction for setting System clock at setting STOP instruction This mode can be set only when the main system clock is used. HALT mode HALT instruction This mode can be set when either the main system clock or the subsystem clock is used. Only CPU clock () is stopped (with oscillation continued). Operation status Clock generator Only the main system clock is stopped. Serial interface (Channel 0) Operation is possible only when external SCK0 input is selected for the serial clock. Operation is possible only when the main system clock operates or external SCK0 is used. Operation is possible only when the main system clock operates. Operation is continued (to set IRQBT at reference time intervals). Operation is possible. Serial interface (Channel 1) Basic interval timer Timer/event counter Watch timer Operation is possible only when external SCK1 input is selected for the serial clock. Operation is stopped. Operation is possible only when TI0 pin input is selected for the count clock. Operation is possible only when fXT is selected for the count clock. Operation is stopped. Operation is possible. Timer/pulse generator Event counter Operation is possible only when the main system clock operates. Operation is possible only when the main system clock operates. Operation is possible only when the main system clock operates. Operation is stopped. A/D converter Operation is stopped. FIP controller/ driver External interrupt CPU Release signal Operation is disabled. (The display off mode is selected before setting.) INT0 is disabled. INT1, INT2, and INT4 are enabled. Operation is stopped. Interrupt request signals sent out from hardware, which are enabled by interrupt enable flags, or RESET input. 142 PD75238 A STOP instruction is used to set the STOP mode, and a HALT instruction is used to set the HALT mode. (A STOP instruction sets bit 3 of PCC, and a HALT instruction sets bit 2 of PCC.) When changing a CPU operation clock pulse with the low-order two bits of PCC, a time lag may occur from the time when PCC is rewritten to the time when the CPU clock signal is changed as indicated in Table 4-1. When changing an operation clock pulse before the standby mode or a CPU clock signal after the standby mode is released, it is necessary to rewrite PCC and set the standby mode after the number of machine cycles required to change the CPU clock pulse elapses. In a standby mode, the contents of all registers and data memory that are stopped during the standby mode, including general registers, flags, mode registers, and output latches, are retained. Cautions 1. When the STOP mode is set, the X1 input is internally connected to VSS (GND potential) to suppress leakage at the crystal oscillator circuitry. This means that the STOP mode cannot be used with a system that uses an external clock. 2. An interrupt request signal is used to release a standby mode. This means that if an interrupt source whose interrupt request flag and interrupt enable flag are both set exists, the initiated standby mode is released immediately after it is set. When the STOP mode is set, therefore, the PD75238 enters the HALT mode immediately after the STOP instruction is executed, then returns to the operation mode after the wait time specified by the BTM register has elapsed. 143 PD75238 6.2 RELEASE OF THE STANDBY MODES The STOP mode and HALT mode are released by a RESET input or the generation of an interrupt request signalNote that is enabled with the interrupt enable flag. Fig. 6-1 shows how the STOP and HALT modes are released. Note INT0 to INT2 are excluded. Fig. 6-1 Standby Mode Release Operation (a) Release of the STOP mode by RESET input Wait approximately 21.8 ms/6.0 MHz Note STOP instruction RESET signal Operating mode Oscillation STOP mode No oscillation HALT mode Oscillation Operating mode Clock (b) Release of the STOP mode by the occurrence of an interrupt Wait (Time set by BTM) STOP instruction Standby release signal Operating mode Oscillation STOP mode No oscillation HALT mode Oscillation Operating mode Clock Remark The dashed line indicates the case where the interrupt request that releases the standby mode is accepted (IME = 1). (c) Release of the HALT mode by RESET input Wait approximately 21.8 ms/6.0 MHz HALT instruction RESET signal Operating mode Operating mode Note HALT mode Oscillation Clock Note 31.3 ms at 4.19 MHz. 144 PD75238 (d) Release of the HALT mode by the occurrence of an interrupt HALT instruction Standby release signal Operating mode HALT mode Oscillation Operating mode Clock Remark The dashed line indicates the case where the interrupt request that releases the standby mode is accepted (IME = 1). The wait times used when the STOP mode is released do not include a time (a in the figure below) required before clock generation is started following the release of the STOP mode, regardless of whether the STOP mode is released by RESET signal input or the generation of an interrupt. STOP mode release Wave-form at the X1 pin a VSS When the STOP mode is released by the occurrence of an interrupt, a wait time is determined by BTM. (See Table 6-2.) Table 6-2 (When fX = 6.0 MHz) BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 Wait timeNote. ( ) indicates the value for fX = 6.0 MHz 0 1 1 1 Approx. 220/fX (Approx. 175 ms) Approx. 217/fX (Approx. 21.8 ms) Approx. 215/fX (Approx. 5.46 ms) Approx. 213/fX (Approx. 1.37 ms) Use prohibited Selection of a Wait Time with BTM Other than above (When fX = 4.19 MHz) BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 Wait timeNote. ( ) indicates the value for fX = 4.19 MHz Approx. 220/fX (Approx. 250 ms) Approx. 217/fX (Approx. 31.3 ms) Approx. 215/fX (Approx. 7.82 ms) Approx. 213/fX (Approx. 1.95 ms) Use prohibited Other than above Note This time does not include the time from the release of the STOP mode to the start of oscillation. 145 PD75238 6.3 OPERATION AFTER A STANDBY MODE IS RELEASED (1) If a standby mode is released by a RESET input, normal reset operation is performed. (2) If a standby mode is released by the occurrence of an interrupt request, bit 3 of the IPS (IME) determines whether to perform a vectored interrupt when the CPU resumes instruction execution. (a) When IME = 0 After the standby mode is released, execution of an instruction (NOP instruction) is restarted immediately after the instruction which set the standby mode. The interrupt request flag is held. (b) When IME = 1 After the standby mode is released, two instructions are executed, then a vector interrupt is caused. However, when the standby mode is released by INTW or INT2 (input of a testable signal), no vector interrupt is caused and the same processing as (a) above is performed. 146 PD75238 7. RESET FUNCTION Fig. 7-1 shows the configuration of the reset (RES) signal generator. Fig. 7-1 Reset Signal Generator RESET Internal reset signal (RES) Fig. 7-2 shows reset operation. The output buffer is set to off at the time of a RESET input. After a reset, the hardware is initialized as indicated in Table 7-1. Fig. 7-2 Reset Operation by RESET Input Wait (approximately 21.8 ms/6.0 MHz)Note RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation Note 31.3 ms at 4.19 MHz. After a reset, the hardware is initialized as indicated in Table 7-1. 147 PD75238 Table 7-1 Hardware Program counter (PC) Statuses of the Hardware after a Reset (1/2) RESET input in a standby mode Low-order 6 bits at address 0000H in program memory are set in PC bits 13 to 8, and the data at address 0001H are set in PC bits 7 to 0. RESET input during operation Low-order 6 bits at address 0000H in program memory are set in PC bits 13 to 8, and the data at address 0001H are set in PC bits 7 to 0. PSW Carry flag (CY) Skip flags (SK0 to SK2) Interrupt status flags (IST1, IST2) Bank enable flags (MBE, RBE) Held 0 0 Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. Held Held 0, 0 Undefined Undefined Undefined 0 0 FFH 0 0, 0 0 Held 0 0 0 0 Held 0 Undefined 0 0 Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. Undefined Undefined 0, 0 Undefined Undefined Undefined 0 0 FFH 0 0, 0 0 Held 0 0 0 0 Undefined 0 Data memory (RAM) General registers (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Stack pointer (SP) Stack bank select register (SBS) Basic interval timer Timer/event counter Counter (BT) Mode register (BTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Watch timer Timer/pulse generator Event counter Mode register (WM) Modulo registers (MODH, MODL) Mode register (TPGM) Counter (T1) Mode register (TM1) Gate control register (GATEC) Serial interface Shift register (SIO0) (Channel 0) Operation mode register (CSIM0) SBI control register (SBIC) Slave address register (SVA) P01/SCK0 output latch Serial interface Shift register (SIO1) (Channel 1) Operation mode register (CSIM1) Serial transfer end flag (EOT) 0 Held 1 Held 0 0 Undefined 1 Undefined 0 0 0 148 PD75238 Table 7-1 Statuses of the Hardware after a Reset (2/2) Hardware A/D converter Mode register (ADM), EOC SA register Bit sequential buffers (BSB0 to BSB3) FIP controller/ Mode register (DSPM) driver Dimmer select register (DIMS) Digit select register (DIGS) Display data memory Output buffer Static mode registers (STATA, STATB) Clock genera- Processor clock control register tor, clock out- (PCC) put circuit System clock control register (SCC) Clock output mode register (CLOM) Interrupt Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt master enable flag (IME) INT0 and INT1 mode registers (IM0, IM1) Digital ports Output buffer (Ports 2 to 7) Output latch (Ports 2 to 7) RESET input in a standby mode 04H (EOC = 1) Undefined Held 0 0 8H Held Off 0, 0 RESET input during operation 04H (EOC = 1) Undefined Undefined 0 0 8H Held Off 0, 0 0 0 0 0 Reset 0 0 0, 0 0 0 Reset 0 0 0, 0 Off Clear 0 0 Off Clear 0 0 I/O mode registers (PMGA, PMGB) Pull-up resistor specification register (POGA) Ports 10 to 15 Output buffer Output latch Port H Output latch Off 0 Held Off 0 Undefined 149 PD75238 8. INSTRUCTION SET 8.1 PD75238 INSTRUCTIONS (1) GETI instruction The GETI instruction references a two-byte table in the program memory and performs the following three types of operations. This single-byte instruction is very useful in reducing the number of program steps. (a) A subroutine call is made to a 16-KB space (0000H to 3FFFH), regarding data in a table as the call address of a call instruction. (b) A branch is made to a 16-KB space (0000H to 3FFFH), regarding data in a table as the branch address of a branch instruction. (c) Data in a table is executed as a double-byte instruction excluding BRCB and the CALLF instructions. (d) Data in a table is executed as the instruction code of two single-byte instructions. As shown in Fig. 3-2, the tables to be referenced by a GETI instruction are located at addresses 0020H to 007FH in the program memory. That is, data can be set in up to 48 tables. When describing a table address as an operand, describe an even address. Cautions 1. A two-byte instruction which can be referenced by a GETI instruction must be a twomachine-cycle instruction. 2. When referencing two single-byte instructions with a GETI instruction, only the combinations listed in the table below are valid. Instruction of first byte MOV A,@HL MOV @HL,A XCH A,@HL Instruction of second byte INCS DECS INCS DECS INCS INCS DECS INCS DECS INCS INCS DECS INCS DECS L L H H HL E E D D DE L L D D MOV A,@DE XCH A,@DE MOV A,@DL XCH A,@DL 3. Branch and subroutine instructions can be referenced by the GETI instruction only when the addresses of the destination and subroutine call are in the 16K-byte space (0000H to 3FFFH). A branch or subroutine instruction to an address from 4000H to 7F7FH cannot be referenced by the GETI instruction. 150 PD75238 Since PC does not increment the counter during execution of a GETI instruction, control returns to the address next to the GETI instruction after the execution of the GETI instruction. When the instruction before a GETI instruction has the skip function, the GETI instruction is skipped in the same way as for other single-byte instructions. When the instruction referenced by a GETI instruction has the skip function, the instructions after the GETI instruction are skipped. When a string effect instruction is referenced by a GETI instruction, the following results are obtained. * When the group of the string effect instruction before the GETI instruction is the same as that of the instruction referenced by the GETI instruction, the effect of the string effect instruction is canceled and the referenced instruction is not skipped. * When the group of the instruction after the GETI instruction is the same as that of the instruction referenced by the GETI instruction, the effect of the string effect instruction caused by the referenced instruction is valid and the instructions after the referenced instruction are skipped. (2) Bit manipulation instructions The PD75238 is provided with bit test instructions, bit transfer instructions, and bit Boolean instructions (AND, OR, and XOR) in addition to normal bit manipulation instructions (set instruction and clear instruction). Manipulation bits are specified by bit manipulation addressing. There are three types of bit manipulation addressing. The table below lists the bits manipulated by each addressing. Addressing fmem.bit Specifiable peripheral hardware RBE/MBE/IST1, IST0/IExxx/IRQxxx Port 0 to port 6 pmem.@L @H+mem.bit Port 0 and port 4 All the peripheral hardware (bitmanipulatable) Specifiable bit address range FB0H to FBFH FF0H to FFFH FC0H to FFFH All the bits of the memory bank specified by MB (bit-manipulatable) xxx: 0, 1, 2, 4, BT, T0, TPG, CSI0, KS, W MB = MBE* MBS 151 PD75238 (3) String effect instructions When two or more instructions in the same group (group A or B) are placed at two or more string effect addresses, the instruction placed at the start point of the string effect instructions is executed. After that, each string effect instruction is executed as an NOP instruction. Group A: MOV A, #n4, Group B: MOV HL, #n8 (4) Base conversion instruction The PD75238 is provided with base conversion instructions to convert the results of addition and subtraction of 4-bit data to a base-n number. When a base-m number is to be obtained, the following combinations of instructions are used for adjustment. MOV XA, #n8 * For addition ADDS A, #16-m ADDC A, @HL ADDS A, #m * For subtraction SUBC A, @HL ADDS A, #m The result of adding or subtracting the contents of the accumulator and the memory addressed by the HL register pair is converted to a base-m number. However, for subtraction, the complement of the obtained result (base-m number) is set in the accumulator. An overflow or underflow is reflected in the carry flag. (In the above combinations, the skip function of the ADDS A, #m instruction is prohibited.) 152 PD75238 8.2 INSTRUCTION SET AND ITS OPERATION (1) Representation format and description method of operands An operand is described in the operand field of each instruction according to the description method corresponding to the operand representation format of the instruction. Refer to the assembler specifications for details. When two or more elements are described in the description method field, select one of them. Uppercase letters, a plus sign (+), and a minus sign (-) are keywords, so they can be used without alteration. Specify an appropriate numeric value or label for immediate data. The symbols shown in format diagrams in Chapters 3 to 5 can be used as a label instead of mem, fmem, pmem, and bit. However, there are some restrictions on usable labels for fmem and pmem. (See (2) in Section 8.1.) Representation format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr1 addr caddr faddr taddr PORTn IExxx RBn MBn Description method X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH/FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-7F7FH immediate data or label 0000H-3F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (bit 0 = 0) or label PORT0-PORT15 IEBT, IECSI0, IET0, IETPG, IE0, IE1, IE2, IEKS, IEW, IE4 RB0-RB3 MB0, MB1, MB2, MB3, MB15 Note Only even addresses can be specified for 8-bit data processing. 153 PD75238 (2) Legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP SBS CY PSW MBE RBE IME IPS RBS MBS PCC . (xx) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : A register, 4-bit accumulator B register, 4-bit accumulator C register, 4-bit accumulator D register, 4-bit accumulator E register, 4-bit accumulator H register, 4-bit accumulator L register, 4-bit accumulator X register, 4-bit accumulator Register pair (XA), 8-bit accumulator Register pair (BC), 8-bit accumulator Register pair (DE), 8-bit accumulator Register pair (HL), 8-bit accumulator Extended register pair (XA') Extended register pair (BC') Extended register pair (DE') Extended register pair (HL') Program counter Stack pointer Stack bank select register Carry flag, bit accumulator Program status word Memory bank enable flag Register bank enable flag Port n (n = 0 to 15) Interrupt master enable flag Interrupt priority specification register Interrupt enable flag Register bank select register Memory bank select register Processor clock control register Address/bit delimiter Contents addressed by xx Hexadecimal data PORTn: IExxx : 154 PD75238 (3) Explanation of the symbols in the addressing area field *1 MB = MBE*MBS (MBS = 0, 1, 2, 3, or 15) MB = 0 MBE = 0: MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1: MB = MBS (MBS = 0, 1, 2, 3, or 15) MB = 15, fmem = FB0H-FBFH or FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-3FFFH addr = (Current PC) -15 to (Current PC) -1 or (Current PC) +2 to (Current PC) +16 caddr = 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH 4000H-4FFFH 5000H-5FFFH 6000H-6FFFH 7000H-7F7FH faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-7F7FH (PC14,13,12 = 00B) or (PC14,13,12 = 01B) or (PC14,13,12 = 10B) or (PC14,13,12 = 11B) or (PC14,13,12 = 100B) or (PC14,13,12 = 101B) or (PC14,13,12 = 110B) or (PC14,13,12 = 111B) Data memory addressing *2 *3 *4 *5 *6 *7 *8 Program memory addressing *9 *10 *11 Remarks 1. 2. 3. 4. MB indicates an accessible memory bank. For *2, MB is always 0 irrespective of MBE and MBS. For *4 and *5, MB is always 15 irrespective of MBE and MBS. *6 to *11 indicate each addressable area. (4) Explanation of the machine cycle column S represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation. S assumes one of the following values: * When no skip operation is performed * When a 3-byte instruction is skipped Caution : S=0 : S=2 * When a 1-byte instruction or 2-byte instruction is skipped: S = 1 The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle (= tCY) of the CPU clock (), and five types of times are available for selection according to the PCC and SCC settings. (See (3) in Section 4.2.) 155 PD75238 Instruction Mnemonic Transfer MOV Operand A,#n4 reg1,#n4 XA,#n8 HL,#n8 rp2,#n8 A,@HL A,@HL+ A,@HLA,@rpa1 XA,@HL @HL,A @HL,XA A,mem XA,mem mem,A mem,XA A,reg XA,rp' reg1,A rp'1,XA XCH A,@HL A,@HL+ A,@HLA,@rpa1 XA,@HL A,mem XA,mem A,reg1 XA,rp' Table reference MOVT XA,@PCDE XA,@PCXA XA, @BCDE XA, @BCXA Number Machine of bytes cycle Operation A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC14-8+DE)ROM XA (PC14-8+XA)ROM XA (BCDE)ROM XA (BCXA)ROM Addressing area Skip condition String effect A 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 String effect A String effect B *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *11 *11 156 PD75238 Instruction Mnemonic Bit transfer MOV1 Operand CY,fmem.bit CY,pmem.@L CY,@H+mem.bit fmem.bit,CY pmem.@L,CY @H+mem.bit,CY Arithmetic/logical ADDS A,#n4 XA,#n8 A,@HL XA,rp' rp'1,XA ADDC A,@HL XA,rp' rp'1,XA SUBS A,@HL XA,rp' rp'1,XA SUBC A,@HL XA,rp' rp'1,XA AND A,#n4 A,@HL XA,rp' rp'1,XA OR A,#n4 A,@HL XA,rp' rp'1,XA XOR A,#n4 A,@HL XA,rp' rp'1,XA Accumula- RORC tor manipulation NOT A A Number Machine of bytes cycle Operation CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A + n4 XA XA + n8 A A + (HL) XA XA + rp' rp'1 rp'1 + XA A,CY A + (HL) + CY XA,CY XA + rp' + CY rp'1,CY rp'1 + XA + CY A A - (HL) XA XA - rp' rp'1 rp'1 - XA A,CY A - (HL) - CY XA,CY XA - rp' - CY rp'1,CY rp'1 - XA - CY Addressing area Skip condition 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1 *1 borrow borrow borrow *1 n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA AA CY A0,A3 CY, An-1 An AA *1 *1 *1 157 PD75238 Instruction Mnemonic Increment/ INCS decrement reg rp1 @HL mem DECS reg rp' Comparison SKE reg,#n4 @HL,#n4 A,@HL XA,@HL A,reg XA,rp' Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY Operand Number Machine of bytes cycle Operation reg reg + 1 rp1 rp1 + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 rp' rp' - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY Addressing area Skip condition reg = 0 rp1 = 00H 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' CY = 1 158 PD75238 Instruction Mnemonic SET1 Memory bit manipulation Operand mem.bit fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit OR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit XOR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit Branch BR addr Number Machine of bytes cycle Operation (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 Skip if (H+mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2+L3-2.bit(L1-0)) = 0 Skip if (H+mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear Addressing area Skip condition 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 -- *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *11 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 Skip if (H+mem3-0.bit) = 1 and clear (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY PC14-0 addr1 (The assembler selects an appropriate instruction from the BR !addr, BRA !addr1, BRCB !caddr, and BR $addr1 instructions.) 5 *7 *6 $addr 1 !addr PCDE PCXA BCDE BCXA BRA BRCB !addr1 !caddr 1 3 2 2 2 2 3 2 2 3 3 3 3 3 3 2 PC14-0 addr1 PC14 0, PC13-0 !addr PC14-0 PC14-8 + DE PC14-0 PC14-8 + XA PC14-0 BCDE PC14-0 BCXA PC14-0 !addr1 PC14-0 PC14,13,12 + caddr11-0 *11 *8 159 PD75238 Instruction Mnemonic Subroutine stack control CALL Operand !addr Number Machine of bytes cycle Operation (SP-5)(SP-6)(SP-3)(SP-4) PC14-0 (SP-2) x, x, MBE, RBE PC14 0, PC13-0 addr, SP SP-6 Addressing area Skip condition 3 4 *6 CALLA !addr1 3 3 (SP-5)(SP-6)(SP-3)(SP-4) PC14-0 (SP-2) x, x, MBE, RBE PC14-0 addr1, SP SP-6 (SP-5)(SP-6)(SP-3)(SP-4) PC14-0 (SP-2) x, x, MBE, RBE PC14-0 0000, faddr, SP SP-6 *11 CALLF !faddr 2 3 *9 RET 1 3 x, x, MBE, RBE (SP+4) PC14-0 (SP+1)(SP)(SP+3)(SP+2) SP SP+6 x, x, MBE, RBE (SP+4) PC14-0 (SP+1) (SP)(SP+3)(SP+2) SP SP+6 then skip unconditionally x, PC14,13,12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1)(SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 IME(IPS.3) 1 IExxx 1 IME(IPS.3) 0 IExxx 0 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation Unconditionally RETS 1 3+S RETI 1 3 PUSH rp BS 1 2 1 2 POP rp BS 1 2 1 2 Interrupt control EI IExxx DI IExxx 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2 2 2 2 1 I/O INNote A,PORTn XA,PORTn OUTNote PORTn,A PORTn,XA CPU control HALT STOP NOP Note MBE = 0, or MBE = 1 and MBS = 15 must be set when an IN/OUT instruction is executed. 160 PD75238 Instruction Mnemonic Special SEL Operand RBn MBn GETINote taddr Number Machine of bytes cycle Operation RBS n (n=0-3) MBS n (n=0,1,2,3,15) * For a TBR instruction PC13-0 (taddr)5-0 + (taddr+1) PC14 0 * For a TCALL instruction (SP-5)(SP-6)(SP-3)(SP-4) PC14-0 (SP-2) x, x, MBE, RBE PC13-0 (taddr)5-0 + (taddr+1) SP SP-6 PC14 0 * For an instruction other than TBR and TCALL Executes the instruction in (taddr)(taddr+1). Addressing area Skip condition 2 2 1 2 2 3 *10 5 4 3 Depends upon the referenced instruction. Note The TBR and TCALL instructions are table definition assembler pseudo instructions of the GETI instructions. 161 PD75238 8.3 INSTRUCTION CODES OF EACH INSTRUCTION (1) Explanations of the symbols for the instruction codes R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 reg A X L H reg E D C B reg1 P2 0 0 0 0 1 1 1 1 P1 0 0 1 1 0 0 1 1 P0 0 1 0 1 0 1 0 1 reg-pair XA XA' HL HL' DE DE' BC BC' rp' rp'1 Q2 0 0 0 1 1 Q1 0 1 1 0 0 Q0 1 0 1 0 1 addressing @HL @HL+ @HL- @DE @DL @rpa1 @rpa P2 0 0 1 1 P1 0 1 0 1 reg-pair XA HL DE rp2 BC rp1 rp N5 0 0 0 0 0 0 0 1 1 1 N2 0 0 0 1 1 1 1 0 0 1 N1 0 1 1 0 0 1 1 0 1 1 N0 0 0 1 0 1 0 1 0 1 0 IExxx IEBT IEW IETPG IET0 IECSI0 IE0 IE2 IE4 IEKS IE1 In : Immediate data for n4 or n8 Dn: Immediate data for mem Bn: Immediate data for bit Nn: Immediate data for n or IExxx Tn: Immediate data for taddr x 1/2 An: Immediate data for the relative address distance (2 to 16) for the branch destination address minus one Sn: Immediate data for the ones complement of the relative address distance (15 to 1) for the branch destination address 162 PD75238 (2) Bit manipulation addressing instruction codes *1 in the operand field indicates that there are three types of bit manipulation addressing, fmem.bit, pmem.@L, and @H+mem.bit. The table below lists the second byte *2 of an instruction code corresponding to the above addressing. Second byte of instruction code 1 1 pmem.@L @H+mem.bit 0 0 0 1 1 0 B1 B1 0 B1 B0 B0 0 B0 F3 F3 G3 D3 F2 F2 G2 D2 F1 F1 G1 D1 F0 F0 G0 D0 *1 fmem.bit Accessible bits FB0H - FBFH manipulatable bits FF0H - FFFH manipulatable bits FC0H-FFFH manipulatable bits Manipulatable bits of accessible memory bank Bn: Immediate data for bit Fn: Immediate data for fmem (Low-order four bits of address) Gn: Immediate data for pmem (Bits 2 to 5 of address) Dn: Immediate data for mem (Low-order four bits of address) 163 PD75238 Instruction Transfer Instruction code Mnemonic MOV Operand A, #n4 reg1, #n4 rp, #n8 A, @rpa XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA XCH A, @rpa XA, @HL A, mem XA, mem A, reg1 XA, rp' Table MOVT reference XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA Bit transfer MOV1 CY, *1 *1 , CY B1 0 1 1 1 I3 I2 I1 I0 10011010 1 0 0 0 1 P2 P1 1 1 1 1 0 0 Q2 Q1 Q0 10101010 11101000 10101010 10100011 10100010 10010011 10010010 10011001 10101010 10011001 10101010 1 1 1 0 1 Q2 Q1 Q0 10101010 10110011 10110010 1 1 0 1 1 R2 R1 R0 10101010 11010100 11010000 11010101 11010001 10111101 10011011 *2 *2 0 1 0 0 0 P2 P1 P0 00010001 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 00010000 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 0 1 1 1 1 R2 R1 R0 0 1 0 1 1 P2 P1 P0 0 1 1 1 0 R2 R1 R0 0 1 0 1 0 P2 P1 P0 00011000 I3 I2 I1 I0 1 R2 R1 R0 I7 I6 I5 I4 I3 I2 I1 I0 B2 B3 164 PD75238 Instruction Instruction code Mnemonic Operand B1 A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA Accumu- RORC lator manipulation NOT A A 0 1 1 0 I3 I2 I1 I0 10111001 11010010 10101010 10101010 10101001 10101010 10101010 10101000 10101010 10101010 10111000 10101010 10101010 10011001 10010000 10101010 10101010 10011001 10100000 10101010 10101010 10011001 10110000 10101010 10101010 10011000 10011001 01011111 1 0 1 1 1 P2 P1 P0 1 0 1 1 0 P2 P1 P0 1 0 1 0 1 P2 P1 P0 1 0 1 0 0 P2 P1 P0 0 1 0 1 I3 I2 I1 I0 1 0 0 1 1 P2 P1 P0 1 0 0 1 0 P2 P1 P0 0 1 0 0 I3 I2 I1 I0 1 1 1 1 1 P2 P1 P0 1 1 1 1 0 P2 P1 P0 0 0 1 1 I3 I2 I1 I0 1 1 1 0 1 P2 P1 P0 1 1 1 0 0 P2 P1 P0 1 1 0 1 1 P2 P1 P0 1 1 0 1 0 P2 P1 P0 1 1 0 0 1 P2 P1 P0 1 1 0 0 0 P2 P1 P0 I7 I6 I5 I4 I3 I2 I1 I0 B2 B3 Arithme- ADDS tic/logical 165 PD75238 Instruction Increment/ decrement Instruction code B1 INCS reg rp1 @HL mem DECS reg rp' Comparison SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag SET1 manipuCLR1 lation SKT NOT1 Memory bit manipulation SET1 CY CY CY CY mem.bit *1 CLR1 mem.bit *1 SKT mem.bit *1 SKF mem.bit *1 SKTCLR AND1 OR1 XOR1 *1 CY, *1 CY, *1 CY, *1 1 1 0 0 0 R2 R1 R0 1 0 0 0 1 P2 P1 0 10011001 10000010 1 1 0 0 1 R2 R1 R0 10101010 10011010 10011001 10000000 10101010 10011001 10101010 11100111 11100110 11010111 11010110 1 0 B1 B0 0 1 0 1 10011101 1 0 B1 B0 0 1 0 0 10011100 1 0 B1 B0 0 1 1 1 10111111 1 0 B1 B0 0 1 1 0 10111110 10011111 10101100 10101110 10111100 D7 D6 D5 D4 D3 D2 D1 D0 *2 D7 D6 D5 D4 D3 D2 D1 D0 *2 D7 D6 D5 D4 D3 D2 D1 D0 *2 D7 D6 D5 D4 D3 D2 D1 D0 *2 *2 *2 *2 *2 00011001 0 0 0 0 1 R2 R1 R0 0 1 0 0 1 P2 P1 P0 0 1 1 0 1 P2 P1 P0 I3 I2 I1 I0 0 R2 R1 R0 0 1 1 0 I3 I2 I1 I0 00000010 D7 D6 D5 D4 D3 D2 D1 D0 B2 B3 Mnemonic Operand 166 PD75238 Instruction Branch Instruction code Mnemonic BR Operand B1 !addr $addr1 (+16) to (+2) (-1) to (-15) B2 00 addr B3 10101011 0 0 0 0 A3 A2 A1 A0 1 1 1 1 S3 S2 S1 S0 10011001 10011001 10011001 10011001 10111010 0101 10101011 10111011 01000 11101110 11100000 11101111 5 PCDE PCXA BCDE BCXA BRA BRCB Subrou- CALL tine stack CALLA control CALLF RET RETS RETI PUSH rp BS POP rp BS I/O IN A, PORTn XA, PORTn OUT PORTn, A PORTn, XA Interrupt control EI IExxx DI IExxx CPU control HALT STOP NOP Special SEL RBn MBn GETI taddr !addr1 !caddr !addr !addr1 !faddr 00000100 00000000 00000101 00000001 0 caddr 01 0 faddr addr addr1 addr1 0 1 0 0 1 P2 P1 1 10011001 0 1 0 0 1 P2 P1 0 10011001 10100011 10100010 10010011 10010010 10011101 10011101 10011100 10011100 10011101 10011101 01100000 10011001 10011001 0 0 T5 T4 T3 T2 T1 T0 0 0 1 0 0 0 N1 N0 0 0 0 1 N3 N2 N1 N0 00000110 1 1 1 1 N3 N2 N1 N0 1 1 1 1 N3 N2 N1 N0 1 1 1 1 N3 N2 N1 N0 1 1 1 1 N3 N2 N1 N0 10110010 1 0 N5 1 1 N2 N1 N0 10110010 1 0 N5 1 1 N2 N1 N0 10100011 10110011 00000111 167 PD75238 9. SPECIFICATION OF MASK OPTIONS The PD75238 provides the following mask options, which enable specifying whether to incorporate the elements below: Pin P40-P43 P50-P53 P70-P73 S0/P120-S3/P123 S4/P130-S7/P133 S8/P140, S9/P141 S10/T15/P142, S11/T14/P143 S12/T13/P150/PH0-S15/T10/P153/PH3 S16/P100-S19/P103 S20/P110-S23/P113 XT1, XT2 Mask option Allows pull-up resistor to be contained bit by bit. Allows pull-down resistor to be contained bit by bit. Allows pull-down resistor to be contained to VLOAD bit by bit. Allows pull-down resistorNote to be contained to VLOAD or VSS bit by bit. Allows feed-back resistor of the subsystem clock oscillator to be deleted. Note Select whether to incorporate the pull-down resistors in VLOAD or VSS in unit of eight bits. Caution In systems without using subsystem clock, power consumption in STOP mode can be more reduced by deleting feed-back resistor of the oscillator. 168 PD75238 10. APPLICATION BLOCK DIAGRAM Power failure detection INT4 T0-T15 S0-S17 Electronic tuner LPF PPO ANn Hsync pulse Fluorescent indicator panel (FIP) 18 segments x 16 digits PD75238 L Voice level R ANn Timer Tuner System computer Remote-control reception Hsync detection PORT7 Key matrix (18 x 4) PC1490 INT0 LED PORTn Remote controller signal Mechanical components SCK0 OSD SCK1 SO1 SO0 PORTn BUZ X1 X2 XT1 XT2 Servo IC BZ Piezo-electric buzzer 4.19/6.0 MHz 32.768 kHz Remark LPF : Low pass filter OSD : On screen display Hsync : Horizontal synchronous 169 PD75238 11. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (Ta = 25 C) Parameter Supply voltage Symbol VDD VLOAD Input voltage VI1 VI2 Ports other than ports 4 and 5 Ports 4 and 5 Built-in pull-up resistor Open drain Output voltage VO VOD High-level output current IOH Pins other than display output pins Display output pins One of pins other than display output pins One pin of S0 to S9 and S16 to S23 One pin of T0 to T15 All pins other than display output pins All display output pins Low-level output current IOL Each pin Peak value rms Total of all pins of Peak value ports 0, 2, 3, and 4 rms Total of all pins of ports 5 to 8 Total power dismission PT Plastic QFP Peak value rms (Ta = -40 to +70 C) (Ta = -40 to +85 C) Operating temperature Storage temperature Topt Tstg Conditions Rating -0.3 to +7.0 VDD - 40 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -0.3 to VDD + 0.3 VDD - 40 to VDD + 0.3 -15 Unit V V V V V V V mA -15 -30 -30 -120 30 15 100 60 100 60 700 510 -40 to +85 -65 to +150 mA mA mA mA mA mA mA mA mA mA mW mW C C RANGE OF SUPPLY VOLTAGE (Ta = -40 to +85 C) Parameter CPUNote 1 Display controller Timer/pulse generator Hardware other than the aboveNote 1 Min. Note 2 Max. 6.0 6.0 6.0 6.0 Unit V V V V Conditions 4.5 4.5 2.7 Notes 1. 2. The CPU does not include the system clock oscillator, the display controller, and the timer/pulse generator. The range of the supply voltage at which the CPU can operate varies according to the cycle time. See the item of AC characteristics. 170 PD75238 CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) Resonator Ceramic resonator Recommended constant X1 X2 Parameter Oscillator frequency (fX)Note 1 Min. 2.0 Typ. Max. 6.2 Unit MHz Conditions VDD = oscillation voltage range After VDD reaches Min. of the oscillation voltage range C1 C2 Oscillation stability timeNote 2 Oscillator frequency (fX)Note 1 2.0 4.19 4 ms Crystal resonator 6.2 MHz X1 X2 C1 C2 Oscillation stability timeNote 2 X1 input frequency (fX)Note 1 X1 input high/low level width (tXH, tXL) 2.0 10 30 6.2 ms ms MHz VDD = 4.5 to 6.0 V External clock X1 X2 81 250 ns PD74HCU04 Notes 1. 2. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. The oscillation stability time means the time required for the oscillation to stabilize after VDD is applied or after the STOP mode is released. CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) Resonator Crystal resonator Recommended constant Parameter Oscillator frequency (fXT)Note 1 Oscillation stability timeNote 2 XT1 input frequency (fXT)Note 1 XT1 input high/low level width (tXTH, tXTL) 32 Min. 32 Typ. 32.768 Max. 35 Unit kHz Conditions XT1 XT2 R 1.0 2 10 100 s s kHz VDD = 4.5 to 6.0 V C3 C4 External clock XT1 XT2 5 15 s Notes 1. 2. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. The oscillation stability time means the time required for the oscillation to stabilize after VDD is applied or after the STOP mode is released. CAPACITANCE (Ta = 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance (Other than display output) I/O capacitance Output capacitance (Display output) Symbol CI CO CIO CO Min. Typ. Max. 15 15 15 35 Unit pF pF pF pF Conditions f = 1 MHz 0 V for pins other than pins to be measured 171 PD75238 DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) Parameter High-level input voltage Symbol VIH1 Min. 0.7VDD Typ. Max. VDD Unit V Conditions Other than ports 0, 1, 4, 5, and 7, RESET, P81, P83, X1, X2, and XT1 Ports 0 and 1, RESET, P81, and P83 X1, X2, and XT1 Port 7 VDD = 4.5 to 6.0 V VIH2 VIH3 VIH4 0.8VDD VDD - 0.4 0.65VDD 0.7VDD VDD VDD VDD VDD VDD 10 0.3VDD V V V V V V V VIH5 0.7VDD 0.7VDD Ports 4 and 5 Built-in pull-up resistor Open drain Low-level input voltage VIL1 0 Other than ports 0 and 1, RESET, P81, P83, X1, X2, and XT1 Ports 0 and 1, RESET, P81, and P83 X1, X2, and XT1 All output pins VDD = 4.5 to 6.0 V (excl. ports 4 and 5, and P03) VDD = 2.7 to 6.0 V Ports 3, 4, and 5 VDD = 4.5 to 6.0 V IOH = -1 mA IOH = -100 A IOL = 15 mA VIL2 VIL3 High-level output voltage VOH 0 0 VDD - 1.0 VDD - 0.5 0.2VDD 0.4 V V V V Low-level output voltage VOL 0.4 2.0 V 0.4 0.5 0.2VDD ILIH1 V V V All output pins VDD = 4.5 to 6.0 V VDD = 2.7 to 6.0 V SB0 and SB1 IOL = 1.6 mA IOL = 400 A Open drain pull-up resistor: 1 k or more VIN = VDD High-level input leakage current 3 A A A A A A A A A mA mA Other than X1, X2, XT1, Ports 4 and 5 X1, X2, and XT1 Ports 4 and 5 Other than X1, X2, and XT1 X1, X2, and XT1 Other than ports 4 and 5 Ports 4 and 5 ILIH2 ILIH3 Low-level input leakage current ILIL1 20 20 -3 VIN = 10 V (open drain) VIN = 0 V ILIL2 High-level output leakage current Low-level output leakage current ILOH1 ILOH2 ILOL1 ILOL2 -20 3 20 -3 -10 VOUT = VDD VOUT = 10 V (open drain) Other than display output VOUT = 0 V Display output VOUT = VLOAD = VDD - 35 V VDD = 4.5 to 6.0 V VOD = VDD - 2 V VDD = 4.5 to 6.0 V Display output current Built-in pull-down resistor (mask option) Built-in pull-up resistor IOD -3 -15 -5.5 -22 80 200 1000 50 40 135 80 300 40 70 60 S0 to S9, S16 to S23 T0 to T15 Port 7 VIN = VDD Display output Ports 0, 1, 2, 3, and 6 (excl. P00) VIN = 0 V Ports 4 and 5 VOUT = VDD - 2.0 V RP7 20 20 k k k k k k k RL RV1 25 15 30 VOD - VLOAD = 35 V VDD = 5 V 10 % VDD = 3 V 10 % VDD = 5 V 10 % VDD = 3 V 10 % RV2 15 10 172 PD75238 DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) Parameter Power supply current Note 1 Symbol IDD1 Min. Typ. 4.5 0.6 IDD2 600 200 IDD1 3 0.5 IDD2 600 200 IDD3 40 Max. 13.5 1.8 1800 600 9 1.5 1800 600 120 Unit mA mA 6.0 MHz crystal resonance C1 = C2 = 22 pFNote 4 4.19 MHz crystal resonance C1 = C2 = 22 pFNote 4 32 crystal resonance kHzNote 5 Conditions Operation VDD = 5 V 10 %Note 2 mode VDD = 3 V 10 %Note 3 HALT mode VDD = 5 V 10 % VDD = 3 V 10 % A A mA mA Operation VDD = 5 V 10 %Note 2 mode VDD = 3 V 10 %Note 3 HALT mode VDD = 5 V 10 % VDD = 3 V 10 % A A A A Operation VDD = 3 V 10 % mode HALT mode VDD = 3 V 10 % IDD4 5 15 IDD5 0.5 0.3 20 10 5 A A A VDD = 5 V 10 % XT1 = 0 V STOP mode VDD = 3 V 10 % Ta = 25 C Notes 1. 2. 3. 4. 5. This current excludes the current which flows through the built-in pull-down or pull-up resistors. Value when the processor clock control register (PCC) is set to 0011 and the PD75238 is operated in the high-speed mode Value when the PCC is set to 0000 and the PD75238 is operated in the low-speed mode This value applies also when the subsystem clock oscillates. This value applies when the system clock control resistor (SCC) is set to 1001 to stop the main system clock pulse and to start the subsystem clock pulse. A/D CONVERTER CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V, AVDD = VDD) Parameter Resolution Absolute accuracyNote 1 Symbol Min. 8 Typ. 8 Max. 8 1.5 2.0 Conversion time Sampling time Analog input voltage Analog input impedance AVREF current tCONV tSAMP VIAN RAN IAREF AVSS 1000 1.0 2.0 168/fX 44/fX AVREF Unit bit LSB 2.5 V AVREF AVDD -10 Ta +85 C -40 Ta < -10 C Conditions 5 s s V M mA Note 2 Note 3 Notes 1. 2. 3. Absolute accuracy excluding quantization error (1/2 LSB) Time from the execution of a conversion start instruction till EOC = 1 (28.0 s at fX = 6.0 MHz, 40.1 s at fX = 4.19 MHz) Time from the execution of a conversion start instruction till the end of sampling (7.33 s at fX = 6.0 MHz, 10.5 s at fX = 4.19 MHz) 173 PD75238 AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (1) Basic operation Parameter CPU clock cycle time (minimum instruction execution time)Note 1 TI0 input frequency Symbol tCY Min. 0.67 2.6 114 fTI 0 0 TI0 input high/low level width Interrupt input high/low level width RESET low level width tTIH, tTIL tINTH, tINTL tRSL 0.48 1.8 Note 2 Typ. Max. 64 64 Unit Conditions Operated by main system clock pulse VDD = 4.5 to 6.0 V s s s MHz kHz 122 125 1 275 Operated by subsystem clock pulse VDD = 4.5 to 6.0 V s s s s s VDD = 4.5 to 6.0 V INT0 INT1, INT2, and INT4 10 10 Notes 1. The cycle time of CPU clock () depends on the connected resonator frequency, the system clock control register (SCC), and the processor clock control register (PCC). The figure on the next page shows the cycle time tCY characteristics for the supply voltage VDD during main system clock operation. 2. This value becomes 2tCY or 128/fX according to the setting of the interrupt mode register (IM0). Cycle time tCY [ s] tCY vs VDD (When the main system clock is operating) 70 64 60 6 5 4 3 Guaranteed operating range 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] 174 PD75238 (2) Serial transfer operation (a) Two-wire and three-wire serial I/O modes (SCK ... Internal clock output): Parameter SCK cycle time Symbol tKCY1 Min. 1340 1600 2680 3800 SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) SCK SO output delay time tKL1 tKH1 tSIK1 (tKCY/2) - 50 (tKCY/2) - 150 150 Typ. Max. Unit ns ns ns ns ns ns ns VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V fX = 6.0 MHz fX = 4.19 MHz fX = 6.0 MHz fX = 4.19 MHz tKSI1 400 ns tKSO1 250 1000 ns ns RL = 1 k, CL = 100 pFNote VDD = 4.5 to 6.0 V Note RL and CL are the resistance and capacitance of the SO output line load respectively. (b) Two-wire and three-wire serial I/O modes (SCK ... External clock input): Parameter SCK cycle time Symbol tKCY2 Min. 800 3200 SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) SCK SO output delay time tKL2 tKH2 tSIK2 400 1600 100 Typ. Max. Unit ns ns ns ns ns VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V tKSI2 400 ns tKSO2 300 1000 ns ns RL = 1 k, CL = 100 pFNote VDD = 4.5 to 6.0 V Note RL and CL are the resistance and capacitance of the SO output line load respectively. 175 PD75238 (c) SBI mode (SCK ... Internal clock output (master)): Parameter SCK cycle time Symbol tKCY3 Min. 1340 1600 2680 3800 SCK high/low level width SB0/SB1 setup time (referred to SCK) SB0/SB1 hold time (referred to SCK) SCK SB0/SB1 output delay time SCK SB0/SB1 SB0/SB1 SCK SB0/SB1 low level width SB0/SB1 high level width tKL3 tKH3 tSIK3 tKCY/2 - 50 tKCY/2 - 150 150 Typ. Max. Unit ns ns ns ns ns ns ns VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V fX = 6.0 MHz fX = 4.19 MHz fX = 6.0 MHz fX = 4.19 MHz tKSI3 tKCY/2 ns tKSO3 0 0 250 1000 ns ns ns ns ns RL = 1 k , CL = 100 pFNote VDD = 4.5 to 6.0 V tKSB tSBK tSBL tKCY tKCY tKCY tSBH tKCY ns Note RL and CL are the resistance and capacitance of the SO output line load respectively. (d) SBI mode (SCK ... External clock input (slave)): Parameter SCK cycle time Symbol tKCY4 Min. 800 3200 SCK high/low level width SB0/SB1 setup time (referred to SCK) SB0/SB1 hold time (referred to SCK) SCK SB0/SB1 output delay time SCK SB0/SB1 SB0/SB1 SCK SB0/SB1 low level width SB0/SB1 high level width tKL4 tKH4 tSIK4 400 1600 100 Typ. Max. Unit ns ns ns ns ns VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V tKSI4 tKCY/2 ns tKSO4 0 0 300 1000 ns ns ns ns ns RL = 1 k , CL = 100 pFNote VDD = 4.5 to 6.0 V tKSB tSBK tSBL tKCY tKCY tKCY tSBH tKCY ns Note RL and CL are the resistance and capacitance of the SO output line load respectively. 176 PD75238 AC Timing Measurement Points (Excluding X1 and XT1 Inputs) 0.8VDD 0.2VDD Measurement point 0.8VDD 0.2VDD Clock Timing 1/fX tXL tXH VDD - 0.5 V X1 input 0.4 V 1/fXT tXTL tXTH VDD - 0.5 V XT1 input 0.4 V TI0 Timing 1/fTI tTIL tTIH TI0 177 PD75238 Serial Transfer Timing Three-wire serial I/O mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 SI Input data tKSO1 SO Output data Two-wire serial I/O mode: tKCY2 tKL2 tKH2 SCK tSIK2 tKSO2 tKSI2 SB0 and SB1 178 PD75238 Serial Transfer Timing Bus release signal transfer: tKCY3 tKCY4 tKL3 tKL4 SCK tSIK3 tSIK4 tKSI3 tKSI4 tKH3 tKH4 tKSB tSBL tSBH tSBK SB0 and SB1 tKSO3 tKSO4 Command signal transfer: tKCY3 tKCY4 tKL3 tKL4 SCK tSIK3 tSIK4 tKSI3 tKSI4 tKH3 tKH4 tKSB tSBK SB0 and SB1 tKSO3 tKSO4 Interrupt Input Timing tINTL tINTH INT0, INT1, INT2 and INT4 RESET Input Timing tRSL RESET 179 PD75238 DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE (Ta = -40 to +85 C) Parameter Data hold supply voltage Data hold supply currentNote 1 Symbol VDDDR IDDDR tSREL tWAIT Min. 2.0 Typ. Max. 6.0 Unit V Conditions 0.1 0 217/fX Note 3 10 A s ms ms VDDDR = 2.0 V Release signal setting time Oscillation stability wait timeNote 2 Release by RESET Release by interrupt request Notes 1. 2. 3. Excluding the current which flows through the built-in pull-up or pull-down resistors CPU operation stop time for preventing unstable operation at the beginning of oscillation This value depends on the settings of the basic interval timer mode register (BTM) shown below. BTM3 -- -- -- -- BTM2 0 0 1 1 Wait time BTM1 0 1 0 1 BTM0 fX = 6.0 MHz 0 1 1 1 220/fX 217/fX 215/fX 213/fX (approx. 175 ms) (approx. 21.8 ms) (approx. 5.46 ms) (approx. 1.37 ms) 220/fX 217/fX 215/fX 213/fX fX = 4.19 MHz (approx. 250 ms) (approx. 31.3 ms) (approx. 7.82 ms) (approx. 1.95 ms) Data Hold Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Data hold mode Operation mode VDD VDDDR STOP instruction execution tSREL RESET tWAIT Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Data hold mode Operation mode VDD VDDDR STOP instruction execution tSREL Standby release signal (interrupt request) tWAIT 180 PD75238 12. CHARACTERISTIC CURVES (FOR REFERENCE) IDD vs VDD (Main System Clock: 6.0 MHz) (Ta = 25 C) 5 5000 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1000 Main system clock HALT mode + 32 kHz oscillation 500 Supply current IDD ( A) Subsystem clock operation mode 100 50 Main system clock STOP mode + 32 kHz oscillation, and subsystem clock HALT mode 10 X1 X2 Crystal resonator 6.0 MHz 22 pF 22 pF XT1 XT2 Crystal resonator 32.768 kHz 330 k 22 pF 22 pF 5 1 0 1 2 3 4 Supply voltage VDD (V) 5 6 7 181 PD75238 IDD vs VDD (Main System Clock: 4.19 MHz) (Ta = 25 C) 5000 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1000 Main system clock HALT mode + 32 kHz oscillation 500 Supply current IDD ( A) Subsystem clock operation mode 100 50 Main system clock STOP mode + 32 kHz oscillation, and subsystem clock HALT mode 10 X1 X2 Crystal resonator 4.19 MHz 30 pF 30 pF XT1 XT2 Crystal resonator 32.768 kHz 330 k 22 pF 22 pF 5 1 0 1 2 3 4 Supply voltage VDD (V) 5 6 7 182 PD75238 13. PACKAGE DIMENSIONS 94 PIN PLASTIC QFP ( 20) A B F2 71 72 48 47 detail of lead end C D S 94 1 24 23 F1 G1 G2 H I M J K P N NOTE L ITEM MILLIMETERS A B C D F1 F2 G1 G2 H I J K L M N P Q R S 23.20.4 20.00.2 20.00.2 23.20.4 1.6 0.8 1.6 0.8 0.350.10 0.15 0.8 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 3.7 0.10.1 5 5 4.0 MAX. INCHES 0.913 +0.017 -0.016 +0.009 0.787 -0.008 0.787 +0.009 -0.008 0.913 +0.017 -0.016 0.063 0.031 0.063 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.146 0.0040.004 55 0.158 MAX. S94GJ-80-5BG-3 Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. M Q R 183 PD75238 5 14. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met when soldering the PD75238. Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Table 14-1 Recommended Soldering Conditions Part number Package 94-pin plastic QFP Symbol WS60-107-1 IR30-107-1 VP15-107-1 Partial heating method PD75238GJ-xxx-5BG Table 14-2 Soldering Conditions Symbol WS60-107-1 Soldering process Wave soldering Soldering conditions Temperature in the soldering vessel: 260 C or below Soldering time: 10 seconds or less Number of soldering processes: 1 Exposure limit: 7 daysNote (10 hours of pre-baking is required at 125 C afterward.) Pre-heating temperature: 120 C max. (package surface temperature) Peak package's surface temperature: 230 C Reflow time: 30 seconds or less (at 210 C or higher) Number of reflow processes: 1 Exposure limit: 7 daysNote (10 hours of pre-baking is required at 125 C afterward.) Peak package's surface temperature: 215 C Reflow time: 40 seconds or less (at 200 C or higher) Number of reflow processes: 1 Exposure limit: 7 daysNote (10 hours of pre-baking is required at 125 C afterward.) Terminal temperature: 300 C or below Flow time: 3 seconds or less (one side per device) IR30-107-1 Infrared ray reflow VP15-107-1 VPS Partial heating method Partial heating method Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 C and relative humidity at 65 % or less. Caution Do not apply more than a single process at a time, except for "Partial heating method." Remark For more details, refer to our document "SMT MANUAL" (IEI-1207). 184 PD75238 APPENDIX A Item ROM RAM Instruction cycle When main system clock is selected When subsystem clock is selected I/O lines (including FIP dual-function pins and excluding FIP-exclusive pins) Total number of I/O lines Number of input lines 33 PD75238 SERIES PRODUCT FUNCTION LIST Product PD75217 24448 x 8 768 x 4 0.95 s/1.91 s/ 15.3 s (at 4.19 MHz) PD75236 16256 x 8 PD75237 24448 x 8 PD75238 PD75P238 32640 x 8 1024 x 4 0.95 s/1.91 s/ 3.82 s/15.3 s (at 4.19 MHz) 0.67 s/1.33 s/2.67 s/10.7 s (at 6.0 MHz) 122 s (at 32.768 kHz) 64 8 16 Number of I/O 20: Eight lines for driving lines LED Number of output lines 5 24 : 12 lines for driving LED 24 A/D converter FIP controller/driver High-voltage output Number of segments Number of digits Timer Serial interface None 26: 40 V (max.) 8 : 8-bit resolution 34 : 40 V (max.) 9 to 16 9 to 24 9 to 16 Five channels SBI/3-wire system Two channels 3-wire system 3-wire system 11 -40 to +85 C 2.7 to 6.0 V 64-pin plastic shrink DIP 64-pin plastic QFP 94-pin plastic QFP 94-pin plastic QFP 94-pin ceramic LCC with a window -40 to +70 C Four channels One channel: Number of interrupt sources Range of operating temperature 10 5 Operating power voltage Package 185 PD75238 5 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for developing a system which employs the PD75238. Language processor RA75X relocatable assembler Host machine PC-9800 series Part number OS MS-DOSTM Ver. 3.10 to Ver. 3.30C PC DOS TM (Ver. 3.1) Distribution media 3.5-inch 2HD S5A13RA75X S5A10RA75X S7B10RA75X 5-inch 2HD 5-inch 2HC IBM PC series PROM programming tools Hardware PG-1500 A PROM programmer with which programs can be written into PROMs through keyboards or by remote control, when connected with the accessory board and optional programmer adapter. Products programmable with the PG-1500 are commonly-used PROMs (256K-bit to 1M-bit) and single chip microcomputers containing a PROM. A PROM programmer adapter for the PD75P238. This adapter is connected to the PG-1500. Software PG-1500 controller This program enables the host machine to control the PG-1500 through the serial and parallel interfaces. Host machine PC-9800 series Part number Distribution media 3.5-inch 2HD 5-inch 2HD PA-75P238GJ OS MS-DOS Ver. 3.10 to Ver. 3.30C PC DOS (Ver. 3.1) S5A13PG1500 S5A10PG1500 S7B10PG1500 IBM PC series 5-inch 2HC 186 PD75238 Debugging tools Hardware IE-75000-RNote The IE-75000-R is an in-circuit emulator available for the 75X series. This emulator is used together with the emulation probe to develop application systems of the PD75238. For efficient debugging, the emulator is connected to the host machine and PROM programmer. IE-75000-R-EM The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001R. The IE-75000-R contains the emulation board. The emulation board is used together with the IE-75000-R or IE-75001-R to evaluate the PD75238. IE-75001-R The IE-75001-R is an in-circuit emulator available for the 75X series. This emulator is used together with the IE-75000-R-EM emulation board (option) and emulation probe to develop application systems of the PD75238. For efficient debugging, the emulator is connected to the host machine and PROM programmer. EP-75238GJ-R EV-9200G-94 Software IE control program The EP-75238GJ-R is an emulation probe for the PD75238 (94-pin plastic QFP). The emulation probe is connected to the IE-75000-R or IE-75001-R when it is used. A 94-pin conversion socket, the EV-9200G-94, attached to the probe facilitates the connection of the prove with the user system. This program enables the host machine to control the IE-75000-R or IE-75001-R through the RS-232-C interface. Host machine OS PC-9800 series MS-DOS Ver. 3.10 to Ver. 3.30C IBM PC series PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD Part number S5A13IE75X S5A10IE75X S7B10IE75X 5-inch 2HD 5-inch 2HC Note Maintenance service only 187 188 Development tool configuration In-circuit emulator Centronics interface RS-232-C IE-75000-R-EM IE control program Host machine PC-9800 series IBM PC series (Symbolic debugging is possible.) IE-75000-R IE-75001-R Note 1 Emulation probe EP-75238GJ-R Note 2 User sysytem PG-1500 controller Built-in PROM PROM programmer PD75P238GJ/KF PG-1500 Relocatable assembler + Programmer adapter Notes 1. The IE-75001-R does not contain the IE-75000-R-EM (to be ordered). 2. EV-9200G-94 PA-75P238GJ PD75238 PD75238 [MEMO] 189 PD75238 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 FIP(R) is a registered trademark of NEC Corporation. MS-DOSTM is a trademark of Microsoft Corporation. PC DOSTM is a trademark of IBM Corporation. |
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