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ICD2061A
Dual Programmable Graphics Clock Generator
Features
* Second generation dual oscillator graphics clock generator * 2 independent clock outputs from 390 KHz to 100 MHz * Individually programmable oscillators using a highly reliable, Manchester-encoded, 21-bit serial data word * 2-pin serial programming interface allows direct connection to most graphics chip sets with no external hardware required * 2 advanced power-down capabilities * Three-state oscillator control disables outputs for test purposes * Phase-locked loop oscillator input derived from single 14.318 MHz crystal * Sophisticated internal loop-filter requires no external components or manufacturing "tweaks" as commonly required with external filters * 5V operation * Low-power, high-speed CMOS technology * Available in 16-pin SOIC package configuration clock chips, while also offering the versatility of serially programmable frequency synthesizers. It features advanced power-down capabilities, making it ideally suited for the portable computer market. The ICD2061A has extended frequency range and improved voltage/temperature stability when compared to first-generation frequency synthesizers. The ICD2061A Dual Programmable Graphics Clock Generator offers two fully user-programmable phase-locked loops in a single package. The outputs may be changed "on the fly" to any desired frequency value between 390 KHz and 100 MHz. The ICD2061A is ideally suited for any design where multiple or varying frequencies are required, replacing more expensive metal can oscillators. Being able to change the output frequency dynamically adds a whole new degree of freedom for the electrical engineer which was previously unavailable with existing crystal oscillator devices. Some examples of the uses for this device include: laptop computers, in which slowing the speed of operation can mean less power consumption or speeding it up can mean faster operation; graphics board dot clocks to allow dynamic synchronization with different brands of monitors or display formats; and on-board test strategies where the ability to skew a system's desired frequency (for example: 10%) allows worst case evaluations. While primarily designed for the graphics subsystem market, the programming versatility of the ICD2061A makes it ideal wherever two variable, yet highly accurate clock sources are required.
Functional Description
The ICD2061A Dual Programmable Graphics Clock Generator features a fully programmable set of clock oscillators which can handle all frequency requirements of most graphics systems. The ICD2061A offers the selection ease of ROM-based
Pin Configuration
S0/CLK S1/DATA AVDD OE GND XTALIN XTALOUT MCLKOUT 1 2 3 4 5 6 7 8
SOIC Top View
16 15 14 13 12 11 10 9 PWRDWN INTCLK INIT1 VDD INIT0 FEATCLK ERROUT VCLKOUT ICD2061A-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 June 1994 - Revised July 16, 1997
ICD2061A
Logic Block Diagram
Powerdown Divisor
MCLKOUT f(REF) XTALIN XTALOUT Reference Frequency VCLK PLL VCLKOUT 2:1 Mux MCLK PLL 2:1 Mux
(Typically 14.31818 MHz Xtal) FEATCLK
PWRDWN INTCLK S0/CLK S1/DATA Decode Logic 6 5 Serial Program 4 3 2 1 0 Register Selects Addr 23 24 INIT1 INIT0 Initialization ROM GND VDD AVDD 2 Register File CNTL Reg 8 0
(Reserved) PWRDWN 20 20 20 20 MREG REG2 REG1 REG0 4 30 21 0 0 0 0 21 21 21 OE 4-21 Serial Reg 0 ERROUT 3:1 Mux 21
Power-On Reset
Power-On Reset State Machine
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ICD2061A
Pin Summary
Name S0/CLK S1/DATA AVDD OE GND XTALIN
[1]
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Description Bit 0 (LSB) of frequency select logic, used to select oscillator frequencies. Clock Input in serial programming mode. (Internal pull-down allows no-connect.) Bit 1 (MSB) of frequency select logic, used to select oscillator frequencies. Data Input in serial programming mode. (Internal pull-down allows no-connect.) +5V to Analog Core Output Enable. Three-states output when pulled LOW. (Internal pull-up allows no connect.) Ground Reference Oscillator input for all phase-locked loops (nominally from a parallel-resonant 14.31818 MHz crystal). Optionally PC System Bus Clock. Oscillator Output to a reference crystal. (Pin is no-connect if external reference oscillator or PC System Bus clock signal is used.) Memory Clock output Video Clock output Error Output: a LOW signals an error during serial programming. External clock input (Feature Clock) (Internal pull-up allows no-connect.) Select power-up initial conditions (LSB) (Internal pull-down allows no-connect.) +5V to I/O Ring Select power-up initial conditions (MSB) (Internal pull-down allows no-connect.) Selects the Feature Clock external clock input as VCLKOUT output (Internal pull-up allows no-connect.) Power-down pin (active LOW) (Internal pull-up allows no-connect if power-down operation not required. See Power Management Issues for specific details concerning the use of this pin.)
XTALOUT[1] MCLKOUT VCLKOUT ERROUT FEATCLK INIT0 VDD INIT1 INTCLK PWRDWN
Note: 1. For best accuracy, use a parallel-resonant crystal, assume CLOAD=17 pF.
Register Definitions
The Register File consists of the following registers and their selection addresses: Register File Table 1. Register Addressing[2] Address 000 001 010 011 100 101 110 Register REG0 REG1 REG2 MREG PWRDWN (Reserved) CNTL Reg Control Register Usage Video Clock Register 1 Video Clock Register 2 Video Clock Register 3 Memory or I/O Timing Clock Divisor for Power-Down mode
On power-on, when the supply voltage rises above a certain threshold voltage (typically 3V, may vary with temperature), the part recognizes the first 16 rising edges of the reference clock, using them as a clocking signal for internal state machines for initialization. Hence for proper initialization and programmability, the power-on reference clock pulses seen by the ICD2061A, should have as good signal integrity and rail-to-rail characteristics as the clock pulses seen under stable working conditions. This is not an issue when using a crystal as reference. The Power-On Reset function operates transparently to the video subsystem. It performs its initialization function and is cleared before the system Power-On Reset permits the system to begin its boot process. The INIT pins must ramp up with VDD if a 1 on either of these pins is desired. They are internally pulled down, and so will default to 0 if left unconnected. The various registers are initialized as follows in Table 2 (all frequencies in MHz). Table 2. Register Initialization--ROM Option 1 INIT1 INIT0 0 1 0 1 MREG 32.500 40.000 50.350 56.644 REG0 25.175 25.175 40.000 40.000 REG1 28.322 28.322 28.322 50.350 REG2 28.322 28.322 28.322 50.350 0 0 1 1
Note: 2. All register values are preserved in power-down mode.
Power-On Reset and Register Initialization The ICD2061A Clock Synthesizer has all of its registers in a known state upon power-up. This is implemented by the Power-On initialization circuitry. Three VGA registers and the Memory Clock register are initialized based on the state of the INIT1 and INIT0 pins at power-up.
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ICD2061A
C5 0 Power-Down Mode 0: Power-Down Mode1 Default (MCLKOUT= PWRDWNDivisor) 1: Power-Down Mode 2 (Xtal Osc shutdown) MUXREF 0: Multiplex f(REF) to VCLKOUT Default 1: Multiplex MCLKOUTto VCLKOUT Timeout Interval 0: Normal Timeout IntervalDefault 1: Twice Normal Timeout Interval Reserved (Must be set to 0) Duty CycleAdjust 0: 1 ns high-time decrease 1: No adjustDefault Reserved (Must be set to 0)
C4 0
C3 0
C2 0
C1 1
C0 0
PS2 PS1 PS0 0 0 0 P Counter Prescale (Reg0) 0: Prescale=2 Default 1: Prescale=4 P Counter Prescale (Reg1) 0: Prescale=2 Default 1: Prescale=4 P Counter Prescale (Reg2) 0: Prescale=2 Default 1: Prescale=4
Figure 1. Control Register Definition Register Selection The Video Clock output is controlled not only by the S0 and S1 bits, but also by the PWRDWN and OE signals. Additionally, the clock synthesizer is multiplexed with an external frequency input (FEATCLK) which corresponds to the IBM VGA Feature Clock standard. Table 3 shows the VCLKOUT selection criteria. Table 3. VCLKOUT Selection OE 0 1 1 1 1 1 1 PWRDWN X 0 1 1 1 1 1 INTCLK X X X X 0 1 X S1 X X 0 0 1 1 1 S0 X X 0 1 0 X 1 VCLKOUT High-Z Forced High REG0 REG1 FEATCLK REG2 REG2 Control Register Definition The Control Register (CNTL Reg) allows the user to adjust various internal options. Most of these options are for special cases, and should have no applicability to standard graphics usage. The register word is defined in Figure 1. Duty Cycle Adjust--This control bit causes a 1 ns decrease in the output waveform high time. The default is no adjustment. In situations in which the capacitive load is beyond device specifications, or where the threshold voltage VTH is to be changed from CMOS to TTL levels, this adjustment can sometimes bring the output closer to 50% duty cycle. The Clock Select pins S0 and S1 have a dual purpose. When these pins are performing serial download, the VCLKOUT signal remains unchanged (unless the currently selected register is the one being programmed). When the pins S0 and S1 are functioning as register selects, a time-out interval is required to determine whether the user desires register select or serial programming. At the end of the timeout interval, new register selection occurs. At this point, the VCLKOUT signal will be multiplexed to the reference signal f(REF) for an additional timeout interval to give the VCO time to settle to its new value. [The timeout interval in both cases is approximately 5 msec--see the timeout interval spec in Switching Characteristics.] When a new frequency is being set for MCLK, or if the active VCLK register is programmed, a glitch-free multiplexing to the Reference Frequency is performed. Once the STOP bit is sent after the MCLK or active VCLK Programming Word, the appropriate output signal will be multiplexed to the reference signal f(REF) for an extra timeout interval (See Switching Characteristics for further details).
The Memory Clock output is controlled by the PWRDWN and OE signals as indicated in Table 4. Table 4. MCLKOUT Selection OE 0 1 1 PWRDWN X 1 0 MCLKOUT High-Z MREG PWRDWN[3]
Notes: 3. Power-Down Mode (1 or 2) is determined by the setting of bit C5 in the CNTL Reg. See Figure 1 Control Register Definition.
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ICD2061A
ERROUT Decode Logic Serial Unlock Decoder Load/Arm Man. Dcdr. Serial Data Register (Address + Data) DEMUX Select 1 of 6 Load Request Reference Frequency f(REF)
To Register File
Watchdog Timer
Figure 2. Serial Programming Block DiagramDetail Timeout Interval--The timeout interval is normally defined as in the Switching Characteristics. It is derived from the MCLK VCO, and if this VCO is programmed to certain extremes, then the timeout may be too short. If this control bit is set, then the timeout interval is doubled. MUXREF--This control bit determines which clock is multiplexed to the VCLKOUT output during frequency changes. While the VCLK VCO changes to a different frequency, a known clock is multiplexed to the output. The default is to multiplex the f(REF) reference frequency, but some graphic controllers cannot run as slow as f(REF). This bit, when set, allows the MCLK to be used as an alternative frequency. Power-Down Mode--This control bit determines which Power-Down Mode the PWRDWN pin will implement. The default (Power-Down Mode 1) forces the MCLKOUT signal to be a function of the PWRDWN register. Power-Down Mode 2 turns off the crystal oscillator and disables all outputs. There is a more detailed description in the section entitled Power Management Issues. P Counter Prescale (REG0, REG1, REG2)--These control bits determine whether or not to prescale the P Counter value, which allows fine tuning the output frequency of the respective register. Prescaling is explained in more detail in various sections of this datasheet. mechanism and Manchester decoder), a watchdog timer, the Serial Data register (Serial Reg) and a Demultiplexer to the Register File (see Figure 2). Unlocking Mechanism The Unlocking Mechanism watches for an initial break sequence, detailed in Figure 3. The initial unlock sequence consists of at least five LOW-to-HIGH transitions of CLK with DATA HIGH, followed immediately by a single LOW-to-HIGH transition of CLK with DATA LOW. Following this unlock sequence, the encoded serial data is clocked into the Serial Data register (Serial Reg). Note that the ICD2061A may not be serially programmed when in Power-Down Mode. Watchdog Timer Following any transition of CLK or DATA, the watchdog timer is reset and begins counting. Throughout the entire programming process, the watchdog timer ensures that successive edges of CLK or DATA do not violate the timeout specification (of 2 msec--see Switching Characteristics.) If a timeout does occur, the lock mechanism is rearmed and the current data in the Serial Data register (Serial Reg) is ignored. Since the VCLK registers are selected by the S0 or S1 bits, and since any change in their state may affect the resultant output frequency, new data input on the Selection Bits is only permitted to pass through to the Decode Logic after the Watchdog Timer has timed out. This delay of S0 or S1 data permits a serial program cycle to take place without affecting the current register selection. The process of serial programming has no effect on the performance of the graphics subsystem. Note that there is a latency amounting to the duration of the Watchdog Timer before any new VCLK register selections take effect.
Serial Programming Architecture
The ICD2061A programming scheme is simple, yet impenetrable to accidental access. Because the only common denominator between most VGA and 8514 controllers is a few clock select pins, these have to perform the dual functions of clock selection and serial programming. The Serial Program Block (See ICD2061A Logic Block Diagram) contains several components: a Serial Unlock Decoder (containing the unlocking
SEL1/DATA
SEL0/CLOCK
1
2
3
4
5
Figure 3. Unlock Sequence
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ICD2061A
Data Bits Start LSB
Address Bits MSB LSB MSB Stop
Bit #
1
2
3
4
5
6
7
8
9
10
11 12 13
14
15
16
17
18 19 I1
20 21 I2 I3
22
23 24 Bit # 0 1 1 VCO Prog. CNTL Reg PWRDWN Reg
VCO Prog. Q'0 Q'1 Q'2 Q'3 Q'4 Q'5 Q'6 M0 M1 M2 P'0 P'1 P'2 P'3 P'4 P'5 P'6 I0 Word CNTL Reg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A0 A1 0 0 1 0
0 PS0 PS1 PS2 C0 C1 C2 C3 C4 C5 0 0 0 0 0 0 P0 P1 P2 P3
PWRDWN 0 Reg
ICD2061A-2
Figure 4. Serial Data Timing Serial Data Register The serial data is clocked into the Serial Data register (Serial Reg) in the following order shown in Figure 4. The serial data is sent using a modified Manchester-encoded data format. This is defined as: 1. An individual data bit is sampled on the rising edge of CLK. 2. The complement of the data bit must be sampled on the previous falling edge of CLK. 3. The Set-Up and Hold Time requirements must be met on both CLK edges. 4. The unlock sequence, start, and stop bits are not Manchester-encoded. For specifics on timing, see the "Serial Programming Timing" section in the switching waveforms. The bits are shifted in this order: a start bit, 21 data bits, 3 address bits (which designate the desired register), and a stop bit (which also functions as a load strobe to transfer the data from the Serial Reg into the desired register). For the VCO registers (REG0, REG1, REG2, MREG), the data is made up of 4 fields: D[20:17] = Index; D[16:10]=P'; D[9:7]=Mux; D[6:0]=Q'. (See the Programming the ICD2061A section for more details on the VCO data word.) For the other registers with fewer than 21 bits (PWRDWN, CNTL Reg), the upper bits are used (starting with the MSB). A total of 24 bits must always be loaded into the Serial Data Register (or an error is issued). Undefined bits should always be set to zero to maintain software compatibility with future enhancements. Following the entry of the last data bit, a stop bit or Load command is issued by bringing data HIGH and toggling CLK HIGH-to-LOW and LOW-to-HIGH. The unlocking mechanism then automatically rearms itself following the load. Only when the watchdog timer has timed out are the S0 and S1 selection pins permitted to return to their normal register select function. Note that the Serial Data register (Serial Reg) that receives the address and data bits is exactly the correct length to accept the data being sent. The stop bit is used as a load command that passes the Serial Reg contents on to the register file location indicated by the address bits. If a stop bit is not received
CLK
after the Serial Data register has been filled, but rather more valid encoded data is received, then all of the received serial data is ignored, the unlocking mechanism rearmed, and an error is issued. The device counts the serial data clock edges to know exactly when the serial buffer is full, and thus to know which bit is the stop bit. Following the stop bit, the unlocking mechanism rearms itself. If corrupt data is detected (i.e., incorrectly Manchester-encoded data), then the unlocking mechanism is rearmed, the serial counter reset, all received data ignored, and ERROUT is asserted. ERROUT Operation The ERROUT signal is used to report when a program error has been detected internally by the ICD2061A. The signal stays active until the next unlock sequence.
Figure 5 shows the basic mechanism used to detect valid and erroneous serial data. Note that the circuit must have different values on the rising and falling edge when sampling the falling edge first. Valid data is read on the rising edge of CLK.
The ERROUT signal is invoked for any of the following error conditions: incorrect Manchester encoding; incorrect length of data word; incorrect stop bit; timeout. Note that if there is no input pin available on the target VGA controller chip to monitor ERROUT, a software routine which counts VSYNC pulses in order to measure output frequency may be used as a determination of programming accuracy.
DATA
D DFF1 Q D D DFF2 valid data Q DFF3 ERROUT Q
Figure 5. Serial Data Timing
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ICD2061A
Programming the ICD2061A
The desired output frequency is defined via a serial interface, with a 24-bit number shifted in. The ICD2061A has two programmable oscillators, requiring a 24-bit programming word (W) to be loaded into each channel's respective registers independently. This word contains 4 fields: Table 5. Programming Word Bit Fields Field Address (A) Index (I) P Counter value (P) Div (D) Q Counter Value (Q)
Notes: 4. MSB (Most Significant Bits) 5. LSB (Least Significant Bits)
VCLK VCO and multiplexing the MCLK VCO over to VCLKOUT, dividing down to the desired frequency. This will significantly reduce heterodyne jitter. Table 7. Index Field (I) I 0000 0001 VCLK fVCO (MHz) 50.0 - 51.0 51.0 - 53.2 53.2 - 58.5 58.5 - 60.7 60.7 - 64.4 64.4 - 66.8 66.8 - 73.5 73.5 - 75.6 75.6 - 80.9 80.9 - 83.2 83.2 - 91.5 91.5 - 100.0 100.0 - 120.0 100.0 - 120.0 Turn off VCLK Mux MCLK to VCLK MCLK fVCO (MHz) 50.0 - 51.0 51.0 - 53.2 53.2 - 58.5 58.5 - 60.7 60.7 - 64.4 64.4 - 66.8 66.8 - 73.5 73.5 - 75.6 75.6 - 80.9 80.9 - 83.2 83.2 - 91.5 91.5 - 100.0 100.0 - 120.0 100.0 - 120./0 100.0 - 120.0 100.0 - 120.0
# of Bits 3 4[4] 7 3 7[5]
0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
The frequency of the Programmable Oscillator f(VCO) is determined by these fields as follows: P'=P-3 Q'=Q-2 f(VCO)=(2 x f(REF) x P/Q) where f(REF)=Reference frequency (between 1 MHz-25 MHz; typically 14.31818 MHz) Note that if a reference frequency other than 14.31818 MHz is used, then the initially loaded ROM frequencies will not be correct. The value of f(VCO) must remain between 50 MHz and 120 MHz inclusive. Therefore, for output frequencies below 50 MHz f(VCO) must be brought into range. To accomplish this, a post-VCO divisor is selected by setting the values of the div field (D). See Table 6. Table 6. Post-VCO Divisor D 000 001 010 011 100 101 110 111 Divisor 1 2 4 8 16 32 64 128
If the desired VCO frequency lies on a boundary in the table--in other words, if it is exactly the upper limit of one entry and the lower limit of the next--then either index value may be used (since both limits are tested). To assist with these calculations, Cypress/IC Designs provides BitCalc (Part #ICD/BCALC), a WindowsTM program that automatically generates the appropriate programming words from the user's reference input and desired output frequencies, as well as assembling the program words for such things as control and power-down registers. Programming Constraints There are five primary programming constraints of which the user must be aware: Table 8. Programming Constraints Parameter f(REF) f(REF)/Q f(VCO) Q P Minimum 1 MHz 200 kHz VCLK: 65 MHz MCLK: 52 MHz 3 4 Maximum 25 MHz 1 MHz VCLK: 165 MHz MCLK: 120 MHz 129 130
The Index Field (I) is used to preset the VCO to an appropriate range. The value for this field should be chosen from the following table. (This table is referenced to the VCO frequency, f(VCO), rather than to the desired output frequency.) Note that VCLK may be shut off, but that MCLK must be left running. When the Index Field is set to 1111, VCLK is turned off and both channels run from the same MCLK VCO. To reduce jitter, one doesn't want the two VCOs to run at integral multiples of each other; therefore, if one does want the clocks to run at 2n (n=0, 1, 2 .. 7) multiples of each other, this is done by turning off the
The constraints have to do with trade-offs between optimum speed with lowest noise, VCO stability, and factors affecting the loop equation. The factors are listed here for completeness' sake; however, by using the BitCalc program, these constraints become transparent.
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ICD2061A
Programming Example--Prescaling=2 (default) The following is an example of the calculations BitCalc performs: Derive the proper programming word for a 39.5 MHz output frequency, using 14.31818 MHz as the reference frequency: Since 39.5 MHz<50 MHz, double it to 79.0 MHz. Set D to 001. Set I to 1000. The result:
(VCO)=79.0=(2 x 14.31818 x P/Q) P/Q = 2.7587
But this precision has its price, namely that the user now has to set and reset the Prescale Bits PS0-2 (corresponding to REG0-2), which involves loading a Control Word (taking care to preserve the current values of the other Control Bits), before the VCO Program Word can be loaded. Once the appropriate Prescale Bits are set, then frequency programming can proceed as before, unless and until it is desired to program a new frequency without prescaling, at which point a new Control Word must first be loaded with the proper bits set, and observing the precautions noted above. To summarize, the sequence is: 1. Set the Prescale bits (load a Control Word)
Table 9. P&Q Value Pairs P 69 80 91 Q 25 29 33 f(VCO) (MHz) 79.0363 78.9969 78.9669 Error (PPM) 460 40 419
2. Program the VCO (load a Program Word) Note that care must be taken not to change the Prescale Bit of the currently active register: the results will be unpredictable at best, and it could cause the VCO to go out of lock.
Choose (P, Q)=(80,29) for best accuracy (40 PPM). Therefore: P'=P-3=80-3=77=1001101 (4dH) Q'=Q-2=29-2=27=0011011 (1bH) and the full programming word, W is: W=I, P', M, Q'=1000, 1001101, 001, 0011011 =100010011010010011011 (11349bH) The programming word W is then sent as a serial bit stream, LSB first. Appropriate start and stop bits must also be included as defined in the Serial Programming Scheme section. Programming Example--Prescaling=4 Assume the desired VCLKOUT frequency is 100 MHz. Table 10 compares the results of using the default prescaling value of 2 and the optional prescaling value of 4. Table 10. Prescale Values Prescale 2 4 Actual Frequency (MHz) 99.84028 99.99998 P 129 110 Q 37 63 Error (PPM) 1600 0
Power Management Issues
Power-Down Mode 1 The ICD2061A contains a mechanism to reduce the quiescent power when stand-by operation is desired. In Power-Down Mode 1 (invoked by pulling, the PWRDWN signal low and having the proper CNTL Reg bit set to zero), both VCOs are shut down, the VCLKOUT output is forced high, and the MCLKOUT output is set to a user-defined low-frequency value to refresh dynamic RAM. The power-down MCLKOUT value is determined by the following equation: MCLKOUTPower-Down=f(REF)/(PWRDWN Reg Divisor Value) The Power-Down register divisor is determined according to the following 4-bit word programmed into the PWRDWN register. (See Table 11.)
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ICD2061A
Table 11. PWRDWN Register Programming PWRDWN bits P3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 P1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 PWRDWN Register Value 0 1 2 3 4 5 6 7 8 9 A B C D E F Power-Down Divisor N/A 32 30 28 26 24 22 20 18 (default) 16 14 12 10 8 6 4 MCLKOUT Power-Down (f(REF)=14.31818 MHz) N/A 447.4 KHz 477.3 KHz 511.4 KHz 550.7 KHz 596.6 KHz 650.8 KHz 715.9 KHz 795.5 KHz 894.9 KHz 1.023 MHz 1.193 MHz 1.432 MHz 1.790 MHz 2.386 MHz 3.580 MHz To calculate total operating current, sum the following terms: VCLKOUT -->C x V x f(VCLK) MCLKOUT--> C x V x f(MCLK) Internal -->12 mA This gives an approximation of the actual operating current. For unconnected output pins, one can assume 5 to 10 pF loading, depending on package type. Table 12. Typical Values Frequency LOW HIGH HIGH Capacitive Load LOW LOW HIGH Current (mA) 15 40 65
On power-up, the value of the PWRDWN Register is loaded with a default value of 8 (1000 binary), which yields an MCLKOUT frequency of 795 KHz (14.31818/18). The default mode is Power-Down Mode 1. Note that the ICD2061A may not be serially programmed when in Power-Down Mode. Power-Down Mode 2 If there is no need for any output during power-down operation, then an alternate Power-Down Mode is available, which will completely shut down all outputs and the reference oscillator, yet still preserve all register contents. This results in the absolute least power consumption. Power-Down Mode 2 is invoked by first programming the power-down bit in the CNTL Reg, and then pulling the PWRDWN pin LOW. The PWRDWN Pin This pin has a standard internal pull-up during normal operation. When the user pulls it down to invoke Power-Down Mode 1 or 2, the normal pull-up resistor is dynamically switched to a weak pull-up, which significantly reduces power consumption. If, after pulling this pin LOW, the pin is allowed to float, the weak pull-up will gradually cause the signal to rise, enabling the normal pull-up, and will eventually turn the device back on. Estimating Total Current Drain Actual current drain is a function of frequency and of circuit loading. The operating current of a given output is given by the equation: I=C x V x f, where: I=current (in mA) C=Load capacitance (max., 25pF) V=output voltage (usually 5V) f=output frequency (in MHz)
When in Power-Down Mode 1, and using a 14.31818 MHz reference crystal, the power consumption should not exceed 7.5 mA. In Power-Down Mode 2, the power consumption should not exceed 50 A.
Output Enable Pin
When the OE pin is asserted (active LOW), all the output pins except XTALOUT and ERROUT enter a high-impedance mode, to support automated board testing.
External Clock Input (Feature Connector Compatibility)
To maintain backward compatibility to the VGA feature connector standard, the video clock output VCLKOUT can multiplex between the clock synthesizer output and the external clock input FEATCLK. This multiplexing is controlled by the INTCLK input signal and appropriate decode of selection signals (SEL0, SEL1). See the section on Register Definitions for more information.
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ICD2061A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage to Ground Potential .................-0.5V to +7.0V DC Input Voltage ......................................... -0.5V to VDD +0.5V Storage Temperature ...................................... -65C to +150C Max soldering temperature (10 sec) ............................ 260C Junction temperature....................................................125C
Operating Range
Ambient Temperature 0C TAMBIENT 70C VDD & AVDD 5V 5%
Electrical Characteristics Over the Operating Range[6]
Parameter VOH VOL VIH VIL IIH IIL IOZ IDD IADD IPD1 IPD2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output Leakage Current Supply Current Analog Power Supply Current Power-Down Current (Mode 1) Power-Down Current (Mode 2) Test Conditions IOH = -4.0mA IOL = 4.0 mA Except on Crystal Pins Except on Crystal Pins VIH = VDD - 0.5 VIL = +0.5V (Three-state) Inputs @ VDD and GND 15 2.0 0.8 105.0 -250.0 10 85.0 10 7.5 50 Min. 2.4 0.4 Max. Unit V V V V A A A mA mA mA A
Note: 6. Input capacitance is typically 10pF, except for the crystal pins.
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ICD2061A
Switching Characteristics Over the Operating Range
Parameter f(REF) t(REF) t1 t2 t3 t4 t5 tfreq1 tfreq2 tA ttimeout tB t6 t7 t8 t9 t10 t11 tserclk tHI tLO tSU tHD tldcmd Name Reference Frequency Reference Clock Period Input Duty Cycle Output Clock Periods Output Duty Cycle Rise Times Fall Times freq1 Output freq2 Output f(REF) Mux Time Timeout Interval tfreq2 Mux Time Three-state CLK Valid Power-Down Power-Up MCLKOUT HIGH MCLKOUT delay t(REF) = 1/f(REF) Duty cycle for the inputs defined as t1A / t1B Output values Duty cycle for the outputs defined as t2A / t2[7] Rise time for the outputs into a 25-pF load Fall time for the outputs into a 25-pF load Old frequency output New frequency output Time clock output remains HIGH while output muxes to reference frequency Internal interval for serial programming and for VCO changes to settle[8] Time clock output remains HIGH while output muxes to new frequency value Time for the outputs to go into three-state mode after OE signal assertion Time for the outputs to recover from three-state mode after OE signal goes HIGH Time for Power-Down Mode of operation to take effect Time for recovery from Power-Down Mode of operation Time for MCLKOUT to go HIGH after PWRDWN is asserted HIGH Delay of MCLKOUT prior to f MCLK signal at output Clock period of serial clock Minimum HIGH time Minimum LOW time Set-Up time Hold time Load command 0 tMCLK/2 2 x t(REF) t(REF) t(REF) 20 10 0 t(REF)+30 t(REF)/2 2 tfreq2/2 0 0 3(t(REF)/2) 10 3/(tfreq2/2) 12 12 12 12 tPWR-DWN 3/(tMCLK/2) 2 ns msec ns ns ns ns ns ns ns msec ns ns ns ns ns Description Reference Oscillator nominal value Min. 1 40 25% 10 40 Max. 25 1000 75% 2564 60 4 4 ns % ns ns Unit MHz ns
Notes: 7. Duty cycle is measured at CMOS threshold levels. At 5V, VTH=2.5V. 8. If the interval is too short, see the Timeout Interval paragraph.
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ICD2061A
Switching Waveforms
Duty Cycle Timing
t1B t1A
ICD2061A-3
Rise and Fall Times
t(REF) t1 XTALIN f(REF)
90% 90%
t2 t4 VCLKOUT MCLKOUT
10% 90% 90% 10%
t5
t2A
ICD2061A-4
State Timing
OE
t6 VCLKOUT MCLKOUT
t7 THREE-STATE OUTPUT
ICD2061A-5
Selection Timing
Selection Recognition Time SEL0 SEL1 ttimeout (Internal Timeout) ttimeout VCO Settle Time New Frequency
VCLKOUT tfreq1 tA t(REF) tB tfreq2
ICD2061A-6
12
ICD2061A
Switching Waveforms (continued)
MCLK and ActiveVCLK Register Programming Timing
Stop Bit VCO Settle Time New Frequency
ttimeout (Internal Timeout)
VCLKOUT MCLKOUT tfreq 1 tA t(REF) tB tfreq 2
ICD2061A-7
Soft Power-Down Timing(Mode 2)
PWRDWN t8 t9 This is when VCLKOUT directly muxes to VCLKPLL (may glitch)
VCLKOUT fVCLK
(forced HIGH) fVCLK [9] t10 t11
MCLKOUT fMCLK fPWRDWN (value from PWRDWN Register) fMCLK [9]
ICD2061A-8
Serial ProgrammingTiming
Unlock Sequence tHI CLK tLO DATA Valid Data Sequence (24 bits) CLK tSU DATA 0 0 1 1 0 tldcmd
ICD2061A-9
tserclk 1 2 tSU 3 4 5 tSU
Nw 5
Start Bit
Stop Bit
t tHD SU
tHD
Note: 9. It takes 2 to 10 msec after Soft Power-Down to guarantee lock of VCLKOUT and MCLKOUT PLLs.
13
ICD2061A
Test Circuit
VDD
DEVICE UNDER TEST
+
CLK out CLOAD
22 AVDD 2.2 F
+
GND
Ordering Information[10]
Ordering Code ICD2061A Package Name S1 Package Type 16-Pin SOIC Operating Range Commercial[11]
Notes: 10. Please call your local Cypress representative. 11. 0C to +70C
Example: order ICD2061ASC-1 for the ICD2061A, 16-pin plastic SOIC, commercial temperature range device with the initial frequencies shown in Table 2.
Document #: 38-00403-A
14
ICD2061A
Package Diagrams
16-Lead Molded SOIC S1
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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