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19-3143; Rev 1; 3/04
KIT ATION EVALU BLE AVAILA
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
General Description Features
Four ADC Channels with Serial LVDS/SLVS Outputs Excellent Dynamic Performance 69.9dB SNR at fIN = 5.3MHz 93.7dBc SFDR at fIN = 5.3MHz -90dB Channel Isolation Ultra-Low Power 135mW per Channel (Normal Operation) 1.5mW Total (Shutdown Mode) Accepts 20% to 80% Clock Duty Cycle Self-Aligning Data-Clock to Data-Output Interface Fully Differential Analog Inputs Wide 1.4VP-P Differential Input Voltage Range Internal/External Reference Option Test Mode for Digital Signal Integrity LVDS Outputs Support Up to 30in FR-4 Backplane Connections Small, 68-Pin QFN with Exposed Paddle Evaluation Kit Available (MAX1127EVKIT)
MAX1126
The MAX1126 quad, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction. This ADC is optimized for low-power, high-dynamic performance for medical imaging, communications, and instrumentation applications. The MAX1126 operates from a 1.7V to 1.9V single supply and consumes only 563mW while delivering a 69.9dB signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1126 features an 813A power-down mode for idle periods. An internal 1.24V precision bandgap reference sets the ADC's full-scale range. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. A single-ended clock controls the conversion process. An internal duty-cycle equalizer allows for wide variations in input-clock duty cycle. An on-chip phaselocked loop (PLL) generates the high-speed serial low-voltage differential signaling (LVDS) clock. The MAX1126 provides serial LVDS outputs for data, clock, and frame alignment signals. The output data is presented in two's complement or binary format. Refer to the MAX1127 data sheet for a pin-compatible 65Msps version of the MAX1126. The MAX1126 is available in a small, 10mm x 10mm x 0.9mm, 68-pin QFN package with exposed paddle and is specified for the extended industrial (-40C to +85C) temperature range.
Ordering Information
PART MAX1126EGK TEMP RANGE -40C to +85C PIN-PACKAGE 68 QFN 10mm x x 10mm x 0.9mm
Pin Configuration
LVDSTEST INTREF PDALL REFIO OVDD 52 51 OUT0P 50 OUT0N 49 OVDD 48 OUT1P 47 OUT1N 46 OVDD 45 CLKOUTP 44 CLKOUTN 43 OVDD 42 FRAMEP 41 FRAMEN 40 OVDD 39 OUT2P 38 OUT2N 37 OVDD 36 OUT3P 35 OUT3N 18 AVDD 19 I.C. 20 AVDD 21 CVDD 22 GND 23 CLK 24 GND 25 AVDD 26 AVDD 27 AVDD 28 DT 29 SLVS/LVDS 30 PLL0 31 PLL1 32 PLL2 33 PLL3 34 OVDD AVDD AVDD AVDD AVDD AVDD GND GND PD3 PD2 PD1 54 PD0 53 T/B 63
68
67
66 EP
65
64
62
61
60
59
58
57
56
55
Applications
Ultrasound and Medical Imaging Positron Emission Tomography (PET) Imaging Multichannel Communication Systems Instrumentation
GND IN0P IN0N GND IN1P IN1N GND AVDD AVDD
1 2 3 4 5 6 7 8 9
MAX1126
AVDD 10 GND 11 IN2P 12 IN2N 13 GND 14 IN3P 15 IN3N 16 GND 17
QFN 10mm x 10mm x 0.9mm
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
ABSOLUTE MAXIMUM RATINGS
AVDD to GND.........................................................-0.3V to +2.0V CVDD to GND ........................................................-0.3V to +3.6V OVDD to GND ........................................................-0.3V to +2.0V IN_P, IN_N to GND...................................-0.3V to (AVDD + 0.3V) CLK to GND .............................................-0.3V to (CVDD + 0.3V) OUT_P, OUT_N, FRAME_, CLKOUT_ to GND................................-0.3V to (OVDD + 0.3V) DT, SLVS/LVDS to GND ...........................-0.3V to (AVDD + 0.3V) PLL0, PLL1, PLL2, PLL3 to GND .............-0.3V to (AVDD + 0.3V) PD0, PD1, PD2, PD3, PDALL to GND......-0.3V to (AVDD + 0.3V) T/B, LVDSTEST to GND ...........................-0.3V to (AVDD + 0.3V) REFIO, INTREF to GND............................-0.3V to (AVDD + 0.3V) I.C. to GND...............................................-0.3V to (AVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 68-Pin QFN 10mm x 10mm x 0.9mm (derated 41.7mW/C above +70C)........................3333.3mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature Range (soldering, 10s)......................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1F, fCLK = 40MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUTS (IN_P, IN_N) Input Differential Range Common-Mode Voltage Range Differential Input Impedance Differential Input Capacitance CONVERSION RATE Maximum Conversion Rate Minimum Conversion Rate Data Latency DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) Signal-to-Noise Ratio (Note 2) Signal-to-Noise and Distortion (First Four Harmonics) (Note 2) Effective Number of Bits (Note 2) SNR SINAD ENOB fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS, TA +25C fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS, TA +25C fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS 66.7 66.7 69.9 69.2 69.8 69.1 11.4 11.3 dB dB Bits fSMAX fSMIN 40 16 6.5 MHz MHz Cycles VID VCMO RIN CIN Differential input (Note 3) Switched capacitor load 1.4 0.75 2 12.5 VP-P V k pF N INL DNL (Note 2) (Note 2) Fixed external reference (Note 2) Fixed external reference (Note 2) -1.5 +0.9 12 0.4 0.25 1 +2.5 Bits LSB LSB % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1F, fCLK = 40MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Spurious-Free Dynamic Range (Note 2) Total Harmonic Distortion (Note 2) Intermodulation Distortion Third-Order Intermodulation Aperture Jitter Aperture Delay Small-Signal Bandwidth Full-Power Bandwidth Output Noise Overdrive Recovery Time tOR SYMBOL SFDR THD IMD IM3 tAJ tAD SSBW LSBW CONDITIONS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS, TA +25C fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS, TA +25C f1 = 12.40125MHz at -6.5dBFS, f2 = 13.60125MHz at -6.5dBFS (Note 2) f1 = 12.40125MHz at -6.5dBFS, f2 = 13.60125MHz at -6.5dBFS (Note 2) (Note 2) (Note 2) Input at -20dBFS (Notes 2 and 4) Input at -0.5dBFS (Notes 2 and 4) IN_P = IN_N RS = 25, CS = 50pF 77.3 MIN TYP 93.7 89 -91.5 -88.7 87.0 89.3 <0.4 1 100 100 0.35 1 -76.3 MAX UNITS dBc dBc dBc dBc psRMS ns MHz MHz LSBRMS Clock cycles
MAX1126
INTERNAL REFERENCE (INTREF = GND, bypass REFIO to GND with 0.1F) INTREF Internal Reference Mode Enable Voltage INTREF Low-Leakage Current REFIO Output Voltage Reference Temperature Coefficient INTREF External Reference Mode Enable Voltage INTREF High-Leakage Current REFIO Input Voltage Range REFIO Input Current CLOCK INPUT (CLK) Input High Voltage Input Low Voltage Clock Duty Cycle Clock Duty-Cycle Tolerance VCLKH VCLKL 50 30 0.8 x CVDD 0.2 x CVDD V V % % IREFIO VREFIO TCREFIO 1.18 (Note 5) 200 1.24 100 1.30 0.1 V A V ppm/C
EXTERNAL REFERENCE (INTREF = AVDD) (Note 5) AVDD 0.1V 200 1.24 <1 V A V A
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3
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
ELECTRICAL CHARACTERISTICS (continued)
(AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1F, fCLK = 40MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input Leakage Input Capacitance SYMBOL DIIN DCIN 0.8 x AVDD 0.2 x AVDD Input at GND, except PLL2 and PLL3 Input Leakage Input Capacitance Differential Output Voltage Output Common-Mode Voltage Rise Time (20% to 80%) Fall Time (80% to 20%) Differential Output Voltage Output Common-Mode Voltage Rise Time (20% to 80%) Fall Time (80% to 20%) POWER-DOWN PD Fall to Output Enable PD Rise to Output Disable POWER REQUIREMENTS AVDD Supply Voltage OVDD Supply Voltage CVDD Supply Voltage AVDD OVDD CVDD 1.7 1.7 1.7 1.8 1.8 1.8 1.9 1.9 3.6 V V V tENABLE tDISABLE 132 10 s ns DIIN DCIN VOHDIFF VOCM tR tF VOHDIFF VOCM tR tF RTERM = 100 RTERM = 100 RTERM = 100, CLOAD = 5pF RTERM = 100, CLOAD = 5pF RTERM = 100 RTERM = 100 RTERM = 100, CLOAD = 5pF RTERM = 100, CLOAD = 5pF 250 1.125 150 150 240 220 120 120 Input at AVDD, except PLL2 and PLL3 PLL2 and PLL3 only 5 450 1.375 LVDS OUTPUTS (OUT_P, OUT_N, SLVS/LVDS = 0 mV V ps ps mV mV ps ps 5 80 200 pF A Input at GND Input at AVDD 5 CONDITIONS MIN TYP MAX 5 80 UNITS A pF
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS/LVDS, PD_, PDALL, T/B) Input High Threshold Input Low Threshold VIH VIL V V
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
4
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1F, fCLK = 40MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS PDALL = 0, all channels active PDALL = 0, all channels active, DT = 1 PDALL = 0, 1 channel active PDALL = 0, PD[3:0] = 1111 PDALL = 1, global power down, PD[3:0] =1111, no clock input PDALL = 0, all channels active PDALL = 0, all channels active, DT = 1 PDALL = 0, 1 channel active PDALL = 0, PD[3:0] = 1111 PDALL = 1, global powerdown, PD[3:0] =1111, no clock input CVDD Supply Current Power Dissipation TIMING CHARACTERISTICS (Note 6) Data Valid to CLKOUT Rise/Fall tOD fCLK = 40MHz, Figure 5 (Notes 6 and 7) (tSAMPLE / (tSAMPLE / tSAMPLE / 24) 24) 24 - 0.15 + 0.15 tSAMPLE / 12 tSAMPLE / 12 (tSAMPLE / (tSAMPLE / tSAMPLE / 24) 24) 24 - 0.15 + 0.15 (tSAMPLE / (tSAMPLE / (tSAMPLE / 2) 2) 2) +0.9 +1.3 +1.7 ns ICVDD PDISS CVDD is used only to bias ESD-protection diodes on CLK input, Figure 2 fIN = 19.3MHz at -0.5dBFS MIN TYP 246 246 76 20 438 A MAX 285 mA UNITS
MAX1126
AVDD Supply Current
IAVDD
fIN = 19.3MHz at -0.5dBFS
51 63 35 30 375
57 mA
OVDD Supply Current
IOVDD
fIN = 19.3MHz at -0.5dBFS
A
0 535 616
mA mW
CLKOUT Output Width High CLKOUT Output Width Low
tCH tCL
Figure 5 Figure 5
ns ns
FRAME Rise to CLKOUT Rise
tCF
Figure 4 (Note 7)
ns
Sample CLK Rise to Frame Rise
tSF
Figure 4 (Notes 7 and 8)
ns
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5
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
ELECTRICAL CHARACTERISTICS (continued)
(AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1F, fCLK = 40MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Crosstalk Gain Matching Phase Matching SYMBOL (Note 2) fIN = 19.3MHz (Note 2) fIN = 19.3.MHz (Note 2) CONDITIONS MIN TYP -90 0.1 1 MAX UNITS dB dB Degrees
CHANNEL-TO-CHANNEL MATCHING
Note 1: Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design and characterization and not subject to production testing. Note 2: See definition in the Parameter Definitions section. Note 3: The MAX1126 internally sets the common-mode voltage to 0.6V (typ) (see Figure 1). The common-mode voltage can be overdriven to between 0.55V and 0.85V. Note 4: Limited by MAX1127EVKIT input circuitry. Note 5: Connect INTREF to GND directly to enable internal reference mode. Connect INTREF to AVDD directly to disable the internal bandgap reference and enable external reference mode. Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level. Note 7: Guaranteed by design and characterization. Not subject to production testing. Note 8: Sample CLK Rise to FRAME RISE timing is measured from 50% of sample clock input level to 50% of FRAME output level.
6
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Typical Operating Characteristics
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 40MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
FFT PLOT (32,768-POINT DATA RECORD)
MAX1126 toc01
FFT PLOT (32,768-POINT DATA RECORD)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 fCLK = 40.96MHz fIN = 19.00125MHz AIN = -0.5dBFS SNR = 69.20dB SINAD = 69.16dB THD = -88.74dBc SFDR = 89.04dBc HD3 HD2
MAX1126 toc02
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 4 8
AMPLITUDE (dBFS)
HD2
HD3
12
16
20
AMPLITUDE (dBFS)
fCLK = 40.96MHz fIN = 5.30125MHz AIN = -0.5dBFS SNR = 69.88dB SINAD = 69.85dB THD = -91.46dBc SFDR = 93.65dBc
0
4
8
12
16
20
FREQUENCY (MHz)
FREQUENCY (MHz)
CROSSTALK (4096-POINT DATA RECORD)
MAX1126 toc03
CROSSTALK (4096-POINT DATA RECORD)
MAX1126 toc04
CROSSTALK (4096-POINT DATA RECORD)
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 MEASURED ON CHANNEL 2, WITH INTERFERING SIGNAL ON CHANNEL 3 fCLK = 39.9997651MHz fIN(IN2) = 5.2831721MHz fIN(IN3) = 19.3260584MHz
MAX1126 toc05
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 4
AMPLITUDE (dBFS)
MEASURED ON CHANNEL 2, WITH INTERFERING SIGNAL ON CHANNEL 0 fCLK = 39.9997651MHz fIN(IN2) = 5.2831721MHz fIN(IN0) = 19.3260584MHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
MEASURED ON CHANNEL 2, WITH INTERFERING SIGNAL ON CHANNEL 1 fCLK = 39.9997651MHz fIN(IN2) = 5.2831721MHz fIN(IN1) = 19.3260584MHz
0
8
12
16
20
0
4
8
12
16
20
0
4
8
12
16
20
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
TWO-TONE INTERMODULATION DISTORTION (32,768-POINT DATA RECORD)
-10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 4 8 12 16 20 FREQUENCY (MHz) fIN(IN1) = 12.40125MHz fIN(IN2) = 13.60125MHz AIN1 = -6.5dBFS AIN2 = -6.5dBFS IMD = 87.0dBc IM3 = 89.3dBc
MAX1126 toc06
GAIN BANDWIDTH PLOT
FULL-POWER BANDWIDTH -0.5dBFS SMALL-SIGNAL BANDWIDTH -20dBFS
MAX1126 toc07
0
1 0 -1 GAIN (dB) -2 -3 -4 -5 1 10 100 LIMITED BY MAX1127EVKIT INPUT CIRCUITRY
1000
ANALOG INPUT FREQUENCY (MHz)
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7
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 40MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1126 toc08
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1126 toc09
72 70 68 SNR (dB) 66 64 62 60 0 20 40 60 fIN (MHz) 80 100
72 70 68 SINAD (dB) 66 64 62 60
120
0
20
40
60 fIN (MHz)
80
100
120
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1126 toc10
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
95 90 85 SFDR (dBc) 80 75 70 65 60 55
MAX1126 toc11
-55 -60 -65 -70 THD (dBc) -75 -80 -85 -90 -95 -100 0 20 40 60 fIN (MHz) 80 100
100
120
0
20
40
60 fIN (MHz)
80
100
120
8
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 40MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER
MAX1126 toc12
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER
fIN = 5.301935MHz 67 62 SINAD (dB) 57 52 47 42 37 32
MAX1126 toc13
72 fIN = 5.301935MHz 67 62 SNR (dB) 57 52 47 42 37 32 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dBFS)
72
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT POWER (dBFS)
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER
MAX1126 toc14
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER
95 90 85 SFDR (dBc) 80 75 70 65 60 55 fIN = 5.301935MHz
MAX1126 toc15
-55 -60 -65 -70 THD (dBc) -75 -80 -85 -90 -95 -100 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dBFS) fIN = 5.301935MHz
100
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT POWER (dBFS)
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9
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 40MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE
MAX1126 toc16
SIGNAL-TO-NOISE PLUS DISTORTION vs. SAMPLING RATE
71 70 69 SINAD (dB) 68 67 66 65 64 63 62 fIN = 5.301935MHz
MAX1126 toc17
72 71 70 69 SNR (dB) 68 67 66 65 64 63 62 20 25 30 fCLK (MHz) 35 fIN = 5.301935MHz
72
40
20
25
30 fCLK (MHz)
35
40
TOTAL HARMONIC DISTORTION vs. SAMPLING RATE
MAX1126 toc18
SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
fIN = 5.301935MHz 100 95 SFDR (dBc) 90 85 80 75
MAX1126 toc19
-75 fIN = 5.301935MHz -80 -85 THD (dBc) -90 -95 -100 -105 20 25 30 fCLK (MHz) 35
105
40
20
25
30 fCLK (MHz)
35
40
10
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 40MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE
MAX1126 toc20
SIGNAL-TO-NOISE PLUS DISTORTION vs. CLOCK DUTY CYCLE
71 70 69 SINAD (dB) 68 67 66 65 64 63 62 fIN = 5.301935MHz
MAX1126 toc21
72 71 70 69 SNR (dB) 68 67 66 65 64 63 62 30 40 50 60 fIN = 5.301935MHz
72
70
30
40
50
60
70
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE
MAX1126 toc22
SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE
fIN = 5.301935MHz 95 90 SFDR (dBc) 85 80 75 70
MAX1126 toc23
-75 fIN = 5.301935MHz -80 -85 THD (dBc) -90 -95 -100 -105 30 40 50 60
100
70
30
40
50
60
70
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
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11
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 40MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
MAX1126 toc24
SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE
fCLK = 40.404040404MHz fIN = 19.29204151MHz 4096-POINT DATA RECORD
MAX1126 toc25
72 fCLK = 40.404040404MHz fIN = 19.29204151MHz 4096-POINT DATA RECORD
72
70
70
SNR (dB)
68
SINAD (dB) -40 -15 10 35 60 85
68
66
66
64
64
62 TEMPERATURE (C)
62 -40 -15 10 35 60 85 TEMPERATURE (C)
TOTAL HARMONIC DISTORTION vs. TEMPERATURE
MAX1126 toc26
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
fCLK = 40.404040404MHz fIN = 19.29204151MHz 4096-POINT DATA RECORD
MAX1126 toc27
-75 -80 -85 -90 -95 -100 -105 -40 -15 10 35 60 fCLK = 40.404040404MHz fIN = 19.29204151MHz 4096-POINT DATA RECORD
100 95 90 SFDR (dBc) 85 80 75 70
THD (dBc)
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
12
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 40MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
ANALOG SUPPLY CURRENT vs. SAMPLING RATE
MAX1126 toc28
DIGITAL SUPPLY CURRENT vs. SAMPLING RATE
MAX1126 toc29
270
70 60 50
260
250
IOVDD (mA) 20 25 30 fCLK (MHz) 35 40
IAVDD (mA)
40 30 20
240
230 10 220 0 20 25 30 fCLK (MHz) 35 40
OFFSET ERROR vs. TEMPERATURE
MAX1126 toc30
GAIN ERROR vs. TEMPERATURE
0.9 0.8 GAIN ERROR (%FS) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
MAX1126 toc31
0.020 0.015 OFFSET ERROR (%FS) 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 -40 -15 10 35 60
1.0
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1126 toc32
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4
MAX1126 toc33
0.6 0.4 0.2 INL (LSB) 0 -0.2 -0.4 -0.6 0
0.5
-0.5 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
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13
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Typical Operating Characteristics (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 40MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1126 toc34
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1126 toc35
INTERNAL REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT
1.35 1.30 VREFIO (V) 1.25 1.20 1.15 NEGATIVE CURRENT FLOWS INTO REFIO
MAX1126 toc36
1.239
1.26
1.40
1.238 VREFIO (V) VREFIO (V)
1.25
1.237
1.24
1.236 AVDD = OVDD 1.235 1.7 1.8 1.9 2.0 2.1 SUPPLY VOLTAGE (V)
1.23 AVDD = OVDD 1.22 -40 -15 10 35 60 85 TEMPERATURE (C)
1.10 1.05 1.00 -400 -300 -200 -100 0 100 200 300 400 IREFIO (A)
Pin Description
PIN 1, 4, 7, 11, 14, 17, 22, 24, 65, 68 2 3 5 6 8, 9, 10, 18, 20, 25, 26, 27, 58-62 12 13 15 16 19 21 23 28 NAME GND IN0P IN0N IN1P IN1N FUNCTION Ground. Connect all GND pins to the same potential. Channel 0 Positive Analog Input Channel 0 Negative Analog Input Channel 1 Positive Analog Input Channel 1 Negative Analog Input Analog Power Input. Connect AVDD to a 1.7V to 1.9V power supply. Bypass each AVDD to GND with a 0.1F capacitor as close to the device as possible. Bypass the AVDD power plane to the GND ground plane with a bulk 2.2F capacitor as close to the device as possible. Connect all AVDD pins to the same potential. Channel 2 Positive Analog Input Channel 2 Negative Analog Input Channel 3 Positive Analog Input Channel 3 Negative Analog Input Internally Connected. Do not connect. Clock Power Input. Connect CVDD to a 1.7V to 3.6V supply. Bypass CVDD to GND with a 0.1F capacitor in parallel with a 2.2F capacitor. Install the bypass capacitors as close to the device as possible. Single-Ended CMOS Clock Input Double Termination Select Input. Drive DT high to select the internal 100 termination between the differential output pairs. Drive DT low to select no internal output termination.
AVDD
IN2P IN2N IN3P IN3N I.C. CVDD CLK DT
14
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Pin Description (continued)
PIN 29 30 31 32 33 34, 37, 40, 43, 46, 49, 52 35 36 38 39 41 42 44 45 47 48 50 51 53 54 55 56 57 63 NAME SLVS/LVDS PLL0 PLL1 PLL2 PLL3 FUNCTION Differential Output Signal Format Select Input. Drive SLVS/LVDS high to select SLVS outputs. Drive SLVS/LVDS low to select LVDS outputs. PLL Control Input 0. PLL0 is reserved for factory testing only and must always be connected to GND. PLL Control Input 1. PLL1 is reserved for factory testing only and must always be connected to GND. PLL Control Input 2. See Table 1 for details. PLL Control Input 3. See Table 1 for details. Output-Driver Power Input. Connect OVDD to a 1.7V to 1.9V power supply. Bypass each OVDD to GND with a 0.1F capacitor as close to the device as possible. Bypass the OVDD power plane to the GND ground plane with a bulk 2.2F capacitor as close to the device as possible. Connect all OVDD pins to the same potential. Channel 3 Negative LVDS/SLVS Output Channel 3 Positive LVDS/SLVS Output Channel 2 Negative LVDS/SLVS Output Channel 2 Positive LVDS/SLVS Output Negative Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. Positive Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. Negative LVDS/SLVS Serial Clock Output Positive LVDS/SLVS Serial Clock Output Channel 1 Negative LVDS/SLVS Output Channel 1 Positive LVDS/SLVS Output Channel 0 Negative LVDS/SLVS Output Channel 0 Positive LVDS/SLVS Output Channel 0 Power-Down Input. Drive PD0 high to power-down channel 0. Drive PD0 low for normal operation. Channel 1 Power-Down Input. Drive PD1 high to power-down channel 1. Drive PD1 low for normal operation. Channel 2 Power-Down Input. Drive PD2 high to power-down channel 2. Drive PD2 low for normal operation. Channel 3 Power-Down Input. Drive PD3 high to power-down channel 3. Drive PD3 low for normal operation. Global Power-Down Input. Drive PDALL high to power-down all channels and reference. Drive PDALL low for normal operation. Output Format Select Input. Drive T/B high to select binary output format. Drive T/B low to select two's complement output format.
OVDD
OUT3N OUT3P OUT2N OUT2P FRAMEN FRAMEP CLKOUTN CLKOUTP OUT1N OUT1P OUT0N OUT0P PD0 PD1 PD2 PD3 PDALL T/B
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15
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Pin Description (continued)
PIN 64 NAME LVDSTEST FUNCTION LVDS Test Pattern Enable Input. Drive LVDSTEST high to enable the output test pattern (000010111101 MSBLSB). As with the analog conversion results, the test pattern data is output LSB first. Drive LVDSTEST low for normal operation. Reference Input/Output. For internal reference operation (INTREF = GND), the reference output voltage is 1.24V. For external reference operation (INTREF = AVDD), apply a stable reference voltage at REFIO. Bypass to GND with a 0.1F capacitor. Internal/External Reference Mode Select Input. For internal reference mode, connect INTREF directly to GND. For external reference mode, connect INTREF directly to AVDD. Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified performance.
66
REFIO
67 --
INTREF EP
Functional Diagram
PDALL PD0 PD1 PD2 PD3 AVDD OVDD DT SLVS/LVDS
REFIO INTREF
REFERENCE SYSTEM
POWER CONTROL
MAX1126
OUTPUT CONTROL
LVDSTEST T/B
IN0P T/H IN0N
12-BIT PIPELINE ADC
12:1 SERIALIZER
OUT0P OUT0N OUT1P
IN1P T/H IN1N
12-BIT PIPELINE ADC
12:1 SERIALIZER LVDS/SLVS OUTPUT DRIVERS
OUT1N OUT2P OUT2N OUT3P OUT3N FRAMEP
IN2P IN2N
T/H
12-BIT PIPELINE ADC
12:1 SERIALIZER
IN3P IN3N
T/H
12-BIT PIPELINE ADC PLL 6x
12:1 SERIALIZER
FRAMEN CLKOUTP
CLK
CLOCK CIRCUITRY
CLKOUTN
CVDD
PLL0 PLL1 PLL2 PLL3
GND
16
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
Detailed Description
The MAX1126 ADC features fully differential inputs, a pipelined architecture, and digital error correction for high-speed signal conversion. The ADC pipeline architecture moves the samples taken at the inputs through the pipeline stages every half clock cycle. The converted digital results are serialized and sent through the LVDS/SLVS output drivers. The total latency from input to output is 6.5 input clock cycles. The MAX1126 offers four separate fully differential channels with synchronized inputs and outputs. Configure the outputs for binary or two's complement with the T/B digital input. Power-down each channel individually or globally to minimize power consumption. ductance amplifier (OTA), and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. Analog inputs IN_P to IN_N are driven differentially. For differential inputs, balance the input impedance of IN_P and IN_N for optimum performance. The MAX1126 analog inputs are self-biased at a common-mode voltage of 0.6V (typ) and allow a differential input voltage swing of 1.4VP-P. The common-mode voltage can be overdriven to between 0.55V and 0.85V. Drive the analog inputs of the MAX1126 in AC-coupled configuration to achieve best dynamic performance. See the Using Transformer Coupling section for a detailed discussion of this configuration.
MAX1126
Input Circuit
Figure 1 displays a simplified functional diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the operational transcon-
SWITCHES SHOWN IN TRACK MODE INTERNALLY GENERATED COMMON-MODE LEVEL*
INTERNAL COMMON-MODE BIAS* AVDD
INTERNAL BIAS*
MAX1126
S2a C1a
S5a
S3a S4a IN_P OUT S4c IN_N S4b C2b C1b S3b GND S2b INTERNAL COMMON-MODE BIAS* S5b S1 OTA OUT C2a
INTERNAL BIAS*
INTERNALLY GENERATED COMMON-MODE LEVEL*
*NOT EXTERNALLY ACCESSIBLE
Figure 1. Internal Input Circuitry ______________________________________________________________________________________ 17
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Reference Configurations (REFIO and INTREF)
The MAX1126 provides an internal 1.24V bandgap reference or can be driven with an external reference voltage. The MAX1126 full-scale analog differential input range is FSR. Full-scale range (FSR) is given by the following equation: V FSR = 700mV x REFIO 1.24 V where VREFIO is the voltage at REFIO, generated internally or externally. For a VREFIO = 1.24V, the full-scale input range is 700mV (1.4VP-P). Internal Reference Mode Connect INTREF to GND to use the internal bandgap reference directly. The internal bandgap reference generates REFIO to be 1.24V with a 100ppm/C temperature coefficient in internal reference mode. Connect an external 0.1F bypass capacitor from REFIO to GND for stability. REFIO sources up to 200A and sinks up to 200A for external circuits, and REFIO has a load regulation of 83mV/mA. The global power-down input (PDALL) enables and disables the reference circuit. REFIO has >1M resistance to GND when the MAX1126 is in power-down mode. The internal reference circuit requires 132s to power-up and settle when power is applied to the MAX1126 or when PDALL transitions from high to low. External Reference Mode The external reference mode allows for more control over the MAX1126 reference voltage and allows multiple converters to use a common reference. Connect INTREF to AVDD to disable the internal reference and enter external reference mode. Apply a stable 1.24V source at REFIO. Bypass REFIO to GND with a 0.1F capacitor. The REFIO input impedance is >1M.
Clock Input (CLK)
The MAX1126 accepts a CMOS-compatible clock signal with a wide 20% to 80% input-clock duty cycle. Drive CLK with an external single-ended clock signal. Figure 2 shows the simplified clock input diagram. Low clock jitter is required for the specified SNR performance of the MAX1126. Analog input sampling occurs on the rising edge of CLK, requiring this edge to provide the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 x log 2 x x fIN x t J where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 69.2dB of SNR with an input frequency of 19.3MHz, the system must have less than 2.8psRMS of clock jitter. In actuality, there are other noise sources, such as thermal noise and quantization noise, that contribute to the system noise requiring the clock jitter to be less than 1.1psRMS to obtain the specified 69.2dB of SNR at 19.3MHz. PLL Inputs (PLLO-PLL3) The MAX1126 features a PLL that generates an output clock signal with 6 times the frequency of the input clock. The output clock signal is used to clock data out of the MAX1126 (see the System Timing Requirements section). Set the PLL2 and PLL3 bits according to the input clock range provided in Table 1. PLL0 and PLL1 are reserved for factory testing and must always be connected to GND.
AVDD
Table 1. PLL2 and PLL3 Configuration
MAX1126
PLL2
DUTY-CYCLE EQUALIZER
CVDD CLK GND
PLL3 0 1 0 1
CLOCK INPUT RANGE (MHz) MIN MAX NOT USED 32.500 24.375 16.000 40.000 32.500 24.375
0 0 1 1
Figure 2. Clock Input Circuitry 18
*PLL0 and PLL11 are reserved for factory testing and must always be connected to GND.
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
N+2 N (VIN_P VIN_N) N+1 tSAMPLE N+3 N+5 N+4 N+7 N+6 N+8 N+9
CLK
6.5 CLOCK-CYCLE DATA LATENCY
(VFRAMEP VFRAMEN)*
(VCLKOUTP VCLKOUTN)
(VOUT_P VOUT_N) OUTPUT DATA FOR SAMPLE N-6 *DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY. OUTPUT DATA FOR SAMPLE N
Figure 3. Global Timing Diagram
N+2 N (VIN_P - VIN_N) tSAMPLE CLK (VFRAMEP VFRAMEN) (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) D5N-7 D6N-7 D7N-7 D8N-7 D9N-7 D10N-7 D11N-7 D0N-6 D1N-6 D2N-6 D3N-6 D4N-6 D5N-6 D6N-6 D7N-6 D8N-6 D9N-6 D10N-6 D11N-6 D0N-5 D1N-5 D2N-5 D3N-5 D4N-5 D5N-5 D6N-5 *DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY. N+1 tSF
tCF
Figure 4. Detailed Two-Conversion Timing Diagram
System Timing Requirements
Figure 3 shows the relationship between the analog inputs, input clock, frame alignment output, serial clock output, and serial data output. The differential analog input (IN_P and IN_N) is sampled on the rising edge of the CLK signal and the resulting data appears at the digital outputs 6.5 clock cycles later. Figure 4 provides a detailed, two-conversion timing diagram of the relationship between the inputs and the outputs.
Clock Output (CLKOUTP, CLKOUTN) The MAX1126 provides a differential clock output that consists of CLKOUTP and CLKOUTN. As shown in Figure 4, the serial output data is clocked out of the MAX1126 on both edges of the clock output. The frequency of the output clock is 6 times the frequency of CLK.
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19
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Frame Alignment Output (FRAMEP, FRAMEN) The MAX1126 provides a differential frame alignment signal that consists of FRAMEP and FRAMEN. As shown in Figure 4, the rising edge of the frame alignment signal corresponds to the first bit (D0) of the 12-bit serial data stream. The frequency of the frame alignment signal is identical to the frequency of the sample clock. Serial Output Data (OUT_P, OUT_N) The MAX1126 provides its conversion results through individual differential outputs consisting of OUT_P and OUT_N. The results are valid 6.5 input clock cycles after the sample is taken. As shown in Figure 3, the output data is clocked out on both edges of the output clock, LSB (D0) first. Figure 5 provides the detailed serial output timing diagram. Output Data Format (T/B), Transfer Functions The MAX1126 output data format is either offset binary or two's complement, depending on the logic input T/B. With T/B low, the output data format is two's complement. With T/B high, the output data format is offset binary. The following equations, Table 2, Figure 6, and Figure 7 define the relationship between the digital output and the analog input. For two's complement (T/B = 0): VIN _ P - VIN _ N = FSR x 2 x and for offset binary (T/B = 1): CODE10 4096
tCH (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) tCL
tOD D0 D1 D2
tOD D3
Figure 5. Serialized Output Detailed Timing Diagram
VIN _ P - VIN _ N = FSR x 2 x
CODE10 - 2048 4096
where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. FSR is the full-scale range as shown in Figures 6 and 7. Keep the capacitive load on the MAX1126 digital outputs as low as possible.
LVDS and SLVS Signals (SLVS/LVDS)
Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high for scalable low-voltage signaling (SLVS) levels at the MAX1126 outputs (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN). See the Electrical Characteristics table for LVDS and SLVS output voltage levels.
LVDS Test Pattern (LVDSTEST)
Drive LVDSTEST high to enable the output test pattern on all LVDS or SLVS output channels. The output test pattern is 0000 1011 1101 MSBLSB. As with the analog conversion results, the test pattern data is output
Table 2. Output Code Table (VREFIO = 1.24V)
TWO'S COMPLEMENT DIGITAL OUTPUT CODE (T/B = 0) HEXADECIMAL EQUIVALENT OF D11 D0 0x7FF 0x7FE 0x001 0x000 0xFFF 0X801 0x800 DECIMAL EQUIVALENT OF D11 D0 +2047 +2046 +1 0 -1 -2047 -2048 OFFSET BINARY DIGITAL OUTPUT CODE (T/B = 1) HEXADECIMAL EQUIVALENT OF D11 D0 0xFFF 0xFFE 0x801 0x800 0x7FF 0x001 0x000 DECIMAL EQUIVALENT OF D11 D0 +4095 +4094 +2049 +2048 +2047 +1 0 VIN_P - VIN_P (mV) (VREFIO = 1.24V)
BINARY D11 D0 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0001 1000 0000 0000
BINARY D11 D0 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
+699.66 +699.32 +0.34 0 -0.34 -699.66 -700.00
20
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
1 LSB = 2 x FSR 4096 FSR TWO'S COMPLEMENT OUTPUT CODE (LSB) 0x7FF 0x7FE 0x7FD FSR = 700mV x VREFIO 1.24V FSR OFFSET BINARY OUTPUT CODE (LSB) 0xFFF 0xFFE 0xFFD 1 LSB = 2 x FSR 4096 FSR FSR = 700mV x VREFIO 1.24V FSR
0x001 0x000 0xFFF
0x801 0x800 0x7FF
0x803 0x802 0x801 0x800 -2047 -2045 -1 0 +1 +2045 +2047
0x003 0x002 0x800 0x000 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Bipolar Transfer Function with Two's Complement Output Code (T/B = 0)
Figure 7. Bipolar Transfer Function with Offset Binary Output Code (T/B = 1)
DT
OUT_P/ CLKOUTP/ FRAMEP
Z0 = 50
directly at the outputs helps eliminate unwanted reflections down the line. This feature is useful in applications where trace lengths are long (>5in) or with mismatched impedance. Drive DT high to select double termination, or drive DT low to disconnect the internal termination resistor (single termination). Selecting double termination increases the OV DD supply current (see the Electrical Characteristics table).
Power-Down Modes
100 100
The MAX1126 offers two types of power-down inputs, PD0-PD3 and PDALL. The power-down modes allow the MAX1126 to efficiently use power by transitioning to a low-power state when conversions are not required. Independent Channel Power-Down (PD0-PD3) PD0-PD3 control the power-down mode of each channel independently. Drive a power-down input high to power down its corresponding input channel. For example, to power down channel 1, drive PD1 high. Drive a power-down input low to place the corresponding input channel in normal operation. The differential output impedance of a powered-down output channel is approximately 378, when DT is low. The output impedance of OUT_P, with respect to OUT_N, is 100 when DT is high. See the Electrical Characteristics table for typical supply currents with powered-down channels. The state of the internal reference is independent of the PD0-PD3 inputs. To power down the internal reference circuitry, drive PDALL high (see the Global PowerDown (PDALL) section).
21
MAX1126
OUT_N/ CLKOUTN/ FRAMEN
Z0 = 50
SWITCHES ARE CLOSED WHEN DT IS HIGH. SWITCHES ARE OPEN WHEN DT IS LOW.
Figure 8. Double Termination
LSB first. Drive LVDSTEST low for normal operation (test pattern disabled).
Double Termination (DT)
As shown in Figure 8, the MAX1126 offers an optional, internal 100 termination between the differential output pairs (OUT_P and OUT_N, CLKOUTP and CLKOUTN, FRAMEP and FRAMEN). In addition to the termination at the end of the line, a second termination
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
Global Power-Down (PDALL) PDALL controls the power-down mode of all channels and the internal reference circuitry. Drive PDALL high to enable global power-down. In global power-down mode, the output impedance of all the LVDS/SLVS outputs is approximately 378, if DT is low. The output impedance of the differential LVDS/SLVS outputs is 100 when DT is high. See the Electrical Characteristics table for typical supply currents with global power-down. The following list shows the state of the analog inputs and digital outputs in global power-down mode: * IN_P, IN_N analog inputs are disconnected from the internal input amplifier. * REFIO has >1M resistance to GND. * OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN have approximately 378 between the output pairs when DT is low. When DT is high, the differential output pairs have 100 between each pair. When operating from the internal reference, the wakeup time from global power-down is typically 132s. When using an external reference, the wake-up time is dependent on the external reference drivers.
MAX1126
Grounding, Bypassing, and Board Layout
The MAX1126 requires high-speed board layout design techniques. Refer to the MAX1127 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass AVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Bypass OVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Bypass CVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. Connect MAX1126 ground pins and the exposed backside paddle to the same ground plane. The MAX1126 relies on the exposed backside paddle connection for a lowinductance ground connection. Isolate the ground plane from any noisy digital system ground planes. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90 turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1126 EV kit data sheet for an example of symmetric input layout.
Applications Information
Using Transformer Coupling
An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX1126 for optimum performance. The MAX1126 input common-mode voltage is internally biased to 0.6V (typ) with fCLK = 40MHz. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion.
Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX1126, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table.
Differential Nonlinearity (DNL)
10 0.1F VIN N.C. 1 T1 2 5 0.1F 4 3 MINICIRCUITS ADT1-1WT 6 39pF IN_P
MAX1126
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1126, DNL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table.
10 IN_N 39pF
Offset Error
Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. For the MAX1126, the ideal midscale digital output transition occurs when there is -1/2 LSB across the analog inputs (Figures 6 and 7).
Figure 9. Transformer-Coupled Input Drive 22
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
Bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.
MAX1126
CLK tAD ANALOG INPUT tAJ SAMPLED DATA
Gain Error
Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1126, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. For the bipolar devices (MAX1126), the full-scale transition point is from 0x7FE to 0x7FF for two's complement output format (0xFFE to 0xFFF for offset binary) and the zero-scale transition point is from 0x800 to 0x801 for two's complement (0x000 to 0x001 for offset binary).
T/H
HOLD
TRACK
HOLD
Figure 10. Aperture Jitter/Delay Specifications
Crosstalk
Crosstalk indicates how well each analog input is isolated from the others. For the MAX1126, a 5.3MHz, -0.5dBFS analog signal is applied to one channel while a 19.3MHz, -0.5dBFS analog signal is applied to all other channels. An FFT is taken on the channel with the 5.3MHz analog signal. From this FFT, the crosstalk is measured as the difference in the 5.3MHz and 19.3MHz amplitudes. For the MAX1126, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2-HD7), and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency, excluding the fundamental and the DC offset.
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. See Figure 10.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD - 1.76 ENOB = 6.02
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay. See Figure 10.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 2 2 2 V2 + V3 + V4 + V5 + V6 + V7 THD = 20 x log V1
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23
Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1126
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6.5dBFS. The intermodulation products are as follows: * 2nd-order intermodulation products (IM2): f1 + f2, f2 - f1 * 3rd-order intermodulation products (IM3): 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1 * 4th-order intermodulation products (IM4): 3 x f1 - f2, 3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1 * 5th-order intermodulation products (IM5): 3 x f1 - 2 x f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1
Gain Matching
Gain matching is a figure of merit that indicates how well the gain of all four ADC channels is matched to each other. For the MAX1126, gain matching is measured by applying the same 19.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 40MHz and the maximum deviation in amplitude is reported in dB as gain matching in the Electrical Characteristics table.
Phase Matching
Phase matching is a figure of merit that indicates how well the phase of all four ADC channels is matched to each other. For the MAX1126, phase matching is measured by applying the same 19.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 40MHz and the maximum deviation in phase is reported in degrees as phase matching in the Electrical Characteristics table.
Third-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -6.5dBFS. The 3rd-order intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an ADC so the signal's slew rate does not limit the ADC's
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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
68L QFN.EPS
MAX1126
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
Note: For the MAX1126 Exposed Pad Variation, the package code is G6800-4.
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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