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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45V16AD641
VirtualChannel
TM
16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE
Description The MC-45V16AD641 is a 16,777,216 words by 64 bits VirtualChannel synchronous dynamic RAM module on which 16 pieces of 64M VirtualChannel SDRAM : PD4565821 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
Features
* 16,777,216 words by 64 bits organization * Clock frequency and access time from CLK
Part number Read Clock Access time from CLK ns (MAX.) 5.4 6 5.4 6 880 840 880 840 Prefetch Maximum supply current mA Operating Restore Channel read / write (Burst) 720 600 720 600 1280 1120 1280 1120 16 Auto Refresh Self
latency frequency MHz (MAX.) MC-45V16AD641KF-A75 MC-45V16AD641KF-A10 MC-45V16AD641EF-A75 MC-45V16AD641EF-A10 2 133 100 133 100
* Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Dual internal banks controlled by BA0 (Bank Select) * Programmable Wrap sequence (Sequential / Interleave) * Programmable burst length (1, 2, 4, 8 and 16) 5 * Read latency (2) * Prefetch Read latency (4) * Auto precharge and without auto precharge * Auto refresh and Self refresh * Single 3.3 V 0.3 V power supply * Interface: LVTTL * Refresh cycle: 4K cycles / 64 ms * 168-pin dual in-line memory module (Pin pitch = 1.27 mm) * Unbuffered type * Serial PD
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M13823EJ6V0DS00 (6th edition) Date Published June 2000 NS CP (K) Printed in Japan
The mark * shows major revised points.
(c)
1998
MC-45V16AD641
5
Ordering Information
Part number Clock frequency MHz (MAX.) MC-45V16AD641KF-A75 MC-45V16AD641KF-A10 MC-45V16AD641EF-A75 MC-45V16AD641EF-A10 133 100 133 100 2 Read latency Prefetch read latency 4 168-pin Dual In-line Memory Module (Socket Type) Edge connector : Gold plated 34.93 mm height 16 pieces of PD4565821G5 (10.16 mm (400) TSOP (II)) (Rev.K) 16 pieces of PD4565821G5 (10.16 mm (400) TSOP (II)) (Rev.E) Package Mounted devices
2
Data Sheet M13823EJ6V0DS00
MC-45V16AD641
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal.
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 NC NC VSS NC NC Vcc /CAS DQMB4 DQMB5 /CS1 /RAS VSS A1 A3 A5 A7 A9 BA0 (A13) A11 Vcc CLK1 NC VSS CKE0 /CS3 DQMB6 DQMB7 NC Vcc NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 NC NC VSS NC NC Vcc /WE DQMB0 DQMB1 /CS0 NC VSS A0 A2 A4 A6 A8 A10 A12 Vcc Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
A0 - A12 BA0 (A13) DQ0 - DQ63 CLK0 - CLK3 CKE0, CKE1 /CS0 - /CS3 /RAS /CAS /WE DQMB0 - DQMB7 SA0 - SA2 SDA SCL VCC VSS WP NC
: Address Inputs : VirtualChannel SDRAM Bank Select : Data Inputs/Outputs : Clock Input : Clock Enable Input : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : DQ Mask Enable : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : Write Protect : No Connection
[Row: A0 - A12, Column: A0 - A6]
Data Sheet M13823EJ6V0DS00
3
MC-45V16AD641
Block Diagram
/WE /CS0 DQMB0 /CS1 /CS2 DQMB2 /CS3
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQMB1
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D0 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D8 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23
DQMB3
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D2 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D10 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
DQMB4
DQ 7 DQM DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0
/CS
/WE
D1
DQ 0 DQM DQ 1 DQ 2 DQ 3 D9 DQ 4 DQ 5 DQ 6 DQ 7
/CS
/WE
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
DQMB6
DQ 4 DQM /CS DQ 7 DQ 6 DQ 5 D3 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 3 DQM /CS DQ 0 DQ 1 DQ 2 D11 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39
DQMB5
DQ 4 DQM /CS DQ 7 DQ 6 DQ 5 D4 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 3 DQM /CS DQ 0 DQ 1 DQ 2 D12 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
DQMB7
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D6 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D14 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
DQ 5 DQM /CS DQ 7 DQ 6 DQ 4 D5 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 2 DQM /CS DQ 0 DQ 1 DQ 3 D13 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D7 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D15 DQ 4 DQ 5 DQ 6 DQ 7
/WE
CLK0
SERIAL PD SDA SCL A0 A1 A2 WP
CLK: D0, D1, D4, D5
CLK2
CLK: D2, D3, D6, D7
3.3 pF
3.3 pF
CLK1
CLK: D8, D9, D12, D13 CLK3
CLK: D10, D11, D14, D15
47 k
SA0 SA1 SA2
3.3 pF
3.3 pF
A0 - A12 BA0 VCC C VSS
A0 - A12: D0 - D15 A13: D0 - D15
/RAS /CAS
/RAS: D0 - D15 CKE1 /CAS: D0 - D15 CKE: D0 - D7
10 CKE: D8-D15
D0 - D15 CKE0 D0 - D15
Remarks 1. The value of all resistors is 10 except CKE1 and WP. 2. D0 - D15: PD4565821 (4M words x 8 bits x 2 banks)
4
Data Sheet M13823EJ6V0DS00
MC-45V16AD641
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 16 0 to +70 -55 to +125 Unit V V mA W C C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 3.0 2.0 -0.3 0 TYP. 3.3 MAX. 3.6 VCC + 0.3 +0.8 70 Unit V V V C
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 CI5 Data input/output capacitance CI/O Test condition A0 - A12, BA0 (A13), /RAS, /CAS, /WE CLK0 - CLK3 CKE0, CKE1 /CS0 - /CS3 DQMB0 - DQMB7 DQ0 - DQ63 MIN. 58 24 32 17 10 11 TYP. MAX. 94 40 52 29 17 19 pF Unit pF
Data Sheet M13823EJ6V0DS00
5
MC-45V16AD641
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol ICC1P tRC tRC (MIN.) Prefetch is executed one time during tRC. ICC1R tRC tRC (MIN.) CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC2NS Active standby current in power down mode Active standby current in non power down mode ICC3NS ICC3P ICC3PS ICC3N CKE VIH (MIN.), tCK = , Input signals are stable. CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. tCK tCK (MIN.), IO = 0 mA Background : precharge standby ICC5 tRC tRC
(MIN.)
Test condition
Grade -A75 -A10 -A75 -A10
MIN.
MAX. 880 840 880 840 16 8 400 128 80 64 400
Unit mA
Notes 1
5 5
Operating current (Prefetch mode at one bank active) Operating current (Restore mode at one bank active) Precharge standby current in power down mode Precharge standby current in non power down mode
mA
1
ICC2P ICC2PS ICC2N
mA
mA
mA
mA
160 -A75 -A10 -A75 -A10 720 600 1,280 1,120 16 16 -16 -500 +16 +500 +1.5 mA mA 3 mA 2
5 5 5
Operating current (Burst mode) Auto refresh current
ICC4
Self refresh current
ICC6
CKE 0.2 V
-A75 -A10
Input leakage current Input leakage current (CKE1) Output leakage current High level output voltage Low level output voltage
II (L)
VI = 0 to 3.6 V, All other pins not under test = 0 V
A A A
V
IO (L) VOH VOL
DOUT is disabled, VO = 0 to 3.6 V IO = - 4.0 mA IO = + 4.0 mA
-1.5 2.4
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6
Data Sheet M13823EJ6V0DS00
MC-45V16AD641
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions * AC measurements assume tT = 1 ns. * Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. * If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.). * An access time is measured at 1.4 V.
tCK tCH CLK tCKS CKE tS Command Address DQM tH tCKH tCL tCH tCK tCL
(Input)
Valid tDS tDH tDS tDH
Data (Input) tAC tLZ Hi-Z
Valid tAC tOH
Valid
tHZ Hi-Z
Data (Output)
Valid
Valid
Data Sheet M13823EJ6V0DS00
7
MC-45V16AD641
5 AC characteristics
Parameter Symbol MIN. Clock cycle time Access time from CLK CLK high level width CLK low level width Data-out hold time Data-out low-impedance time Data-out high-impedance time Data-in setup time Data-in hold time Address, Command, DQM setup time Address, Command, DQM hold time CKE setup time CKE hold time CKE setup time (Power down exit) Transition time Refresh time (4,096 refresh cycles) Mode register set cycle time tCK tAC tCH tCL tOH tLZ tHZ tDS tDH tS tH tCKS tCKH tCKSP tT tREF tRSC 7.5 - 2.5 2.5 2.7 0 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.5 - 2 -A75 MAX. - 5.4 - - - - 5.4 - - - - - - - 30 64 - MIN. 10 - 3 3 3 0 3 2 1 2 1 2 1 2 1 - 2 -A10 MAX. - 6 - - - - 6 - - - - - - - 30 64 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms CLK 1 1 Unit Note
Note 1. Output load.
Z = 50 Output 50 pF
8
Data Sheet M13823EJ6V0DS00
MC-45V16AD641
5 AC characteristics (Background to Background operation)
Parameter Symbol MIN. Same Bank Operation ACT to ACT/REF Command period REF to REF/ ACT Command period ACT to PRE Command period PRE to ACT / REF Command period ACT to PFC/PFCA/ PPF/PPFA Command delay time ACT to PFR Command delay time (Prefetch Read Operation) PFC to PRE Command delay time PFCA / PFR to ACT/REF Command delay time PPF to PRE Command delay time PPFA to ACT/REF Command delay time RST / RSTA to ACT(R)
Note1
-A 75 MAX. MIN.
-A10 MAX.
Unit
Notes
tRC tRCF tRAS tRP tAPD tAPRD tPPL tPAL tPPP tPPA tRAD
67.5 67.5 52 20 15 20 22.5 45 45 67.5 7.5
- - 120,000 - - - - - - - 30
80 80 60 20 20 20 30 50 60 80 10
- - 120,000 - - - - - - - 40
ns ns ns ns ns ns ns ns ns ns ns 2
Command delay time
Same, Other Bank Operation ACT(R)
Note1
to PFC/PFCA/PFR/ PPF/PPFA
tRPD
37.5
- - -
40
- - -
ns
Command delay time PFC to PFC / PFCA Command delay time PPF to PPF / PPFA Command delay time tPPD tPPPD 22.5 45 30 60 ns ns
Other Bank Operation ACT to ACT/ACT(R) or ACT(R) to ACT Command delay time ACT(R) to ACT(R) Command delay time PFC /PFCA to RST /RSTA Command delay time PPF /PPFA to RST /RSTA Command delay time tRRD tRRDR tPRD tPPRD 15 30 22.5 45 - - - - 20 40 30 60 - - - - ns ns ns ns
Notes 1. ACT (R) command is ACT command after RST command. 2. The another background operation and same channel foreground operation are illegal while tRAD period.
Data Sheet M13823EJ6V0DS00
9
MC-45V16AD641
5 AC characteristics (Foreground to Foreground operation)
Parameter Symbol MIN. READ/WRITE to READ/WRITE Command delay time tCCD 7.5 -A75 MAX. - MIN. 10 -A10 MAX. - ns Unit Note
5
AC characteristics (Background to Foreground operation) (after same channel Prefetch/Restore)
Parameter Symbol MIN. PFC/PFCA/PPF/PPFA to READ/WRITE Command delay time PPF/PPFA to READ/WRITE Command delay time (2nd prefetch channel read write) ACT(R) to READ/WRITE Command delay time tRCD 30 - 40 - ns 1 tPPCD 37.5 - 50 - ns tPCD 15 -A75 MAX. - MIN. 20 -A10 MAX. - ns Unit Note
Note 1. ACT (R) command is ACT command after RST command.
10
Data Sheet M13823EJ6V0DS00
MC-45V16AD641
Serial PD
Byte No. 0 Function Described Defines the number of bytes written into serial PD memory 1 Total number of bytes of serial PD memory 2 3 4 5 6 7 8 Fundamental memory type Number of row addresses Number of column addresses Number of banks Data width Data width (continued) Voltage interface standard Read latency (/CAS latency) = 2 cycle time -A75 -A10 -A75 -A10 08H 0DH 07H 02H 40H 00H 01H 75H A0H 54H 60H 00H 80H 08H 00H 01H 1FH 02H 02H 01H 01H 00H 0EH 00H tRP (MIN.) -A75 -A10 14H 14H 0FH 14H 0FH 14H 34H 3CH 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 20 ns 20 ns 15 ns 20 ns 15 ns 20 ns 52 ns 60 ns VC SDRAM 13 rows 7 columns 2 banks 64 bits 0 LVTTL 7.5 ns 10 ns 5.4 ns 6 ns None Normal x8 None 1 clock 1, 2, 4, 8, 16 2 banks 2 0 0 08H 0 0 0 0 1 0 0 0 256 bytes Hex 80H Bit 7 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
(1/2)
Notes 128 bytes
5
9
5
10
Read latency (/CAS latency) = 2 access time
11 12 13 14 15 16 17
DIMM configuration type Refresh rate / type VC SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each VC SDRAM Read latency (/CAS latency) supported /CS latency supported /WE latency supported VC SDRAM module attributes VC SDRAM device attributes : general
*
18 19 20 21 22
* * * * *
23-26 27
28
tRRD (MIN.)
-A75 -A10
29
tAPD (MIN.)
-A75 -A10
30
tRAS (MIN.)
-A75 -A10
Data Sheet M13823EJ6V0DS00
11
MC-45V16AD641
(2/2)
Byte No. 31 Function Described Module bank density Address and command signal input setup time -A75 -A10 -A75 -A10 -A75 -A10 Hex 10H 15H 20H 08H 10H 15H 20H 08H 10H 04H 04H 0FH 14H 02H 04H 07H Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 5 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit 4 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 Bit 3 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 Bit 2 0 1 0 0 0 1 0 0 0 1 1 1 1 0 1 1 Bit 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 Bit 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 Notes 64M bytes 1.5 ns 2 ns 0.8 ns 1 ns 1.5 ns 2 ns 0.8 ns 1 ns 4 clocks 4 clocks 15 ns 20 ns 2 bits 16 128 bits
* * * * * *
32
33
Address and command signal input hold time
34
Data signal input setup time
35
Data signal input hold time
-A75 -A10
36
Prefetch read latency
-A75 -A10
37
tPCD (MIN.)
-A75 -A10
38 39 40 41-61 62
Number of segment addresses Number of channels Depth of channels
SPD revision Checksum for bytes 0 - 62 -A75 -A10
02H 3EH B2H
0 0 1
0 0 0
0 1 1
0 1 1
0 1 0
0 1 0
1 1 1
0 0 0
2.0
* *
63
64-71 72 73-90 91-92 93-94 95-98
Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision code Manufacturing date Assembly serial number
99-125 Mfg specific
Timing Charts Please refer to the PD4565421, 4565821, 4565161 Data sheet (M13022E).
12
Data Sheet M13823EJ6V0DS00
MC-45V16AD641
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) R2 F1 Q R1 A J B I G H K C D A1 (AREA A) M2 (AREA A)
ITEM A A1 B C D D1 D2 E F1 F2 G H I J K L M M1 M2 N P Q R1 R2 S T U1 U2 V W X Y1 Y2 Z1 Z2 MILLIMETERS 133.35 133.350.13 11.43 36.83 6.35 2.0 3.125 54.61 2.44 3.18 6.35 1.27 (T.P.) 8.89 24.495 42.18 17.78 34.930.13 15.15 19.78 4.0 MAX. 1.0 R2.0 4.00.10 9.53 3.0 1.270.1 4.0 MIN. 4.0 MIN. 0.20.15 1.00.05 2.540.10 3.0 MIN. 2.26 3.0 MIN. 2.26 M168S-50A78
Y1 Y2
Z1 Z2
N F2
M
L B S
(OPTIONAL HOLES)
U1
U2 T
E
M1 (AREA B) detail of A part W detail of B part D2
V X
P D1
Data Sheet M13823EJ6V0DS00
13
MC-45V16AD641
Revision History
Edition / Date This edition 4th edition / Jun. 1999 p.1 p.2 p.3 p.6 p.8 Page Previous edition p.1 p.2 p.3 p.6 p.8 Modification Note 1 p.9 p.9 Deletion -A70, tRCPD, tDAL Modification PIN No.53, No.63 Deletion -A70 Type of revision Deletion -A70 Description Location
Modification tAPD (Parameter), tRPD (Parameter) p.10 p.10 Deletion -A70
Modification tPCD (Parameter) p.11 p.12 p.14 5th edition / Dec. 1999 p.1 p.2 p.3 p.11 p.12 p.14 p.1 p.2 p.3 Addition Addition Addition Revision History MC-45V16AD641EF-A75, MC-45V16AD641EF-A10, MC-45V16AD641EF-A15 MC-45V16AD641EF-A75, MC-45V16AD641EF-A10, MC-45V16AD641EF-A15 Deletion -A70
Modification Pin Configuration (WP) Deletion Note
p.4
p.4
Modification Block Diagram (WP) Deletion Remarks 2
p.5 p.8 p.13 6th edition / Jun. 2000 p.1 p.2 p.6 p.8
p.5 p.8 p.13 p.1 p.2 p.6 p.8
Modification Capacitance Modification tHZ (-A75 (MAX.), -A15 (MAX.)) Modification Package Drawing Deletion -A15
Modification tT (-A75(MIN.)) p.9 p.10 p.11 p.9 p.10 p.11 Modification Byte No. 18 Deletion p.12 p.11, 12 p.12 Deletion Addition Byte No. 23, 24 -A15 Byte No. 32-35, -A75 Deletion -A15
Modification Byte No. 63
14
Data Sheet M13823EJ6V0DS00
MC-45V16AD641
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M13823EJ6V0DS00
15
MC-45V16AD641
VirtualChannel is a trademark of NEC Corporation.
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
* The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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